VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106626

Last change on this file since 106626 was 106626, checked in by vboxsync, 5 weeks ago

Disassembler: Re-arrange the ARMv8 tables to allow for multiple decoders for a single instruction class in case instructions in the same class require different decoding, implement decoding of 2-source instructions, bugref:10394
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1/* $Id: DisasmInternal-armv8.h 106626 2024-10-23 16:54:39Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseImmsImmrN,
64 kDisParmParseHw,
65 kDisParmParseCond,
66 kDisParmParsePState,
67 kDisParmParseCRnCRm,
68 kDisParmParseSysReg,
69 kDisParmParseSh12,
70 kDisParmParseImmTbz,
71 kDisParmParseShift,
72 kDisParmParseShiftAmount,
73 kDisParmParseImmMemOff,
74 kDisParmParseSImmMemOff,
75 kDisParmParseSImmMemOffUnscaled,
76 kDisParmParseOption,
77 kDisParmParseS,
78 kDisParmParseSetPreIndexed,
79 kDisParmParseSetPostIndexed,
80 kDisParmParseFpType,
81 kDisParmParseFpReg,
82 kDisParmParseFpScale,
83 kDisParmParseFpFixupFCvt,
84 kDisParmParseSimdRegScalar,
85 kDisParmParseImmHImmB,
86 kDisParmParseSf,
87 kDisParmParseMax
88} DISPARMPARSEIDX;
89/** @} */
90
91
92/**
93 * Decoder step.
94 */
95typedef struct DISARMV8INSNPARAM
96{
97 /** The parser to use for the decode step. */
98 DISPARMPARSEIDX idxParse;
99 /** Bit index at which the field starts. */
100 uint8_t idxBitStart;
101 /** Size of the bit field. */
102 uint8_t cBits;
103 /** The parameter this decoder param contributes to. */
104 uint8_t idxParam;
105} DISARMV8INSNPARAM;
106typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
107typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
108
109#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
110#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
111 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
112
113#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
114
115
116/**
117 * Opcode structure.
118 */
119typedef struct DISARMV8OPCODE
120{
121 /** The value of the fixed bits of the instruction. */
122 uint32_t fValue;
123 /** Special flags for the opcode. */
124 uint32_t fFlags;
125 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
126 PCDISARMV8INSNPARAM paDecode;
127 /** The generic opcode structure. */
128 DISOPCODE Opc;
129} DISARMV8OPCODE;
130/** Pointer to a const opcode. */
131typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
132
133
134/**
135 * Opcode decode index.
136 */
137typedef enum DISARMV8OPCDECODE
138{
139 kDisArmV8OpcDecodeNop = 0,
140 kDisArmV8OpcDecodeLookup,
141 kDisArmV8OpcDecodeCollate,
142 kDisArmV8OpcDecodeMax
143} DISARMV8OPCDECODE;
144
145
146/**
147 * Decoder stage type.
148 */
149typedef enum kDisArmV8DecodeType
150{
151 kDisArmV8DecodeType_Invalid = 0,
152 kDisArmV8DecodeType_Map,
153 kDisArmV8DecodeType_Table,
154 kDisArmV8DecodeType_InsnClass,
155 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
156} kDisArmV8DecodeType;
157
158
159/**
160 * Decode header.
161 */
162typedef struct DISARMV8DECODEHDR
163{
164 /** Next stage decoding type. */
165 kDisArmV8DecodeType enmDecodeType;
166 /** Number of entries in the next decoder stage or
167 * opcodes in the instruction class. */
168 uint32_t cDecode;
169} DISARMV8DECODEHDR;
170/** Pointer to a decode header. */
171typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
172/** Pointer to a const decode header. */
173typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
174typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
175
176
177/**
178 * Instruction class descriptor.
179 */
180typedef struct DISARMV8INSNCLASS
181{
182 /** Decoder header. */
183 DISARMV8DECODEHDR Hdr;
184 /** Pointer to the arry of opcodes. */
185 PCDISARMV8OPCODE paOpcodes;
186 /** The mask of fixed instruction bits. */
187 uint32_t fFixedInsn;
188 /** Opcode decoder function. */
189 DISARMV8OPCDECODE enmOpcDecode;
190 /** The mask of the bits relevant for decoding. */
191 uint32_t fMask;
192 /** Number of bits to shift to get an index. */
193 uint32_t cShift;
194 /** Parameter types. */
195 DISARMV8OPPARM aenmParamTypes[4];
196 /** The array of decoding steps. */
197 PCDISARMV8INSNPARAM paParms;
198} DISARMV8INSNCLASS;
199/** Pointer to a constant instruction class descriptor. */
200typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
201
202/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
203#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
204/** The instruction class is using the 64-bit register encoding only. */
205#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
206/** The instruction class is using the 32-bit register encoding only. */
207#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
208
209
210#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
211 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
212#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
213 DIS_ARMV8_INSN_DECODE_TERM \
214 }; \
215 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
216#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
217 DIS_ARMV8_INSN_DECODE_TERM \
218 }; \
219 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
220#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
221 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \
222 }; \
223 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
224 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
225 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
226 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
227 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \
228 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
229#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
230 a_enmParamType1, a_enmParamType2, a_enmParamType3) \
231 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
232 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone)
233#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
234 a_enmParamType1, a_enmParamType2) \
235 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
236 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone)
237#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
238 a_enmParamType1) \
239 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
240 a_enmParamType1, kDisArmv8OpParmNone)
241#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
242 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
243 kDisArmv8OpParmNone)
244
245
246#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \
247 DIS_ARMV8_INSN_PARAM_NONE }
248
249/**
250 * Decoder lookup table entry.
251 */
252typedef struct DISARMV8DECODETBLENTRY
253{
254 /** The mask to apply to the instruction. */
255 uint32_t fMask;
256 /** The value the masked instruction must match for the entry to match. */
257 uint32_t fValue;
258 /** The next stage followed when there is a match. */
259 PCDISARMV8DECODEHDR pHdrNext;
260} DISARMV8DECODETBLENTRY;
261typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
262typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
263
264
265#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
266 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
267
268
269/**
270 * Decoder lookup table using masks and values.
271 */
272typedef struct DISARMV8DECODETBL
273{
274 /** The header for the decoder lookup table. */
275 DISARMV8DECODEHDR Hdr;
276 /** Pointer to the individual entries. */
277 PCDISARMV8DECODETBLENTRY paEntries;
278} DISARMV8DECODETBL;
279/** Pointer to a const decode table. */
280typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
281
282
283#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
284 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
285
286#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
287 }; \
288 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
289 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
290
291
292/**
293 * Decoder map when direct indexing is possible.
294 */
295typedef struct DISARMV8DECODEMAP
296{
297 /** The header for the decoder map. */
298 DISARMV8DECODEHDR Hdr;
299 /** The bitmask used to decide where to go next. */
300 uint32_t fMask;
301 /** Amount to shift to get at the index. */
302 uint32_t cShift;
303 /** Pointer to the array of pointers to the next stage to index into. */
304 PPCDISARMV8DECODEHDR papNext;
305} DISARMV8DECODEMAP;
306/** Pointer to a const decode map. */
307typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
308
309#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
310 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
311
312#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
313 }; \
314 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
315 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
316
317#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
318 }; \
319 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
320 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
321
322
323#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
324 }; \
325 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
326 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
327
328#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
329#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
330
331
332/** @name Decoder maps.
333 * @{ */
334extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
335
336extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
337/** @} */
338
339
340/** @} */
341#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
342
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