VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106746

Last change on this file since 106746 was 106746, checked in by vboxsync, 3 months ago

Disassembler: Decode SIMD ldr/str instructions, bugref:10394
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File size: 10.7 KB
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1/* $Id: DisasmInternal-armv8.h 106746 2024-10-28 13:14:22Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseAddrGprSp,
64 kDisParmParseRegFixed31,
65 kDisParmParseImmsImmrN,
66 kDisParmParseHw,
67 kDisParmParseCond,
68 kDisParmParsePState,
69 kDisParmParseCRnCRm,
70 kDisParmParseSysReg,
71 kDisParmParseSh12,
72 kDisParmParseImmTbz,
73 kDisParmParseShift,
74 kDisParmParseShiftAmount,
75 kDisParmParseImmMemOff,
76 kDisParmParseSImmMemOff,
77 kDisParmParseSImmMemOffUnscaled,
78 kDisParmParseOption,
79 kDisParmParseS,
80 kDisParmParseSetPreIndexed,
81 kDisParmParseSetPostIndexed,
82 kDisParmParseFpType,
83 kDisParmParseFpReg,
84 kDisParmParseFpScale,
85 kDisParmParseFpFixupFCvt,
86 kDisParmParseSimdRegSize,
87 kDisParmParseSimdRegSize64,
88 kDisParmParseSimdRegSize128,
89 kDisParmParseSimdRegScalar,
90 kDisParmParseImmHImmB,
91 kDisParmParseSf,
92 kDisParmParseImmX16,
93 kDisParmParseMax
94} DISPARMPARSEIDX;
95/** @} */
96
97
98/**
99 * Decoder step.
100 */
101typedef struct DISARMV8INSNPARAM
102{
103 /** The parser to use for the decode step. */
104 DISPARMPARSEIDX idxParse;
105 /** Bit index at which the field starts. */
106 uint8_t idxBitStart;
107 /** Size of the bit field. */
108 uint8_t cBits;
109 /** The parameter this decoder param contributes to. */
110 uint8_t idxParam;
111} DISARMV8INSNPARAM;
112typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
113typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
114
115#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
116#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
117 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
118
119#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
120
121
122/**
123 * Opcode structure.
124 */
125typedef struct DISARMV8OPCODE
126{
127 /** The value of the fixed bits of the instruction. */
128 uint32_t fValue;
129 /** Special flags for the opcode. */
130 uint32_t fFlags;
131 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
132 PCDISARMV8INSNPARAM paDecode;
133 /** The generic opcode structure. */
134 DISOPCODE Opc;
135} DISARMV8OPCODE;
136/** Pointer to a const opcode. */
137typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
138
139
140/**
141 * Opcode decode index.
142 */
143typedef enum DISARMV8OPCDECODE
144{
145 kDisArmV8OpcDecodeNop = 0,
146 kDisArmV8OpcDecodeLookup,
147 kDisArmV8OpcDecodeCollate,
148 kDisArmV8OpcDecodeMax
149} DISARMV8OPCDECODE;
150
151
152/**
153 * Decoder stage type.
154 */
155typedef enum kDisArmV8DecodeType
156{
157 kDisArmV8DecodeType_Invalid = 0,
158 kDisArmV8DecodeType_Map,
159 kDisArmV8DecodeType_Table,
160 kDisArmV8DecodeType_InsnClass,
161 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
162} kDisArmV8DecodeType;
163
164
165/**
166 * Decode header.
167 */
168typedef struct DISARMV8DECODEHDR
169{
170 /** Next stage decoding type. */
171 kDisArmV8DecodeType enmDecodeType;
172 /** Number of entries in the next decoder stage or
173 * opcodes in the instruction class. */
174 uint32_t cDecode;
175} DISARMV8DECODEHDR;
176/** Pointer to a decode header. */
177typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
178/** Pointer to a const decode header. */
179typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
180typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
181
182
183/**
184 * Instruction class descriptor.
185 */
186typedef struct DISARMV8INSNCLASS
187{
188 /** Decoder header. */
189 DISARMV8DECODEHDR Hdr;
190 /** Pointer to the arry of opcodes. */
191 PCDISARMV8OPCODE paOpcodes;
192 /** The mask of fixed instruction bits. */
193 uint32_t fFixedInsn;
194 /** Opcode decoder function. */
195 DISARMV8OPCDECODE enmOpcDecode;
196 /** The mask of the bits relevant for decoding. */
197 uint32_t fMask;
198 /** Number of bits to shift to get an index. */
199 uint32_t cShift;
200 /** The array of decoding steps. */
201 PCDISARMV8INSNPARAM paParms;
202} DISARMV8INSNCLASS;
203/** Pointer to a constant instruction class descriptor. */
204typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
205
206/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
207#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
208/** The instruction class is using the 64-bit register encoding only. */
209#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
210/** The instruction class is using the 32-bit register encoding only. */
211#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
212
213
214#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
215 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
216#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
217 DIS_ARMV8_INSN_DECODE_TERM \
218 }; \
219 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
220#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
221 DIS_ARMV8_INSN_DECODE_TERM \
222 }; \
223 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
224#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
225 }; \
226 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
227 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
228 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
229 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
230 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
231
232/**
233 * Decoder lookup table entry.
234 */
235typedef struct DISARMV8DECODETBLENTRY
236{
237 /** The mask to apply to the instruction. */
238 uint32_t fMask;
239 /** The value the masked instruction must match for the entry to match. */
240 uint32_t fValue;
241 /** The next stage followed when there is a match. */
242 PCDISARMV8DECODEHDR pHdrNext;
243} DISARMV8DECODETBLENTRY;
244typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
245typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
246
247
248#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
249 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
250
251
252/**
253 * Decoder lookup table using masks and values.
254 */
255typedef struct DISARMV8DECODETBL
256{
257 /** The header for the decoder lookup table. */
258 DISARMV8DECODEHDR Hdr;
259 /** Pointer to the individual entries. */
260 PCDISARMV8DECODETBLENTRY paEntries;
261} DISARMV8DECODETBL;
262/** Pointer to a const decode table. */
263typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
264
265
266#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
267 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
268
269#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
270 }; \
271 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
272 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
273
274
275/**
276 * Decoder map when direct indexing is possible.
277 */
278typedef struct DISARMV8DECODEMAP
279{
280 /** The header for the decoder map. */
281 DISARMV8DECODEHDR Hdr;
282 /** The bitmask used to decide where to go next. */
283 uint32_t fMask;
284 /** Amount to shift to get at the index. */
285 uint32_t cShift;
286 /** Pointer to the array of pointers to the next stage to index into. */
287 PPCDISARMV8DECODEHDR papNext;
288} DISARMV8DECODEMAP;
289/** Pointer to a const decode map. */
290typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
291
292#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
293 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
294
295#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
296 }; \
297 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
298 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
299
300#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
301 }; \
302 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
303 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
304
305
306#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
307 }; \
308 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
309 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
310
311#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
312#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
313
314
315/** @name Decoder maps.
316 * @{ */
317extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
318
319extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
320/** @} */
321
322
323/** @} */
324#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
325
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