VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106758

Last change on this file since 106758 was 106758, checked in by vboxsync, 3 months ago

Disassembler: Decode ldraa/ldrab instructions, bugref:10394
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 10.8 KB
Line 
1/* $Id: DisasmInternal-armv8.h 106758 2024-10-28 15:54:21Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseAddrGprSp,
64 kDisParmParseRegFixed31,
65 kDisParmParseImmsImmrN,
66 kDisParmParseHw,
67 kDisParmParseCond,
68 kDisParmParsePState,
69 kDisParmParseCRnCRm,
70 kDisParmParseSysReg,
71 kDisParmParseSh12,
72 kDisParmParseImmTbz,
73 kDisParmParseShift,
74 kDisParmParseShiftAmount,
75 kDisParmParseImmMemOff,
76 kDisParmParseSImmMemOff,
77 kDisParmParseSImmMemOffUnscaled,
78 kDisParmParseOption,
79 kDisParmParseS,
80 kDisParmParseSetPreIndexed,
81 kDisParmParseSetPostIndexed,
82 kDisParmParseFpType,
83 kDisParmParseFpReg,
84 kDisParmParseFpScale,
85 kDisParmParseFpFixupFCvt,
86 kDisParmParseSimdRegSize,
87 kDisParmParseSimdRegSize32,
88 kDisParmParseSimdRegSize64,
89 kDisParmParseSimdRegSize128,
90 kDisParmParseSimdRegScalar,
91 kDisParmParseImmHImmB,
92 kDisParmParseSf,
93 kDisParmParseImmX16,
94 kDisParmParseLdrPacImm,
95 kDisParmParseLdrPacW,
96 kDisParmParseMax
97} DISPARMPARSEIDX;
98/** @} */
99
100
101/**
102 * Decoder step.
103 */
104typedef struct DISARMV8INSNPARAM
105{
106 /** The parser to use for the decode step. */
107 DISPARMPARSEIDX idxParse;
108 /** Bit index at which the field starts. */
109 uint8_t idxBitStart;
110 /** Size of the bit field. */
111 uint8_t cBits;
112 /** The parameter this decoder param contributes to. */
113 uint8_t idxParam;
114} DISARMV8INSNPARAM;
115typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
116typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
117
118#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
119#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
120 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
121
122#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
123
124
125/**
126 * Opcode structure.
127 */
128typedef struct DISARMV8OPCODE
129{
130 /** The value of the fixed bits of the instruction. */
131 uint32_t fValue;
132 /** Special flags for the opcode. */
133 uint32_t fFlags;
134 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
135 PCDISARMV8INSNPARAM paDecode;
136 /** The generic opcode structure. */
137 DISOPCODE Opc;
138} DISARMV8OPCODE;
139/** Pointer to a const opcode. */
140typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
141
142
143/**
144 * Opcode decode index.
145 */
146typedef enum DISARMV8OPCDECODE
147{
148 kDisArmV8OpcDecodeNop = 0,
149 kDisArmV8OpcDecodeLookup,
150 kDisArmV8OpcDecodeCollate,
151 kDisArmV8OpcDecodeMax
152} DISARMV8OPCDECODE;
153
154
155/**
156 * Decoder stage type.
157 */
158typedef enum kDisArmV8DecodeType
159{
160 kDisArmV8DecodeType_Invalid = 0,
161 kDisArmV8DecodeType_Map,
162 kDisArmV8DecodeType_Table,
163 kDisArmV8DecodeType_InsnClass,
164 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
165} kDisArmV8DecodeType;
166
167
168/**
169 * Decode header.
170 */
171typedef struct DISARMV8DECODEHDR
172{
173 /** Next stage decoding type. */
174 kDisArmV8DecodeType enmDecodeType;
175 /** Number of entries in the next decoder stage or
176 * opcodes in the instruction class. */
177 uint32_t cDecode;
178} DISARMV8DECODEHDR;
179/** Pointer to a decode header. */
180typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
181/** Pointer to a const decode header. */
182typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
183typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
184
185
186/**
187 * Instruction class descriptor.
188 */
189typedef struct DISARMV8INSNCLASS
190{
191 /** Decoder header. */
192 DISARMV8DECODEHDR Hdr;
193 /** Pointer to the arry of opcodes. */
194 PCDISARMV8OPCODE paOpcodes;
195 /** The mask of fixed instruction bits. */
196 uint32_t fFixedInsn;
197 /** Opcode decoder function. */
198 DISARMV8OPCDECODE enmOpcDecode;
199 /** The mask of the bits relevant for decoding. */
200 uint32_t fMask;
201 /** Number of bits to shift to get an index. */
202 uint32_t cShift;
203 /** The array of decoding steps. */
204 PCDISARMV8INSNPARAM paParms;
205} DISARMV8INSNCLASS;
206/** Pointer to a constant instruction class descriptor. */
207typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
208
209/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
210#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
211/** The instruction class is using the 64-bit register encoding only. */
212#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
213/** The instruction class is using the 32-bit register encoding only. */
214#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
215
216
217#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
218 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
219#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
220 DIS_ARMV8_INSN_DECODE_TERM \
221 }; \
222 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
223#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
224 DIS_ARMV8_INSN_DECODE_TERM \
225 }; \
226 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
227#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
228 }; \
229 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
230 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
231 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
232 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
233 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
234
235/**
236 * Decoder lookup table entry.
237 */
238typedef struct DISARMV8DECODETBLENTRY
239{
240 /** The mask to apply to the instruction. */
241 uint32_t fMask;
242 /** The value the masked instruction must match for the entry to match. */
243 uint32_t fValue;
244 /** The next stage followed when there is a match. */
245 PCDISARMV8DECODEHDR pHdrNext;
246} DISARMV8DECODETBLENTRY;
247typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
248typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
249
250
251#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
252 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
253
254
255/**
256 * Decoder lookup table using masks and values.
257 */
258typedef struct DISARMV8DECODETBL
259{
260 /** The header for the decoder lookup table. */
261 DISARMV8DECODEHDR Hdr;
262 /** Pointer to the individual entries. */
263 PCDISARMV8DECODETBLENTRY paEntries;
264} DISARMV8DECODETBL;
265/** Pointer to a const decode table. */
266typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
267
268
269#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
270 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
271
272#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
273 }; \
274 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
275 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
276
277
278/**
279 * Decoder map when direct indexing is possible.
280 */
281typedef struct DISARMV8DECODEMAP
282{
283 /** The header for the decoder map. */
284 DISARMV8DECODEHDR Hdr;
285 /** The bitmask used to decide where to go next. */
286 uint32_t fMask;
287 /** Amount to shift to get at the index. */
288 uint32_t cShift;
289 /** Pointer to the array of pointers to the next stage to index into. */
290 PPCDISARMV8DECODEHDR papNext;
291} DISARMV8DECODEMAP;
292/** Pointer to a const decode map. */
293typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
294
295#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
296 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
297
298#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
299 }; \
300 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
301 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
302
303#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
304 }; \
305 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
306 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
307
308
309#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
310 }; \
311 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
312 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
313
314#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
315#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
316
317
318/** @name Decoder maps.
319 * @{ */
320extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
321
322extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
323/** @} */
324
325
326/** @} */
327#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
328
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette