VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 99332

Last change on this file since 99332 was 99320, checked in by vboxsync, 20 months ago

Disassember: Continue work on the ARMv8 disassember, defining the instruction table layout and intermediate structures for decoding, bugref:10394 [scm fix]

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 7.5 KB
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1/* $Id: DisasmInternal-armv8.h 99320 2023-04-06 19:32:20Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseImm,
54 kDisParmParseImmRel,
55 kDisParmParseImmAdr,
56 kDisParmParseReg,
57 kDisParmParseImmsImmrN,
58 kDisParmParseHw,
59 kDisParmParseCond,
60 kDisParmParseMax
61} DISPARMPARSEIDX;
62/** @} */
63
64
65typedef struct DISARMV8INSNPARAM
66{
67 /** The parser to use for the parameter. */
68 DISPARMPARSEIDX idxParse;
69 /** Bit index at which the field starts. */
70 uint8_t idxBitStart;
71 /** Size of the bit field. */
72 uint8_t cBits;
73} DISARMV8INSNPARAM;
74typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
75typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
76
77#define DIS_ARMV8_INSN_PARAM_NONE { kDisParmParseNop, 0, 0 }
78#define DIS_ARMV8_INSN_PARAM_CREATE(a_idxParse, a_idxBitStart, a_cBits) \
79 { a_idxParse, a_idxBitStart, a_cBits }
80
81
82/**
83 * Opcode decode index.
84 */
85typedef enum DISARMV8OPCDECODE
86{
87 kDisArmV8OpcDecodeNop = 0,
88 kDisArmV8OpcDecodeMax
89} DISARMV8OPCDECODE;
90
91
92/**
93 * Decoder stage type.
94 */
95typedef enum kDisArmV8DecodeType
96{
97 kDisArmV8DecodeType_Invalid = 0,
98 kDisArmV8DecodeType_Map,
99 kDisArmV8DecodeType_Table,
100 kDisArmV8DecodeType_InsnClass,
101 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
102} kDisArmV8DecodeType;
103
104
105/**
106 * Decode header.
107 */
108typedef struct DISARMV8DECODEHDR
109{
110 /** Next stage decoding type. */
111 kDisArmV8DecodeType enmDecodeType;
112 /** Number of entries in the next decoder stage or
113 * opcodes in the instruction class. */
114 uint32_t cDecode;
115} DISARMV8DECODEHDR;
116/** Pointer to a decode header. */
117typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
118/** Pointer to a const decode header. */
119typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
120typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
121
122
123/**
124 * Instruction class descriptor.
125 */
126typedef struct DISARMV8INSNCLASS
127{
128 /** Decoder header. */
129 DISARMV8DECODEHDR Hdr;
130 /** Pointer to the arry of opcodes. */
131 PCDISOPCODE paOpcodes;
132 /** Some flags for this instruction class. */
133 uint32_t fClass;
134 /** Opcode decoder function. */
135 DISARMV8OPCDECODE enmOpcDecode;
136 /** The mask of the bits relevant for decoding. */
137 uint32_t fMask;
138 /** Number of bits to shift to get an index. */
139 uint32_t cShift;
140 /** The parameters. */
141 DISARMV8INSNPARAM aParms[4];
142} DISARMV8INSNCLASS;
143/** Pointer to a constant instruction class descriptor. */
144typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
145
146/** The instruction class distinguishes between a 32-bit and 64-bit variant using the sf bit (bit 31). */
147#define DISARMV8INSNCLASS_F_SF RT_BIT_32(0)
148/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
149#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
150/** The instruction class is using the 64-bit register encoding only. */
151#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
152
153
154#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
155 static const DISOPCODE a_Name ## Opcodes[] = {
156#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \
157 }; \
158 static const DISARMV8INSNCLASS a_Name = { { kDisArmV8DecodeType_InsnClass, RT_ELEMENTS(a_Name ## Opcodes) }, &a_Name ## Opcodes[0],\
159 a_fClass, a_enmOpcDecode, a_fMask, a_cShift, {
160#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END } }
161
162/**
163 * Decoder lookup table entry.
164 */
165typedef struct DISARMV8DECODETBLENTRY
166{
167 /** The mask to apply to the instruction. */
168 uint32_t fMask;
169 /** The value the masked instruction must match for the entry to match. */
170 uint32_t fValue;
171 /** The next stage followed when there is a match. */
172 PCDISARMV8DECODEHDR pHdrNext;
173} DISARMV8DECODETBLENTRY;
174typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
175typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
176
177
178#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
179 { a_fMask, a_fValue, &a_pNext.Hdr }
180
181
182/**
183 * Decoder lookup table using masks and values.
184 */
185typedef struct DISARMV8DECODETBL
186{
187 /** The header for the decoder lookup table. */
188 DISARMV8DECODEHDR Hdr;
189 /** Pointer to the individual entries. */
190 PCDISARMV8DECODETBLENTRY paEntries;
191} DISARMV8DECODETBL;
192/** Pointer to a const decode table. */
193typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
194
195
196#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
197 static const DISARMV8DECODETBLENTRY a_Name ## TblEnt[] = {
198
199#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
200 }; \
201 static const DISARMV8DECODETBL a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(a_Name ## TblEnt) }, &a_Name ## TblEnt[0] }
202
203
204/**
205 * Decoder map when direct indexing is possible.
206 */
207typedef struct DISARMV8DECODEMAP
208{
209 /** The header for the decoder map. */
210 DISARMV8DECODEHDR Hdr;
211 /** The bitmask used to decide where to go next. */
212 uint32_t fMask;
213 /** Amount to shift to get at the index. */
214 uint32_t cShift;
215 /** Pointer to the array of pointers to the next stage to index into. */
216 PPCDISARMV8DECODEHDR papNext;
217} DISARMV8DECODEMAP;
218/** Pointer to a const decode map. */
219typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
220
221#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
222 static const PCDISARMV8DECODEHDR a_Name ## MapHdrs[] = {
223
224#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
225 }; \
226 static const DISARMV8DECODEMAP a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(a_Name ## MapHdrs) }, a_fMask, a_cShift, &a_Name ## MapHdrs[0] }
227
228#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
229 }; \
230 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(a_Name ## MapHdrs) }, a_fMask, a_cShift, &a_Name ## MapHdrs[0] }
231
232#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
233#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) &a_Next.Hdr
234
235
236/** @name Decoder maps.
237 * @{ */
238extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
239
240extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_ArmV8A64DecodeL0;
241/** @} */
242
243
244/** @} */
245#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
246
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