VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 41675

Last change on this file since 41675 was 41675, checked in by vboxsync, 12 years ago

DIS: The start of the scoping exercise... Fixed PREFIX_ADDRSIZE that I just busted in the previous commit.
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  • Property svn:keywords set to Id Revision
  • Property svn:sync_process set to export
File size: 28.6 KB
Line 
1/* $Id: DisasmReg.cpp 41675 2012-06-12 20:27:37Z vboxsync $ */
2/** @file
3 * VBox disassembler- Register Info Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_DIS
23#include <VBox/dis.h>
24#include <VBox/disopcode.h>
25#include <VBox/err.h>
26#include <VBox/log.h>
27#include <VBox/vmm/cpum.h>
28#include <iprt/assert.h>
29#include <iprt/string.h>
30#include <iprt/stdarg.h>
31#include "DisasmInternal.h"
32#include "DisasmTables.h"
33
34
35/*******************************************************************************
36* Global Variables *
37*******************************************************************************/
38
39/**
40 * Array for accessing 64-bit general registers in VMMREGFRAME structure
41 * by register's index from disasm.
42 */
43static const unsigned g_aReg64Index[] =
44{
45 RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
46 RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
47 RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
48 RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
49 RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
50 RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
51 RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
52 RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
53 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
54 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
55 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
56 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
57 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
58 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
59 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
60 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
61};
62
63/**
64 * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
65 */
66#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
67#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
68#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
69
70/**
71 * Array for accessing 32-bit general registers in VMMREGFRAME structure
72 * by register's index from disasm.
73 */
74static const unsigned g_aReg32Index[] =
75{
76 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
77 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
78 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
79 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
80 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
81 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
82 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
83 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_EDI */
84 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8D */
85 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9D */
86 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10D */
87 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11D */
88 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12D */
89 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13D */
90 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14D */
91 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15D */
92};
93
94/**
95 * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
96 */
97#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
98/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
99 * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
100 * values also set the upper 32 bits of the register to zero. Consequently
101 * there is no need for an instruction movzlq.''
102 */
103#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
104#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
105
106/**
107 * Array for accessing 16-bit general registers in CPUMCTXCORE structure
108 * by register's index from disasm.
109 */
110static const unsigned g_aReg16Index[] =
111{
112 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
113 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
114 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
115 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
116 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
117 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
118 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
119 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_DI */
120 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8W */
121 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9W */
122 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10W */
123 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11W */
124 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12W */
125 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13W */
126 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14W */
127 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15W */
128};
129
130/**
131 * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
132 */
133#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
134#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
135#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
136
137/**
138 * Array for accessing 8-bit general registers in CPUMCTXCORE structure
139 * by register's index from disasm.
140 */
141static const unsigned g_aReg8Index[] =
142{
143 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
144 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
145 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
146 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
147 RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* USE_REG_AH */
148 RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* USE_REG_CH */
149 RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* USE_REG_DH */
150 RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* USE_REG_BH */
151 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8B */
152 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9B */
153 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10B*/
154 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11B */
155 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12B */
156 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13B */
157 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14B */
158 RT_OFFSETOF(CPUMCTXCORE, r15), /* USE_REG_R15B */
159 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SPL; with REX prefix only */
160 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BPL; with REX prefix only */
161 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SIL; with REX prefix only */
162 RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DIL; with REX prefix only */
163};
164
165/**
166 * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
167 */
168#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
169#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
170#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
171
172/**
173 * Array for accessing segment registers in CPUMCTXCORE structure
174 * by register's index from disasm.
175 */
176static const unsigned g_aRegSegIndex[] =
177{
178 RT_OFFSETOF(CPUMCTXCORE, es), /* DIS_SELREG_ES */
179 RT_OFFSETOF(CPUMCTXCORE, cs), /* DIS_SELREG_CS */
180 RT_OFFSETOF(CPUMCTXCORE, ss), /* DIS_SELREG_SS */
181 RT_OFFSETOF(CPUMCTXCORE, ds), /* DIS_SELREG_DS */
182 RT_OFFSETOF(CPUMCTXCORE, fs), /* DIS_SELREG_FS */
183 RT_OFFSETOF(CPUMCTXCORE, gs) /* DIS_SELREG_GS */
184};
185
186static const unsigned g_aRegHidSegIndex[] =
187{
188 RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */
189 RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */
190 RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */
191 RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */
192 RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */
193 RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */
194};
195
196/**
197 * Macro for accessing segment registers in CPUMCTXCORE structure.
198 */
199#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
200#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
201
202//*****************************************************************************
203//*****************************************************************************
204DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
205{
206 int subtype = OP_PARM_VSUBTYPE(pParam->param);
207
208 if (subtype == OP_PARM_v)
209 {
210 switch(pCpu->opmode)
211 {
212 case DISCPUMODE_32BIT:
213 subtype = OP_PARM_d;
214 break;
215 case DISCPUMODE_64BIT:
216 subtype = OP_PARM_q;
217 break;
218 case DISCPUMODE_16BIT:
219 subtype = OP_PARM_w;
220 break;
221 default:
222 /* make gcc happy */
223 break;
224 }
225 }
226
227 switch(subtype)
228 {
229 case OP_PARM_b:
230 return 1;
231
232 case OP_PARM_w:
233 return 2;
234
235 case OP_PARM_d:
236 return 4;
237
238 case OP_PARM_q:
239 case OP_PARM_dq:
240 return 8;
241
242 case OP_PARM_p: /* far pointer */
243 if (pCpu->addrmode == DISCPUMODE_32BIT)
244 return 6; /* 16:32 */
245 else
246 if (pCpu->addrmode == DISCPUMODE_64BIT)
247 return 12; /* 16:64 */
248 else
249 return 4; /* 16:16 */
250
251 default:
252 if (pParam->cb)
253 return pParam->cb;
254 else //@todo dangerous!!!
255 return 4;
256 }
257}
258//*****************************************************************************
259//*****************************************************************************
260DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
261{
262 if (pCpu->prefix & DISPREFIX_SEG)
263 {
264 /* Use specified SEG: prefix. */
265 return pCpu->enmPrefixSeg;
266 }
267 else
268 {
269 /* Guess segment register by parameter type. */
270 if (pParam->flags & (USE_REG_GEN32|USE_REG_GEN64|USE_REG_GEN16))
271 {
272 AssertCompile(USE_REG_ESP == USE_REG_RSP);
273 AssertCompile(USE_REG_EBP == USE_REG_RBP);
274 AssertCompile(USE_REG_ESP == USE_REG_SP);
275 AssertCompile(USE_REG_EBP == USE_REG_BP);
276 if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
277 return DIS_SELREG_SS;
278 }
279 /* Default is use DS: for data access. */
280 return DIS_SELREG_DS;
281 }
282}
283//*****************************************************************************
284//*****************************************************************************
285DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
286{
287 Assert(pCpu->prefix & DISPREFIX_SEG);
288 switch(pCpu->enmPrefixSeg)
289 {
290 case DIS_SELREG_ES:
291 return 0x26;
292 case DIS_SELREG_CS:
293 return 0x2E;
294 case DIS_SELREG_SS:
295 return 0x36;
296 case DIS_SELREG_DS:
297 return 0x3E;
298 case DIS_SELREG_FS:
299 return 0x64;
300 case DIS_SELREG_GS:
301 return 0x65;
302 default:
303 AssertFailed();
304 return 0;
305 }
306}
307
308
309/**
310 * Returns the value of the specified 8 bits general purpose register
311 *
312 */
313DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
314{
315 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
316
317 *pVal = DIS_READ_REG8(pCtx, reg8);
318 return VINF_SUCCESS;
319}
320
321/**
322 * Returns the value of the specified 16 bits general purpose register
323 *
324 */
325DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
326{
327 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
328
329 *pVal = DIS_READ_REG16(pCtx, reg16);
330 return VINF_SUCCESS;
331}
332
333/**
334 * Returns the value of the specified 32 bits general purpose register
335 *
336 */
337DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
338{
339 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
340
341 *pVal = DIS_READ_REG32(pCtx, reg32);
342 return VINF_SUCCESS;
343}
344
345/**
346 * Returns the value of the specified 64 bits general purpose register
347 *
348 */
349DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
350{
351 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
352
353 *pVal = DIS_READ_REG64(pCtx, reg64);
354 return VINF_SUCCESS;
355}
356
357/**
358 * Returns the pointer to the specified 8 bits general purpose register
359 *
360 */
361DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
362{
363 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
364
365 *ppReg = DIS_PTR_REG8(pCtx, reg8);
366 return VINF_SUCCESS;
367}
368
369/**
370 * Returns the pointer to the specified 16 bits general purpose register
371 *
372 */
373DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
374{
375 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
376
377 *ppReg = DIS_PTR_REG16(pCtx, reg16);
378 return VINF_SUCCESS;
379}
380
381/**
382 * Returns the pointer to the specified 32 bits general purpose register
383 *
384 */
385DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
386{
387 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
388
389 *ppReg = DIS_PTR_REG32(pCtx, reg32);
390 return VINF_SUCCESS;
391}
392
393/**
394 * Returns the pointer to the specified 64 bits general purpose register
395 *
396 */
397DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
398{
399 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
400
401 *ppReg = DIS_PTR_REG64(pCtx, reg64);
402 return VINF_SUCCESS;
403}
404
405/**
406 * Returns the value of the specified segment register
407 *
408 */
409DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal)
410{
411 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
412
413 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
414 *pVal = DIS_READ_REGSEG(pCtx, sel);
415 return VINF_SUCCESS;
416}
417
418/**
419 * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
420 *
421 */
422DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
423{
424 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
425
426 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
427 *pVal = DIS_READ_REGSEG(pCtx, sel);
428 *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
429 return VINF_SUCCESS;
430}
431
432/**
433 * Updates the value of the specified 64 bits general purpose register
434 *
435 */
436DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
437{
438 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
439
440 DIS_WRITE_REG64(pRegFrame, reg64, val64);
441 return VINF_SUCCESS;
442}
443
444/**
445 * Updates the value of the specified 32 bits general purpose register
446 *
447 */
448DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
449{
450 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
451
452 DIS_WRITE_REG32(pRegFrame, reg32, val32);
453 return VINF_SUCCESS;
454}
455
456/**
457 * Updates the value of the specified 16 bits general purpose register
458 *
459 */
460DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
461{
462 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
463
464 DIS_WRITE_REG16(pRegFrame, reg16, val16);
465 return VINF_SUCCESS;
466}
467
468/**
469 * Updates the specified 8 bits general purpose register
470 *
471 */
472DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
473{
474 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
475
476 DIS_WRITE_REG8(pRegFrame, reg8, val8);
477 return VINF_SUCCESS;
478}
479
480/**
481 * Updates the specified segment register
482 *
483 */
484DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val)
485{
486 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
487
488 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
489 DIS_WRITE_REGSEG(pCtx, sel, val);
490 return VINF_SUCCESS;
491}
492
493/**
494 * Returns the value of the parameter in pParam
495 *
496 * @returns VBox error code
497 * @param pCtx CPU context structure pointer
498 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
499 * set correctly.
500 * @param pParam Pointer to the parameter to parse
501 * @param pParamVal Pointer to parameter value (OUT)
502 * @param parmtype Parameter type
503 *
504 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
505 *
506 */
507DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
508{
509 memset(pParamVal, 0, sizeof(*pParamVal));
510
511 if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
512 {
513 // Effective address
514 pParamVal->type = PARMTYPE_ADDRESS;
515 pParamVal->size = pParam->cb;
516
517 if (pParam->flags & USE_BASE)
518 {
519 if (pParam->flags & USE_REG_GEN8)
520 {
521 pParamVal->flags |= PARAM_VAL8;
522 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
523 }
524 else
525 if (pParam->flags & USE_REG_GEN16)
526 {
527 pParamVal->flags |= PARAM_VAL16;
528 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
529 }
530 else
531 if (pParam->flags & USE_REG_GEN32)
532 {
533 pParamVal->flags |= PARAM_VAL32;
534 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
535 }
536 else
537 if (pParam->flags & USE_REG_GEN64)
538 {
539 pParamVal->flags |= PARAM_VAL64;
540 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
541 }
542 else
543 {
544 AssertFailed();
545 return VERR_INVALID_PARAMETER;
546 }
547 }
548 // Note that scale implies index (SIB byte)
549 if (pParam->flags & USE_INDEX)
550 {
551 if (pParam->flags & USE_REG_GEN16)
552 {
553 uint16_t val16;
554
555 pParamVal->flags |= PARAM_VAL16;
556 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
557
558 Assert(!(pParam->flags & USE_SCALE)); /* shouldn't be possible in 16 bits mode */
559
560 pParamVal->val.val16 += val16;
561 }
562 else
563 if (pParam->flags & USE_REG_GEN32)
564 {
565 uint32_t val32;
566
567 pParamVal->flags |= PARAM_VAL32;
568 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
569
570 if (pParam->flags & USE_SCALE)
571 val32 *= pParam->scale;
572
573 pParamVal->val.val32 += val32;
574 }
575 else
576 if (pParam->flags & USE_REG_GEN64)
577 {
578 uint64_t val64;
579
580 pParamVal->flags |= PARAM_VAL64;
581 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
582
583 if (pParam->flags & USE_SCALE)
584 val64 *= pParam->scale;
585
586 pParamVal->val.val64 += val64;
587 }
588 else
589 AssertFailed();
590 }
591
592 if (pParam->flags & USE_DISPLACEMENT8)
593 {
594 if (pCpu->mode == DISCPUMODE_32BIT)
595 pParamVal->val.val32 += (int32_t)pParam->uDisp.i8;
596 else
597 if (pCpu->mode == DISCPUMODE_64BIT)
598 pParamVal->val.val64 += (int64_t)pParam->uDisp.i8;
599 else
600 pParamVal->val.val16 += (int16_t)pParam->uDisp.i8;
601 }
602 else
603 if (pParam->flags & USE_DISPLACEMENT16)
604 {
605 if (pCpu->mode == DISCPUMODE_32BIT)
606 pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
607 else
608 if (pCpu->mode == DISCPUMODE_64BIT)
609 pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
610 else
611 pParamVal->val.val16 += pParam->uDisp.i16;
612 }
613 else
614 if (pParam->flags & USE_DISPLACEMENT32)
615 {
616 if (pCpu->mode == DISCPUMODE_32BIT)
617 pParamVal->val.val32 += pParam->uDisp.i32;
618 else
619 pParamVal->val.val64 += pParam->uDisp.i32;
620 }
621 else
622 if (pParam->flags & USE_DISPLACEMENT64)
623 {
624 Assert(pCpu->mode == DISCPUMODE_64BIT);
625 pParamVal->val.val64 += pParam->uDisp.i64;
626 }
627 else
628 if (pParam->flags & USE_RIPDISPLACEMENT32)
629 {
630 Assert(pCpu->mode == DISCPUMODE_64BIT);
631 /* Relative to the RIP of the next instruction. */
632 pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pCpu->opsize;
633 }
634 return VINF_SUCCESS;
635 }
636
637 if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
638 {
639 if (parmtype == PARAM_DEST)
640 {
641 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
642 pParamVal->type = PARMTYPE_REGISTER;
643 pParamVal->size = pParam->cb;
644 return VINF_SUCCESS;
645 }
646 //else PARAM_SOURCE
647
648 pParamVal->type = PARMTYPE_IMMEDIATE;
649
650 if (pParam->flags & USE_REG_GEN8)
651 {
652 pParamVal->flags |= PARAM_VAL8;
653 pParamVal->size = sizeof(uint8_t);
654 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
655 }
656 else
657 if (pParam->flags & USE_REG_GEN16)
658 {
659 pParamVal->flags |= PARAM_VAL16;
660 pParamVal->size = sizeof(uint16_t);
661 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
662 }
663 else
664 if (pParam->flags & USE_REG_GEN32)
665 {
666 pParamVal->flags |= PARAM_VAL32;
667 pParamVal->size = sizeof(uint32_t);
668 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
669 }
670 else
671 if (pParam->flags & USE_REG_GEN64)
672 {
673 pParamVal->flags |= PARAM_VAL64;
674 pParamVal->size = sizeof(uint64_t);
675 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
676 }
677 else
678 {
679 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
680 pParamVal->type = PARMTYPE_REGISTER;
681 }
682 Assert(!(pParam->flags & USE_IMMEDIATE));
683 return VINF_SUCCESS;
684 }
685
686 if (pParam->flags & USE_IMMEDIATE)
687 {
688 pParamVal->type = PARMTYPE_IMMEDIATE;
689 if (pParam->flags & (USE_IMMEDIATE8|USE_IMMEDIATE8_REL))
690 {
691 pParamVal->flags |= PARAM_VAL8;
692 if (pParam->cb == 2)
693 {
694 pParamVal->size = sizeof(uint16_t);
695 pParamVal->val.val16 = (uint8_t)pParam->parval;
696 }
697 else
698 {
699 pParamVal->size = sizeof(uint8_t);
700 pParamVal->val.val8 = (uint8_t)pParam->parval;
701 }
702 }
703 else
704 if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
705 {
706 pParamVal->flags |= PARAM_VAL16;
707 pParamVal->size = sizeof(uint16_t);
708 pParamVal->val.val16 = (uint16_t)pParam->parval;
709 AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
710 }
711 else
712 if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
713 {
714 pParamVal->flags |= PARAM_VAL32;
715 pParamVal->size = sizeof(uint32_t);
716 pParamVal->val.val32 = (uint32_t)pParam->parval;
717 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
718 }
719 else
720 if (pParam->flags & (USE_IMMEDIATE64 | USE_IMMEDIATE64_REL | USE_IMMEDIATE64_SX8))
721 {
722 pParamVal->flags |= PARAM_VAL64;
723 pParamVal->size = sizeof(uint64_t);
724 pParamVal->val.val64 = pParam->parval;
725 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->flags & USE_IMMEDIATE64_SX8)) );
726 }
727 else
728 if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
729 {
730 pParamVal->flags |= PARAM_VALFARPTR16;
731 pParamVal->size = sizeof(uint16_t)*2;
732 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
733 pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
734 Assert(pParamVal->size == pParam->cb);
735 }
736 else
737 if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
738 {
739 pParamVal->flags |= PARAM_VALFARPTR32;
740 pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
741 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
742 pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
743 Assert(pParam->cb == 8);
744 }
745 }
746 return VINF_SUCCESS;
747}
748
749/**
750 * Returns the pointer to a register of the parameter in pParam. We need this
751 * pointer when an interpreted instruction updates a register as a side effect.
752 * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
753 * be every register.
754 *
755 * @returns VBox error code
756 * @param pCtx CPU context structure pointer
757 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
758 * set correctly.
759 * @param pParam Pointer to the parameter to parse
760 * @param pReg Pointer to parameter value (OUT)
761 * @param cbsize Parameter size (OUT)
762 *
763 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
764 *
765 */
766DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
767{
768 NOREF(pCpu);
769 if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
770 {
771 if (pParam->flags & USE_REG_GEN8)
772 {
773 uint8_t *pu8Reg;
774 if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
775 {
776 *pcbSize = sizeof(uint8_t);
777 *ppReg = (void *)pu8Reg;
778 return VINF_SUCCESS;
779 }
780 }
781 else
782 if (pParam->flags & USE_REG_GEN16)
783 {
784 uint16_t *pu16Reg;
785 if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
786 {
787 *pcbSize = sizeof(uint16_t);
788 *ppReg = (void *)pu16Reg;
789 return VINF_SUCCESS;
790 }
791 }
792 else
793 if (pParam->flags & USE_REG_GEN32)
794 {
795 uint32_t *pu32Reg;
796 if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
797 {
798 *pcbSize = sizeof(uint32_t);
799 *ppReg = (void *)pu32Reg;
800 return VINF_SUCCESS;
801 }
802 }
803 else
804 if (pParam->flags & USE_REG_GEN64)
805 {
806 uint64_t *pu64Reg;
807 if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
808 {
809 *pcbSize = sizeof(uint64_t);
810 *ppReg = (void *)pu64Reg;
811 return VINF_SUCCESS;
812 }
813 }
814 }
815 return VERR_INVALID_PARAMETER;
816}
817
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