VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 41690

Last change on this file since 41690 was 41690, checked in by vboxsync, 12 years ago

DIS: More cleanups.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
  • Property svn:sync_process set to export
File size: 28.7 KB
Line 
1/* $Id: DisasmReg.cpp 41690 2012-06-13 18:12:25Z vboxsync $ */
2/** @file
3 * VBox disassembler- Register Info Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_DIS
23#include <VBox/dis.h>
24#include <VBox/disopcode.h>
25#include <VBox/err.h>
26#include <VBox/log.h>
27#include <VBox/vmm/cpum.h>
28#include <iprt/assert.h>
29#include <iprt/string.h>
30#include <iprt/stdarg.h>
31#include "DisasmInternal.h"
32
33
34/*******************************************************************************
35* Global Variables *
36*******************************************************************************/
37
38/**
39 * Array for accessing 64-bit general registers in VMMREGFRAME structure
40 * by register's index from disasm.
41 */
42static const unsigned g_aReg64Index[] =
43{
44 RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
45 RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
46 RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
47 RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
48 RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
49 RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
50 RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
51 RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
52 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
53 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
54 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
55 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
56 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
57 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
58 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
59 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
60};
61
62/**
63 * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
64 */
65#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
66#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
67#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
68
69/**
70 * Array for accessing 32-bit general registers in VMMREGFRAME structure
71 * by register's index from disasm.
72 */
73static const unsigned g_aReg32Index[] =
74{
75 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
76 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
77 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
78 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
79 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
80 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
81 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
82 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_EDI */
83 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8D */
84 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9D */
85 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10D */
86 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11D */
87 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12D */
88 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13D */
89 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14D */
90 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15D */
91};
92
93/**
94 * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
95 */
96#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
97/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
98 * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
99 * values also set the upper 32 bits of the register to zero. Consequently
100 * there is no need for an instruction movzlq.''
101 */
102#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
103#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
104
105/**
106 * Array for accessing 16-bit general registers in CPUMCTXCORE structure
107 * by register's index from disasm.
108 */
109static const unsigned g_aReg16Index[] =
110{
111 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
112 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
113 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
114 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
115 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
116 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
117 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
118 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_DI */
119 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8W */
120 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9W */
121 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10W */
122 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11W */
123 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12W */
124 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13W */
125 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14W */
126 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15W */
127};
128
129/**
130 * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
131 */
132#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
133#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
134#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
135
136/**
137 * Array for accessing 8-bit general registers in CPUMCTXCORE structure
138 * by register's index from disasm.
139 */
140static const unsigned g_aReg8Index[] =
141{
142 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
143 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
144 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
145 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
146 RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* USE_REG_AH */
147 RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* USE_REG_CH */
148 RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* USE_REG_DH */
149 RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* USE_REG_BH */
150 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8B */
151 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9B */
152 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10B*/
153 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11B */
154 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12B */
155 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13B */
156 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14B */
157 RT_OFFSETOF(CPUMCTXCORE, r15), /* USE_REG_R15B */
158 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SPL; with REX prefix only */
159 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BPL; with REX prefix only */
160 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SIL; with REX prefix only */
161 RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DIL; with REX prefix only */
162};
163
164/**
165 * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
166 */
167#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
168#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
169#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
170
171/**
172 * Array for accessing segment registers in CPUMCTXCORE structure
173 * by register's index from disasm.
174 */
175static const unsigned g_aRegSegIndex[] =
176{
177 RT_OFFSETOF(CPUMCTXCORE, es), /* DIS_SELREG_ES */
178 RT_OFFSETOF(CPUMCTXCORE, cs), /* DIS_SELREG_CS */
179 RT_OFFSETOF(CPUMCTXCORE, ss), /* DIS_SELREG_SS */
180 RT_OFFSETOF(CPUMCTXCORE, ds), /* DIS_SELREG_DS */
181 RT_OFFSETOF(CPUMCTXCORE, fs), /* DIS_SELREG_FS */
182 RT_OFFSETOF(CPUMCTXCORE, gs) /* DIS_SELREG_GS */
183};
184
185static const unsigned g_aRegHidSegIndex[] =
186{
187 RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */
188 RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */
189 RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */
190 RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */
191 RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */
192 RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */
193};
194
195/**
196 * Macro for accessing segment registers in CPUMCTXCORE structure.
197 */
198#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
199#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
200
201//*****************************************************************************
202//*****************************************************************************
203DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
204{
205 int subtype = OP_PARM_VSUBTYPE(pParam->param);
206
207 if (subtype == OP_PARM_v)
208 {
209 switch(pCpu->opmode)
210 {
211 case DISCPUMODE_32BIT:
212 subtype = OP_PARM_d;
213 break;
214 case DISCPUMODE_64BIT:
215 subtype = OP_PARM_q;
216 break;
217 case DISCPUMODE_16BIT:
218 subtype = OP_PARM_w;
219 break;
220 default:
221 /* make gcc happy */
222 break;
223 }
224 }
225
226 switch(subtype)
227 {
228 case OP_PARM_b:
229 return 1;
230
231 case OP_PARM_w:
232 return 2;
233
234 case OP_PARM_d:
235 return 4;
236
237 case OP_PARM_q:
238 case OP_PARM_dq:
239 return 8;
240
241 case OP_PARM_p: /* far pointer */
242 if (pCpu->addrmode == DISCPUMODE_32BIT)
243 return 6; /* 16:32 */
244 else
245 if (pCpu->addrmode == DISCPUMODE_64BIT)
246 return 12; /* 16:64 */
247 else
248 return 4; /* 16:16 */
249
250 default:
251 if (pParam->cb)
252 return pParam->cb;
253 else //@todo dangerous!!!
254 return 4;
255 }
256}
257//*****************************************************************************
258//*****************************************************************************
259DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
260{
261 if (pCpu->prefix & DISPREFIX_SEG)
262 {
263 /* Use specified SEG: prefix. */
264 return pCpu->enmPrefixSeg;
265 }
266 else
267 {
268 /* Guess segment register by parameter type. */
269 if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16))
270 {
271 AssertCompile(USE_REG_ESP == USE_REG_RSP);
272 AssertCompile(USE_REG_EBP == USE_REG_RBP);
273 AssertCompile(USE_REG_ESP == USE_REG_SP);
274 AssertCompile(USE_REG_EBP == USE_REG_BP);
275 if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
276 return DIS_SELREG_SS;
277 }
278 /* Default is use DS: for data access. */
279 return DIS_SELREG_DS;
280 }
281}
282//*****************************************************************************
283//*****************************************************************************
284DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
285{
286 Assert(pCpu->prefix & DISPREFIX_SEG);
287 switch(pCpu->enmPrefixSeg)
288 {
289 case DIS_SELREG_ES:
290 return 0x26;
291 case DIS_SELREG_CS:
292 return 0x2E;
293 case DIS_SELREG_SS:
294 return 0x36;
295 case DIS_SELREG_DS:
296 return 0x3E;
297 case DIS_SELREG_FS:
298 return 0x64;
299 case DIS_SELREG_GS:
300 return 0x65;
301 default:
302 AssertFailed();
303 return 0;
304 }
305}
306
307
308/**
309 * Returns the value of the specified 8 bits general purpose register
310 *
311 */
312DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
313{
314 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
315
316 *pVal = DIS_READ_REG8(pCtx, reg8);
317 return VINF_SUCCESS;
318}
319
320/**
321 * Returns the value of the specified 16 bits general purpose register
322 *
323 */
324DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
325{
326 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
327
328 *pVal = DIS_READ_REG16(pCtx, reg16);
329 return VINF_SUCCESS;
330}
331
332/**
333 * Returns the value of the specified 32 bits general purpose register
334 *
335 */
336DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
337{
338 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
339
340 *pVal = DIS_READ_REG32(pCtx, reg32);
341 return VINF_SUCCESS;
342}
343
344/**
345 * Returns the value of the specified 64 bits general purpose register
346 *
347 */
348DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
349{
350 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
351
352 *pVal = DIS_READ_REG64(pCtx, reg64);
353 return VINF_SUCCESS;
354}
355
356/**
357 * Returns the pointer to the specified 8 bits general purpose register
358 *
359 */
360DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
361{
362 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
363
364 *ppReg = DIS_PTR_REG8(pCtx, reg8);
365 return VINF_SUCCESS;
366}
367
368/**
369 * Returns the pointer to the specified 16 bits general purpose register
370 *
371 */
372DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
373{
374 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
375
376 *ppReg = DIS_PTR_REG16(pCtx, reg16);
377 return VINF_SUCCESS;
378}
379
380/**
381 * Returns the pointer to the specified 32 bits general purpose register
382 *
383 */
384DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
385{
386 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
387
388 *ppReg = DIS_PTR_REG32(pCtx, reg32);
389 return VINF_SUCCESS;
390}
391
392/**
393 * Returns the pointer to the specified 64 bits general purpose register
394 *
395 */
396DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
397{
398 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
399
400 *ppReg = DIS_PTR_REG64(pCtx, reg64);
401 return VINF_SUCCESS;
402}
403
404/**
405 * Returns the value of the specified segment register
406 *
407 */
408DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal)
409{
410 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
411
412 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
413 *pVal = DIS_READ_REGSEG(pCtx, sel);
414 return VINF_SUCCESS;
415}
416
417/**
418 * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
419 *
420 */
421DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
422{
423 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
424
425 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
426 *pVal = DIS_READ_REGSEG(pCtx, sel);
427 *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
428 return VINF_SUCCESS;
429}
430
431/**
432 * Updates the value of the specified 64 bits general purpose register
433 *
434 */
435DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
436{
437 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
438
439 DIS_WRITE_REG64(pRegFrame, reg64, val64);
440 return VINF_SUCCESS;
441}
442
443/**
444 * Updates the value of the specified 32 bits general purpose register
445 *
446 */
447DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
448{
449 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
450
451 DIS_WRITE_REG32(pRegFrame, reg32, val32);
452 return VINF_SUCCESS;
453}
454
455/**
456 * Updates the value of the specified 16 bits general purpose register
457 *
458 */
459DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
460{
461 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
462
463 DIS_WRITE_REG16(pRegFrame, reg16, val16);
464 return VINF_SUCCESS;
465}
466
467/**
468 * Updates the specified 8 bits general purpose register
469 *
470 */
471DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
472{
473 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
474
475 DIS_WRITE_REG8(pRegFrame, reg8, val8);
476 return VINF_SUCCESS;
477}
478
479/**
480 * Updates the specified segment register
481 *
482 */
483DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val)
484{
485 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
486
487 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
488 DIS_WRITE_REGSEG(pCtx, sel, val);
489 return VINF_SUCCESS;
490}
491
492/**
493 * Returns the value of the parameter in pParam
494 *
495 * @returns VBox error code
496 * @param pCtx CPU context structure pointer
497 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
498 * set correctly.
499 * @param pParam Pointer to the parameter to parse
500 * @param pParamVal Pointer to parameter value (OUT)
501 * @param parmtype Parameter type
502 *
503 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
504 *
505 */
506DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
507{
508 memset(pParamVal, 0, sizeof(*pParamVal));
509
510 if (DISUSE_IS_EFFECTIVE_ADDR(pParam->fUse))
511 {
512 // Effective address
513 pParamVal->type = PARMTYPE_ADDRESS;
514 pParamVal->size = pParam->cb;
515
516 if (pParam->fUse & DISUSE_BASE)
517 {
518 if (pParam->fUse & DISUSE_REG_GEN8)
519 {
520 pParamVal->flags |= PARAM_VAL8;
521 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
522 }
523 else
524 if (pParam->fUse & DISUSE_REG_GEN16)
525 {
526 pParamVal->flags |= PARAM_VAL16;
527 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
528 }
529 else
530 if (pParam->fUse & DISUSE_REG_GEN32)
531 {
532 pParamVal->flags |= PARAM_VAL32;
533 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
534 }
535 else
536 if (pParam->fUse & DISUSE_REG_GEN64)
537 {
538 pParamVal->flags |= PARAM_VAL64;
539 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
540 }
541 else
542 {
543 AssertFailed();
544 return VERR_INVALID_PARAMETER;
545 }
546 }
547 // Note that scale implies index (SIB byte)
548 if (pParam->fUse & DISUSE_INDEX)
549 {
550 if (pParam->fUse & DISUSE_REG_GEN16)
551 {
552 uint16_t val16;
553
554 pParamVal->flags |= PARAM_VAL16;
555 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
556
557 Assert(!(pParam->fUse & DISUSE_SCALE)); /* shouldn't be possible in 16 bits mode */
558
559 pParamVal->val.val16 += val16;
560 }
561 else
562 if (pParam->fUse & DISUSE_REG_GEN32)
563 {
564 uint32_t val32;
565
566 pParamVal->flags |= PARAM_VAL32;
567 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
568
569 if (pParam->fUse & DISUSE_SCALE)
570 val32 *= pParam->scale;
571
572 pParamVal->val.val32 += val32;
573 }
574 else
575 if (pParam->fUse & DISUSE_REG_GEN64)
576 {
577 uint64_t val64;
578
579 pParamVal->flags |= PARAM_VAL64;
580 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
581
582 if (pParam->fUse & DISUSE_SCALE)
583 val64 *= pParam->scale;
584
585 pParamVal->val.val64 += val64;
586 }
587 else
588 AssertFailed();
589 }
590
591 if (pParam->fUse & DISUSE_DISPLACEMENT8)
592 {
593 if (pCpu->mode == DISCPUMODE_32BIT)
594 pParamVal->val.val32 += (int32_t)pParam->uDisp.i8;
595 else
596 if (pCpu->mode == DISCPUMODE_64BIT)
597 pParamVal->val.val64 += (int64_t)pParam->uDisp.i8;
598 else
599 pParamVal->val.val16 += (int16_t)pParam->uDisp.i8;
600 }
601 else
602 if (pParam->fUse & DISUSE_DISPLACEMENT16)
603 {
604 if (pCpu->mode == DISCPUMODE_32BIT)
605 pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
606 else
607 if (pCpu->mode == DISCPUMODE_64BIT)
608 pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
609 else
610 pParamVal->val.val16 += pParam->uDisp.i16;
611 }
612 else
613 if (pParam->fUse & DISUSE_DISPLACEMENT32)
614 {
615 if (pCpu->mode == DISCPUMODE_32BIT)
616 pParamVal->val.val32 += pParam->uDisp.i32;
617 else
618 pParamVal->val.val64 += pParam->uDisp.i32;
619 }
620 else
621 if (pParam->fUse & DISUSE_DISPLACEMENT64)
622 {
623 Assert(pCpu->mode == DISCPUMODE_64BIT);
624 pParamVal->val.val64 += pParam->uDisp.i64;
625 }
626 else
627 if (pParam->fUse & DISUSE_RIPDISPLACEMENT32)
628 {
629 Assert(pCpu->mode == DISCPUMODE_64BIT);
630 /* Relative to the RIP of the next instruction. */
631 pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pCpu->opsize;
632 }
633 return VINF_SUCCESS;
634 }
635
636 if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
637 {
638 if (parmtype == PARAM_DEST)
639 {
640 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
641 pParamVal->type = PARMTYPE_REGISTER;
642 pParamVal->size = pParam->cb;
643 return VINF_SUCCESS;
644 }
645 //else PARAM_SOURCE
646
647 pParamVal->type = PARMTYPE_IMMEDIATE;
648
649 if (pParam->fUse & DISUSE_REG_GEN8)
650 {
651 pParamVal->flags |= PARAM_VAL8;
652 pParamVal->size = sizeof(uint8_t);
653 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
654 }
655 else
656 if (pParam->fUse & DISUSE_REG_GEN16)
657 {
658 pParamVal->flags |= PARAM_VAL16;
659 pParamVal->size = sizeof(uint16_t);
660 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
661 }
662 else
663 if (pParam->fUse & DISUSE_REG_GEN32)
664 {
665 pParamVal->flags |= PARAM_VAL32;
666 pParamVal->size = sizeof(uint32_t);
667 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
668 }
669 else
670 if (pParam->fUse & DISUSE_REG_GEN64)
671 {
672 pParamVal->flags |= PARAM_VAL64;
673 pParamVal->size = sizeof(uint64_t);
674 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
675 }
676 else
677 {
678 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
679 pParamVal->type = PARMTYPE_REGISTER;
680 }
681 Assert(!(pParam->fUse & DISUSE_IMMEDIATE));
682 return VINF_SUCCESS;
683 }
684
685 if (pParam->fUse & DISUSE_IMMEDIATE)
686 {
687 pParamVal->type = PARMTYPE_IMMEDIATE;
688 if (pParam->fUse & (DISUSE_IMMEDIATE8|DISUSE_IMMEDIATE8_REL))
689 {
690 pParamVal->flags |= PARAM_VAL8;
691 if (pParam->cb == 2)
692 {
693 pParamVal->size = sizeof(uint16_t);
694 pParamVal->val.val16 = (uint8_t)pParam->parval;
695 }
696 else
697 {
698 pParamVal->size = sizeof(uint8_t);
699 pParamVal->val.val8 = (uint8_t)pParam->parval;
700 }
701 }
702 else
703 if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
704 {
705 pParamVal->flags |= PARAM_VAL16;
706 pParamVal->size = sizeof(uint16_t);
707 pParamVal->val.val16 = (uint16_t)pParam->parval;
708 AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
709 }
710 else
711 if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
712 {
713 pParamVal->flags |= PARAM_VAL32;
714 pParamVal->size = sizeof(uint32_t);
715 pParamVal->val.val32 = (uint32_t)pParam->parval;
716 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
717 }
718 else
719 if (pParam->fUse & (DISUSE_IMMEDIATE64 | DISUSE_IMMEDIATE64_REL | DISUSE_IMMEDIATE64_SX8))
720 {
721 pParamVal->flags |= PARAM_VAL64;
722 pParamVal->size = sizeof(uint64_t);
723 pParamVal->val.val64 = pParam->parval;
724 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
725 }
726 else
727 if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16))
728 {
729 pParamVal->flags |= PARAM_VALFARPTR16;
730 pParamVal->size = sizeof(uint16_t)*2;
731 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
732 pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
733 Assert(pParamVal->size == pParam->cb);
734 }
735 else
736 if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_32))
737 {
738 pParamVal->flags |= PARAM_VALFARPTR32;
739 pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
740 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
741 pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
742 Assert(pParam->cb == 8);
743 }
744 }
745 return VINF_SUCCESS;
746}
747
748/**
749 * Returns the pointer to a register of the parameter in pParam. We need this
750 * pointer when an interpreted instruction updates a register as a side effect.
751 * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
752 * be every register.
753 *
754 * @returns VBox error code
755 * @param pCtx CPU context structure pointer
756 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
757 * set correctly.
758 * @param pParam Pointer to the parameter to parse
759 * @param pReg Pointer to parameter value (OUT)
760 * @param cbsize Parameter size (OUT)
761 *
762 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
763 *
764 */
765DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
766{
767 NOREF(pCpu);
768 if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
769 {
770 if (pParam->fUse & DISUSE_REG_GEN8)
771 {
772 uint8_t *pu8Reg;
773 if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
774 {
775 *pcbSize = sizeof(uint8_t);
776 *ppReg = (void *)pu8Reg;
777 return VINF_SUCCESS;
778 }
779 }
780 else
781 if (pParam->fUse & DISUSE_REG_GEN16)
782 {
783 uint16_t *pu16Reg;
784 if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
785 {
786 *pcbSize = sizeof(uint16_t);
787 *ppReg = (void *)pu16Reg;
788 return VINF_SUCCESS;
789 }
790 }
791 else
792 if (pParam->fUse & DISUSE_REG_GEN32)
793 {
794 uint32_t *pu32Reg;
795 if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
796 {
797 *pcbSize = sizeof(uint32_t);
798 *ppReg = (void *)pu32Reg;
799 return VINF_SUCCESS;
800 }
801 }
802 else
803 if (pParam->fUse & DISUSE_REG_GEN64)
804 {
805 uint64_t *pu64Reg;
806 if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
807 {
808 *pcbSize = sizeof(uint64_t);
809 *ppReg = (void *)pu64Reg;
810 return VINF_SUCCESS;
811 }
812 }
813 }
814 return VERR_INVALID_PARAMETER;
815}
816
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