DisasmReg.cpp@ 8188

Last change on this file since 8188 was 8168, checked in by vboxsync, 17 years ago
Rebranding: coupla missing headers.
Property svn:sync_process set to `export`
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1	/** @file
2	*
3	* VBox disassembler:
4	* Core components
5	*/
6
7	/*
8	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19	* Clara, CA 95054 USA or visit http://www.sun.com if you need
20	* additional information or have any questions.
21	*/
22
23
24	/*******************************************************************************
25	* Header Files *
26	*******************************************************************************/
27	#define LOG_GROUP LOG_GROUP_DIS
28	#ifdef USING_VISUAL_STUDIO
29	# include <stdafx.h>
30	#endif
31
32	#include <VBox/dis.h>
33	#include <VBox/disopcode.h>
34	#include <VBox/cpum.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39	#include <iprt/stdarg.h>
40	#include "DisasmInternal.h"
41	#include "DisasmTables.h"
42
43	#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
44	# include <stdlib.h>
45	# include <stdio.h>
46	#endif
47
48
49	/*******************************************************************************
50	* Global Variables *
51	*******************************************************************************/
52
53	/**
54	* Array for accessing 64-bit general registers in VMMREGFRAME structure
55	* by register's index from disasm.
56	*/
57	static const unsigned g_aReg64Index[] =
58	{
59	RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
60	RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
61	RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
62	RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
63	RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
64	RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
65	RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
66	RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
67	RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
68	RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
69	RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
70	RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
71	RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
72	RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
73	RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
74	RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
75	};
76
77	/**
78	* Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
79	*/
80	#define DIS_READ_REG64(p, idx) ((uint64_t )((char *)(p) + g_aReg64Index[idx]))
81	#define DIS_WRITE_REG64(p, idx, val) ((uint64_t )((char *)(p) + g_aReg64Index[idx]) = val)
82	#define DIS_PTR_REG64(p, idx) ( (uint64_t )((char )(p) + g_aReg64Index[idx]))
83
84	/**
85	* Array for accessing 32-bit general registers in VMMREGFRAME structure
86	* by register's index from disasm.
87	*/
88	static const unsigned g_aReg32Index[] =
89	{
90	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
91	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
92	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
93	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
94	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
95	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
96	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
97	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_EDI */
98	};
99
100	/**
101	* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
102	*/
103	#define DIS_READ_REG32(p, idx) ((uint32_t )((char *)(p) + g_aReg32Index[idx]))
104	#define DIS_WRITE_REG32(p, idx, val) ((uint32_t )((char *)(p) + g_aReg32Index[idx]) = val)
105	#define DIS_PTR_REG32(p, idx) ( (uint32_t )((char )(p) + g_aReg32Index[idx]))
106
107	/**
108	* Array for accessing 16-bit general registers in CPUMCTXCORE structure
109	* by register's index from disasm.
110	*/
111	static const unsigned g_aReg16Index[] =
112	{
113	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
114	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
115	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
116	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
117	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
118	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
119	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
120	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DI */
121	};
122
123	/**
124	* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
125	*/
126	#define DIS_READ_REG16(p, idx) ((uint16_t )((char *)(p) + g_aReg16Index[idx]))
127	#define DIS_WRITE_REG16(p, idx, val) ((uint16_t )((char *)(p) + g_aReg16Index[idx]) = val)
128	#define DIS_PTR_REG16(p, idx) ( (uint16_t )((char )(p) + g_aReg16Index[idx]))
129
130	/**
131	* Array for accessing 8-bit general registers in CPUMCTXCORE structure
132	* by register's index from disasm.
133	*/
134	static const unsigned g_aReg8Index[] =
135	{
136	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
137	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
138	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
139	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
140	RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
141	RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
142	RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
143	RT_OFFSETOF(CPUMCTXCORE, ebx) + 1 /* USE_REG_BH */
144	};
145
146	/**
147	* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
148	*/
149	#define DIS_READ_REG8(p, idx) ((uint8_t )((char *)(p) + g_aReg8Index[idx]))
150	#define DIS_WRITE_REG8(p, idx, val) ((uint8_t )((char *)(p) + g_aReg8Index[idx]) = val)
151	#define DIS_PTR_REG8(p, idx) ( (uint8_t )((char )(p) + g_aReg8Index[idx]))
152
153	/**
154	* Array for accessing segment registers in CPUMCTXCORE structure
155	* by register's index from disasm.
156	*/
157	static const unsigned g_aRegSegIndex[] =
158	{
159	RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */
160	RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */
161	RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */
162	RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */
163	RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */
164	RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */
165	};
166
167	static const unsigned g_aRegHidSegIndex[] =
168	{
169	RT_OFFSETOF(CPUMCTXCORE, esHid), /* USE_REG_ES */
170	RT_OFFSETOF(CPUMCTXCORE, csHid), /* USE_REG_CS */
171	RT_OFFSETOF(CPUMCTXCORE, ssHid), /* USE_REG_SS */
172	RT_OFFSETOF(CPUMCTXCORE, dsHid), /* USE_REG_DS */
173	RT_OFFSETOF(CPUMCTXCORE, fsHid), /* USE_REG_FS */
174	RT_OFFSETOF(CPUMCTXCORE, gsHid) /* USE_REG_GS */
175	};
176
177	/**
178	* Macro for accessing segment registers in CPUMCTXCORE structure.
179	*/
180	#define DIS_READ_REGSEG(p, idx) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])))
181	#define DIS_WRITE_REGSEG(p, idx, val) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])) = val)
182
183	//*****************************************************************************
184	//*****************************************************************************
185	DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
186	{
187	int subtype = OP_PARM_VSUBTYPE(pParam->param);
188
189	if (subtype == OP_PARM_v)
190	{
191	subtype = (pCpu->opmode == CPUMODE_32BIT) ? OP_PARM_d : OP_PARM_w;
192	}
193
194	switch(subtype)
195	{
196	case OP_PARM_b:
197	return 1;
198
199	case OP_PARM_w:
200	return 2;
201
202	case OP_PARM_d:
203	return 4;
204
205	case OP_PARM_q:
206	case OP_PARM_dq:
207	return 8;
208
209	case OP_PARM_p:
210	if (pCpu->addrmode == CPUMODE_32BIT)
211	return 8;
212	else
213	return 4;
214
215	default:
216	if (pParam->size)
217	return pParam->size;
218	else //@todo dangerous!!!
219	return 4;
220	}
221	}
222	//*****************************************************************************
223	//*****************************************************************************
224	DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
225	{
226	if (pCpu->prefix & PREFIX_SEG)
227	{
228	/* Use specified SEG: prefix. */
229	return pCpu->prefix_seg;
230	}
231	else
232	{
233	/* Guess segment register by parameter type. */
234	if (pParam->flags & USE_REG_GEN32)
235	{
236	if (pParam->base.reg_gen32 == USE_REG_ESP \|\| pParam->base.reg_gen32 == USE_REG_EBP)
237	return USE_REG_SS;
238	}
239	else
240	if (pParam->flags & USE_REG_GEN16)
241	{
242	if (pParam->base.reg_gen16 == USE_REG_SP \|\| pParam->base.reg_gen16 == USE_REG_BP)
243	return USE_REG_SS;
244	}
245	/* Default is use DS: for data access. */
246	return USE_REG_DS;
247	}
248	}
249	//*****************************************************************************
250	//*****************************************************************************
251	DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
252	{
253	Assert(pCpu->prefix & PREFIX_SEG);
254	switch(pCpu->prefix_seg)
255	{
256	case USE_REG_ES:
257	return 0x26;
258	case USE_REG_CS:
259	return 0x2E;
260	case USE_REG_SS:
261	return 0x36;
262	case USE_REG_DS:
263	return 0x3E;
264	case USE_REG_FS:
265	return 0x64;
266	case USE_REG_GS:
267	return 0x65;
268	default:
269	AssertFailed();
270	return 0;
271	}
272	}
273
274
275	/**
276	* Returns the value of the specified 8 bits general purpose register
277	*
278	*/
279	DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
280	{
281	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
282
283	*pVal = DIS_READ_REG8(pCtx, reg8);
284	return VINF_SUCCESS;
285	}
286
287	/**
288	* Returns the value of the specified 16 bits general purpose register
289	*
290	*/
291	DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
292	{
293	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
294
295	*pVal = DIS_READ_REG16(pCtx, reg16);
296	return VINF_SUCCESS;
297	}
298
299	/**
300	* Returns the value of the specified 32 bits general purpose register
301	*
302	*/
303	DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
304	{
305	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
306
307	*pVal = DIS_READ_REG32(pCtx, reg32);
308	return VINF_SUCCESS;
309	}
310
311	/**
312	* Returns the value of the specified 64 bits general purpose register
313	*
314	*/
315	DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
316	{
317	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
318
319	*pVal = DIS_READ_REG64(pCtx, reg64);
320	return VINF_SUCCESS;
321	}
322
323	/**
324	* Returns the pointer to the specified 8 bits general purpose register
325	*
326	*/
327	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
328	{
329	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
330
331	*ppReg = DIS_PTR_REG8(pCtx, reg8);
332	return VINF_SUCCESS;
333	}
334
335	/**
336	* Returns the pointer to the specified 16 bits general purpose register
337	*
338	*/
339	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
340	{
341	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
342
343	*ppReg = DIS_PTR_REG16(pCtx, reg16);
344	return VINF_SUCCESS;
345	}
346
347	/**
348	* Returns the pointer to the specified 32 bits general purpose register
349	*
350	*/
351	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
352	{
353	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
354
355	*ppReg = DIS_PTR_REG32(pCtx, reg32);
356	return VINF_SUCCESS;
357	}
358
359	/**
360	* Returns the pointer to the specified 64 bits general purpose register
361	*
362	*/
363	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
364	{
365	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
366
367	*ppReg = DIS_PTR_REG64(pCtx, reg64);
368	return VINF_SUCCESS;
369	}
370
371	/**
372	* Returns the value of the specified segment register
373	*
374	*/
375	DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal)
376	{
377	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
378
379	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
380	*pVal = DIS_READ_REGSEG(pCtx, sel);
381	return VINF_SUCCESS;
382	}
383
384	/**
385	* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
386	*
387	*/
388	DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL pVal, CPUMSELREGHID *ppSelHidReg)
389	{
390	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
391
392	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
393	*pVal = DIS_READ_REGSEG(pCtx, sel);
394	ppSelHidReg = (CPUMSELREGHID )((char *)pCtx + g_aRegHidSegIndex[sel]);
395	return VINF_SUCCESS;
396	}
397
398	/**
399	* Updates the value of the specified 64 bits general purpose register
400	*
401	*/
402	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
403	{
404	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
405
406	DIS_WRITE_REG64(pRegFrame, reg64, val64);
407	return VINF_SUCCESS;
408	}
409
410	/**
411	* Updates the value of the specified 32 bits general purpose register
412	*
413	*/
414	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
415	{
416	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
417
418	DIS_WRITE_REG32(pRegFrame, reg32, val32);
419	return VINF_SUCCESS;
420	}
421
422	/**
423	* Updates the value of the specified 16 bits general purpose register
424	*
425	*/
426	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
427	{
428	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
429
430	DIS_WRITE_REG16(pRegFrame, reg16, val16);
431	return VINF_SUCCESS;
432	}
433
434	/**
435	* Updates the specified 8 bits general purpose register
436	*
437	*/
438	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
439	{
440	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
441
442	DIS_WRITE_REG8(pRegFrame, reg8, val8);
443	return VINF_SUCCESS;
444	}
445
446	/**
447	* Updates the specified segment register
448	*
449	*/
450	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL val)
451	{
452	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
453
454	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
455	DIS_WRITE_REGSEG(pCtx, sel, val);
456	return VINF_SUCCESS;
457	}
458
459	/**
460	* Returns the value of the parameter in pParam
461	*
462	* @returns VBox error code
463	* @param pCtx CPU context structure pointer
464	* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
465	* set correctly.
466	* @param pParam Pointer to the parameter to parse
467	* @param pParamVal Pointer to parameter value (OUT)
468	* @param parmtype Parameter type
469	*
470	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
471	*
472	*/
473	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
474	{
475	memset(pParamVal, 0, sizeof(*pParamVal));
476
477	if (pParam->flags & (USE_BASE\|USE_INDEX\|USE_DISPLACEMENT32\|USE_DISPLACEMENT16\|USE_DISPLACEMENT8))
478	{
479	// Effective address
480	pParamVal->type = PARMTYPE_ADDRESS;
481	pParamVal->size = pParam->size;
482
483	if (pParam->flags & USE_BASE)
484	{
485	if (pParam->flags & USE_REG_GEN8)
486	{
487	pParamVal->flags \|= PARAM_VAL8;
488	if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen8, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
489	}
490	else
491	if (pParam->flags & USE_REG_GEN16)
492	{
493	pParamVal->flags \|= PARAM_VAL16;
494	if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen16, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
495	}
496	else
497	if (pParam->flags & USE_REG_GEN32)
498	{
499	pParamVal->flags \|= PARAM_VAL32;
500	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen32, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
501	}
502	else
503	if (pParam->flags & USE_REG_GEN64)
504	{
505	pParamVal->flags \|= PARAM_VAL64;
506	if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen64, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
507	}
508	else {
509	AssertFailed();
510	return VERR_INVALID_PARAMETER;
511	}
512	}
513	// Note that scale implies index (SIB byte)
514	if (pParam->flags & USE_INDEX)
515	{
516	uint32_t val32;
517
518	pParamVal->flags \|= PARAM_VAL32;
519	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
520
521	if (pParam->flags & USE_SCALE)
522	{
523	val32 *= pParam->scale;
524	}
525	pParamVal->val.val32 += val32;
526	}
527
528	if (pParam->flags & USE_DISPLACEMENT8)
529	{
530	if (pCpu->mode & CPUMODE_32BIT)
531	{
532	pParamVal->val.val32 += (int32_t)pParam->disp8;
533	}
534	else
535	{
536	pParamVal->val.val16 += (int16_t)pParam->disp8;
537	}
538	}
539	else
540	if (pParam->flags & USE_DISPLACEMENT16)
541	{
542	if (pCpu->mode & CPUMODE_32BIT)
543	{
544	pParamVal->val.val32 += (int32_t)pParam->disp16;
545	}
546	else
547	{
548	pParamVal->val.val16 += pParam->disp16;
549	}
550	}
551	else
552	if (pParam->flags & USE_DISPLACEMENT32)
553	{
554	if (pCpu->mode & CPUMODE_32BIT)
555	{
556	pParamVal->val.val32 += pParam->disp32;
557	}
558	else
559	{
560	Assert(0);
561	}
562	}
563	return VINF_SUCCESS;
564	}
565
566	if (pParam->flags & (USE_REG_GEN8\|USE_REG_GEN16\|USE_REG_GEN32\|USE_REG_GEN64\|USE_REG_FP\|USE_REG_MMX\|USE_REG_XMM\|USE_REG_CR\|USE_REG_DBG\|USE_REG_SEG\|USE_REG_TEST))
567	{
568	if (parmtype == PARAM_DEST)
569	{
570	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
571	pParamVal->type = PARMTYPE_REGISTER;
572	pParamVal->size = pParam->size;
573	return VINF_SUCCESS;
574	}
575	//else PARAM_SOURCE
576
577	pParamVal->type = PARMTYPE_IMMEDIATE;
578
579	if (pParam->flags & USE_REG_GEN8)
580	{
581	pParamVal->flags \|= PARAM_VAL8;
582	pParamVal->size = sizeof(uint8_t);
583	if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen8, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
584	}
585	else
586	if (pParam->flags & USE_REG_GEN16)
587	{
588	pParamVal->flags \|= PARAM_VAL16;
589	pParamVal->size = sizeof(uint16_t);
590	if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen16, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
591	}
592	else
593	if (pParam->flags & USE_REG_GEN32)
594	{
595	pParamVal->flags \|= PARAM_VAL32;
596	pParamVal->size = sizeof(uint32_t);
597	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen32, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
598	}
599	else
600	if (pParam->flags & USE_REG_GEN64)
601	{
602	pParamVal->flags \|= PARAM_VAL64;
603	pParamVal->size = sizeof(uint64_t);
604	if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen64, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
605	}
606	else
607	{
608	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
609	pParamVal->type = PARMTYPE_REGISTER;
610	}
611	}
612
613	if (pParam->flags & USE_IMMEDIATE)
614	{
615	pParamVal->type = PARMTYPE_IMMEDIATE;
616	if (pParam->flags & (USE_IMMEDIATE8\|USE_IMMEDIATE8_REL))
617	{
618	pParamVal->flags \|= PARAM_VAL8;
619	if (pParam->size == 2)
620	{
621	pParamVal->size = sizeof(uint16_t);
622	pParamVal->val.val16 = (uint8_t)pParam->parval;
623	}
624	else
625	{
626	pParamVal->size = sizeof(uint8_t);
627	pParamVal->val.val8 = (uint8_t)pParam->parval;
628	}
629	}
630	else
631	if (pParam->flags & (USE_IMMEDIATE16\|USE_IMMEDIATE16_REL\|USE_IMMEDIATE_ADDR_0_16\|USE_IMMEDIATE16_SX8))
632	{
633	pParamVal->flags \|= PARAM_VAL16;
634	pParamVal->size = sizeof(uint16_t);
635	pParamVal->val.val16 = (uint16_t)pParam->parval;
636	Assert(pParamVal->size == pParam->size \|\| ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)) );
637	}
638	else
639	if (pParam->flags & (USE_IMMEDIATE32\|USE_IMMEDIATE32_REL\|USE_IMMEDIATE_ADDR_0_32\|USE_IMMEDIATE32_SX8))
640	{
641	pParamVal->flags \|= PARAM_VAL32;
642	pParamVal->size = sizeof(uint32_t);
643	pParamVal->val.val32 = (uint32_t)pParam->parval;
644	Assert(pParamVal->size == pParam->size \|\| ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
645	}
646	else
647	if (pParam->flags & (USE_IMMEDIATE64))
648	{
649	pParamVal->flags \|= PARAM_VAL64;
650	pParamVal->size = sizeof(uint64_t);
651	pParamVal->val.val64 = pParam->parval;
652	Assert(pParamVal->size == pParam->size);
653	}
654	else
655	if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
656	{
657	pParamVal->flags \|= PARAM_VALFARPTR16;
658	pParamVal->size = sizeof(uint16_t)*2;
659	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
660	pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
661	Assert(pParamVal->size == pParam->size);
662	}
663	else
664	if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
665	{
666	pParamVal->flags \|= PARAM_VALFARPTR32;
667	pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
668	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
669	pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
670	Assert(pParam->size == 8);
671	}
672	}
673	return VINF_SUCCESS;
674	}
675
676	/**
677	* Returns the pointer to a register of the parameter in pParam. We need this
678	* pointer when an interpreted instruction updates a register as a side effect.
679	* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
680	* be every register.
681	*
682	* @returns VBox error code
683	* @param pCtx CPU context structure pointer
684	* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
685	* set correctly.
686	* @param pParam Pointer to the parameter to parse
687	* @param pReg Pointer to parameter value (OUT)
688	* @param cbsize Parameter size (OUT)
689	*
690	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
691	*
692	*/
693	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void *ppReg, size_t pcbSize)
694	{
695	if (pParam->flags & (USE_REG_GEN8\|USE_REG_GEN16\|USE_REG_GEN32\|USE_REG_FP\|USE_REG_MMX\|USE_REG_XMM\|USE_REG_CR\|USE_REG_DBG\|USE_REG_SEG\|USE_REG_TEST))
696	{
697	if (pParam->flags & USE_REG_GEN8)
698	{
699	uint8_t *pu8Reg;
700	if (VBOX_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen8, &pu8Reg)))
701	{
702	*pcbSize = sizeof(uint8_t);
703	ppReg = (void )pu8Reg;
704	return VINF_SUCCESS;
705	}
706	}
707	else
708	if (pParam->flags & USE_REG_GEN16)
709	{
710	uint16_t *pu16Reg;
711	if (VBOX_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen16, &pu16Reg)))
712	{
713	*pcbSize = sizeof(uint16_t);
714	ppReg = (void )pu16Reg;
715	return VINF_SUCCESS;
716	}
717	}
718	else
719	if (pParam->flags & USE_REG_GEN32)
720	{
721	uint32_t *pu32Reg;
722	if (VBOX_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen32, &pu32Reg)))
723	{
724	*pcbSize = sizeof(uint32_t);
725	ppReg = (void )pu32Reg;
726	return VINF_SUCCESS;
727	}
728	}
729	else
730	if (pParam->flags & USE_REG_GEN64)
731	{
732	uint64_t *pu64Reg;
733	if (VBOX_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen64, &pu64Reg)))
734	{
735	*pcbSize = sizeof(uint64_t);
736	ppReg = (void )pu64Reg;
737	return VINF_SUCCESS;
738	}
739	}
740	}
741	return VERR_INVALID_PARAMETER;
742	}
743	//*****************************************************************************
744	//*****************************************************************************

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source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 8188

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