DisasmReg.cpp@ 8373

Last change on this file since 8373 was 8364, checked in by vboxsync, 17 years ago
Use the right tables
Property svn:sync_process set to `export`
File size: 25.3 KB

Line
1	/** @file
2	*
3	* VBox disassembler:
4	* Core components
5	*/
6
7	/*
8	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19	* Clara, CA 95054 USA or visit http://www.sun.com if you need
20	* additional information or have any questions.
21	*/
22
23
24	/*******************************************************************************
25	* Header Files *
26	*******************************************************************************/
27	#define LOG_GROUP LOG_GROUP_DIS
28	#ifdef USING_VISUAL_STUDIO
29	# include <stdafx.h>
30	#endif
31
32	#include <VBox/dis.h>
33	#include <VBox/disopcode.h>
34	#include <VBox/cpum.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39	#include <iprt/stdarg.h>
40	#include "DisasmInternal.h"
41	#include "DisasmTables.h"
42
43	#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
44	# include <stdlib.h>
45	# include <stdio.h>
46	#endif
47
48
49	/*******************************************************************************
50	* Global Variables *
51	*******************************************************************************/
52
53	/**
54	* Array for accessing 64-bit general registers in VMMREGFRAME structure
55	* by register's index from disasm.
56	*/
57	static const unsigned g_aReg64Index[] =
58	{
59	RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
60	RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
61	RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
62	RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
63	RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
64	RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
65	RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
66	RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
67	RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
68	RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
69	RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
70	RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
71	RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
72	RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
73	RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
74	RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
75	};
76
77	/**
78	* Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
79	*/
80	#define DIS_READ_REG64(p, idx) ((uint64_t )((char *)(p) + g_aReg64Index[idx]))
81	#define DIS_WRITE_REG64(p, idx, val) ((uint64_t )((char *)(p) + g_aReg64Index[idx]) = val)
82	#define DIS_PTR_REG64(p, idx) ( (uint64_t )((char )(p) + g_aReg64Index[idx]))
83
84	/**
85	* Array for accessing 32-bit general registers in VMMREGFRAME structure
86	* by register's index from disasm.
87	*/
88	static const unsigned g_aReg32Index[] =
89	{
90	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
91	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
92	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
93	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
94	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
95	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
96	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
97	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_EDI */
98	};
99
100	/**
101	* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
102	*/
103	#define DIS_READ_REG32(p, idx) ((uint32_t )((char *)(p) + g_aReg32Index[idx]))
104	#define DIS_WRITE_REG32(p, idx, val) ((uint32_t )((char *)(p) + g_aReg32Index[idx]) = val)
105	#define DIS_PTR_REG32(p, idx) ( (uint32_t )((char )(p) + g_aReg32Index[idx]))
106
107	/**
108	* Array for accessing 16-bit general registers in CPUMCTXCORE structure
109	* by register's index from disasm.
110	*/
111	static const unsigned g_aReg16Index[] =
112	{
113	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
114	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
115	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
116	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
117	RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
118	RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
119	RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
120	RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DI */
121	};
122
123	/**
124	* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
125	*/
126	#define DIS_READ_REG16(p, idx) ((uint16_t )((char *)(p) + g_aReg16Index[idx]))
127	#define DIS_WRITE_REG16(p, idx, val) ((uint16_t )((char *)(p) + g_aReg16Index[idx]) = val)
128	#define DIS_PTR_REG16(p, idx) ( (uint16_t )((char )(p) + g_aReg16Index[idx]))
129
130	/**
131	* Array for accessing 8-bit general registers in CPUMCTXCORE structure
132	* by register's index from disasm.
133	*/
134	static const unsigned g_aReg8Index[] =
135	{
136	RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
137	RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
138	RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
139	RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
140	RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
141	RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
142	RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
143	RT_OFFSETOF(CPUMCTXCORE, ebx) + 1 /* USE_REG_BH */
144	};
145
146	/**
147	* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
148	*/
149	#define DIS_READ_REG8(p, idx) ((uint8_t )((char *)(p) + g_aReg8Index[idx]))
150	#define DIS_WRITE_REG8(p, idx, val) ((uint8_t )((char *)(p) + g_aReg8Index[idx]) = val)
151	#define DIS_PTR_REG8(p, idx) ( (uint8_t )((char )(p) + g_aReg8Index[idx]))
152
153	/**
154	* Array for accessing segment registers in CPUMCTXCORE structure
155	* by register's index from disasm.
156	*/
157	static const unsigned g_aRegSegIndex[] =
158	{
159	RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */
160	RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */
161	RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */
162	RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */
163	RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */
164	RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */
165	};
166
167	static const unsigned g_aRegHidSegIndex[] =
168	{
169	RT_OFFSETOF(CPUMCTXCORE, esHid), /* USE_REG_ES */
170	RT_OFFSETOF(CPUMCTXCORE, csHid), /* USE_REG_CS */
171	RT_OFFSETOF(CPUMCTXCORE, ssHid), /* USE_REG_SS */
172	RT_OFFSETOF(CPUMCTXCORE, dsHid), /* USE_REG_DS */
173	RT_OFFSETOF(CPUMCTXCORE, fsHid), /* USE_REG_FS */
174	RT_OFFSETOF(CPUMCTXCORE, gsHid) /* USE_REG_GS */
175	};
176
177	/**
178	* Macro for accessing segment registers in CPUMCTXCORE structure.
179	*/
180	#define DIS_READ_REGSEG(p, idx) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])))
181	#define DIS_WRITE_REGSEG(p, idx, val) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])) = val)
182
183	//*****************************************************************************
184	//*****************************************************************************
185	DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
186	{
187	int subtype = OP_PARM_VSUBTYPE(pParam->param);
188
189	if (subtype == OP_PARM_v)
190	{
191	subtype = (pCpu->opmode == CPUMODE_32BIT) ? OP_PARM_d : OP_PARM_w;
192	}
193
194	switch(subtype)
195	{
196	case OP_PARM_b:
197	return 1;
198
199	case OP_PARM_w:
200	return 2;
201
202	case OP_PARM_d:
203	return 4;
204
205	case OP_PARM_q:
206	case OP_PARM_dq:
207	return 8;
208
209	case OP_PARM_p: /* far pointer */
210	if (pCpu->addrmode == CPUMODE_32BIT)
211	return 6; /* 16:32 */
212	else
213	if (pCpu->addrmode == CPUMODE_64BIT)
214	return 12; /* 16:64 */
215	else
216	return 4; /* 16:16 */
217
218	default:
219	if (pParam->size)
220	return pParam->size;
221	else //@todo dangerous!!!
222	return 4;
223	}
224	}
225	//*****************************************************************************
226	//*****************************************************************************
227	DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
228	{
229	if (pCpu->prefix & PREFIX_SEG)
230	{
231	/* Use specified SEG: prefix. */
232	return pCpu->prefix_seg;
233	}
234	else
235	{
236	/* Guess segment register by parameter type. */
237	if (pParam->flags & (USE_REG_GEN32\|USE_REG_GEN64\|USE_REG_GEN16))
238	{
239	AssertCompile(USE_REG_ESP == USE_REG_RSP);
240	AssertCompile(USE_REG_EBP == USE_REG_RBP);
241	AssertCompile(USE_REG_ESP == USE_REG_SP);
242	AssertCompile(USE_REG_EBP == USE_REG_BP);
243	if (pParam->base.reg_gen == USE_REG_ESP \|\| pParam->base.reg_gen == USE_REG_EBP)
244	return USE_REG_SS;
245	}
246	/* Default is use DS: for data access. */
247	return USE_REG_DS;
248	}
249	}
250	//*****************************************************************************
251	//*****************************************************************************
252	DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
253	{
254	Assert(pCpu->prefix & PREFIX_SEG);
255	switch(pCpu->prefix_seg)
256	{
257	case USE_REG_ES:
258	return 0x26;
259	case USE_REG_CS:
260	return 0x2E;
261	case USE_REG_SS:
262	return 0x36;
263	case USE_REG_DS:
264	return 0x3E;
265	case USE_REG_FS:
266	return 0x64;
267	case USE_REG_GS:
268	return 0x65;
269	default:
270	AssertFailed();
271	return 0;
272	}
273	}
274
275
276	/**
277	* Returns the value of the specified 8 bits general purpose register
278	*
279	*/
280	DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
281	{
282	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
283
284	*pVal = DIS_READ_REG8(pCtx, reg8);
285	return VINF_SUCCESS;
286	}
287
288	/**
289	* Returns the value of the specified 16 bits general purpose register
290	*
291	*/
292	DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
293	{
294	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
295
296	*pVal = DIS_READ_REG16(pCtx, reg16);
297	return VINF_SUCCESS;
298	}
299
300	/**
301	* Returns the value of the specified 32 bits general purpose register
302	*
303	*/
304	DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
305	{
306	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
307
308	*pVal = DIS_READ_REG32(pCtx, reg32);
309	return VINF_SUCCESS;
310	}
311
312	/**
313	* Returns the value of the specified 64 bits general purpose register
314	*
315	*/
316	DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
317	{
318	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
319
320	*pVal = DIS_READ_REG64(pCtx, reg64);
321	return VINF_SUCCESS;
322	}
323
324	/**
325	* Returns the pointer to the specified 8 bits general purpose register
326	*
327	*/
328	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
329	{
330	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
331
332	*ppReg = DIS_PTR_REG8(pCtx, reg8);
333	return VINF_SUCCESS;
334	}
335
336	/**
337	* Returns the pointer to the specified 16 bits general purpose register
338	*
339	*/
340	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
341	{
342	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
343
344	*ppReg = DIS_PTR_REG16(pCtx, reg16);
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Returns the pointer to the specified 32 bits general purpose register
350	*
351	*/
352	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
353	{
354	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
355
356	*ppReg = DIS_PTR_REG32(pCtx, reg32);
357	return VINF_SUCCESS;
358	}
359
360	/**
361	* Returns the pointer to the specified 64 bits general purpose register
362	*
363	*/
364	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
365	{
366	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
367
368	*ppReg = DIS_PTR_REG64(pCtx, reg64);
369	return VINF_SUCCESS;
370	}
371
372	/**
373	* Returns the value of the specified segment register
374	*
375	*/
376	DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal)
377	{
378	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
379
380	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
381	*pVal = DIS_READ_REGSEG(pCtx, sel);
382	return VINF_SUCCESS;
383	}
384
385	/**
386	* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
387	*
388	*/
389	DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL pVal, CPUMSELREGHID *ppSelHidReg)
390	{
391	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
392
393	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
394	*pVal = DIS_READ_REGSEG(pCtx, sel);
395	ppSelHidReg = (CPUMSELREGHID )((char *)pCtx + g_aRegHidSegIndex[sel]);
396	return VINF_SUCCESS;
397	}
398
399	/**
400	* Updates the value of the specified 64 bits general purpose register
401	*
402	*/
403	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
404	{
405	AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
406
407	DIS_WRITE_REG64(pRegFrame, reg64, val64);
408	return VINF_SUCCESS;
409	}
410
411	/**
412	* Updates the value of the specified 32 bits general purpose register
413	*
414	*/
415	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
416	{
417	AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
418
419	DIS_WRITE_REG32(pRegFrame, reg32, val32);
420	return VINF_SUCCESS;
421	}
422
423	/**
424	* Updates the value of the specified 16 bits general purpose register
425	*
426	*/
427	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
428	{
429	AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
430
431	DIS_WRITE_REG16(pRegFrame, reg16, val16);
432	return VINF_SUCCESS;
433	}
434
435	/**
436	* Updates the specified 8 bits general purpose register
437	*
438	*/
439	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
440	{
441	AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
442
443	DIS_WRITE_REG8(pRegFrame, reg8, val8);
444	return VINF_SUCCESS;
445	}
446
447	/**
448	* Updates the specified segment register
449	*
450	*/
451	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL val)
452	{
453	AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
454
455	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
456	DIS_WRITE_REGSEG(pCtx, sel, val);
457	return VINF_SUCCESS;
458	}
459
460	/**
461	* Returns the value of the parameter in pParam
462	*
463	* @returns VBox error code
464	* @param pCtx CPU context structure pointer
465	* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
466	* set correctly.
467	* @param pParam Pointer to the parameter to parse
468	* @param pParamVal Pointer to parameter value (OUT)
469	* @param parmtype Parameter type
470	*
471	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
472	*
473	*/
474	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
475	{
476	memset(pParamVal, 0, sizeof(*pParamVal));
477
478	if (pParam->flags & (USE_BASE\|USE_INDEX\|USE_DISPLACEMENT32\|USE_DISPLACEMENT16\|USE_DISPLACEMENT8))
479	{
480	// Effective address
481	pParamVal->type = PARMTYPE_ADDRESS;
482	pParamVal->size = pParam->size;
483
484	if (pParam->flags & USE_BASE)
485	{
486	if (pParam->flags & USE_REG_GEN8)
487	{
488	pParamVal->flags \|= PARAM_VAL8;
489	if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
490	}
491	else
492	if (pParam->flags & USE_REG_GEN16)
493	{
494	pParamVal->flags \|= PARAM_VAL16;
495	if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
496	}
497	else
498	if (pParam->flags & USE_REG_GEN32)
499	{
500	pParamVal->flags \|= PARAM_VAL32;
501	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
502	}
503	else
504	if (pParam->flags & USE_REG_GEN64)
505	{
506	pParamVal->flags \|= PARAM_VAL64;
507	if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
508	}
509	else {
510	AssertFailed();
511	return VERR_INVALID_PARAMETER;
512	}
513	}
514	// Note that scale implies index (SIB byte)
515	if (pParam->flags & USE_INDEX)
516	{
517	uint32_t val32;
518
519	pParamVal->flags \|= PARAM_VAL32;
520	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
521
522	if (pParam->flags & USE_SCALE)
523	val32 *= pParam->scale;
524
525	pParamVal->val.val32 += val32;
526	}
527
528	if (pParam->flags & USE_DISPLACEMENT8)
529	{
530	if (pCpu->mode & CPUMODE_32BIT)
531	pParamVal->val.val32 += (int32_t)pParam->disp8;
532	else
533	pParamVal->val.val16 += (int16_t)pParam->disp8;
534	}
535	else
536	if (pParam->flags & USE_DISPLACEMENT16)
537	{
538	if (pCpu->mode & CPUMODE_32BIT)
539	pParamVal->val.val32 += (int32_t)pParam->disp16;
540	else
541	pParamVal->val.val16 += pParam->disp16;
542	}
543	else
544	if (pParam->flags & USE_DISPLACEMENT32)
545	{
546	if (pCpu->mode & CPUMODE_32BIT)
547	pParamVal->val.val32 += pParam->disp32;
548	else
549	AssertFailed();
550	}
551	return VINF_SUCCESS;
552	}
553
554	if (pParam->flags & (USE_REG_GEN8\|USE_REG_GEN16\|USE_REG_GEN32\|USE_REG_GEN64\|USE_REG_FP\|USE_REG_MMX\|USE_REG_XMM\|USE_REG_CR\|USE_REG_DBG\|USE_REG_SEG\|USE_REG_TEST))
555	{
556	if (parmtype == PARAM_DEST)
557	{
558	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
559	pParamVal->type = PARMTYPE_REGISTER;
560	pParamVal->size = pParam->size;
561	return VINF_SUCCESS;
562	}
563	//else PARAM_SOURCE
564
565	pParamVal->type = PARMTYPE_IMMEDIATE;
566
567	if (pParam->flags & USE_REG_GEN8)
568	{
569	pParamVal->flags \|= PARAM_VAL8;
570	pParamVal->size = sizeof(uint8_t);
571	if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
572	}
573	else
574	if (pParam->flags & USE_REG_GEN16)
575	{
576	pParamVal->flags \|= PARAM_VAL16;
577	pParamVal->size = sizeof(uint16_t);
578	if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
579	}
580	else
581	if (pParam->flags & USE_REG_GEN32)
582	{
583	pParamVal->flags \|= PARAM_VAL32;
584	pParamVal->size = sizeof(uint32_t);
585	if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
586	}
587	else
588	if (pParam->flags & USE_REG_GEN64)
589	{
590	pParamVal->flags \|= PARAM_VAL64;
591	pParamVal->size = sizeof(uint64_t);
592	if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
593	}
594	else
595	{
596	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
597	pParamVal->type = PARMTYPE_REGISTER;
598	}
599	}
600
601	if (pParam->flags & USE_IMMEDIATE)
602	{
603	pParamVal->type = PARMTYPE_IMMEDIATE;
604	if (pParam->flags & (USE_IMMEDIATE8\|USE_IMMEDIATE8_REL))
605	{
606	pParamVal->flags \|= PARAM_VAL8;
607	if (pParam->size == 2)
608	{
609	pParamVal->size = sizeof(uint16_t);
610	pParamVal->val.val16 = (uint8_t)pParam->parval;
611	}
612	else
613	{
614	pParamVal->size = sizeof(uint8_t);
615	pParamVal->val.val8 = (uint8_t)pParam->parval;
616	}
617	}
618	else
619	if (pParam->flags & (USE_IMMEDIATE16\|USE_IMMEDIATE16_REL\|USE_IMMEDIATE_ADDR_0_16\|USE_IMMEDIATE16_SX8))
620	{
621	pParamVal->flags \|= PARAM_VAL16;
622	pParamVal->size = sizeof(uint16_t);
623	pParamVal->val.val16 = (uint16_t)pParam->parval;
624	Assert(pParamVal->size == pParam->size \|\| ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)) );
625	}
626	else
627	if (pParam->flags & (USE_IMMEDIATE32\|USE_IMMEDIATE32_REL\|USE_IMMEDIATE_ADDR_0_32\|USE_IMMEDIATE32_SX8))
628	{
629	pParamVal->flags \|= PARAM_VAL32;
630	pParamVal->size = sizeof(uint32_t);
631	pParamVal->val.val32 = (uint32_t)pParam->parval;
632	Assert(pParamVal->size == pParam->size \|\| ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
633	}
634	else
635	if (pParam->flags & (USE_IMMEDIATE64))
636	{
637	pParamVal->flags \|= PARAM_VAL64;
638	pParamVal->size = sizeof(uint64_t);
639	pParamVal->val.val64 = pParam->parval;
640	Assert(pParamVal->size == pParam->size);
641	}
642	else
643	if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
644	{
645	pParamVal->flags \|= PARAM_VALFARPTR16;
646	pParamVal->size = sizeof(uint16_t)*2;
647	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
648	pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
649	Assert(pParamVal->size == pParam->size);
650	}
651	else
652	if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
653	{
654	pParamVal->flags \|= PARAM_VALFARPTR32;
655	pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
656	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
657	pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
658	Assert(pParam->size == 8);
659	}
660	}
661	return VINF_SUCCESS;
662	}
663
664	/**
665	* Returns the pointer to a register of the parameter in pParam. We need this
666	* pointer when an interpreted instruction updates a register as a side effect.
667	* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
668	* be every register.
669	*
670	* @returns VBox error code
671	* @param pCtx CPU context structure pointer
672	* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
673	* set correctly.
674	* @param pParam Pointer to the parameter to parse
675	* @param pReg Pointer to parameter value (OUT)
676	* @param cbsize Parameter size (OUT)
677	*
678	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
679	*
680	*/
681	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void *ppReg, size_t pcbSize)
682	{
683	if (pParam->flags & (USE_REG_GEN8\|USE_REG_GEN16\|USE_REG_GEN32\|USE_REG_FP\|USE_REG_MMX\|USE_REG_XMM\|USE_REG_CR\|USE_REG_DBG\|USE_REG_SEG\|USE_REG_TEST))
684	{
685	if (pParam->flags & USE_REG_GEN8)
686	{
687	uint8_t *pu8Reg;
688	if (VBOX_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
689	{
690	*pcbSize = sizeof(uint8_t);
691	ppReg = (void )pu8Reg;
692	return VINF_SUCCESS;
693	}
694	}
695	else
696	if (pParam->flags & USE_REG_GEN16)
697	{
698	uint16_t *pu16Reg;
699	if (VBOX_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
700	{
701	*pcbSize = sizeof(uint16_t);
702	ppReg = (void )pu16Reg;
703	return VINF_SUCCESS;
704	}
705	}
706	else
707	if (pParam->flags & USE_REG_GEN32)
708	{
709	uint32_t *pu32Reg;
710	if (VBOX_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
711	{
712	*pcbSize = sizeof(uint32_t);
713	ppReg = (void )pu32Reg;
714	return VINF_SUCCESS;
715	}
716	}
717	else
718	if (pParam->flags & USE_REG_GEN64)
719	{
720	uint64_t *pu64Reg;
721	if (VBOX_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
722	{
723	*pcbSize = sizeof(uint64_t);
724	ppReg = (void )pu64Reg;
725	return VINF_SUCCESS;
726	}
727	}
728	}
729	return VERR_INVALID_PARAMETER;
730	}
731	//*****************************************************************************
732	//*****************************************************************************

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source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 8373

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