DisasmTables-armv8-a64-ld-st.cpp.h@ 106746

Last change on this file since 106746 was 106746, checked in by vboxsync, 3 months ago
Disassembler: Decode SIMD ldr/str instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64-ld-st.cpp.h 106746 2024-10-28 13:14:22Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64 - Lods & Stores.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
30	*
31	* Note: The size,opc bitfields are concatenated to form an index.
32	*/
33	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
34	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
35	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
36	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
37	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
38	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
39	DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
40	DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
41	DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
42	DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
43	DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
44	DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
45	DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
46	DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
47	DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
48	DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
49	DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
50	INVALID_OPCODE,
51	DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
52	DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
53	INVALID_OPCODE, /** @todo PRFM */
54	INVALID_OPCODE,
55	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /fFixedInsn/,
56	kDisArmV8OpcDecodeCollate,
57	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
58
59
60	/* SIMD STR/LDR */
61	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmSimd)
62	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
63	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /idxParam/),
64	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
65	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
66	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUImmSimd128)
67	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
68	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /idxParam/),
69	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
70	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
71	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmSimd)
72	DIS_ARMV8_OP( 0x3d000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
73	DIS_ARMV8_OP( 0x3d400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
74	DIS_ARMV8_OP_ALT_DECODE(0x3d800000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
75	DIS_ARMV8_OP_ALT_DECODE(0x3dc00000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
76	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmSimd, 0x3fc00000 /fFixedInsn/,
77	kDisArmV8OpcDecodeNop,
78	RT_BIT_32(22) \| RT_BIT_32(23), 22);
79
80
81	/*
82	* C4.1.94 - Loads and Stores - Load/Store register variants
83	*
84	* Differentiate further based on the VR field.
85	*
86	* Bit 26
87	* +-------------------------------------------
88	* 0 GPR variants.
89	* 1 SIMD/FP variants
90	*/
91	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
92	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
93	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmSimd),
94	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
95
96
97	/*
98	* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
99	*
100	* Note: The size,opc bitfields are concatenated to form an index.
101	*/
102	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
103	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
104	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
105	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /idxParam/),
109	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
110	DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
111	DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
112	DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
113	DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
114	DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
115	DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
116	DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
117	DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
118	DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
119	DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
120	DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
121	INVALID_OPCODE,
122	DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
123	DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
124	INVALID_OPCODE, /** @todo PRFM */
125	INVALID_OPCODE,
126	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /fFixedInsn/,
127	kDisArmV8OpcDecodeCollate,
128	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
129
130
131	/*
132	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
133	*
134	* Differentiate further based on the VR field.
135	*
136	* Bit 26
137	* +-------------------------------------------
138	* 0 GPR variants.
139	* 1 SIMD/FP variants
140	*/
141	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
142	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
143	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
144	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
145
146
147	/*
148	* C4.1.94 - Loads and Stores - Load/Store register variants
149	*
150	* Differentiate further based on the op2<1:0> field.
151	*
152	* Bit 11 10
153	* +-------------------------------------------
154	* 0 0 Atomic memory operations
155	* 0 1 Load/store register (pac)
156	* 1 0 Load/store register (register offset)
157	* 1 1 Load/store register (pac)
158	*/
159	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
160	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
161	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
162	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
163	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
164	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
165
166
167	/*
168	* STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
169	*
170	* Note: The size,opc bitfields are concatenated to form an index.
171	*/
172	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
173	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
174	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
175	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
176	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
177	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
178	DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
179	DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
180	DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
181	DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
182	DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
183	DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
184	DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
185	DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
186	DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
187	DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
188	DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
189	INVALID_OPCODE,
190	DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
191	DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
192	INVALID_OPCODE, /** @todo PRFUM */
193	INVALID_OPCODE,
194	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /fFixedInsn/,
195	kDisArmV8OpcDecodeCollate,
196	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
197
198
199	/*
200	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
201	*
202	* Differentiate further based on the VR field.
203	*
204	* Bit 26
205	* +-------------------------------------------
206	* 0 GPR variants.
207	* 1 SIMD/FP variants
208	*/
209	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
210	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
211	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
212	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
213
214
215	/*
216	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
217	*
218	* Note: The size,opc bitfields are concatenated to form an index.
219	*/
220	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
221	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
222	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
223	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
224	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
225	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /idxParam/),
226	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
227	DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
228	DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
229	DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
230	DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
231	DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
232	DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
234	DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
235	DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
236	DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
237	DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
238	INVALID_OPCODE,
239	DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
240	DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
241	INVALID_OPCODE,
242	INVALID_OPCODE,
243	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /fFixedInsn/,
244	kDisArmV8OpcDecodeCollate,
245	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
246
247
248	/*
249	* C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
250	*
251	* Differentiate further based on the VR field.
252	*
253	* Bit 26
254	* +-------------------------------------------
255	* 0 GPR variants.
256	* 1 SIMD/FP variants
257	*/
258	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
259	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
260	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
261	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
262
263
264	/*
265	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
266	*
267	* Note: The size,opc bitfields are concatenated to form an index.
268	*/
269	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
270	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
271	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
272	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
273	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
274	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /idxParam/),
275	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
276	DIS_ARMV8_OP(0x38000400, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
277	DIS_ARMV8_OP(0x38400400, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
278	DIS_ARMV8_OP_EX(0x38800400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
279	DIS_ARMV8_OP_EX(0x38c00400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
280	DIS_ARMV8_OP(0x78000400, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
281	DIS_ARMV8_OP(0x78400400, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
282	DIS_ARMV8_OP_EX(0x78800400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
283	DIS_ARMV8_OP_EX(0x78c00400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
284	DIS_ARMV8_OP(0xb8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
285	DIS_ARMV8_OP(0xb8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
286	DIS_ARMV8_OP_EX(0xb8800400, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
287	INVALID_OPCODE,
288	DIS_ARMV8_OP(0xf8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
289	DIS_ARMV8_OP(0xf8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
290	INVALID_OPCODE,
291	INVALID_OPCODE,
292	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /fFixedInsn/,
293	kDisArmV8OpcDecodeCollate,
294	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
295
296
297	/*
298	* C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
299	*
300	* Differentiate further based on the VR field.
301	*
302	* Bit 26
303	* +-------------------------------------------
304	* 0 GPR variants.
305	* 1 SIMD/FP variants
306	*/
307	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
308	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
309	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
310	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
311
312
313	/*
314	* STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
315	*
316	* Note: The size,opc bitfields are concatenated to form an index.
317	*/
318	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
319	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
320	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
321	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
322	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
323	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
324	DIS_ARMV8_OP(0x38000800, "sttrb", OP_ARMV8_A64_STTRB, DISOPTYPE_HARMLESS),
325	DIS_ARMV8_OP(0x38400800, "ldtrb", OP_ARMV8_A64_LDTRB, DISOPTYPE_HARMLESS),
326	DIS_ARMV8_OP_EX(0x38800800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
327	DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
328	DIS_ARMV8_OP(0x78000800, "sttrh", OP_ARMV8_A64_STTRH, DISOPTYPE_HARMLESS),
329	DIS_ARMV8_OP(0x78400800, "ldtrh", OP_ARMV8_A64_LDTRH, DISOPTYPE_HARMLESS),
330	DIS_ARMV8_OP_EX(0x78800800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
331	DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
332	DIS_ARMV8_OP(0xb8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
333	DIS_ARMV8_OP(0xb8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
334	DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw", OP_ARMV8_A64_LDTRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
335	INVALID_OPCODE,
336	DIS_ARMV8_OP(0xf8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
337	DIS_ARMV8_OP(0xf8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
338	INVALID_OPCODE,
339	INVALID_OPCODE,
340	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /fFixedInsn/,
341	kDisArmV8OpcDecodeCollate,
342	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
343
344
345	/*
346	* C4.1.94 - Loads and Stores - Load/Store register variants
347	*
348	* Differentiate further based on the op2<1:0> field.
349	*
350	* Bit 11 10
351	* +-------------------------------------------
352	* 0 0 Load/store register (unscaled immediate)
353	* 0 1 Load/store register (immediate post-indexed)
354	* 1 0 Load/store register (unprivileged)
355	* 1 1 Load/store register (immediate pre-indexed)
356	*/
357	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
358	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
359	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
360	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv), /* No vector variants. */
361	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
362	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) \| RT_BIT_32(11), 10);
363
364
365	/*
366	* C4.1.94 - Loads and Stores - Load/Store register variants
367	*
368	* Differentiate further based on the op2<11> field.
369	*
370	* Bit 21
371	* +-------------------------------------------
372	* 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
373	* 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
374	*/
375	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
376	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
377	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
378	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
379
380
381	/*
382	* C4.1.94 - Loads and Stores - Load/Store register variants
383	*
384	* Differentiate further based on the op2<14> field.
385	*
386	* Bit 24
387	* +-------------------------------------------
388	* 0 All the other Load/store register variants and Atomic memory operations.
389	* 1 Load/store register (unsigned immediate).
390	*/
391	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
392	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
393	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
394	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
395
396
397	/*
398	* STP/LDP/STGP/LDPSW
399	*
400	* Note: The opc,L bitfields are concatenated to form an index.
401	*/
402	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
403	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
404	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
405	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
406	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
407	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
408	DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
409	DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
410	INVALID_OPCODE,
411	INVALID_OPCODE,
412	DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
413	DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
414	INVALID_OPCODE,
415	INVALID_OPCODE,
416	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /fFixedInsn/,
417	kDisArmV8OpcDecodeCollate,
418	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
419
420
421	/*
422	* STP/LDP/STGP/LDPSW - pre-indexed variant.
423	*
424	* Note: The opc,L bitfields are concatenated to form an index.
425	*/
426	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
427	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
428	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
429	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
430	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
431	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /idxParam/),
432	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
433	DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
434	DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
435	INVALID_OPCODE,
436	INVALID_OPCODE,
437	DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
438	DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
439	INVALID_OPCODE,
440	INVALID_OPCODE,
441	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /fFixedInsn/,
442	kDisArmV8OpcDecodeCollate,
443	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
444
445
446	/*
447	* STP/LDP/STGP/LDPSW - post-indexed variant.
448	*
449	* Note: The opc,L bitfields are concatenated to form an index.
450	*/
451	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
452	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
453	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
454	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
455	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
456	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /idxParam/),
457	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
458	DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
459	DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
460	INVALID_OPCODE,
461	INVALID_OPCODE,
462	DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
463	DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
464	INVALID_OPCODE,
465	INVALID_OPCODE,
466	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /fFixedInsn/,
467	kDisArmV8OpcDecodeCollate,
468	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
469
470
471	/*
472	* stnp/LDNP - no-allocate variant.
473	*
474	* Note: The opc,L bitfields are concatenated to form an index.
475	*/
476	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocGpr)
477	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
478	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
479	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
480	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
481	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocGpr)
482	DIS_ARMV8_OP_EX(0x28000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
483	DIS_ARMV8_OP_EX(0x28400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
484	INVALID_OPCODE,
485	INVALID_OPCODE,
486	DIS_ARMV8_OP_EX(0xa8000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
487	DIS_ARMV8_OP_EX(0xa8400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
488	INVALID_OPCODE,
489	INVALID_OPCODE,
490	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocGpr, 0xffc00000 /fFixedInsn/,
491	kDisArmV8OpcDecodeCollate,
492	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
493
494
495	/*
496	* C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
497	*
498	* Differentiate further based on the VR field.
499	*
500	* Bit 26
501	* +-------------------------------------------
502	* 0 GPR variants.
503	* 1 SIMD/FP variants
504	*/
505	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
506	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
507	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
508	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
509
510
511	/*
512	* C4.1.94 - Loads and Stores - Load/Store register pair variants
513	*
514	* Differentiate further based on the op2<14:13> field.
515	*
516	* Bit 24 23
517	* +-------------------------------------------
518	* 0 0 Load/store no-allocate pair (offset)
519	* 0 1 Load/store register pair (post-indexed)
520	* 1 0 Load/store register pair (offset).
521	* 1 1 Load/store register pair (pre-indexed).
522	*/
523	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
524	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAlloc),
525	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
526	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
527	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
528	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) \| RT_BIT_32(24), 23);
529
530
531	/*
532	* C4.1.94 - Loads and Stores
533	*
534	* Differentiate further based on the op0<1:0> field.
535	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
536	*
537	* Bit 29 28
538	* +-------------------------------------------
539	* 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
540	* Load/store ordered / Compare and swap
541	* 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
542	* LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
543	* 1 0 Load/store no-allocate pair / Load/store register pair /
544	* 1 1 Load/store register / Atomic memory operations
545	*/
546	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
547	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
548	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
549	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
550	DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
551	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) \| RT_BIT_32(29), 28);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h@ 106746

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