VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h@ 106752

Last change on this file since 106752 was 106752, checked in by vboxsync, 3 months ago

Disassembler: Decode SIMD ldur/stur (unscaled immediate) instructions, bugref:10394

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1/* $Id: DisasmTables-armv8-a64-ld-st.cpp.h 106752 2024-10-28 14:09:29Z vboxsync $ */
2/** @file
3 * VBox disassembler - Tables for ARMv8 A64 - Lods & Stores.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
30 *
31 * Note: The size,opc bitfields are concatenated to form an index.
32 */
33DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
34 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
35 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
36 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
37 DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
38DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
39 DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
40 DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
41 DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
42 DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
43 DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
44 DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
45 DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
46 DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
47 DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
48 DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
49 DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
50 INVALID_OPCODE,
51 DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
52 DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
53 INVALID_OPCODE, /** @todo PRFM */
54 INVALID_OPCODE,
55DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /*fFixedInsn*/,
56 kDisArmV8OpcDecodeCollate,
57 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
58
59
60/* SIMD STR/LDR */
61DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmSimd)
62 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
63 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
64 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
65 DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
66DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUImmSimd128)
67 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
68 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
69 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
70 DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
71DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmSimd)
72 DIS_ARMV8_OP( 0x3d000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
73 DIS_ARMV8_OP( 0x3d400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
74 DIS_ARMV8_OP_ALT_DECODE(0x3d800000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
75 DIS_ARMV8_OP_ALT_DECODE(0x3dc00000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
76DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmSimd, 0x3fc00000 /*fFixedInsn*/,
77 kDisArmV8OpcDecodeNop,
78 RT_BIT_32(22) | RT_BIT_32(23), 22);
79
80
81/*
82 * C4.1.94 - Loads and Stores - Load/Store register variants
83 *
84 * Differentiate further based on the VR field.
85 *
86 * Bit 26
87 * +-------------------------------------------
88 * 0 GPR variants.
89 * 1 SIMD/FP variants
90 */
91DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
92 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
93 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmSimd),
94DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
95
96
97/*
98 * STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
99 *
100 * Note: The size,opc bitfields are concatenated to form an index.
101 */
102DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
103 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
104 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
105 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
106 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
107 DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
108 DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
109DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
110 DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
111 DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
112 DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
113 DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
114 DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
115 DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
116 DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
117 DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
118 DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
119 DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
120 DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
121 INVALID_OPCODE,
122 DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
123 DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
124 INVALID_OPCODE, /** @todo PRFM */
125 INVALID_OPCODE,
126DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /*fFixedInsn*/,
127 kDisArmV8OpcDecodeCollate,
128 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
129
130
131/* SIMD LDR/STR */
132DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffSimd)
133 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
134 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
135 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
136 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
137 DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
138 DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
139DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegOffSimd128)
140 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
141 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
142 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
143 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
144 DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
145 DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
146DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffSimd)
147 DIS_ARMV8_OP( 0x3c200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
148 DIS_ARMV8_OP( 0x3c600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
149 DIS_ARMV8_OP_ALT_DECODE(0x3ca00800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS, LdStRegOffSimd128), /** @todo size == 0. */
150 DIS_ARMV8_OP_ALT_DECODE(0x3ce00800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS, LdStRegOffSimd128), /** @todo size == 0. */
151DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffSimd, 0x3fe00c00 /*fFixedInsn*/,
152 kDisArmV8OpcDecodeNop,
153 RT_BIT_32(22) | RT_BIT_32(23), 22);
154
155
156/*
157 * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
158 *
159 * Differentiate further based on the VR field.
160 *
161 * Bit 26
162 * +-------------------------------------------
163 * 0 GPR variants.
164 * 1 SIMD/FP variants
165 */
166DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
167 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
168 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffSimd),
169DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
170
171
172/*
173 * C4.1.94 - Loads and Stores - Load/Store register variants
174 *
175 * Differentiate further based on the op2<1:0> field.
176 *
177 * Bit 11 10
178 * +-------------------------------------------
179 * 0 0 Atomic memory operations
180 * 0 1 Load/store register (pac)
181 * 1 0 Load/store register (register offset)
182 * 1 1 Load/store register (pac)
183 */
184DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
185 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
186 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
187 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
188 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
189DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) | RT_BIT_32(11), 10);
190
191
192/*
193 * STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
194 *
195 * Note: The size,opc bitfields are concatenated to form an index.
196 */
197DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
198 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
199 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
200 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
201 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
202DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
203 DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
204 DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
205 DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
206 DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
207 DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
208 DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
209 DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
210 DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
211 DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
212 DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
213 DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
214 INVALID_OPCODE,
215 DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
216 DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
217 INVALID_OPCODE, /** @todo PRFUM */
218 INVALID_OPCODE,
219DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /*fFixedInsn*/,
220 kDisArmV8OpcDecodeCollate,
221 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
222
223
224/* SIMD STUR/LDUR */
225DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmSimd)
226 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
227 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
228 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
229 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
230DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUnscaledImmSimd128)
231 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
232 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
233 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
234 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
235DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmSimd)
236 DIS_ARMV8_OP( 0x3c000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
237 DIS_ARMV8_OP( 0x3c400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
238 DIS_ARMV8_OP_ALT_DECODE(0x3c800000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
239 DIS_ARMV8_OP_ALT_DECODE(0x3cc00000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
240DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmSimd, 0x3fe00c00 /*fFixedInsn*/,
241 kDisArmV8OpcDecodeNop,
242 RT_BIT_32(22) | RT_BIT_32(23), 22);
243
244
245/*
246 * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
247 *
248 * Differentiate further based on the VR field.
249 *
250 * Bit 26
251 * +-------------------------------------------
252 * 0 GPR variants.
253 * 1 SIMD/FP variants
254 */
255DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
256 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
257 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmSimd),
258DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
259
260
261/*
262 * STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
263 *
264 * Note: The size,opc bitfields are concatenated to form an index.
265 */
266DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
267 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
268 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
269 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
270 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
271 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /*idxParam*/),
272DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
273 DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
274 DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
275 DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
276 DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
277 DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
278 DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
279 DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
280 DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
281 DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
282 DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
283 DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
284 INVALID_OPCODE,
285 DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
286 DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
287 INVALID_OPCODE,
288 INVALID_OPCODE,
289DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /*fFixedInsn*/,
290 kDisArmV8OpcDecodeCollate,
291 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
292
293
294/*
295 * C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
296 *
297 * Differentiate further based on the VR field.
298 *
299 * Bit 26
300 * +-------------------------------------------
301 * 0 GPR variants.
302 * 1 SIMD/FP variants
303 */
304DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
305 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
306 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
307DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
308
309
310/*
311 * STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
312 *
313 * Note: The size,opc bitfields are concatenated to form an index.
314 */
315DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
316 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
317 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
318 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
319 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
320 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/),
321DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
322 DIS_ARMV8_OP(0x38000400, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
323 DIS_ARMV8_OP(0x38400400, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
324 DIS_ARMV8_OP_EX(0x38800400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
325 DIS_ARMV8_OP_EX(0x38c00400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
326 DIS_ARMV8_OP(0x78000400, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
327 DIS_ARMV8_OP(0x78400400, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
328 DIS_ARMV8_OP_EX(0x78800400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
329 DIS_ARMV8_OP_EX(0x78c00400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
330 DIS_ARMV8_OP(0xb8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
331 DIS_ARMV8_OP(0xb8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
332 DIS_ARMV8_OP_EX(0xb8800400, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
333 INVALID_OPCODE,
334 DIS_ARMV8_OP(0xf8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
335 DIS_ARMV8_OP(0xf8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
336 INVALID_OPCODE,
337 INVALID_OPCODE,
338DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /*fFixedInsn*/,
339 kDisArmV8OpcDecodeCollate,
340 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
341
342
343/*
344 * C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
345 *
346 * Differentiate further based on the VR field.
347 *
348 * Bit 26
349 * +-------------------------------------------
350 * 0 GPR variants.
351 * 1 SIMD/FP variants
352 */
353DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
354 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
355 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
356DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
357
358
359/*
360 * STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
361 *
362 * Note: The size,opc bitfields are concatenated to form an index.
363 */
364DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
365 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
366 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
367 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
368 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
369DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
370 DIS_ARMV8_OP(0x38000800, "sttrb", OP_ARMV8_A64_STTRB, DISOPTYPE_HARMLESS),
371 DIS_ARMV8_OP(0x38400800, "ldtrb", OP_ARMV8_A64_LDTRB, DISOPTYPE_HARMLESS),
372 DIS_ARMV8_OP_EX(0x38800800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
373 DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
374 DIS_ARMV8_OP(0x78000800, "sttrh", OP_ARMV8_A64_STTRH, DISOPTYPE_HARMLESS),
375 DIS_ARMV8_OP(0x78400800, "ldtrh", OP_ARMV8_A64_LDTRH, DISOPTYPE_HARMLESS),
376 DIS_ARMV8_OP_EX(0x78800800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
377 DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
378 DIS_ARMV8_OP(0xb8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
379 DIS_ARMV8_OP(0xb8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
380 DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw", OP_ARMV8_A64_LDTRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
381 INVALID_OPCODE,
382 DIS_ARMV8_OP(0xf8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
383 DIS_ARMV8_OP(0xf8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
384 INVALID_OPCODE,
385 INVALID_OPCODE,
386DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /*fFixedInsn*/,
387 kDisArmV8OpcDecodeCollate,
388 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
389
390
391/*
392 * C4.1.94 - Loads and Stores - Load/Store register variants
393 *
394 * Differentiate further based on the op2<1:0> field.
395 *
396 * Bit 11 10
397 * +-------------------------------------------
398 * 0 0 Load/store register (unscaled immediate)
399 * 0 1 Load/store register (immediate post-indexed)
400 * 1 0 Load/store register (unprivileged)
401 * 1 1 Load/store register (immediate pre-indexed)
402 */
403DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
404 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
405 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
406 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv), /* No vector variants. */
407 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
408DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) | RT_BIT_32(11), 10);
409
410
411/*
412 * C4.1.94 - Loads and Stores - Load/Store register variants
413 *
414 * Differentiate further based on the op2<11> field.
415 *
416 * Bit 21
417 * +-------------------------------------------
418 * 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
419 * 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
420 */
421DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
422 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
423 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
424DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
425
426
427/*
428 * C4.1.94 - Loads and Stores - Load/Store register variants
429 *
430 * Differentiate further based on the op2<14> field.
431 *
432 * Bit 24
433 * +-------------------------------------------
434 * 0 All the other Load/store register variants and Atomic memory operations.
435 * 1 Load/store register (unsigned immediate).
436 */
437DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
438 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
439 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
440DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
441
442
443/*
444 * STP/LDP/STGP/LDPSW
445 *
446 * Note: The opc,L bitfields are concatenated to form an index.
447 */
448DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
449 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
450 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
451 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
452 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
453DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
454 DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
455 DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
456 INVALID_OPCODE,
457 INVALID_OPCODE,
458 DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
459 DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
460 INVALID_OPCODE,
461 INVALID_OPCODE,
462DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /*fFixedInsn*/,
463 kDisArmV8OpcDecodeCollate,
464 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
465
466
467/*
468 * STP/LDP/STGP/LDPSW - pre-indexed variant.
469 *
470 * Note: The opc,L bitfields are concatenated to form an index.
471 */
472DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
473 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
474 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
475 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
476 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
477 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /*idxParam*/),
478DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
479 DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
480 DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
481 INVALID_OPCODE,
482 INVALID_OPCODE,
483 DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
484 DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
485 INVALID_OPCODE,
486 INVALID_OPCODE,
487DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /*fFixedInsn*/,
488 kDisArmV8OpcDecodeCollate,
489 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
490
491
492/*
493 * STP/LDP/STGP/LDPSW - post-indexed variant.
494 *
495 * Note: The opc,L bitfields are concatenated to form an index.
496 */
497DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
498 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
499 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
500 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
501 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
502 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /*idxParam*/),
503DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
504 DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
505 DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
506 INVALID_OPCODE,
507 INVALID_OPCODE,
508 DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
509 DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
510 INVALID_OPCODE,
511 INVALID_OPCODE,
512DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /*fFixedInsn*/,
513 kDisArmV8OpcDecodeCollate,
514 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
515
516
517/*
518 * stnp/LDNP - no-allocate variant.
519 *
520 * Note: The opc,L bitfields are concatenated to form an index.
521 */
522DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocGpr)
523 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
524 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
525 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
526 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
527DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocGpr)
528 DIS_ARMV8_OP_EX(0x28000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
529 DIS_ARMV8_OP_EX(0x28400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
530 INVALID_OPCODE,
531 INVALID_OPCODE,
532 DIS_ARMV8_OP_EX(0xa8000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
533 DIS_ARMV8_OP_EX(0xa8400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
534 INVALID_OPCODE,
535 INVALID_OPCODE,
536DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocGpr, 0xffc00000 /*fFixedInsn*/,
537 kDisArmV8OpcDecodeCollate,
538 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
539
540
541/*
542 * C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
543 *
544 * Differentiate further based on the VR field.
545 *
546 * Bit 26
547 * +-------------------------------------------
548 * 0 GPR variants.
549 * 1 SIMD/FP variants
550 */
551DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
552 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
553 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
554DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
555
556
557/*
558 * C4.1.94 - Loads and Stores - Load/Store register pair variants
559 *
560 * Differentiate further based on the op2<14:13> field.
561 *
562 * Bit 24 23
563 * +-------------------------------------------
564 * 0 0 Load/store no-allocate pair (offset)
565 * 0 1 Load/store register pair (post-indexed)
566 * 1 0 Load/store register pair (offset).
567 * 1 1 Load/store register pair (pre-indexed).
568 */
569DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
570 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAlloc),
571 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
572 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
573 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
574DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) | RT_BIT_32(24), 23);
575
576
577/*
578 * C4.1.94 - Loads and Stores
579 *
580 * Differentiate further based on the op0<1:0> field.
581 * Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
582 *
583 * Bit 29 28
584 * +-------------------------------------------
585 * 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
586 * Load/store ordered / Compare and swap
587 * 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
588 * LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
589 * 1 0 Load/store no-allocate pair / Load/store register pair /
590 * 1 1 Load/store register / Atomic memory operations
591 */
592DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
593 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
594 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
595 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
596 DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
597DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) | RT_BIT_32(29), 28);
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