1 | /* $Id: DisasmTables-armv8-a64-ld-st.cpp.h 106752 2024-10-28 14:09:29Z vboxsync $ */
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2 | /** @file
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3 | * VBox disassembler - Tables for ARMv8 A64 - Lods & Stores.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2023-2024 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
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30 | *
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31 | * Note: The size,opc bitfields are concatenated to form an index.
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32 | */
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33 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
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34 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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35 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
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36 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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37 | DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
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38 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
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39 | DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
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40 | DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
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41 | DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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42 | DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
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43 | DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
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44 | DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
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45 | DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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46 | DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
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47 | DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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48 | DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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49 | DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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50 | INVALID_OPCODE,
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51 | DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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52 | DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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53 | INVALID_OPCODE, /** @todo PRFM */
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54 | INVALID_OPCODE,
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55 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /*fFixedInsn*/,
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56 | kDisArmV8OpcDecodeCollate,
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57 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
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58 |
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59 |
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60 | /* SIMD STR/LDR */
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61 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmSimd)
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62 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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63 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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64 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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65 | DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
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66 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUImmSimd128)
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67 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
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68 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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69 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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70 | DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
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71 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmSimd)
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72 | DIS_ARMV8_OP( 0x3d000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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73 | DIS_ARMV8_OP( 0x3d400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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74 | DIS_ARMV8_OP_ALT_DECODE(0x3d800000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
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75 | DIS_ARMV8_OP_ALT_DECODE(0x3dc00000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS, LdStRegUImmSimd128), /** @todo size == 0. */
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76 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmSimd, 0x3fc00000 /*fFixedInsn*/,
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77 | kDisArmV8OpcDecodeNop,
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78 | RT_BIT_32(22) | RT_BIT_32(23), 22);
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79 |
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80 |
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81 | /*
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82 | * C4.1.94 - Loads and Stores - Load/Store register variants
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83 | *
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84 | * Differentiate further based on the VR field.
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85 | *
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86 | * Bit 26
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87 | * +-------------------------------------------
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88 | * 0 GPR variants.
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89 | * 1 SIMD/FP variants
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90 | */
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91 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
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92 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
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93 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmSimd),
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94 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
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95 |
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96 |
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97 | /*
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98 | * STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
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99 | *
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100 | * Note: The size,opc bitfields are concatenated to form an index.
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101 | */
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102 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
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103 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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104 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
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105 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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106 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
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107 | DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
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108 | DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
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109 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
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110 | DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
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111 | DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
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112 | DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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113 | DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
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114 | DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
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115 | DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
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116 | DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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117 | DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
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118 | DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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119 | DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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120 | DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
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121 | INVALID_OPCODE,
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122 | DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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123 | DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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124 | INVALID_OPCODE, /** @todo PRFM */
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125 | INVALID_OPCODE,
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126 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /*fFixedInsn*/,
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127 | kDisArmV8OpcDecodeCollate,
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128 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
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129 |
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130 |
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131 | /* SIMD LDR/STR */
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132 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffSimd)
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133 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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134 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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135 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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136 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
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137 | DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
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138 | DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
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139 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegOffSimd128)
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140 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
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141 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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142 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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143 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
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144 | DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
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145 | DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
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146 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffSimd)
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147 | DIS_ARMV8_OP( 0x3c200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
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148 | DIS_ARMV8_OP( 0x3c600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
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149 | DIS_ARMV8_OP_ALT_DECODE(0x3ca00800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS, LdStRegOffSimd128), /** @todo size == 0. */
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150 | DIS_ARMV8_OP_ALT_DECODE(0x3ce00800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS, LdStRegOffSimd128), /** @todo size == 0. */
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151 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffSimd, 0x3fe00c00 /*fFixedInsn*/,
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152 | kDisArmV8OpcDecodeNop,
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153 | RT_BIT_32(22) | RT_BIT_32(23), 22);
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154 |
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155 |
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156 | /*
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157 | * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
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158 | *
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159 | * Differentiate further based on the VR field.
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160 | *
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161 | * Bit 26
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162 | * +-------------------------------------------
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163 | * 0 GPR variants.
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164 | * 1 SIMD/FP variants
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165 | */
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166 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
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167 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
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168 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffSimd),
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169 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
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170 |
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171 |
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172 | /*
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173 | * C4.1.94 - Loads and Stores - Load/Store register variants
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174 | *
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175 | * Differentiate further based on the op2<1:0> field.
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176 | *
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177 | * Bit 11 10
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178 | * +-------------------------------------------
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179 | * 0 0 Atomic memory operations
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180 | * 0 1 Load/store register (pac)
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181 | * 1 0 Load/store register (register offset)
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182 | * 1 1 Load/store register (pac)
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183 | */
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184 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
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185 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
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186 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
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187 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
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188 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
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189 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) | RT_BIT_32(11), 10);
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190 |
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191 |
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192 | /*
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193 | * STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
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194 | *
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195 | * Note: The size,opc bitfields are concatenated to form an index.
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196 | */
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197 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
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198 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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199 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
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200 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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201 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
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202 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
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203 | DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
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204 | DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
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205 | DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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206 | DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
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207 | DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
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208 | DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
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209 | DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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210 | DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
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211 | DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
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212 | DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
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213 | DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
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214 | INVALID_OPCODE,
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215 | DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
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216 | DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
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217 | INVALID_OPCODE, /** @todo PRFUM */
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218 | INVALID_OPCODE,
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219 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /*fFixedInsn*/,
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220 | kDisArmV8OpcDecodeCollate,
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221 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
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222 |
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223 |
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224 | /* SIMD STUR/LDUR */
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225 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmSimd)
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226 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
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227 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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228 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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229 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
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230 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUnscaledImmSimd128)
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231 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
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232 | DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /*idxParam*/),
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233 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
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234 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
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235 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmSimd)
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236 | DIS_ARMV8_OP( 0x3c000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
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237 | DIS_ARMV8_OP( 0x3c400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
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238 | DIS_ARMV8_OP_ALT_DECODE(0x3c800000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
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239 | DIS_ARMV8_OP_ALT_DECODE(0x3cc00000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
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240 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmSimd, 0x3fe00c00 /*fFixedInsn*/,
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241 | kDisArmV8OpcDecodeNop,
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242 | RT_BIT_32(22) | RT_BIT_32(23), 22);
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243 |
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244 |
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245 | /*
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246 | * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
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247 | *
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248 | * Differentiate further based on the VR field.
|
---|
249 | *
|
---|
250 | * Bit 26
|
---|
251 | * +-------------------------------------------
|
---|
252 | * 0 GPR variants.
|
---|
253 | * 1 SIMD/FP variants
|
---|
254 | */
|
---|
255 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
|
---|
256 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
|
---|
257 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmSimd),
|
---|
258 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
|
---|
259 |
|
---|
260 |
|
---|
261 | /*
|
---|
262 | * STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
|
---|
263 | *
|
---|
264 | * Note: The size,opc bitfields are concatenated to form an index.
|
---|
265 | */
|
---|
266 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
|
---|
267 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
|
---|
268 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
269 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
|
---|
270 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
|
---|
271 | DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /*idxParam*/),
|
---|
272 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
|
---|
273 | DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
|
---|
274 | DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
|
---|
275 | DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
276 | DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
277 | DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
|
---|
278 | DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
|
---|
279 | DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
280 | DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
281 | DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
|
---|
282 | DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
|
---|
283 | DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
284 | INVALID_OPCODE,
|
---|
285 | DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
|
---|
286 | DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
|
---|
287 | INVALID_OPCODE,
|
---|
288 | INVALID_OPCODE,
|
---|
289 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /*fFixedInsn*/,
|
---|
290 | kDisArmV8OpcDecodeCollate,
|
---|
291 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
292 |
|
---|
293 |
|
---|
294 | /*
|
---|
295 | * C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
|
---|
296 | *
|
---|
297 | * Differentiate further based on the VR field.
|
---|
298 | *
|
---|
299 | * Bit 26
|
---|
300 | * +-------------------------------------------
|
---|
301 | * 0 GPR variants.
|
---|
302 | * 1 SIMD/FP variants
|
---|
303 | */
|
---|
304 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
|
---|
305 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
|
---|
306 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
|
---|
307 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
|
---|
308 |
|
---|
309 |
|
---|
310 | /*
|
---|
311 | * STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
|
---|
312 | *
|
---|
313 | * Note: The size,opc bitfields are concatenated to form an index.
|
---|
314 | */
|
---|
315 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
|
---|
316 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
|
---|
317 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
318 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
|
---|
319 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
|
---|
320 | DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/),
|
---|
321 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
|
---|
322 | DIS_ARMV8_OP(0x38000400, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
|
---|
323 | DIS_ARMV8_OP(0x38400400, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
|
---|
324 | DIS_ARMV8_OP_EX(0x38800400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
325 | DIS_ARMV8_OP_EX(0x38c00400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
326 | DIS_ARMV8_OP(0x78000400, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
|
---|
327 | DIS_ARMV8_OP(0x78400400, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
|
---|
328 | DIS_ARMV8_OP_EX(0x78800400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
329 | DIS_ARMV8_OP_EX(0x78c00400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
330 | DIS_ARMV8_OP(0xb8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
|
---|
331 | DIS_ARMV8_OP(0xb8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
|
---|
332 | DIS_ARMV8_OP_EX(0xb8800400, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
333 | INVALID_OPCODE,
|
---|
334 | DIS_ARMV8_OP(0xf8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
|
---|
335 | DIS_ARMV8_OP(0xf8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
|
---|
336 | INVALID_OPCODE,
|
---|
337 | INVALID_OPCODE,
|
---|
338 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /*fFixedInsn*/,
|
---|
339 | kDisArmV8OpcDecodeCollate,
|
---|
340 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
341 |
|
---|
342 |
|
---|
343 | /*
|
---|
344 | * C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
|
---|
345 | *
|
---|
346 | * Differentiate further based on the VR field.
|
---|
347 | *
|
---|
348 | * Bit 26
|
---|
349 | * +-------------------------------------------
|
---|
350 | * 0 GPR variants.
|
---|
351 | * 1 SIMD/FP variants
|
---|
352 | */
|
---|
353 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
|
---|
354 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
|
---|
355 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
|
---|
356 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
|
---|
357 |
|
---|
358 |
|
---|
359 | /*
|
---|
360 | * STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
|
---|
361 | *
|
---|
362 | * Note: The size,opc bitfields are concatenated to form an index.
|
---|
363 | */
|
---|
364 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
|
---|
365 | DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
|
---|
366 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
367 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/),
|
---|
368 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
|
---|
369 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
|
---|
370 | DIS_ARMV8_OP(0x38000800, "sttrb", OP_ARMV8_A64_STTRB, DISOPTYPE_HARMLESS),
|
---|
371 | DIS_ARMV8_OP(0x38400800, "ldtrb", OP_ARMV8_A64_LDTRB, DISOPTYPE_HARMLESS),
|
---|
372 | DIS_ARMV8_OP_EX(0x38800800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
373 | DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
374 | DIS_ARMV8_OP(0x78000800, "sttrh", OP_ARMV8_A64_STTRH, DISOPTYPE_HARMLESS),
|
---|
375 | DIS_ARMV8_OP(0x78400800, "ldtrh", OP_ARMV8_A64_LDTRH, DISOPTYPE_HARMLESS),
|
---|
376 | DIS_ARMV8_OP_EX(0x78800800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
377 | DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
378 | DIS_ARMV8_OP(0xb8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
|
---|
379 | DIS_ARMV8_OP(0xb8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
|
---|
380 | DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw", OP_ARMV8_A64_LDTRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
381 | INVALID_OPCODE,
|
---|
382 | DIS_ARMV8_OP(0xf8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
|
---|
383 | DIS_ARMV8_OP(0xf8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
|
---|
384 | INVALID_OPCODE,
|
---|
385 | INVALID_OPCODE,
|
---|
386 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /*fFixedInsn*/,
|
---|
387 | kDisArmV8OpcDecodeCollate,
|
---|
388 | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
389 |
|
---|
390 |
|
---|
391 | /*
|
---|
392 | * C4.1.94 - Loads and Stores - Load/Store register variants
|
---|
393 | *
|
---|
394 | * Differentiate further based on the op2<1:0> field.
|
---|
395 | *
|
---|
396 | * Bit 11 10
|
---|
397 | * +-------------------------------------------
|
---|
398 | * 0 0 Load/store register (unscaled immediate)
|
---|
399 | * 0 1 Load/store register (immediate post-indexed)
|
---|
400 | * 1 0 Load/store register (unprivileged)
|
---|
401 | * 1 1 Load/store register (immediate pre-indexed)
|
---|
402 | */
|
---|
403 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
|
---|
404 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
|
---|
405 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
|
---|
406 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv), /* No vector variants. */
|
---|
407 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
|
---|
408 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) | RT_BIT_32(11), 10);
|
---|
409 |
|
---|
410 |
|
---|
411 | /*
|
---|
412 | * C4.1.94 - Loads and Stores - Load/Store register variants
|
---|
413 | *
|
---|
414 | * Differentiate further based on the op2<11> field.
|
---|
415 | *
|
---|
416 | * Bit 21
|
---|
417 | * +-------------------------------------------
|
---|
418 | * 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
|
---|
419 | * 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
|
---|
420 | */
|
---|
421 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
|
---|
422 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
|
---|
423 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
|
---|
424 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
|
---|
425 |
|
---|
426 |
|
---|
427 | /*
|
---|
428 | * C4.1.94 - Loads and Stores - Load/Store register variants
|
---|
429 | *
|
---|
430 | * Differentiate further based on the op2<14> field.
|
---|
431 | *
|
---|
432 | * Bit 24
|
---|
433 | * +-------------------------------------------
|
---|
434 | * 0 All the other Load/store register variants and Atomic memory operations.
|
---|
435 | * 1 Load/store register (unsigned immediate).
|
---|
436 | */
|
---|
437 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
|
---|
438 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
|
---|
439 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
|
---|
440 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
|
---|
441 |
|
---|
442 |
|
---|
443 | /*
|
---|
444 | * STP/LDP/STGP/LDPSW
|
---|
445 | *
|
---|
446 | * Note: The opc,L bitfields are concatenated to form an index.
|
---|
447 | */
|
---|
448 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
|
---|
449 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
450 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
|
---|
451 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
|
---|
452 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
|
---|
453 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
|
---|
454 | DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
455 | DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
456 | INVALID_OPCODE,
|
---|
457 | INVALID_OPCODE,
|
---|
458 | DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
459 | DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
460 | INVALID_OPCODE,
|
---|
461 | INVALID_OPCODE,
|
---|
462 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /*fFixedInsn*/,
|
---|
463 | kDisArmV8OpcDecodeCollate,
|
---|
464 | RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
465 |
|
---|
466 |
|
---|
467 | /*
|
---|
468 | * STP/LDP/STGP/LDPSW - pre-indexed variant.
|
---|
469 | *
|
---|
470 | * Note: The opc,L bitfields are concatenated to form an index.
|
---|
471 | */
|
---|
472 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
|
---|
473 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
474 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
|
---|
475 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
|
---|
476 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
|
---|
477 | DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /*idxParam*/),
|
---|
478 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
|
---|
479 | DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
480 | DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
481 | INVALID_OPCODE,
|
---|
482 | INVALID_OPCODE,
|
---|
483 | DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
484 | DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
485 | INVALID_OPCODE,
|
---|
486 | INVALID_OPCODE,
|
---|
487 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /*fFixedInsn*/,
|
---|
488 | kDisArmV8OpcDecodeCollate,
|
---|
489 | RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
490 |
|
---|
491 |
|
---|
492 | /*
|
---|
493 | * STP/LDP/STGP/LDPSW - post-indexed variant.
|
---|
494 | *
|
---|
495 | * Note: The opc,L bitfields are concatenated to form an index.
|
---|
496 | */
|
---|
497 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
|
---|
498 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
499 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
|
---|
500 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
|
---|
501 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
|
---|
502 | DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /*idxParam*/),
|
---|
503 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
|
---|
504 | DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
505 | DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
506 | INVALID_OPCODE,
|
---|
507 | INVALID_OPCODE,
|
---|
508 | DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
509 | DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
510 | INVALID_OPCODE,
|
---|
511 | INVALID_OPCODE,
|
---|
512 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /*fFixedInsn*/,
|
---|
513 | kDisArmV8OpcDecodeCollate,
|
---|
514 | RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
515 |
|
---|
516 |
|
---|
517 | /*
|
---|
518 | * stnp/LDNP - no-allocate variant.
|
---|
519 | *
|
---|
520 | * Note: The opc,L bitfields are concatenated to form an index.
|
---|
521 | */
|
---|
522 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocGpr)
|
---|
523 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
|
---|
524 | DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
|
---|
525 | DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /*idxParam*/),
|
---|
526 | DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
|
---|
527 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocGpr)
|
---|
528 | DIS_ARMV8_OP_EX(0x28000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
529 | DIS_ARMV8_OP_EX(0x28400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
|
---|
530 | INVALID_OPCODE,
|
---|
531 | INVALID_OPCODE,
|
---|
532 | DIS_ARMV8_OP_EX(0xa8000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
533 | DIS_ARMV8_OP_EX(0xa8400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
|
---|
534 | INVALID_OPCODE,
|
---|
535 | INVALID_OPCODE,
|
---|
536 | DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocGpr, 0xffc00000 /*fFixedInsn*/,
|
---|
537 | kDisArmV8OpcDecodeCollate,
|
---|
538 | RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
|
---|
539 |
|
---|
540 |
|
---|
541 | /*
|
---|
542 | * C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
|
---|
543 | *
|
---|
544 | * Differentiate further based on the VR field.
|
---|
545 | *
|
---|
546 | * Bit 26
|
---|
547 | * +-------------------------------------------
|
---|
548 | * 0 GPR variants.
|
---|
549 | * 1 SIMD/FP variants
|
---|
550 | */
|
---|
551 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
|
---|
552 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
|
---|
553 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
|
---|
554 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
|
---|
555 |
|
---|
556 |
|
---|
557 | /*
|
---|
558 | * C4.1.94 - Loads and Stores - Load/Store register pair variants
|
---|
559 | *
|
---|
560 | * Differentiate further based on the op2<14:13> field.
|
---|
561 | *
|
---|
562 | * Bit 24 23
|
---|
563 | * +-------------------------------------------
|
---|
564 | * 0 0 Load/store no-allocate pair (offset)
|
---|
565 | * 0 1 Load/store register pair (post-indexed)
|
---|
566 | * 1 0 Load/store register pair (offset).
|
---|
567 | * 1 1 Load/store register pair (pre-indexed).
|
---|
568 | */
|
---|
569 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
|
---|
570 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAlloc),
|
---|
571 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
|
---|
572 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
|
---|
573 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
|
---|
574 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) | RT_BIT_32(24), 23);
|
---|
575 |
|
---|
576 |
|
---|
577 | /*
|
---|
578 | * C4.1.94 - Loads and Stores
|
---|
579 | *
|
---|
580 | * Differentiate further based on the op0<1:0> field.
|
---|
581 | * Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
|
---|
582 | *
|
---|
583 | * Bit 29 28
|
---|
584 | * +-------------------------------------------
|
---|
585 | * 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
|
---|
586 | * Load/store ordered / Compare and swap
|
---|
587 | * 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
|
---|
588 | * LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
|
---|
589 | * 1 0 Load/store no-allocate pair / Load/store register pair /
|
---|
590 | * 1 1 Load/store register / Atomic memory operations
|
---|
591 | */
|
---|
592 | DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
|
---|
593 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
|
---|
594 | DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
|
---|
595 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
|
---|
596 | DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
|
---|
597 | DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) | RT_BIT_32(29), 28);
|
---|