DisasmTables-armv8-a64.cpp@ 106657

Last change on this file since 106657 was 106657, checked in by vboxsync, 3 months ago
Disassembler: Decode pre-indexed load instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 106657 2024-10-24 12:42:39Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fValue, 0, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43	#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44	{ a_fValue, a_fFlags, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45	#define DIS_ARMV8_OP_ALT_DECODE(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_aAltDecode) \
46	{ a_fValue, 0, &g_aArmV8A64Insn ## a_aAltDecode ## Decode[0], OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
47
48
49	#ifndef DIS_CORE_ONLY
50	static char g_szInvalidOpcode[] = "Invalid Opcode";
51	#endif
52
53	#define INVALID_OPCODE \
54	DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
55
56
57	/* Invalid opcode */
58	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
59	{
60	OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
61	};
62
63
64	/* Include the secondary tables. */
65	#include "DisasmTables-armv8-a64-simd-fp.cpp.h"
66
67	/* UDF */
68	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
69	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /idxParam/),
70	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
71	DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
72	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Rsvd, 0xffff0000 /fFixedInsn/,
73	kDisArmV8OpcDecodeNop, 0xffff0000, 16);
74
75	/* ADR/ADRP */
76	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
77	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
78	DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
79	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
80	DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
81	DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
82	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Adr, 0x9f000000 /fFixedInsn/,
83	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
84
85
86	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
87	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
88	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
89	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
91	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /idxParam/),
92	DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /idxParam/),
93	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
94	DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
95	DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
96	DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
97	DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
98	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubImm, 0x7f800000 /fFixedInsn/,
99	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
100
101
102	/* ADD/ADDS/SUB/SUBS - shifted register variant */
103	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
104	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
105	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
109	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
110	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
111	DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
112	DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
113	DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
114	DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
115	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubShiftReg, 0x7f200000 /fFixedInsn/,
116	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
117
118
119	/* AND/ORR/EOR/ANDS */
120	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
121	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
122	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
123	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
124	DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
125	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
126	DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
127	DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
128	DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
129	DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
130	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogicalImm, 0x7f800000 /fFixedInsn/,
131	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
132
133
134	/* MOVN/MOVZ/MOVK */
135	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
136	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
137	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
138	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /idxParam/),
139	DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /idxParam/),
140	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
141	DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
142	INVALID_OPCODE,
143	DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
144	DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
145	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(MoveWide, 0x7f800000 /fFixedInsn/,
146	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
147
148
149	/* SBFM/BFM/UBFM */
150	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
151	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
152	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
156	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
157	DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
158	DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
159	DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
160	INVALID_OPCODE,
161	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Bitfield, 0x7f800000 /fFixedInsn/,
162	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
163
164
165	/*
166	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
167	* data processing (immediate) instruction classes:
168	*
169	* Bit 25 24 23
170	* +-------------------------------------------
171	* 0 0 x PC-rel. addressing.
172	* 0 1 0 Add/subtract (immediate)
173	* 0 1 1 Add/subtract (immediate, with tags)
174	* 1 0 0 Logical (immediate)
175	* 1 0 1 Move wide (immediate)
176	* 1 1 0 Bitfield
177	* 1 1 1 Extract
178	*/
179	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
180	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
181	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
182	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
183	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
184	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
185	DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
186	DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
187	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */
188	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
189
190
191	/* B.cond/BC.cond */
192	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
193	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
194	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /idxParam/),
195	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
196	DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
197	DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
198	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondBr, 0xff000010 /fFixedInsn/,
199	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4);
200
201
202	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
203	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
204	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /idxParam/),
205	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
206	DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
207	DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
208	DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
209	DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
210	DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
211	DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
212	DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
213	DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
214	DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
215	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Excp, 0xffe0001f /fFixedInsn/,
216	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0);
217
218
219	/* WFET/WFIT */
220	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
221	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
222	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
223	DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
224	DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
225	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysReg, 0xffffffe0 /fFixedInsn/,
226	kDisArmV8OpcDecodeNop, 0xfe0, 5);
227
228
229	/* Various hint instructions */
230	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
231	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
232	DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
234	DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
235	DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
236	DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
237	DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
238	DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
239	DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
240	DIS_ARMV8_OP(0xd503211f, "pacia1716", OP_ARMV8_A64_PACIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
241	INVALID_OPCODE,
242	DIS_ARMV8_OP(0xd503215f, "pacib1716", OP_ARMV8_A64_PACIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
243	INVALID_OPCODE,
244	DIS_ARMV8_OP(0xd503219f, "autia1716", OP_ARMV8_A64_AUTIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
245	INVALID_OPCODE,
246	DIS_ARMV8_OP(0xd50321df, "autib1716", OP_ARMV8_A64_AUTIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
247	INVALID_OPCODE,
248	DIS_ARMV8_OP(0xd503221f, "esb", OP_ARMV8_A64_ESB, DISOPTYPE_HARMLESS), /* FEAT_RAS */
249	DIS_ARMV8_OP(0xd503223f, "psb csync", OP_ARMV8_A64_PSB, DISOPTYPE_HARMLESS), /* FEAT_SPE */
250	DIS_ARMV8_OP(0xd503225f, "tsb csync", OP_ARMV8_A64_TSB, DISOPTYPE_HARMLESS), /* FEAT_TRF */
251	DIS_ARMV8_OP(0xd503227f, "gcsb dsync", OP_ARMV8_A64_GCSB, DISOPTYPE_HARMLESS), /* FEAT_GCS */
252	DIS_ARMV8_OP(0xd503229f, "csdb", OP_ARMV8_A64_CSDB, DISOPTYPE_HARMLESS),
253	INVALID_OPCODE,
254	DIS_ARMV8_OP(0xd50322df, "clrbhb", OP_ARMV8_A64_CLRBHB, DISOPTYPE_HARMLESS), /* FEAT_CLRBHB */
255	INVALID_OPCODE,
256	DIS_ARMV8_OP(0xd503231f, "paciaz", OP_ARMV8_A64_PACIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
257	DIS_ARMV8_OP(0xd503233f, "paciasp", OP_ARMV8_A64_PACIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
258	DIS_ARMV8_OP(0xd503235f, "pacibz", OP_ARMV8_A64_PACIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
259	DIS_ARMV8_OP(0xd503237f, "pacibsp", OP_ARMV8_A64_PACIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
260	DIS_ARMV8_OP(0xd503239f, "autiaz", OP_ARMV8_A64_AUTIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
261	DIS_ARMV8_OP(0xd50323bf, "autiasp", OP_ARMV8_A64_AUTIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
262	DIS_ARMV8_OP(0xd50323df, "autibz", OP_ARMV8_A64_AUTIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
263	DIS_ARMV8_OP(0xd50323ff, "autibsp", OP_ARMV8_A64_AUTIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
264	DIS_ARMV8_OP(0xd503241f, "bti", OP_ARMV8_A64_BTI, DISOPTYPE_HARMLESS), /* FEAT_BTI */
265	INVALID_OPCODE,
266	DIS_ARMV8_OP(0xd503245f, "bti c", OP_ARMV8_A64_BTI_C, DISOPTYPE_HARMLESS), /* FEAT_BTI */
267	INVALID_OPCODE,
268	DIS_ARMV8_OP(0xd503249f, "bti j", OP_ARMV8_A64_BTI_J, DISOPTYPE_HARMLESS), /* FEAT_BTI */
269	INVALID_OPCODE,
270	DIS_ARMV8_OP(0xd50324df, "bti jc", OP_ARMV8_A64_BTI_JC, DISOPTYPE_HARMLESS), /* FEAT_BTI */
271	INVALID_OPCODE,
272	DIS_ARMV8_OP(0xd503251f, "chkfeat x16", OP_ARMV8_A64_CHKFEAT, DISOPTYPE_HARMLESS), /* FEAT_CHK */
273	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Hints, 0xffffffff /fFixedInsn/,
274	kDisArmV8OpcDecodeNop, 0xfe0, 5);
275
276
277	/* CLREX */
278	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
279	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
280	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
281	INVALID_OPCODE,
282	INVALID_OPCODE,
283	DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
284	INVALID_OPCODE,
285	DIS_ARMV8_OP(0xD503309f, "dsb", OP_ARMV8_A64_DSB, DISOPTYPE_HARMLESS),
286	DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
287	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DecBarriers, 0xfffff0ff /fFixedInsn/,
288	kDisArmV8OpcDecodeNop, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
289
290
291	/* Barrier instructions, we divide these instructions further based on the op2 field. */
292	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
293	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
294	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
295	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
296	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
297	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DSB - Encoding */
298	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
299	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
300	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
301	DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
302
303
304	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
305	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
306	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value, gets validated by the next decoder stage. */
307	DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
308	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
309	DIS_ARMV8_OP(0xd500401f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
310	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(PState, 0xfff8f01f /fFixedInsn/,
311	kDisArmV8OpcDecodeNop, 0, 0);
312
313
314	/* TSTART/TTEST */
315	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
316	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
317	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
318	DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
319	DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
320	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysResult, 0xfffffffe /fFixedInsn/,
321	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8);
322
323
324	/* SYS */
325	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
326	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /idxParam/),
327	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
328	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /idxParam/),
329	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 3 /idxParam/),
330	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
331	DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
332	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Sys, 0xfff80000 /fFixedInsn/,
333	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
334
335
336	/* SYSL */
337	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
338	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
339	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /idxParam/),
340	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
341	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /idxParam/),
342	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
343	DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
344	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysL, 0xfff80000 /fFixedInsn/,
345	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
346
347
348	/* MSR */
349	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
350	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
351	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 1 /idxParam/),
352	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
353	DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
354	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Msr, 0xfff00000 /fFixedInsn/,
355	kDisArmV8OpcDecodeNop, 0, 0);
356
357
358	/* MRS */
359	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
360	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
361	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
362	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
363	DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
364	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Mrs, 0xfff00000 /fFixedInsn/,
365	kDisArmV8OpcDecodeNop, 0, 0);
366
367
368	/* BR/BRAAZ/BRABZ */
369	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Br)
370	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
371	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Br)
372	DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
373	INVALID_OPCODE,
374	DIS_ARMV8_OP(0xd61f081f, "braaz", OP_ARMV8_A64_BRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
375	DIS_ARMV8_OP(0xd61f0c1f, "brabz", OP_ARMV8_A64_BRABZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
376	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Br, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
377	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
378
379
380	/* BLR/BLRAAZ/BLRABZ */
381	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Blr)
382	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
383	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Blr)
384	DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
385	INVALID_OPCODE,
386	DIS_ARMV8_OP(0xd63f081f, "blraaz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
387	DIS_ARMV8_OP(0xd63f0c1f, "blrabz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
388	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Blr, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
389	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
390
391
392	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Ret)
393	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
394	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(RetPAuth)
395	DIS_ARMV8_INSN_DECODE(kDisParmParseRegFixed31, 5, 5, 0 /idxParam/),
396	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Ret)
397	DIS_ARMV8_OP( 0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
398	INVALID_OPCODE,
399	DIS_ARMV8_OP_ALT_DECODE(0xd65f081f, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
400	DIS_ARMV8_OP_ALT_DECODE(0xd65f0c1f, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
401	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Ret, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
402	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
403
404
405	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Eret)
406	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Eret)
407	DIS_ARMV8_OP(0xd69f03e0, "eret", OP_ARMV8_A64_ERET, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
408	INVALID_OPCODE,
409	DIS_ARMV8_OP(0xd69f0bff, "eretaa", OP_ARMV8_A64_ERETAA, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
410	DIS_ARMV8_OP(0xd69f0fff, "eretab", OP_ARMV8_A64_ERETAB, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
411	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Eret, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
412	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
413
414
415	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Drps)
416	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Drps)
417	DIS_ARMV8_OP(0xd6bf03e0, "drps", OP_ARMV8_A64_DRPS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
418	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Drps, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
419	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
420
421
422	/* BRAA/BRAB */
423	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BraaBrab)
424	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
425	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
426	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BraaBrab)
427	INVALID_OPCODE,
428	INVALID_OPCODE,
429	DIS_ARMV8_OP(0xd71f0800, "braa", OP_ARMV8_A64_BRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
430	DIS_ARMV8_OP(0xd71f0c00, "brab", OP_ARMV8_A64_BRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
431	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BraaBrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
432	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
433
434
435	/* BRAA/BRAB */
436	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BlraaBlrab) /** @todo Could use the same decoder as for braa/brab and save a bit of table size. */
437	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
438	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
439	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BlraaBlrab)
440	INVALID_OPCODE,
441	INVALID_OPCODE,
442	DIS_ARMV8_OP(0xd73f0800, "blraa", OP_ARMV8_A64_BLRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
443	DIS_ARMV8_OP(0xd73f0c00, "blrab", OP_ARMV8_A64_BLRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
444	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BlraaBlrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
445	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
446
447
448	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
449	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
450	DIS_ARMV8_DECODE_MAP_ENTRY(Br), /* BR/BRAAZ/BRABZ */
451	DIS_ARMV8_DECODE_MAP_ENTRY(Blr), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
452	DIS_ARMV8_DECODE_MAP_ENTRY(Ret), /* RET/RETAA/RETAB */
453	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
454	DIS_ARMV8_DECODE_MAP_ENTRY(Eret), /* ERET/ERETAA/ERETAB */
455	DIS_ARMV8_DECODE_MAP_ENTRY(Drps), /* DRPS */
456	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
457	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
458	DIS_ARMV8_DECODE_MAP_ENTRY(BraaBrab), /* BRAA/BRAB */
459	DIS_ARMV8_DECODE_MAP_ENTRY(BlraaBlrab), /* BRAA/BRAB */
460	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
461	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
462	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
463	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
464	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
465	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
466	DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
467
468
469	/* B/BL */
470	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
471	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
472	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
473	DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
474	DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
475	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(UncondBrImm, 0xfc000000 /fFixedInsn/,
476	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
477
478
479	/* CBZ/CBNZ */
480	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
481	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
482	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
483	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
484	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
485	DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
486	DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
487	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CmpBrImm, 0x7f000000 /fFixedInsn/,
488	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
489
490
491	/* TBZ/TBNZ */
492	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
493	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not an SF bit but has the same meaning. */
494	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
495	DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /idxParam/), /* Hardcoded bit offsets in parser. */
496	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
497	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
498	DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
499	DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
500	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(TestBrImm, 0x7f000000 /fFixedInsn/,
501	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
502
503
504	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
505	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
506	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
507	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
508	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
509	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
510	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
511	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
512	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
513	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
514	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
515	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
516	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
517	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
518	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
519	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
520	DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
521
522
523	/* AND/ORR/EOR/ANDS */
524	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
525	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
526	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
527	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
528	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
529	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
530	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
531	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
532	DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
533	DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
534	DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
535	DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
536	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN0, 0x7f200000 /fFixedInsn/,
537	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
538
539
540	/* AND/ORR/EOR/ANDS */
541	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
542	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
543	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
544	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
545	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
546	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
547	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
548	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
549	DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
550	DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
551	DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
552	DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
553	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN1, 0x7f200000 /fFixedInsn/,
554	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
555
556
557	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
558	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
559	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
560	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
561
562
563	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
564	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
565	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24);
566
567
568	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
569	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
570	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
571	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
572
573
574	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
575	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
576	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
577	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
578
579
580	/* CCMN/CCMP */
581	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
582	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
583	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
584	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 1 /idxParam/),
585	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
586	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
587	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
588	DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
589	DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
590	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondCmpReg, 0x7fe00c10 /fFixedInsn/,
591	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
592
593
594	/**
595	* C4.1.95 - Data Processing - Register
596	*
597	* The conditional compare instructions differentiate between register and immediate
598	* variant based on the 11th bit (part of op3).
599	*/
600	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
601	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
602	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional compare immediate */
603	DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
604
605
606	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
607	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src32Bit)
608	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
609	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
610	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
611	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
612	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src32Bit)
613	INVALID_OPCODE,
614	INVALID_OPCODE,
615	DIS_ARMV8_OP(0x1ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
616	DIS_ARMV8_OP(0x1ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
617	INVALID_OPCODE,
618	INVALID_OPCODE,
619	INVALID_OPCODE,
620	INVALID_OPCODE,
621	DIS_ARMV8_OP(0x1ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
622	DIS_ARMV8_OP(0x1ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
623	DIS_ARMV8_OP(0x1ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
624	DIS_ARMV8_OP(0x1ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
625	INVALID_OPCODE,
626	INVALID_OPCODE,
627	INVALID_OPCODE,
628	INVALID_OPCODE,
629	DIS_ARMV8_OP(0x1ac04000, "crc32b", OP_ARMV8_A64_CRC32B, DISOPTYPE_HARMLESS),
630	DIS_ARMV8_OP(0x1ac04400, "crc32h", OP_ARMV8_A64_CRC32H, DISOPTYPE_HARMLESS),
631	DIS_ARMV8_OP(0x1ac04800, "crc32w", OP_ARMV8_A64_CRC32W, DISOPTYPE_HARMLESS),
632	INVALID_OPCODE,
633	DIS_ARMV8_OP(0x1ac05000, "crc32cb", OP_ARMV8_A64_CRC32CB, DISOPTYPE_HARMLESS),
634	DIS_ARMV8_OP(0x1ac05400, "crc32ch", OP_ARMV8_A64_CRC32CH, DISOPTYPE_HARMLESS),
635	DIS_ARMV8_OP(0x1ac05800, "crc32cw", OP_ARMV8_A64_CRC32CW, DISOPTYPE_HARMLESS),
636	INVALID_OPCODE,
637	DIS_ARMV8_OP(0x1ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
638	DIS_ARMV8_OP(0x1ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
639	DIS_ARMV8_OP(0x1ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
640	DIS_ARMV8_OP(0x1ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS),
641	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src32Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
642	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
643
644
645	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
646	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src64Bit)
647	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
648	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
649	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
650	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcCrc32X)
651	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
652	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
653	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
654	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcSubp)
655	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
656	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
657	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
658	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcIrg)
659	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
660	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
661	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
662	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcGmi)
663	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
664	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
665	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
666	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src64Bit)
667	DIS_ARMV8_OP_ALT_DECODE(0x9ac00000, "subp", OP_ARMV8_A64_SUBP, DISOPTYPE_HARMLESS, Reg2SrcSubp),
668	INVALID_OPCODE,
669	DIS_ARMV8_OP( 0x9ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
670	DIS_ARMV8_OP( 0x9ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
671	DIS_ARMV8_OP_ALT_DECODE(0x9ac01000, "irg", OP_ARMV8_A64_IRG, DISOPTYPE_HARMLESS, Reg2SrcIrg),
672	DIS_ARMV8_OP_ALT_DECODE(0x9ac01400, "gmi", OP_ARMV8_A64_GMI, DISOPTYPE_HARMLESS, Reg2SrcGmi),
673	INVALID_OPCODE,
674	INVALID_OPCODE,
675	DIS_ARMV8_OP( 0x9ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
676	DIS_ARMV8_OP( 0x9ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
677	DIS_ARMV8_OP( 0x9ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
678	DIS_ARMV8_OP( 0x9ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
679	INVALID_OPCODE, /** @todo PACGA (FEAT_PAuth). */
680	INVALID_OPCODE,
681	INVALID_OPCODE,
682	INVALID_OPCODE,
683	INVALID_OPCODE,
684	INVALID_OPCODE,
685	INVALID_OPCODE,
686	DIS_ARMV8_OP_ALT_DECODE(0x9ac04c00, "crc32x", OP_ARMV8_A64_CRC32X, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
687	INVALID_OPCODE,
688	INVALID_OPCODE,
689	INVALID_OPCODE,
690	DIS_ARMV8_OP_ALT_DECODE(0x9ac05c00, "crc32cx", OP_ARMV8_A64_CRC32CX, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
691	DIS_ARMV8_OP( 0x9ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
692	DIS_ARMV8_OP( 0x9ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
693	DIS_ARMV8_OP( 0x9ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
694	DIS_ARMV8_OP( 0x9ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS)
695	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src64Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
696	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
697
698
699	/* SUBPS */
700	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Subps)
701	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
702	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
703	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
704	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Subps)
705	DIS_ARMV8_OP(0xbac00000, "subps", OP_ARMV8_A64_SUBPS, DISOPTYPE_HARMLESS),
706	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Subps, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
707	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
708
709
710	/**
711	* C4.1.95 - Data Processing - Register - 2-source
712	*
713	* Differentiate between 32-bit and 64-bit groups based on the SF bit.
714	* Not done as a general decoder step because there are different instructions in each group.
715	*/
716	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src)
717	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src32Bit), /* Data-processing (2-source, 32-bit) */
718	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src64Bit), /* Data-processing (2-source, 64-bit) */
719	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src, 31);
720
721
722	/**
723	* C4.1.95 - Data Processing - Register - 2-source
724	*
725	* Differentiate between SUBPS and the rest based on the S bit.
726	*/
727	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2SrcSubps)
728	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src), /* Data-processing (2-source) */
729	DIS_ARMV8_DECODE_MAP_ENTRY(Subps), /* Subps */
730	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2SrcSubps, 29);
731
732
733	/* RBIT/REV16/REV/CLZ/CLS/CTZ/CNT/ABS/REV32 */
734	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg1SrcInsn)
735	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
736	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
737	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
738	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg1SrcInsn)
739	DIS_ARMV8_OP(0x5ac00000, "rbit", OP_ARMV8_A64_RBIT, DISOPTYPE_HARMLESS),
740	DIS_ARMV8_OP(0x5ac00400, "rev16", OP_ARMV8_A64_REV16, DISOPTYPE_HARMLESS),
741	DIS_ARMV8_OP(0x5ac00800, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo REV32 if SF1 is 1 (why must this be so difficult ARM?). */
742	DIS_ARMV8_OP(0x5ac00c00, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo SF must be 1, otherwise unallocated. */
743	DIS_ARMV8_OP(0x5ac01000, "clz", OP_ARMV8_A64_CLZ, DISOPTYPE_HARMLESS),
744	DIS_ARMV8_OP(0x5ac01400, "cls", OP_ARMV8_A64_CLS, DISOPTYPE_HARMLESS),
745	DIS_ARMV8_OP(0x5ac01800, "ctz", OP_ARMV8_A64_CTZ, DISOPTYPE_HARMLESS),
746	DIS_ARMV8_OP(0x5ac01c00, "cnt", OP_ARMV8_A64_CNT, DISOPTYPE_HARMLESS),
747	DIS_ARMV8_OP(0x5ac02000, "abs", OP_ARMV8_A64_ABS, DISOPTYPE_HARMLESS),
748	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg1SrcInsn, 0x7ffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
749	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
750
751
752	/**
753	* C4.1.95 - Data Processing - Register - 1-source
754	*
755	* Differentiate between standard and FEAT_PAuth instructions based on opcode2 field.
756	*/
757	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg1Src)
758	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1SrcInsn), /* Data-processing (1-source) */
759	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data-processing (1-source, FEAT_PAuth) */
760	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg1Src, 16);
761
762
763	/**
764	* C4.1.95 - Data Processing - Register - 2-source / 1-source
765	*
766	* The 2-source and 1-source instruction classes differentiate based on bit 30.
767	*/
768	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src1Src)
769	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2SrcSubps), /* Data-processing (2-source) */
770	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1Src), /* Data-processing (1-source) */
771	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src1Src, 30);
772
773
774	/*
775	* C4.1.95 - Data Processing - Register
776	*
777	* The op1 field is already decoded in the previous step and is 1 when being here,
778	* leaving us with the following possible values:
779	*
780	* Bit 24 23 22 21
781	* +-------------------------------------------
782	* 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
783	* 0 0 0 1 UNALLOC
784	* 0 0 1 0 Conditional compare (register / immediate)
785	* 0 0 1 1 UNALLOC
786	* 0 1 0 0 Conditional select
787	* 0 1 0 1 UNALLOC
788	* 0 1 1 0 Data processing (2-source or 1-source depending on op0).
789	* 0 1 1 1 UNALLOC
790	* 1 x x x Data processing 3-source
791	*/
792	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
793	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract with carry. */
794	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
795	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp),
796	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
797	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional select. */
798	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
799	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src1Src),
800	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
801	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
802	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
803	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
804	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
805	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
806	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
807	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
808	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
809	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
810
811
812	/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
813	*
814	* Note: The size,opc bitfields are concatenated to form an index.
815	*/
816	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
817	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
818	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
819	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
820	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
821	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
822	DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
823	DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
824	DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
825	DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
826	DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
827	DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
828	DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
829	DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
830	DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
831	DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
832	DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
833	INVALID_OPCODE,
834	DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
835	DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
836	INVALID_OPCODE, /** @todo PRFM */
837	INVALID_OPCODE,
838	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /fFixedInsn/,
839	kDisArmV8OpcDecodeCollate,
840	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
841
842
843	/*
844	* C4.1.94 - Loads and Stores - Load/Store register variants
845	*
846	* Differentiate further based on the VR field.
847	*
848	* Bit 26
849	* +-------------------------------------------
850	* 0 GPR variants.
851	* 1 SIMD/FP variants
852	*/
853	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
854	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
855	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
856	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
857
858
859	/*
860	* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
861	*
862	* Note: The size,opc bitfields are concatenated to form an index.
863	*/
864	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
865	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
866	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
867	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
868	DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /idxParam/),
869	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /idxParam/),
870	DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /idxParam/),
871	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
872	DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
873	DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
874	DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
875	DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
876	DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
877	DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
878	DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
879	DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
880	DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
881	DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
882	DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
883	INVALID_OPCODE,
884	DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
885	DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
886	INVALID_OPCODE, /** @todo PRFM */
887	INVALID_OPCODE,
888	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /fFixedInsn/,
889	kDisArmV8OpcDecodeCollate,
890	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
891
892
893	/*
894	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
895	*
896	* Differentiate further based on the VR field.
897	*
898	* Bit 26
899	* +-------------------------------------------
900	* 0 GPR variants.
901	* 1 SIMD/FP variants
902	*/
903	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
904	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
905	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
906	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
907
908
909	/*
910	* C4.1.94 - Loads and Stores - Load/Store register variants
911	*
912	* Differentiate further based on the op2<1:0> field.
913	*
914	* Bit 11 10
915	* +-------------------------------------------
916	* 0 0 Atomic memory operations
917	* 0 1 Load/store register (pac)
918	* 1 0 Load/store register (register offset)
919	* 1 1 Load/store register (pac)
920	*/
921	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
922	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
923	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
924	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
925	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
926	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
927
928
929	/*
930	* STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
931	*
932	* Note: The size,opc bitfields are concatenated to form an index.
933	*/
934	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
935	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
936	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
937	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
938	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
939	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
940	DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
941	DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
942	DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
943	DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
944	DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
945	DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
946	DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
947	DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
948	DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
949	DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
950	DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
951	INVALID_OPCODE,
952	DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
953	DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
954	INVALID_OPCODE, /** @todo PRFUM */
955	INVALID_OPCODE,
956	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /fFixedInsn/,
957	kDisArmV8OpcDecodeCollate,
958	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
959
960
961	/*
962	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
963	*
964	* Differentiate further based on the VR field.
965	*
966	* Bit 26
967	* +-------------------------------------------
968	* 0 GPR variants.
969	* 1 SIMD/FP variants
970	*/
971	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
972	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
973	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
974	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
975
976
977	/*
978	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
979	*
980	* Note: The size,opc bitfields are concatenated to form an index.
981	*/
982	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
983	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
984	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
985	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
986	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
987	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /idxParam/),
988	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
989	DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
990	DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
991	DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
992	DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
993	DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
994	DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
995	DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
996	DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
997	DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
998	DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
999	DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1000	INVALID_OPCODE,
1001	DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
1002	DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
1003	INVALID_OPCODE,
1004	INVALID_OPCODE,
1005	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /fFixedInsn/,
1006	kDisArmV8OpcDecodeCollate,
1007	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1008
1009
1010	/*
1011	* C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
1012	*
1013	* Differentiate further based on the VR field.
1014	*
1015	* Bit 26
1016	* +-------------------------------------------
1017	* 0 GPR variants.
1018	* 1 SIMD/FP variants
1019	*/
1020	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
1021	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
1022	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1023	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
1024
1025
1026	/*
1027	* C4.1.94 - Loads and Stores - Load/Store register variants
1028	*
1029	* Differentiate further based on the op2<1:0> field.
1030	*
1031	* Bit 11 10
1032	* +-------------------------------------------
1033	* 0 0 Load/store register (unscaled immediate)
1034	* 0 1 Load/store register (immediate post-indexed)
1035	* 1 0 Load/store register (unprivileged)
1036	* 1 1 Load/store register (immediate pre-indexed)
1037	*/
1038	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
1039	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
1040	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1041	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1042	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
1043	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) \| RT_BIT_32(11), 10);
1044
1045
1046	/*
1047	* C4.1.94 - Loads and Stores - Load/Store register variants
1048	*
1049	* Differentiate further based on the op2<11> field.
1050	*
1051	* Bit 21
1052	* +-------------------------------------------
1053	* 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
1054	* 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
1055	*/
1056	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
1057	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
1058	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
1059	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
1060
1061
1062	/*
1063	* C4.1.94 - Loads and Stores - Load/Store register variants
1064	*
1065	* Differentiate further based on the op2<14> field.
1066	*
1067	* Bit 24
1068	* +-------------------------------------------
1069	* 0 All the other Load/store register variants and Atomic memory operations.
1070	* 1 Load/store register (unsigned immediate).
1071	*/
1072	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
1073	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
1074	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
1075	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
1076
1077
1078	/*
1079	* STP/LDP/STGP/LDPSW
1080	*
1081	* Note: The opc,L bitfields are concatenated to form an index.
1082	*/
1083	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
1084	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1085	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1086	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1087	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1088	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
1089	DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1090	DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1091	INVALID_OPCODE,
1092	INVALID_OPCODE,
1093	DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1094	DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1095	INVALID_OPCODE,
1096	INVALID_OPCODE,
1097	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /fFixedInsn/,
1098	kDisArmV8OpcDecodeCollate,
1099	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1100
1101
1102	/*
1103	* STP/LDP/STGP/LDPSW - pre-indexed variant.
1104	*
1105	* Note: The opc,L bitfields are concatenated to form an index.
1106	*/
1107	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
1108	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1109	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1110	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1111	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1112	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /idxParam/),
1113	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
1114	DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1115	DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1116	INVALID_OPCODE,
1117	INVALID_OPCODE,
1118	DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1119	DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1120	INVALID_OPCODE,
1121	INVALID_OPCODE,
1122	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /fFixedInsn/,
1123	kDisArmV8OpcDecodeCollate,
1124	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1125
1126
1127	/*
1128	* STP/LDP/STGP/LDPSW - post-indexed variant.
1129	*
1130	* Note: The opc,L bitfields are concatenated to form an index.
1131	*/
1132	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
1133	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1134	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1135	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1136	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1137	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /idxParam/),
1138	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
1139	DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1140	DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1141	INVALID_OPCODE,
1142	INVALID_OPCODE,
1143	DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1144	DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1145	INVALID_OPCODE,
1146	INVALID_OPCODE,
1147	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /fFixedInsn/,
1148	kDisArmV8OpcDecodeCollate,
1149	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1150
1151
1152	/*
1153	* C4.1.94 - Loads and Stores - Load/Store register pair variants
1154	*
1155	* Differentiate further based on the op2<14:13> field.
1156	*
1157	* Bit 24 23
1158	* +-------------------------------------------
1159	* 0 0 Load/store no-allocate pair (offset)
1160	* 0 1 Load/store register pair (post-indexed)
1161	* 1 0 Load/store register pair (offset).
1162	* 1 1 Load/store register pair (pre-indexed).
1163	*/
1164	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
1165	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1166	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
1167	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
1168	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
1169	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) \| RT_BIT_32(24), 23);
1170
1171
1172	/*
1173	* C4.1.94 - Loads and Stores
1174	*
1175	* Differentiate further based on the op0<1:0> field.
1176	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
1177	*
1178	* Bit 29 28
1179	* +-------------------------------------------
1180	* 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
1181	* Load/store ordered / Compare and swap
1182	* 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
1183	* LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
1184	* 1 0 Load/store no-allocate pair / Load/store register pair /
1185	* 1 1 Load/store register / Atomic memory operations
1186	*/
1187	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
1188	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1189	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1190	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
1191	DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
1192	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) \| RT_BIT_32(29), 28);
1193
1194
1195	/*
1196	* C4.1 of the ARMv8 architecture reference manual has the following table for the
1197	* topmost decoding level (Level 0 in our terms), x means don't care:
1198	*
1199	* Bit 28 27 26 25
1200	* +-------------------------------------------
1201	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1202	* 0 0 0 1 UNALLOC
1203	* 0 0 1 0 SVE encodings
1204	* 0 0 1 1 UNALLOC
1205	* 1 0 0 x Data processing immediate
1206	* 1 0 1 x Branch, exception generation and system instructions
1207	* x 1 x 0 Loads and stores
1208	* x 1 0 1 Data processing - register
1209	* x 1 1 1 Data processing - SIMD and floating point
1210	*
1211	* In order to save us some fiddling with the don't care bits we blow up the lookup table
1212	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
1213	* lookup table for the next level:
1214	* Bit 28 27 26 25
1215	* +-------------------------------------------
1216	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1217	* 1 0 0 0 1 UNALLOC
1218	* 2 0 0 1 0 SVE encodings
1219	* 3 0 0 1 1 UNALLOC
1220	* 4 0 1 0 0 Loads and stores
1221	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1222	* 6 0 1 1 0 Loads and stores
1223	* 7 0 1 1 1 Data processing - SIMD and floating point
1224	* 8 1 0 0 0 Data processing immediate
1225	* 9 1 0 0 1 Data processing immediate
1226	* 10 1 0 1 0 Branch, exception generation and system instructions
1227	* 11 1 0 1 1 Branch, exception generation and system instructions
1228	* 12 1 1 0 0 Loads and stores
1229	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1230	* 14 1 1 1 0 Loads and stores
1231	* 15 1 1 1 1 Data processing - SIMD and floating point
1232	*/
1233	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
1234	DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
1235	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1236	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
1237	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1238	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1239	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
1240	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1241	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0), /* Data processing (SIMD & FP) (op0<0> 0) */
1242	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1243	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1244	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1245	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1246	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1247	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
1248	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1249	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1) /* Data processing (SIMD & FP) (op0<0> 1). */
1250	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 106657

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