DisasmTables-armv8-a64.cpp@ 105736

Last change on this file since 105736 was 105736, checked in by vboxsync, 3 months ago
Disassembler/ARMv8: Build fix and add support conditionals, bugref:10388
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1	/* $Id: DisasmTables-armv8-a64.cpp 105736 2024-08-19 17:41:36Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fMask, a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fMask, a_fValue, OP(a_szOpcode, 0, 0, 0, a_uOpcode, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, a_fOpType) }
43
44	#ifndef DIS_CORE_ONLY
45	static char g_szInvalidOpcode[] = "Invalid Opcode";
46	#endif
47
48	#define INVALID_OPCODE \
49	DIS_ARMV8_OP(0xffffffff, 0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
50
51
52	/* Invalid opcode */
53	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
54	{
55	OP(g_szInvalidOpcode, 0, 0, 0, OP_ARMV8_INVALID, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, DISOPTYPE_INVALID)
56	};
57
58
59	/* UDF */
60	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnRsvd)
61	DIS_ARMV8_OP(0xffff0000, 0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
62	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_aArmV8A64InsnRsvd, 0 /fClass/,
63	kDisArmV8OpcDecodeNop, 0xffff0000, 16)
64	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16, 0 /idxParam/),
65	DIS_ARMV8_INSN_PARAM_NONE,
66	DIS_ARMV8_INSN_PARAM_NONE,
67	DIS_ARMV8_INSN_PARAM_NONE
68	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
69
70
71	/* ADR/ADRP */
72	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Adr)
73	DIS_ARMV8_OP(0x9f000000, 0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
74	DIS_ARMV8_OP(0x9f000000, 0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
75	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT,
76	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31)
77	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
78	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
79	DIS_ARMV8_INSN_PARAM_NONE,
80	DIS_ARMV8_INSN_PARAM_NONE
81	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
82
83
84	/* ADD/ADDS/SUB/SUBS */
85	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64AddSubImm)
86	DIS_ARMV8_OP(0x7f800000, 0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
87	DIS_ARMV8_OP(0x7f800000, 0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
88	DIS_ARMV8_OP(0x7f800000, 0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
89	DIS_ARMV8_OP(0x7f800000, 0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
90	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF,
91	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
92	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
93	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /idxParam/),
94	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 12, 2 /idxParam/),
95	DIS_ARMV8_INSN_PARAM_NONE
96	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
97
98
99	/* AND/ORR/EOR/ANDS */
100	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64LogicalImm)
101	DIS_ARMV8_OP(0x7f800000, 0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
102	DIS_ARMV8_OP(0x7f800000, 0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
103	DIS_ARMV8_OP(0x7f800000, 0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
104	DIS_ARMV8_OP(0x7f800000, 0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
105	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF,
106	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
107	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
108	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 6, 1 /idxParam/),
109	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
110	DIS_ARMV8_INSN_PARAM_NONE
111	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
112
113
114	/* MOVN/MOVZ/MOVK */
115	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64MoveWide)
116	DIS_ARMV8_OP(0x7f800000, 0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
117	INVALID_OPCODE,
118	DIS_ARMV8_OP(0x7f800000, 0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
119	DIS_ARMV8_OP(0x7f800000, 0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
120	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF,
121	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
122	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
123	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 1 /idxParam/),
124	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseHw, 21, 2, 2 /idxParam/),
125	DIS_ARMV8_INSN_PARAM_NONE
126	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
127
128
129	/* SBFM/BFM/UBFM */
130	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Bitfield)
131	DIS_ARMV8_OP(0x7f800000, 0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
132	DIS_ARMV8_OP(0x7f800000, 0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
133	DIS_ARMV8_OP(0x7f800000, 0x23000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
134	INVALID_OPCODE,
135	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Bitfield, DISARMV8INSNCLASS_F_SF \| DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT,
136	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
137	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
138	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /idxParam/),
139	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
140	DIS_ARMV8_INSN_PARAM_NONE
141	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
142
143
144	/*
145	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
146	* data processing (immediate) instruction classes:
147	*
148	* Bit 25 24 23
149	* +-------------------------------------------
150	* 0 0 x PC-rel. addressing.
151	* 0 1 0 Add/subtract (immediate)
152	* 0 1 1 Add/subtract (immediate, with tags)
153	* 1 0 0 Logical (immediate)
154	* 1 0 1 Move wide (immediate)
155	* 1 1 0 Bitfield
156	* 1 1 1 Extract
157	*/
158	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnDataProcessingImm)
159	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Adr),
160	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Adr),
161	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64AddSubImm),
162	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
163	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LogicalImm),
164	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64MoveWide),
165	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Bitfield),
166	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */
167	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnDataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
168
169
170	/* B.cond/BC.cond */
171	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CondBr)
172	DIS_ARMV8_OP(0xff000010, 0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
173	DIS_ARMV8_OP(0xff000010, 0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
174	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CondBr, 0 /fClass/,
175	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4)
176	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
177	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
178	DIS_ARMV8_INSN_PARAM_NONE,
179	DIS_ARMV8_INSN_PARAM_NONE
180	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
181
182
183	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
184	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Excp)
185	DIS_ARMV8_OP(0xffe0001f, 0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
186	DIS_ARMV8_OP(0xffe0001f, 0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
187	DIS_ARMV8_OP(0xffe0001f, 0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
188	DIS_ARMV8_OP(0xffe0001f, 0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
189	DIS_ARMV8_OP(0xffe0001f, 0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
190	DIS_ARMV8_OP(0xffe0001f, 0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
191	DIS_ARMV8_OP(0xffe0001f, 0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
192	DIS_ARMV8_OP(0xffe0001f, 0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
193	DIS_ARMV8_OP(0xffe0001f, 0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
194	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Excp, 0 /fClass/,
195	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0)
196	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 0 /idxParam/),
197	DIS_ARMV8_INSN_PARAM_NONE,
198	DIS_ARMV8_INSN_PARAM_NONE,
199	DIS_ARMV8_INSN_PARAM_NONE
200	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
201
202
203	/* WFET/WFIT */
204	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysReg)
205	DIS_ARMV8_OP(0xffffffe0, 0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
206	DIS_ARMV8_OP(0xffffffe0, 0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
207	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysReg, DISARMV8INSNCLASS_F_FORCED_64BIT,
208	kDisArmV8OpcDecodeNop, 0xfe0, 5)
209	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
210	DIS_ARMV8_INSN_PARAM_NONE,
211	DIS_ARMV8_INSN_PARAM_NONE,
212	DIS_ARMV8_INSN_PARAM_NONE
213	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
214
215
216	/* Various hint instructions */
217	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Hints)
218	DIS_ARMV8_OP(0xffffffff, 0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
219	DIS_ARMV8_OP(0xffffffff, 0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
220	DIS_ARMV8_OP(0xffffffff, 0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
221	DIS_ARMV8_OP(0xffffffff, 0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
222	DIS_ARMV8_OP(0xffffffff, 0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
223	DIS_ARMV8_OP(0xffffffff, 0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
224	DIS_ARMV8_OP(0xffffffff, 0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
225	DIS_ARMV8_OP(0xffffffff, 0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
226	/** @todo */
227	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Hints, 0 /fClass/,
228	kDisArmV8OpcDecodeNop, 0xfe0, 5)
229	DIS_ARMV8_INSN_PARAM_NONE,
230	DIS_ARMV8_INSN_PARAM_NONE,
231	DIS_ARMV8_INSN_PARAM_NONE,
232	DIS_ARMV8_INSN_PARAM_NONE
233	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
234
235
236	/* CLREX */
237	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64DecBarriers)
238	DIS_ARMV8_OP(0xfffff0ff, 0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
239	DIS_ARMV8_OP(0xfffff0ff, 0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
240	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64DecBarriers, 0 /fClass/,
241	kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5)
242	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 0 /idxParam/),
243	DIS_ARMV8_INSN_PARAM_NONE,
244	DIS_ARMV8_INSN_PARAM_NONE,
245	DIS_ARMV8_INSN_PARAM_NONE
246	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
247
248
249	/* Barrier instructions, we divide these instructions further based on the op2 field. */
250	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DecodeBarriers)
251	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
252	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
253	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64DecBarriers), /* CLREX */
254	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
255	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
256	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64DecBarriers), /* DMB */
257	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
258	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
259	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
260
261
262	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
263	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64PState)
264	DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED),
265	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64PState, 0 /fClass/,
266	kDisArmV8OpcDecodeNop, 0, 0)
267	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
268	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value */
269	DIS_ARMV8_INSN_PARAM_NONE,
270	DIS_ARMV8_INSN_PARAM_NONE
271	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
272
273
274	/* TSTART/TTEST */
275	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysResult)
276	DIS_ARMV8_OP(0xfffffffe, 0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
277	DIS_ARMV8_OP(0xfffffffe, 0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
278	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysResult, DISARMV8INSNCLASS_F_FORCED_64BIT,
279	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8)
280	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
281	DIS_ARMV8_INSN_PARAM_NONE,
282	DIS_ARMV8_INSN_PARAM_NONE,
283	DIS_ARMV8_INSN_PARAM_NONE
284	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
285
286
287	/* SYS */
288	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Sys)
289	DIS_ARMV8_OP(0xfff80000, 0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
290	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Sys, DISARMV8INSNCLASS_F_FORCED_64BIT,
291	kDisArmV8OpcDecodeNop, 0, 0)
292	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 0 /idxParam/),
293	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
294	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 2 /idxParam/),
295	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 3 /idxParam/)
296	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
297
298
299	/* SYSL */
300	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysL)
301	DIS_ARMV8_OP(0xfff80000, 0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
302	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysL, DISARMV8INSNCLASS_F_FORCED_64BIT,
303	kDisArmV8OpcDecodeNop, 0, 0)
304	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
305	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 1 /idxParam/),
306	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
307	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 3 /idxParam/)
308	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
309
310
311	/* MSR */
312	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Msr)
313	DIS_ARMV8_OP(0xfff00000, 0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
314	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Msr, DISARMV8INSNCLASS_F_FORCED_64BIT,
315	kDisArmV8OpcDecodeNop, 0, 0)
316	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
317	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 1 /idxParam/),
318	DIS_ARMV8_INSN_PARAM_NONE,
319	DIS_ARMV8_INSN_PARAM_NONE
320	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
321
322
323	/* MRS */
324	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Mrs)
325	DIS_ARMV8_OP(0xfff00000, 0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
326	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Mrs, DISARMV8INSNCLASS_F_FORCED_64BIT,
327	kDisArmV8OpcDecodeNop, 0, 0)
328	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
329	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
330	DIS_ARMV8_INSN_PARAM_NONE,
331	DIS_ARMV8_INSN_PARAM_NONE
332	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
333
334
335	/* RET/RETAA/RETAB */
336	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Ret)
337	DIS_ARMV8_OP(0xfffffc1f, 0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS),
338	DIS_ARMV8_OP(0xfffffc1f, 0xd65f0800, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS),
339	DIS_ARMV8_OP(0xfffffc1f, 0xd65f0c00, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS),
340	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Ret, DISARMV8INSNCLASS_F_FORCED_64BIT,
341	kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0)
342	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 0 /idxParam/),
343	DIS_ARMV8_INSN_PARAM_NONE,
344	DIS_ARMV8_INSN_PARAM_NONE,
345	DIS_ARMV8_INSN_PARAM_NONE
346	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
347
348
349	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
350	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64UncondBrReg)
351	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
352	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
353	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Ret), /* RET/RETAA/RETAB */
354	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
355	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
356	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
357	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
358	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
359	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
360	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
361	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
362	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
363	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
364	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
365	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
366	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
367	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
368
369
370	/* B/BL */
371	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64UncondBrImm)
372	DIS_ARMV8_OP(0xfc000000, 0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
373	DIS_ARMV8_OP(0xfc000000, 0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
374	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64UncondBrImm, 0 /fClass/,
375	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31)
376	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
377	DIS_ARMV8_INSN_PARAM_NONE,
378	DIS_ARMV8_INSN_PARAM_NONE,
379	DIS_ARMV8_INSN_PARAM_NONE
380	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
381
382
383	/* CBZ/CBNZ */
384	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CmpBrImm)
385	DIS_ARMV8_OP(0x7f000000, 0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
386	DIS_ARMV8_OP(0x7f000000, 0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
387	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CmpBrImm, DISARMV8INSNCLASS_F_SF,
388	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24)
389	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
390	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
391	DIS_ARMV8_INSN_PARAM_NONE,
392	DIS_ARMV8_INSN_PARAM_NONE
393	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
394
395
396	/* TBZ/TBNZ */
397	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64TestBrImm)
398	DIS_ARMV8_OP(0x7f000000, 0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
399	DIS_ARMV8_OP(0x7f000000, 0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
400	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64TestBrImm, DISARMV8INSNCLASS_F_SF,
401	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24)
402	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /idxParam/),
403	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 19, 5, 1 /idxParam/),
404	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
405	DIS_ARMV8_INSN_PARAM_NONE
406	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
407
408
409	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(g_ArmV8A64BrExcpSys)
410	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), g_ArmV8A64CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
411	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), g_ArmV8A64Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
412	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, g_ArmV8A64SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
413	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, g_ArmV8A64Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
414	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, g_ArmV8A64DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
415	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, g_ArmV8A64PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
416	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
417	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, g_ArmV8A64Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
418	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, g_ArmV8A64SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
419	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, g_ArmV8A64Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
420	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, g_ArmV8A64Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
421	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, g_ArmV8A64UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
422	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, g_ArmV8A64UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
423	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, g_ArmV8A64CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
424	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, g_ArmV8A64TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
425	DIS_ARMV8_DECODE_TBL_DEFINE_END(g_ArmV8A64BrExcpSys);
426
427
428	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64LogicalAddSubReg)
429	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Logical (shifted register) */
430	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Add/subtract (shifted/extended register) */
431	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64LogicalAddSubReg, RT_BIT_32(24), 24);
432
433
434	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DataProcReg)
435	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
436	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DataProcReg, RT_BIT_32(24), 24);
437
438
439	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64LdSt)
440	DIS_ARMV8_OP(0xbfc00000, 0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
441	DIS_ARMV8_OP(0xbfc00000, 0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
442	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LdSt, 0 /fClass/,
443	kDisArmV8OpcDecodeLookup, 0xbfc00000, 0)
444	DIS_ARMV8_INSN_PARAM_CREATE( kDisParmParseIs32Bit, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET),
445	DIS_ARMV8_INSN_PARAM_CREATE( kDisParmParseReg, 0, 5, 0 /idxParam/),
446	DIS_ARMV8_INSN_PARAM_CREATE_EX(kDisParmParseReg, 5, 5, 1 /idxParam/, DIS_ARMV8_INSN_PARAM_F_ADDR_BEGIN),
447	DIS_ARMV8_INSN_PARAM_CREATE_EX(kDisParmParseImm, 10, 12, 2 /idxParam/, DIS_ARMV8_INSN_PARAM_F_ADDR_END),
448	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
449
450
451	/*
452	* C4.1 of the ARMv8 architecture reference manual has the following table for the
453	* topmost decoding level (Level 0 in our terms), x means don't care:
454	*
455	* Bit 28 27 26 25
456	* +-------------------------------------------
457	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
458	* 0 0 0 1 UNALLOC
459	* 0 0 1 0 SVE encodings
460	* 0 0 1 1 UNALLOC
461	* 1 0 0 x Data processing immediate
462	* 1 0 1 x Branch, exception generation and system instructions
463	* x 1 x 0 Loads and stores
464	* x 1 0 1 Data processing - register
465	* x 1 1 1 Data processing - SIMD and floating point
466	*
467	* In order to save us some fiddling with the don't care bits we blow up the lookup table
468	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
469	* lookup table for the next level:
470	* Bit 28 27 26 25
471	* +-------------------------------------------
472	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
473	* 1 0 0 0 1 UNALLOC
474	* 2 0 0 1 0 SVE encodings
475	* 3 0 0 1 1 UNALLOC
476	* 4 0 1 0 0 Loads and stores
477	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
478	* 6 0 1 1 0 Loads and stores
479	* 7 0 1 1 1 Data processing - SIMD and floating point
480	* 8 1 0 0 0 Data processing immediate
481	* 9 1 0 0 1 Data processing immediate
482	* 10 1 0 1 0 Branch, exception generation and system instructions
483	* 11 1 0 1 1 Branch, exception generation and system instructions
484	* 12 1 1 0 0 Loads and stores
485	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
486	* 14 1 1 1 0 Loads and stores
487	* 15 1 1 1 1 Data processing - SIMD and floating point
488	*/
489	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DecodeL0)
490	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnRsvd), /* Reserved class or SME encoding (@todo). */
491	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
492	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
493	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
494	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */
495	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
496	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */
497	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data processing (SIMD & FP) */
498	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnDataProcessingImm), /* Data processing (immediate). */
499	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnDataProcessingImm), /* Data processing (immediate). */
500	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64BrExcpSys), /* Branches / Exception generation and system instructions. */
501	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64BrExcpSys), /* Branches / Exception generation and system instructions. */
502	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LdSt), /* Load/Stores. */
503	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
504	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */
505	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /* Data processing (SIMD & FP). */
506	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(g_ArmV8A64DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 105736

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