DisasmTables-armv8-a64.cpp@ 105827

Last change on this file since 105827 was 105815, checked in by vboxsync, 6 months ago
Disassembler/ARMv8: Started decoding more ldr/str instruction variants, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 105815 2024-08-22 12:25:28Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fValue, 0, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43	#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44	{ a_fValue, a_fFlags, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45
46	#ifndef DIS_CORE_ONLY
47	static char g_szInvalidOpcode[] = "Invalid Opcode";
48	#endif
49
50	#define INVALID_OPCODE \
51	DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
52
53
54	/* Invalid opcode */
55	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
56	{
57	OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
58	};
59
60
61	/* UDF */
62	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
63	DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
64	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
65	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /idxParam/),
66	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Rsvd, 0xffff0000 /fFixedInsn/, 0 /fClass/,
67	kDisArmV8OpcDecodeNop, 0xffff0000, 16,
68	kDisArmv8OpParmImm);
69
70	/* ADR/ADRP */
71	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
72	DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
73	DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
74	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
75	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
76	DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Adr, 0x9f000000 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
78	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31,
79	kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel);
80
81
82	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
83	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
84	DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
85	DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
86	DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
87	DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
88	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
89	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
91	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /idxParam/),
92	DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /idxParam/),
93	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubImm, 0x7f800000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
94	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
95	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm);
96
97
98	/* ADD/ADDS/SUB/SUBS - shifted register variant */
99	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
100	DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
101	DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
102	DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
103	DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
104	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
105	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 16, 5, 2 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
109	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
110	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubShiftReg, 0x7f200000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
111	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
112	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr);
113
114
115	/* AND/ORR/EOR/ANDS */
116	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
117	DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
118	DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
119	DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
120	DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
121	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
122	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
123	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
124	DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
125	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogicalImm, 0x7f800000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
126	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
127	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm);
128
129
130	/* MOVN/MOVZ/MOVK */
131	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
132	DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
133	INVALID_OPCODE,
134	DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
135	DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
136	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
137	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
138	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /idxParam/),
139	DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /idxParam/),
140	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(MoveWide, 0x7f800000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
141	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
142	kDisArmv8OpParmGpr, kDisArmv8OpParmImm);
143
144
145	/* SBFM/BFM/UBFM */
146	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
147	DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
148	DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
149	DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
150	INVALID_OPCODE,
151	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
152	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
156	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(Bitfield, 0x7f800000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF \| DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT,
157	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
158	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImm);
159
160
161	/*
162	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
163	* data processing (immediate) instruction classes:
164	*
165	* Bit 25 24 23
166	* +-------------------------------------------
167	* 0 0 x PC-rel. addressing.
168	* 0 1 0 Add/subtract (immediate)
169	* 0 1 1 Add/subtract (immediate, with tags)
170	* 1 0 0 Logical (immediate)
171	* 1 0 1 Move wide (immediate)
172	* 1 1 0 Bitfield
173	* 1 1 1 Extract
174	*/
175	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
176	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
177	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
178	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
179	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
180	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
181	DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
182	DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
183	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */
184	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
185
186
187	/* B.cond/BC.cond */
188	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
189	DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
190	DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
191	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
192	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
193	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /idxParam/),
194	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(CondBr, 0xff000010 /fFixedInsn/, 0 /fClass/,
195	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4,
196	kDisArmv8OpParmImmRel);
197
198
199	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
200	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
201	DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
202	DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
203	DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
204	DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
205	DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
206	DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
207	DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
208	DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
209	DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
210	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
211	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /idxParam/),
212	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Excp, 0xffe0001f /fFixedInsn/, 0 /fClass/,
213	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0,
214	kDisArmv8OpParmImm);
215
216
217	/* WFET/WFIT */
218	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
219	DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
220	DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
221	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
222	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
223	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysReg, 0xffffffe0 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
224	kDisArmV8OpcDecodeNop, 0xfe0, 5,
225	kDisArmv8OpParmGpr);
226
227
228	/* Various hint instructions */
229	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
230	DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
231	DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
232	DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
234	DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
235	DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
236	DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
237	DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
238	/** @todo */
239	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
240	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Hints, 0xffffffff /fFixedInsn/, 0 /fClass/,
241	kDisArmV8OpcDecodeNop, 0xfe0, 5);
242
243
244	/* CLREX */
245	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
246	DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
247	DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
248	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
249	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
250	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(DecBarriers, 0xfffff0ff /fFixedInsn/, 0 /fClass/,
251	kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5,
252	kDisArmv8OpParmImm);
253
254
255	/* Barrier instructions, we divide these instructions further based on the op2 field. */
256	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
257	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
258	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
259	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
260	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
261	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
262	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
263	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
264	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
265	DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
266
267
268	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
269	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
270	DIS_ARMV8_OP(0xd503305f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
271	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
272	DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
273	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value */
274	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(PState, 0xfffff0ff /fFixedInsn/, 0 /fClass/,
275	kDisArmV8OpcDecodeNop, 0, 0,
276	kDisArmv8OpParmImm, kDisArmv8OpParmNone); /** @todo */
277
278
279	/* TSTART/TTEST */
280	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
281	DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
282	DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
283	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
284	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
285	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysResult, 0xfffffffe /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
286	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8,
287	kDisArmv8OpParmGpr);
288
289
290	/* SYS */
291	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
292	DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
293	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
294	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /idxParam/),
295	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
296	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /idxParam/),
297	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 3 /idxParam/),
298	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Sys, 0xfff80000 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
299	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
300
301
302	/* SYSL */
303	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
304	DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
305	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
306	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
307	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /idxParam/),
308	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
309	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /idxParam/),
310	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(SysL, 0xfff80000 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
311	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
312
313
314	/* MSR */
315	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
316	DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
317	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
318	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
319	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 1 /idxParam/),
320	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Msr, 0xfff00000 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
321	kDisArmV8OpcDecodeNop, 0, 0,
322	kDisArmv8OpParmSysReg, kDisArmv8OpParmGpr);
323
324
325	/* MRS */
326	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
327	DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
328	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
329	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
330	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
331	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Mrs, 0xfff00000 /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
332	kDisArmV8OpcDecodeNop, 0, 0,
333	kDisArmv8OpParmGpr, kDisArmv8OpParmSysReg);
334
335
336	/* BR/BRAA/BRAAZ/BRAB/BRABZ/BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ/RET/RETAA/RETAB */
337	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BrBlrRet)
338	DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
339	DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
340	/** @todo All the FEAT_PAuth related branch instructions. */
341	DIS_ARMV8_OP(0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
342	DIS_ARMV8_OP(0xd65f0800, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
343	DIS_ARMV8_OP(0xd65f0c00, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
344	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BrBlrRet)
345	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 0 /idxParam/),
346	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(BrBlrRet, 0xfffffc1f /fFixedInsn/, DISARMV8INSNCLASS_F_FORCED_64BIT,
347	kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0,
348	kDisArmv8OpParmGpr);
349
350
351	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
352	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
353	DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BR/BRAA/BRAAZ/BRAB/BRABZ */
354	DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
355	DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* RET/RETAA/RETAB */
356	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
357	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
358	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
359	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
360	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
361	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
362	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
363	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
364	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
365	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
366	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
367	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
368	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
369	DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
370
371
372	/* B/BL */
373	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
374	DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
375	DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
376	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
377	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
378	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(UncondBrImm, 0xfc000000 /fFixedInsn/, 0 /fClass/,
379	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31,
380	kDisArmv8OpParmImmRel);
381
382
383	/* CBZ/CBNZ */
384	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
385	DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
386	DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
387	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
388	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
389	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
390	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(CmpBrImm, 0x7f000000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
391	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24,
392	kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel);
393
394
395	/* TBZ/TBNZ */
396	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
397	DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
398	DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
399	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
400	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
401	DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /idxParam/), /* Hardcoded bit offsets in parser. */
402	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
403	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(TestBrImm, 0x7f000000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF, /* Not an SF bit but has the same meaning. */
404	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24,
405	kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImmRel);
406
407
408	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
409	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
410	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
411	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
412	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
413	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
414	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
415	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
416	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
417	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
418	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
419	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
420	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
421	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
422	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
423	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
424	DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
425
426
427	/* AND/ORR/EOR/ANDS */
428	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
429	DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
430	DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
431	DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
432	DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
433	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
434	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
435	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
436	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 16, 5, 2 /idxParam/),
437	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
438	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
439	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN0, 0x7f200000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
440	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
441	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr);
442
443
444	/* AND/ORR/EOR/ANDS */
445	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
446	DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
447	DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
448	DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
449	DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
450	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
451	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
452	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
453	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 16, 5, 2 /idxParam/),
454	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
455	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
456	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN1, 0x7f200000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
457	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29,
458	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr);
459
460
461	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
462	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
463	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
464	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
465
466
467	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
468	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
469	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24);
470
471
472	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
473	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
474	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
475	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
476
477
478	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
479	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
480	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
481	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
482
483
484	/* CCMN/CCMP */
485	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
486	DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
487	DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
488	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
489	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 0 /idxParam/),
490	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 16, 5, 1 /idxParam/),
491	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
492	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
493	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(CondCmpReg, 0x7fe00c10 /fFixedInsn/, DISARMV8INSNCLASS_F_SF,
494	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30,
495	kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmCond);
496
497
498	/**
499	* C4.1.95 - Data Processing - Register
500	*
501	* The conditional compare instructions differentiate between register and immediate
502	* variant based on the 11th bit (part of op3).
503	*/
504	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
505	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
506	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional compare immediate */
507	DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
508
509
510	/*
511	* C4.1.95 - Data Processing - Register
512	*
513	* The op1 field is already decoded in the previous step and is 1 when being here,
514	* leaving us with the following possible values:
515	*
516	* Bit 24 23 22 21
517	* +-------------------------------------------
518	* 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
519	* 0 0 0 1 UNALLOC
520	* 0 0 1 0 Conditional compare (register / immediate)
521	* 0 0 1 1 UNALLOC
522	* 0 1 0 0 Conditional select
523	* 0 1 0 1 UNALLOC
524	* 0 1 1 0 Data processing (2-source or 1-source depending on op0).
525	* 0 1 1 1 UNALLOC
526	* 1 x x x Data processing 3-source
527	*/
528	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
529	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract with carry. */
530	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
531	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp), /** @todo Conditional compare. */
532	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
533	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional select. */
534	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
535	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 2-source/1-source. */
536	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
537	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
538	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
539	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
540	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
541	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
542	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
543	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
544	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
545	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
546
547
548	/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
549	*
550	* Note: The size,opc bitfields are concatenated to form an index.
551	*/
552	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
553	DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
554	DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
555	DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
556	DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
557	DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
558	DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
559	DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
560	DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
561	DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
562	DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
563	DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
564	INVALID_OPCODE,
565	DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
566	DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
567	INVALID_OPCODE, /** @todo PRFM */
568	INVALID_OPCODE,
569	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
570	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
571	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
572	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
573	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
574	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegUImmGpr, 0xffc00000 /fFixedInsn/, 0 /fClass/,
575	kDisArmV8OpcDecodeCollate,
576	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22,
577	kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr);
578
579
580	/*
581	* C4.1.94 - Loads and Stores - Load/Store register variants
582	*
583	* Differentiate further based on the VR field.
584	*
585	* Bit 26
586	* +-------------------------------------------
587	* 0 GPR variants.
588	* 1 SIMD/FP variants
589	*/
590	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
591	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
592	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
593	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
594
595
596	/*
597	* C4.1.94 - Loads and Stores - Load/Store register variants
598	*
599	* Differentiate further based on the op2<14> field.
600	*
601	* Bit 14
602	* +-------------------------------------------
603	* 0 All the other Load/store register variants and Atomic memory operations.
604	* 1 Load/store register (unsigned immediate).
605	*/
606	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
607	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
608	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
609	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
610
611
612	/*
613	* C4.1.94 - Loads and Stores
614	*
615	* Differentiate further based on the op0<1:0> field.
616	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
617	*
618	* Bit 29 28
619	* +-------------------------------------------
620	* 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
621	* Load/store ordered / Compare and swap
622	* 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
623	* LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
624	* 1 0 Load/store no-allocate pair / Load/store register pair /
625	* 1 1 Load/store register / Atomic memory operations
626	*/
627	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
628	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
629	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
630	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
631	DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
632	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) \| RT_BIT_32(29), 28);
633
634
635	/*
636	* C4.1 of the ARMv8 architecture reference manual has the following table for the
637	* topmost decoding level (Level 0 in our terms), x means don't care:
638	*
639	* Bit 28 27 26 25
640	* +-------------------------------------------
641	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
642	* 0 0 0 1 UNALLOC
643	* 0 0 1 0 SVE encodings
644	* 0 0 1 1 UNALLOC
645	* 1 0 0 x Data processing immediate
646	* 1 0 1 x Branch, exception generation and system instructions
647	* x 1 x 0 Loads and stores
648	* x 1 0 1 Data processing - register
649	* x 1 1 1 Data processing - SIMD and floating point
650	*
651	* In order to save us some fiddling with the don't care bits we blow up the lookup table
652	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
653	* lookup table for the next level:
654	* Bit 28 27 26 25
655	* +-------------------------------------------
656	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
657	* 1 0 0 0 1 UNALLOC
658	* 2 0 0 1 0 SVE encodings
659	* 3 0 0 1 1 UNALLOC
660	* 4 0 1 0 0 Loads and stores
661	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
662	* 6 0 1 1 0 Loads and stores
663	* 7 0 1 1 1 Data processing - SIMD and floating point
664	* 8 1 0 0 0 Data processing immediate
665	* 9 1 0 0 1 Data processing immediate
666	* 10 1 0 1 0 Branch, exception generation and system instructions
667	* 11 1 0 1 1 Branch, exception generation and system instructions
668	* 12 1 1 0 0 Loads and stores
669	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
670	* 14 1 1 1 0 Loads and stores
671	* 15 1 1 1 1 Data processing - SIMD and floating point
672	*/
673	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
674	DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
675	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
676	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
677	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
678	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
679	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
680	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
681	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data processing (SIMD & FP) */
682	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
683	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
684	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
685	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
686	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
687	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
688	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
689	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /* Data processing (SIMD & FP). */
690	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 105827

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