VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 106624

Last change on this file since 106624 was 106618, checked in by vboxsync, 3 months ago

Disassembler: Get rid of fClass member and convert the only real use to a decoder step, bugref:10394

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1/* $Id: DisasmTables-armv8-a64.cpp 106618 2024-10-23 11:59:34Z vboxsync $ */
2/** @file
3 * VBox disassembler - Tables for ARMv8 A64.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#include <VBox/dis.h>
33#include <VBox/disopcode-armv8.h>
34#include "DisasmInternal-armv8.h"
35
36
37/*********************************************************************************************************************************
38* Global Variables *
39*********************************************************************************************************************************/
40
41#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42 { a_fValue, 0, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44 { a_fValue, a_fFlags, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45
46#ifndef DIS_CORE_ONLY
47static char g_szInvalidOpcode[] = "Invalid Opcode";
48#endif
49
50#define INVALID_OPCODE \
51 DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
52
53
54/* Invalid opcode */
55DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
56{
57 OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
58};
59
60
61/* Include the secondary tables. */
62#include "DisasmTables-armv8-a64-simd-fp.cpp.h"
63
64/* UDF */
65DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
66 DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
67DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
68 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /*idxParam*/),
69DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Rsvd, 0xffff0000 /*fFixedInsn*/,
70 kDisArmV8OpcDecodeNop, 0xffff0000, 16,
71 kDisArmv8OpParmImm);
72
73/* ADR/ADRP */
74DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
75 DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
76 DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
77DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
78 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
79 DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /*idxParam*/),
80DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Adr, 0x9f000000 /*fFixedInsn*/,
81 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31,
82 kDisArmv8OpParmReg, kDisArmv8OpParmImmRel);
83
84
85/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
86DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
87 DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
88 DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
89 DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
90 DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
91DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
92 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
93 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
94 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /*idxParam*/),
95 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /*idxParam*/),
96 DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /*idxParam*/),
97DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubImm, 0x7f800000 /*fFixedInsn*/,
98 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
99 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
100
101
102/* ADD/ADDS/SUB/SUBS - shifted register variant */
103DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
104 DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
105 DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
106 DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
107 DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
108DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
109 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
110 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
111 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /*idxParam*/),
112 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /*idxParam*/),
113 DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /*idxParam*/),
114 DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/),
115DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubShiftReg, 0x7f200000 /*fFixedInsn*/,
116 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
117 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
118
119
120/* AND/ORR/EOR/ANDS */
121DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
122 DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
123 DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
124 DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
125 DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
126DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
127 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
128 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /*idxParam*/),
129 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /*idxParam*/),
130 DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /*idxParam*/),
131DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogicalImm, 0x7f800000 /*fFixedInsn*/,
132 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
133 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
134
135
136/* MOVN/MOVZ/MOVK */
137DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
138 DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
139 INVALID_OPCODE,
140 DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
141 DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
142DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
143 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
144 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
145 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /*idxParam*/),
146 DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /*idxParam*/),
147DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(MoveWide, 0x7f800000 /*fFixedInsn*/,
148 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
149 kDisArmv8OpParmReg, kDisArmv8OpParmImm);
150
151
152/* SBFM/BFM/UBFM */
153DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
154 DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
155 DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
156 DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
157 INVALID_OPCODE,
158DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
159 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
160 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
161 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /*idxParam*/),
162 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /*idxParam*/),
163 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /*idxParam*/),
164DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(Bitfield, 0x7f800000 /*fFixedInsn*/,
165 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
166 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm, kDisArmv8OpParmImm);
167
168
169/*
170 * C4.1.65 of the ARMv8 architecture reference manual has the following table for the
171 * data processing (immediate) instruction classes:
172 *
173 * Bit 25 24 23
174 * +-------------------------------------------
175 * 0 0 x PC-rel. addressing.
176 * 0 1 0 Add/subtract (immediate)
177 * 0 1 1 Add/subtract (immediate, with tags)
178 * 1 0 0 Logical (immediate)
179 * 1 0 1 Move wide (immediate)
180 * 1 1 0 Bitfield
181 * 1 1 1 Extract
182 */
183DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
184 DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
185 DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
186 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
187 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
188 DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
189 DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
190 DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
191 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */
192DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) | RT_BIT_32(24) | RT_BIT_32(25), 23);
193
194
195/* B.cond/BC.cond */
196DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
197 DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
198 DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
199DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
200 DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
201 DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /*idxParam*/),
202DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(CondBr, 0xff000010 /*fFixedInsn*/,
203 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4,
204 kDisArmv8OpParmImmRel);
205
206
207/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
208DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
209 DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
210 DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT | DISOPTYPE_PRIVILEGED),
211 DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT | DISOPTYPE_PRIVILEGED),
212 DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
213 DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
214 DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), /* FEAT_TME */
215 DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
216 DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
217 DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT),
218DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
219 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /*idxParam*/),
220DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Excp, 0xffe0001f /*fFixedInsn*/,
221 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0,
222 kDisArmv8OpParmImm);
223
224
225/* WFET/WFIT */
226DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
227 DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
228 DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
229DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
230 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
231DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysReg, 0xffffffe0 /*fFixedInsn*/,
232 kDisArmV8OpcDecodeNop, 0xfe0, 5,
233 kDisArmv8OpParmReg);
234
235
236/* Various hint instructions */
237DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
238 DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
239 DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
240 DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
241 DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
242 DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
243 DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
244 DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
245 DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
246 /** @todo */
247DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
248DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Hints, 0xffffffff /*fFixedInsn*/,
249 kDisArmV8OpcDecodeNop, 0xfe0, 5);
250
251
252/* CLREX */
253DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
254 INVALID_OPCODE,
255 INVALID_OPCODE,
256 DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
257 INVALID_OPCODE,
258 DIS_ARMV8_OP(0xD503309f, "dsb", OP_ARMV8_A64_DSB, DISOPTYPE_HARMLESS),
259 DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
260DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
261 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /*idxParam*/),
262DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(DecBarriers, 0xfffff0ff /*fFixedInsn*/,
263 kDisArmV8OpcDecodeNop, RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7), 5,
264 kDisArmv8OpParmImm);
265
266
267/* Barrier instructions, we divide these instructions further based on the op2 field. */
268DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
269 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
270 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
271 DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
272 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
273 DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DSB - Encoding */
274 DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
275 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
276 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
277DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7), 5);
278
279
280/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
281DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
282 DIS_ARMV8_OP(0xd500401f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
283DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
284 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /*idxParam*/), /* CRm field encodes the immediate value, gets validated by the next decoder stage. */
285 DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /*idxParam*/), /* This is special for the MSR instruction. */
286DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(PState, 0xfff8f01f /*fFixedInsn*/,
287 kDisArmV8OpcDecodeNop, 0, 0,
288 kDisArmv8OpParmPState, kDisArmv8OpParmImm);
289
290
291/* TSTART/TTEST */
292DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
293 DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), /* FEAT_TME */
294 DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
295DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
296 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
297DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysResult, 0xfffffffe /*fFixedInsn*/,
298 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8,
299 kDisArmv8OpParmReg);
300
301
302/* SYS */
303DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
304 DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
305DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
306 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /*idxParam*/),
307 DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /*idxParam*/),
308 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /*idxParam*/),
309 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 3 /*idxParam*/),
310DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Sys, 0xfff80000 /*fFixedInsn*/,
311 kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
312
313
314/* SYSL */
315DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
316 DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
317DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
318 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
319 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /*idxParam*/),
320 DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /*idxParam*/),
321 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /*idxParam*/),
322DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(SysL, 0xfff80000 /*fFixedInsn*/,
323 kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
324
325
326/* MSR */
327DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
328 DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED),
329DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
330 DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /*idxParam*/),
331 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 1 /*idxParam*/),
332DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Msr, 0xfff00000 /*fFixedInsn*/,
333 kDisArmV8OpcDecodeNop, 0, 0,
334 kDisArmv8OpParmSysReg, kDisArmv8OpParmReg);
335
336
337/* MRS */
338DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
339 DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED),
340DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
341 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
342 DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /*idxParam*/),
343DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Mrs, 0xfff00000 /*fFixedInsn*/,
344 kDisArmV8OpcDecodeNop, 0, 0,
345 kDisArmv8OpParmReg, kDisArmv8OpParmSysReg);
346
347
348/* BR/BRAA/BRAAZ/BRAB/BRABZ/BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ/RET/RETAA/RETAB */
349DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BrBlrRet)
350 DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
351 DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
352 /** @todo All the FEAT_PAuth related branch instructions. */
353 DIS_ARMV8_OP(0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
354 DIS_ARMV8_OP(0xd65f0800, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
355 DIS_ARMV8_OP(0xd65f0c00, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
356DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BrBlrRet)
357 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /*idxParam*/),
358DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(BrBlrRet, 0xfffffc1f /*fFixedInsn*/,
359 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0,
360 kDisArmv8OpParmReg);
361
362
363/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
364DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
365 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BR/BRAA/BRAAZ/BRAB/BRABZ */
366 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
367 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* RET/RETAA/RETAB */
368 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
369 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
370 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
371 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
372 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
373 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
374 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
375 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
376 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
377 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
378 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
379 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
380 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
381DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21);
382
383
384/* B/BL */
385DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
386 DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
387 DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
388DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
389 DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /*idxParam*/),
390DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(UncondBrImm, 0xfc000000 /*fFixedInsn*/,
391 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31,
392 kDisArmv8OpParmImmRel);
393
394
395/* CBZ/CBNZ */
396DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
397 DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
398 DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
399DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
400 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
401 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
402 DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /*idxParam*/),
403DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(CmpBrImm, 0x7f000000 /*fFixedInsn*/,
404 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24,
405 kDisArmv8OpParmReg, kDisArmv8OpParmImmRel);
406
407
408/* TBZ/TBNZ */
409DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
410 DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
411 DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
412DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
413 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not an SF bit but has the same meaning. */
414 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
415 DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /*idxParam*/), /* Hardcoded bit offsets in parser. */
416 DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /*idxParam*/),
417DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(TestBrImm, 0x7f000000 /*fFixedInsn*/,
418 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24,
419 kDisArmv8OpParmReg, kDisArmv8OpParmImm, kDisArmv8OpParmImmRel);
420
421
422DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
423 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
424 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30) | RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
425 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
426 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
427 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
428 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
429 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
430 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
431 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
432 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
433 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
434 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
435 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
436 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
437 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
438DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
439
440
441/* AND/ORR/EOR/ANDS */
442DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
443 DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
444 DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
445 DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
446 DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
447DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
448 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
449 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
450 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /*idxParam*/),
451 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /*idxParam*/),
452 DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /*idxParam*/),
453 DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/),
454DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN0, 0x7f200000 /*fFixedInsn*/,
455 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
456 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
457
458
459/* AND/ORR/EOR/ANDS */
460DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
461 DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
462 DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
463 DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
464 DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
465DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
466 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
467 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
468 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /*idxParam*/),
469 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /*idxParam*/),
470 DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /*idxParam*/),
471 DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/),
472DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN1, 0x7f200000 /*fFixedInsn*/,
473 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
474 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
475
476
477DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
478 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
479 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
480DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
481
482
483DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
484 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
485DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24);
486
487
488DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
489 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
490 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
491DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
492
493
494DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
495 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
496 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
497DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
498
499
500/* CCMN/CCMP */
501DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
502 DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
503 DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
504DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
505 DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
506 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /*idxParam*/),
507 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 1 /*idxParam*/),
508 DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /*idxParam*/),
509 DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /*idxParam*/),
510DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(CondCmpReg, 0x7fe00c10 /*fFixedInsn*/,
511 kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30,
512 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm, kDisArmv8OpParmCond);
513
514
515/**
516 * C4.1.95 - Data Processing - Register
517 *
518 * The conditional compare instructions differentiate between register and immediate
519 * variant based on the 11th bit (part of op3).
520 */
521DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
522 DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
523 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional compare immediate */
524DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
525
526
527/*
528 * C4.1.95 - Data Processing - Register
529 *
530 * The op1 field is already decoded in the previous step and is 1 when being here,
531 * leaving us with the following possible values:
532 *
533 * Bit 24 23 22 21
534 * +-------------------------------------------
535 * 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
536 * 0 0 0 1 UNALLOC
537 * 0 0 1 0 Conditional compare (register / immediate)
538 * 0 0 1 1 UNALLOC
539 * 0 1 0 0 Conditional select
540 * 0 1 0 1 UNALLOC
541 * 0 1 1 0 Data processing (2-source or 1-source depending on op0).
542 * 0 1 1 1 UNALLOC
543 * 1 x x x Data processing 3-source
544 */
545DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
546 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract with carry. */
547 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
548 DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp), /** @todo Conditional compare. */
549 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
550 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional select. */
551 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
552 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 2-source/1-source. */
553 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
554 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
555 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
556 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
557 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
558 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
559 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
560 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
561 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
562DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21);
563
564
565/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
566 *
567 * Note: The size,opc bitfields are concatenated to form an index.
568 */
569DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
570 DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
571 DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
572 DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
573 DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
574 DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
575 DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
576 DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
577 DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
578 DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
579 DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
580 DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
581 INVALID_OPCODE,
582 DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
583 DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
584 INVALID_OPCODE, /** @todo PRFM */
585 INVALID_OPCODE,
586DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
587 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
588 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
589 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /*idxParam*/),
590 DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/),
591DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegUImmGpr, 0xffc00000 /*fFixedInsn*/,
592 kDisArmV8OpcDecodeCollate,
593 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22,
594 kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
595
596
597/*
598 * C4.1.94 - Loads and Stores - Load/Store register variants
599 *
600 * Differentiate further based on the VR field.
601 *
602 * Bit 26
603 * +-------------------------------------------
604 * 0 GPR variants.
605 * 1 SIMD/FP variants
606 */
607DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
608 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
609 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
610DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
611
612
613/*
614 * STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
615 *
616 * Note: The size,opc bitfields are concatenated to form an index.
617 */
618DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
619 DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
620 DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
621 DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
622 DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
623 DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
624 DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
625 DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
626 DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
627 DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
628 DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
629 DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
630 INVALID_OPCODE,
631 DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
632 DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
633 INVALID_OPCODE, /** @todo PRFM */
634 INVALID_OPCODE,
635DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
636 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
637 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
638 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /*idxParam*/),
639 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/),
640 DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /*idxParam*/),
641 DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /*idxParam*/),
642DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegOffGpr, 0xffe00c00 /*fFixedInsn*/,
643 kDisArmV8OpcDecodeCollate,
644 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22,
645 kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
646
647
648/*
649 * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
650 *
651 * Differentiate further based on the VR field.
652 *
653 * Bit 26
654 * +-------------------------------------------
655 * 0 GPR variants.
656 * 1 SIMD/FP variants
657 */
658DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
659 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
660 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
661DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
662
663
664/*
665 * C4.1.94 - Loads and Stores - Load/Store register variants
666 *
667 * Differentiate further based on the op2<1:0> field.
668 *
669 * Bit 11 10
670 * +-------------------------------------------
671 * 0 0 Atomic memory operations
672 * 0 1 Load/store register (pac)
673 * 1 0 Load/store register (register offset)
674 * 1 1 Load/store register (pac)
675 */
676DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
677 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
678 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
679 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
680 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
681DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) | RT_BIT_32(11), 10);
682
683
684/*
685 * STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
686 *
687 * Note: The size,opc bitfields are concatenated to form an index.
688 */
689DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
690 DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
691 DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
692 DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
693 DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
694 DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
695 DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
696 DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
697 DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
698 DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
699 DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
700 DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
701 INVALID_OPCODE,
702 DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
703 DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
704 INVALID_OPCODE, /** @todo PRFUM */
705 INVALID_OPCODE,
706DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
707 DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
708 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
709 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /*idxParam*/),
710 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /*idxParam*/),
711DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegUnscaledImmGpr, 0xffe00c00 /*fFixedInsn*/,
712 kDisArmV8OpcDecodeCollate,
713 RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22,
714 kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
715
716
717/*
718 * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
719 *
720 * Differentiate further based on the VR field.
721 *
722 * Bit 26
723 * +-------------------------------------------
724 * 0 GPR variants.
725 * 1 SIMD/FP variants
726 */
727DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
728 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
729 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
730DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
731
732
733/*
734 * C4.1.94 - Loads and Stores - Load/Store register variants
735 *
736 * Differentiate further based on the op2<1:0> field.
737 *
738 * Bit 11 10
739 * +-------------------------------------------
740 * 0 0 Load/store register (unscaled immediate)
741 * 0 1 Load/store register (immediate post-indexed)
742 * 1 0 Load/store register (unprivileged)
743 * 1 1 Load/store register (immediate pre-indexed)
744 */
745DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
746 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
747 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
748 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
749 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
750DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) | RT_BIT_32(11), 10);
751
752
753/*
754 * C4.1.94 - Loads and Stores - Load/Store register variants
755 *
756 * Differentiate further based on the op2<11> field.
757 *
758 * Bit 21
759 * +-------------------------------------------
760 * 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
761 * 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
762 */
763DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
764 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
765 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
766DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
767
768
769/*
770 * C4.1.94 - Loads and Stores - Load/Store register variants
771 *
772 * Differentiate further based on the op2<14> field.
773 *
774 * Bit 24
775 * +-------------------------------------------
776 * 0 All the other Load/store register variants and Atomic memory operations.
777 * 1 Load/store register (unsigned immediate).
778 */
779DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
780 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
781 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
782DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
783
784
785/*
786 * STP/LDP/STGP/LDPSW
787 *
788 * Note: The opc,L bitfields are concatenated to form an index.
789 */
790DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
791 DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
792 DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
793 INVALID_OPCODE,
794 INVALID_OPCODE,
795 DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
796 DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
797 INVALID_OPCODE,
798 INVALID_OPCODE,
799DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
800 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
801 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
802 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 2 /*idxParam*/),
803 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
804DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairOff, 0xffc00000 /*fFixedInsn*/,
805 kDisArmV8OpcDecodeCollate,
806 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
807 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
808
809
810/*
811 * STP/LDP/STGP/LDPSW - pre-indexed variant.
812 *
813 * Note: The opc,L bitfields are concatenated to form an index.
814 */
815DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
816 DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
817 DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
818 INVALID_OPCODE,
819 INVALID_OPCODE,
820 DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
821 DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
822 INVALID_OPCODE,
823 INVALID_OPCODE,
824DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
825 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
826 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
827 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 2 /*idxParam*/),
828 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
829 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /*idxParam*/),
830DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairPreIndex, 0xffc00000 /*fFixedInsn*/,
831 kDisArmV8OpcDecodeCollate,
832 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
833 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
834
835
836/*
837 * STP/LDP/STGP/LDPSW - post-indexed variant.
838 *
839 * Note: The opc,L bitfields are concatenated to form an index.
840 */
841DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
842 DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
843 DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
844 INVALID_OPCODE,
845 INVALID_OPCODE,
846 DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
847 DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
848 INVALID_OPCODE,
849 INVALID_OPCODE,
850DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
851 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /*idxParam*/),
852 DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /*idxParam*/),
853 DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 2 /*idxParam*/),
854 DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /*idxParam*/),
855 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /*idxParam*/),
856DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairPostIndex, 0xffc00000 /*fFixedInsn*/,
857 kDisArmV8OpcDecodeCollate,
858 RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
859 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmAddrInGpr);
860
861
862/*
863 * C4.1.94 - Loads and Stores - Load/Store register pair variants
864 *
865 * Differentiate further based on the op2<14:13> field.
866 *
867 * Bit 24 23
868 * +-------------------------------------------
869 * 0 0 Load/store no-allocate pair (offset)
870 * 0 1 Load/store register pair (post-indexed)
871 * 1 0 Load/store register pair (offset).
872 * 1 1 Load/store register pair (pre-indexed).
873 */
874DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
875 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
876 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
877 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
878 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
879DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) | RT_BIT_32(24), 23);
880
881
882/*
883 * C4.1.94 - Loads and Stores
884 *
885 * Differentiate further based on the op0<1:0> field.
886 * Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
887 *
888 * Bit 29 28
889 * +-------------------------------------------
890 * 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
891 * Load/store ordered / Compare and swap
892 * 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
893 * LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
894 * 1 0 Load/store no-allocate pair / Load/store register pair /
895 * 1 1 Load/store register / Atomic memory operations
896 */
897DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
898 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
899 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
900 DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
901 DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
902DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) | RT_BIT_32(29), 28);
903
904
905/*
906 * C4.1 of the ARMv8 architecture reference manual has the following table for the
907 * topmost decoding level (Level 0 in our terms), x means don't care:
908 *
909 * Bit 28 27 26 25
910 * +-------------------------------------------
911 * 0 0 0 0 Reserved or SME encoding (depends on bit 31).
912 * 0 0 0 1 UNALLOC
913 * 0 0 1 0 SVE encodings
914 * 0 0 1 1 UNALLOC
915 * 1 0 0 x Data processing immediate
916 * 1 0 1 x Branch, exception generation and system instructions
917 * x 1 x 0 Loads and stores
918 * x 1 0 1 Data processing - register
919 * x 1 1 1 Data processing - SIMD and floating point
920 *
921 * In order to save us some fiddling with the don't care bits we blow up the lookup table
922 * which gives us 16 possible values (4 bits) we can use as an index into the decoder
923 * lookup table for the next level:
924 * Bit 28 27 26 25
925 * +-------------------------------------------
926 * 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
927 * 1 0 0 0 1 UNALLOC
928 * 2 0 0 1 0 SVE encodings
929 * 3 0 0 1 1 UNALLOC
930 * 4 0 1 0 0 Loads and stores
931 * 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
932 * 6 0 1 1 0 Loads and stores
933 * 7 0 1 1 1 Data processing - SIMD and floating point
934 * 8 1 0 0 0 Data processing immediate
935 * 9 1 0 0 1 Data processing immediate
936 * 10 1 0 1 0 Branch, exception generation and system instructions
937 * 11 1 0 1 1 Branch, exception generation and system instructions
938 * 12 1 1 0 0 Loads and stores
939 * 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
940 * 14 1 1 1 0 Loads and stores
941 * 15 1 1 1 1 Data processing - SIMD and floating point
942 */
943DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
944 DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
945 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
946 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
947 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
948 DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
949 DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
950 DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
951 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0), /* Data processing (SIMD & FP) (op0<0> 0) */
952 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
953 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
954 DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
955 DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
956 DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
957 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
958 DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
959 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1) /* Data processing (SIMD & FP) (op0<0> 1). */
960DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28), 25);
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