DisasmTables-armv8-a64.cpp@ 106686

Last change on this file since 106686 was 106680, checked in by vboxsync, 7 months ago
Disasembler: Decode extr instruction, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 106680 2024-10-25 09:18:06Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fValue, 0, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43	#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44	{ a_fValue, a_fFlags, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45	#define DIS_ARMV8_OP_ALT_DECODE(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_aAltDecode) \
46	{ a_fValue, 0, &g_aArmV8A64Insn ## a_aAltDecode ## Decode[0], OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
47
48
49	#ifndef DIS_CORE_ONLY
50	static char g_szInvalidOpcode[] = "Invalid Opcode";
51	#endif
52
53	#define INVALID_OPCODE \
54	DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
55
56
57	/* Invalid opcode */
58	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
59	{
60	OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
61	};
62
63
64	/* Include the secondary tables. */
65	#include "DisasmTables-armv8-a64-simd-fp.cpp.h"
66
67	/* UDF */
68	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
69	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /idxParam/),
70	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
71	DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
72	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Rsvd, 0xffff0000 /fFixedInsn/,
73	kDisArmV8OpcDecodeNop, 0xffff0000, 16);
74
75	/* ADR/ADRP */
76	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
77	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
78	DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
79	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
80	DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
81	DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
82	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Adr, 0x9f000000 /fFixedInsn/,
83	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
84
85
86	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
87	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
88	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
89	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
91	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /idxParam/),
92	DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /idxParam/),
93	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
94	DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
95	DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
96	DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
97	DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
98	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubImm, 0x7f800000 /fFixedInsn/,
99	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
100
101
102	/* ADD/ADDS/SUB/SUBS - shifted register variant */
103	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
104	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
105	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
109	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
110	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
111	DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
112	DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
113	DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
114	DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
115	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubShiftReg, 0x7f200000 /fFixedInsn/,
116	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
117
118
119	/* AND/ORR/EOR/ANDS */
120	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
121	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
122	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
123	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
124	DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
125	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
126	DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
127	DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
128	DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
129	DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
130	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogicalImm, 0x7f800000 /fFixedInsn/,
131	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
132
133
134	/* MOVN/MOVZ/MOVK */
135	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
136	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
137	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
138	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /idxParam/),
139	DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /idxParam/),
140	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
141	DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
142	INVALID_OPCODE,
143	DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
144	DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
145	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(MoveWide, 0x7f800000 /fFixedInsn/,
146	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
147
148
149	/* SBFM/BFM/UBFM */
150	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
151	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
152	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
156	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
157	DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
158	DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
159	DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
160	INVALID_OPCODE,
161	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Bitfield, 0x7f800000 /fFixedInsn/,
162	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
163
164
165	/* SBFM/BFM/UBFM */
166	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Extract) /** @todo N must match SF, and for sf == 0 -> imms<5> == 0. */
167	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
168	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
170	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
171	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
172	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Extract)
173	DIS_ARMV8_OP(0x13800000, "extr", OP_ARMV8_A64_EXTR, DISOPTYPE_HARMLESS),
174	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Extract, 0x7fa00000 /fFixedInsn/,
175	kDisArmV8OpcDecodeNop, 0, 0);
176
177
178	/*
179	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
180	* data processing (immediate) instruction classes:
181	*
182	* Bit 25 24 23
183	* +-------------------------------------------
184	* 0 0 x PC-rel. addressing.
185	* 0 1 0 Add/subtract (immediate)
186	* 0 1 1 Add/subtract (immediate, with tags)
187	* 1 0 0 Logical (immediate)
188	* 1 0 1 Move wide (immediate)
189	* 1 1 0 Bitfield
190	* 1 1 1 Extract
191	*/
192	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
193	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
194	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
195	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
196	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
197	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
198	DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
199	DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
200	DIS_ARMV8_DECODE_MAP_ENTRY(Extract)
201	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
202
203
204	/* B.cond/BC.cond */
205	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
206	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
207	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /idxParam/),
208	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
209	DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
210	DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
211	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondBr, 0xff000010 /fFixedInsn/,
212	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4);
213
214
215	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
216	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
217	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /idxParam/),
218	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
219	DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
220	DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
221	DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
222	DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
223	DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
224	DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
225	DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
226	DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
227	DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
228	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Excp, 0xffe0001f /fFixedInsn/,
229	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0);
230
231
232	/* WFET/WFIT */
233	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
234	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
235	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
236	DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
237	DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
238	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysReg, 0xffffffe0 /fFixedInsn/,
239	kDisArmV8OpcDecodeNop, 0xfe0, 5);
240
241
242	/* Various hint instructions */
243	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
244	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
245	DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
246	DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
247	DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
248	DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
249	DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
250	DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
251	DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
252	DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
253	DIS_ARMV8_OP(0xd503211f, "pacia1716", OP_ARMV8_A64_PACIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
254	INVALID_OPCODE,
255	DIS_ARMV8_OP(0xd503215f, "pacib1716", OP_ARMV8_A64_PACIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
256	INVALID_OPCODE,
257	DIS_ARMV8_OP(0xd503219f, "autia1716", OP_ARMV8_A64_AUTIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
258	INVALID_OPCODE,
259	DIS_ARMV8_OP(0xd50321df, "autib1716", OP_ARMV8_A64_AUTIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
260	INVALID_OPCODE,
261	DIS_ARMV8_OP(0xd503221f, "esb", OP_ARMV8_A64_ESB, DISOPTYPE_HARMLESS), /* FEAT_RAS */
262	DIS_ARMV8_OP(0xd503223f, "psb csync", OP_ARMV8_A64_PSB, DISOPTYPE_HARMLESS), /* FEAT_SPE */
263	DIS_ARMV8_OP(0xd503225f, "tsb csync", OP_ARMV8_A64_TSB, DISOPTYPE_HARMLESS), /* FEAT_TRF */
264	DIS_ARMV8_OP(0xd503227f, "gcsb dsync", OP_ARMV8_A64_GCSB, DISOPTYPE_HARMLESS), /* FEAT_GCS */
265	DIS_ARMV8_OP(0xd503229f, "csdb", OP_ARMV8_A64_CSDB, DISOPTYPE_HARMLESS),
266	INVALID_OPCODE,
267	DIS_ARMV8_OP(0xd50322df, "clrbhb", OP_ARMV8_A64_CLRBHB, DISOPTYPE_HARMLESS), /* FEAT_CLRBHB */
268	INVALID_OPCODE,
269	DIS_ARMV8_OP(0xd503231f, "paciaz", OP_ARMV8_A64_PACIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
270	DIS_ARMV8_OP(0xd503233f, "paciasp", OP_ARMV8_A64_PACIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
271	DIS_ARMV8_OP(0xd503235f, "pacibz", OP_ARMV8_A64_PACIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
272	DIS_ARMV8_OP(0xd503237f, "pacibsp", OP_ARMV8_A64_PACIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
273	DIS_ARMV8_OP(0xd503239f, "autiaz", OP_ARMV8_A64_AUTIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
274	DIS_ARMV8_OP(0xd50323bf, "autiasp", OP_ARMV8_A64_AUTIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
275	DIS_ARMV8_OP(0xd50323df, "autibz", OP_ARMV8_A64_AUTIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
276	DIS_ARMV8_OP(0xd50323ff, "autibsp", OP_ARMV8_A64_AUTIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
277	DIS_ARMV8_OP(0xd503241f, "bti", OP_ARMV8_A64_BTI, DISOPTYPE_HARMLESS), /* FEAT_BTI */
278	INVALID_OPCODE,
279	DIS_ARMV8_OP(0xd503245f, "bti c", OP_ARMV8_A64_BTI_C, DISOPTYPE_HARMLESS), /* FEAT_BTI */
280	INVALID_OPCODE,
281	DIS_ARMV8_OP(0xd503249f, "bti j", OP_ARMV8_A64_BTI_J, DISOPTYPE_HARMLESS), /* FEAT_BTI */
282	INVALID_OPCODE,
283	DIS_ARMV8_OP(0xd50324df, "bti jc", OP_ARMV8_A64_BTI_JC, DISOPTYPE_HARMLESS), /* FEAT_BTI */
284	INVALID_OPCODE,
285	DIS_ARMV8_OP(0xd503251f, "chkfeat x16", OP_ARMV8_A64_CHKFEAT, DISOPTYPE_HARMLESS), /* FEAT_CHK */
286	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Hints, 0xffffffff /fFixedInsn/,
287	kDisArmV8OpcDecodeNop, 0xfe0, 5);
288
289
290	/* CLREX */
291	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
292	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
293	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
294	INVALID_OPCODE,
295	INVALID_OPCODE,
296	DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
297	INVALID_OPCODE,
298	DIS_ARMV8_OP(0xD503309f, "dsb", OP_ARMV8_A64_DSB, DISOPTYPE_HARMLESS),
299	DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
300	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DecBarriers, 0xfffff0ff /fFixedInsn/,
301	kDisArmV8OpcDecodeNop, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
302
303
304	/* Barrier instructions, we divide these instructions further based on the op2 field. */
305	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
306	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
307	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
308	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
309	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
310	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DSB - Encoding */
311	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
312	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
313	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
314	DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
315
316
317	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
318	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
319	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value, gets validated by the next decoder stage. */
320	DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
321	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
322	DIS_ARMV8_OP(0xd500401f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
323	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(PState, 0xfff8f01f /fFixedInsn/,
324	kDisArmV8OpcDecodeNop, 0, 0);
325
326
327	/* TSTART/TTEST */
328	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
329	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
330	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
331	DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
332	DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
333	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysResult, 0xfffffffe /fFixedInsn/,
334	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8);
335
336
337	/* SYS */
338	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
339	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /idxParam/),
340	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
341	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /idxParam/),
342	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 3 /idxParam/),
343	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
344	DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
345	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Sys, 0xfff80000 /fFixedInsn/,
346	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
347
348
349	/* SYSL */
350	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
351	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
352	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /idxParam/),
353	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
354	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /idxParam/),
355	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
356	DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
357	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysL, 0xfff80000 /fFixedInsn/,
358	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
359
360
361	/* MSR */
362	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
363	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
364	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 1 /idxParam/),
365	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
366	DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
367	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Msr, 0xfff00000 /fFixedInsn/,
368	kDisArmV8OpcDecodeNop, 0, 0);
369
370
371	/* MRS */
372	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
373	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
374	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
375	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
376	DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
377	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Mrs, 0xfff00000 /fFixedInsn/,
378	kDisArmV8OpcDecodeNop, 0, 0);
379
380
381	/* BR/BRAAZ/BRABZ */
382	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Br)
383	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
384	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Br)
385	DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
386	INVALID_OPCODE,
387	DIS_ARMV8_OP(0xd61f081f, "braaz", OP_ARMV8_A64_BRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
388	DIS_ARMV8_OP(0xd61f0c1f, "brabz", OP_ARMV8_A64_BRABZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
389	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Br, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
390	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
391
392
393	/* BLR/BLRAAZ/BLRABZ */
394	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Blr)
395	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
396	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Blr)
397	DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
398	INVALID_OPCODE,
399	DIS_ARMV8_OP(0xd63f081f, "blraaz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
400	DIS_ARMV8_OP(0xd63f0c1f, "blrabz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
401	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Blr, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
402	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
403
404
405	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Ret)
406	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
407	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(RetPAuth)
408	DIS_ARMV8_INSN_DECODE(kDisParmParseRegFixed31, 5, 5, 0 /idxParam/),
409	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Ret)
410	DIS_ARMV8_OP( 0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
411	INVALID_OPCODE,
412	DIS_ARMV8_OP_ALT_DECODE(0xd65f081f, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
413	DIS_ARMV8_OP_ALT_DECODE(0xd65f0c1f, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
414	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Ret, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
415	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
416
417
418	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Eret)
419	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Eret)
420	DIS_ARMV8_OP(0xd69f03e0, "eret", OP_ARMV8_A64_ERET, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
421	INVALID_OPCODE,
422	DIS_ARMV8_OP(0xd69f0bff, "eretaa", OP_ARMV8_A64_ERETAA, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
423	DIS_ARMV8_OP(0xd69f0fff, "eretab", OP_ARMV8_A64_ERETAB, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
424	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Eret, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
425	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
426
427
428	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Drps)
429	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Drps)
430	DIS_ARMV8_OP(0xd6bf03e0, "drps", OP_ARMV8_A64_DRPS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
431	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Drps, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
432	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
433
434
435	/* BRAA/BRAB */
436	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BraaBrab)
437	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
438	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
439	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BraaBrab)
440	INVALID_OPCODE,
441	INVALID_OPCODE,
442	DIS_ARMV8_OP(0xd71f0800, "braa", OP_ARMV8_A64_BRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
443	DIS_ARMV8_OP(0xd71f0c00, "brab", OP_ARMV8_A64_BRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
444	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BraaBrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
445	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
446
447
448	/* BRAA/BRAB */
449	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BlraaBlrab) /** @todo Could use the same decoder as for braa/brab and save a bit of table size. */
450	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
451	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
452	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BlraaBlrab)
453	INVALID_OPCODE,
454	INVALID_OPCODE,
455	DIS_ARMV8_OP(0xd73f0800, "blraa", OP_ARMV8_A64_BLRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
456	DIS_ARMV8_OP(0xd73f0c00, "blrab", OP_ARMV8_A64_BLRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
457	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BlraaBlrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
458	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
459
460
461	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
462	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
463	DIS_ARMV8_DECODE_MAP_ENTRY(Br), /* BR/BRAAZ/BRABZ */
464	DIS_ARMV8_DECODE_MAP_ENTRY(Blr), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
465	DIS_ARMV8_DECODE_MAP_ENTRY(Ret), /* RET/RETAA/RETAB */
466	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
467	DIS_ARMV8_DECODE_MAP_ENTRY(Eret), /* ERET/ERETAA/ERETAB */
468	DIS_ARMV8_DECODE_MAP_ENTRY(Drps), /* DRPS */
469	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
470	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
471	DIS_ARMV8_DECODE_MAP_ENTRY(BraaBrab), /* BRAA/BRAB */
472	DIS_ARMV8_DECODE_MAP_ENTRY(BlraaBlrab), /* BRAA/BRAB */
473	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
474	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
475	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
476	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
477	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
478	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
479	DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
480
481
482	/* B/BL */
483	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
484	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
485	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
486	DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
487	DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
488	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(UncondBrImm, 0xfc000000 /fFixedInsn/,
489	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
490
491
492	/* CBZ/CBNZ */
493	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
494	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
495	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
496	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
497	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
498	DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
499	DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
500	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CmpBrImm, 0x7f000000 /fFixedInsn/,
501	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
502
503
504	/* TBZ/TBNZ */
505	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
506	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not an SF bit but has the same meaning. */
507	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
508	DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /idxParam/), /* Hardcoded bit offsets in parser. */
509	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
510	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
511	DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
512	DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
513	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(TestBrImm, 0x7f000000 /fFixedInsn/,
514	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
515
516
517	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
518	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
519	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
520	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
521	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
522	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
523	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
524	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
525	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
526	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
527	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
528	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
529	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
530	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
531	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
532	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
533	DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
534
535
536	/* AND/ORR/EOR/ANDS */
537	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
538	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
539	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
540	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
541	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
542	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
543	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
544	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
545	DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
546	DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
547	DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
548	DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
549	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN0, 0x7f200000 /fFixedInsn/,
550	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
551
552
553	/* AND/ORR/EOR/ANDS */
554	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
555	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
556	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
557	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
558	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
559	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
560	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
561	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
562	DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
563	DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
564	DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
565	DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
566	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN1, 0x7f200000 /fFixedInsn/,
567	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
568
569
570	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
571	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
572	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
573	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
574
575
576	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
577	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
578	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24);
579
580
581	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
582	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
583	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
584	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
585
586
587	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
588	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
589	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
590	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
591
592
593	/* CCMN/CCMP */
594	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
595	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
596	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
597	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 1 /idxParam/),
598	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
599	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
600	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
601	DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
602	DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
603	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondCmpReg, 0x7fe00c10 /fFixedInsn/,
604	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
605
606
607	/**
608	* C4.1.95 - Data Processing - Register
609	*
610	* The conditional compare instructions differentiate between register and immediate
611	* variant based on the 11th bit (part of op3).
612	*/
613	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
614	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
615	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional compare immediate */
616	DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
617
618
619	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
620	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src32Bit)
621	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
622	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
623	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
624	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
625	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src32Bit)
626	INVALID_OPCODE,
627	INVALID_OPCODE,
628	DIS_ARMV8_OP(0x1ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
629	DIS_ARMV8_OP(0x1ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
630	INVALID_OPCODE,
631	INVALID_OPCODE,
632	INVALID_OPCODE,
633	INVALID_OPCODE,
634	DIS_ARMV8_OP(0x1ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
635	DIS_ARMV8_OP(0x1ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
636	DIS_ARMV8_OP(0x1ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
637	DIS_ARMV8_OP(0x1ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
638	INVALID_OPCODE,
639	INVALID_OPCODE,
640	INVALID_OPCODE,
641	INVALID_OPCODE,
642	DIS_ARMV8_OP(0x1ac04000, "crc32b", OP_ARMV8_A64_CRC32B, DISOPTYPE_HARMLESS),
643	DIS_ARMV8_OP(0x1ac04400, "crc32h", OP_ARMV8_A64_CRC32H, DISOPTYPE_HARMLESS),
644	DIS_ARMV8_OP(0x1ac04800, "crc32w", OP_ARMV8_A64_CRC32W, DISOPTYPE_HARMLESS),
645	INVALID_OPCODE,
646	DIS_ARMV8_OP(0x1ac05000, "crc32cb", OP_ARMV8_A64_CRC32CB, DISOPTYPE_HARMLESS),
647	DIS_ARMV8_OP(0x1ac05400, "crc32ch", OP_ARMV8_A64_CRC32CH, DISOPTYPE_HARMLESS),
648	DIS_ARMV8_OP(0x1ac05800, "crc32cw", OP_ARMV8_A64_CRC32CW, DISOPTYPE_HARMLESS),
649	INVALID_OPCODE,
650	DIS_ARMV8_OP(0x1ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
651	DIS_ARMV8_OP(0x1ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
652	DIS_ARMV8_OP(0x1ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
653	DIS_ARMV8_OP(0x1ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS),
654	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src32Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
655	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
656
657
658	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
659	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src64Bit)
660	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
661	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
662	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
663	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcCrc32X)
664	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
665	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
666	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
667	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcSubp)
668	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
669	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
670	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
671	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcIrg)
672	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
673	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
674	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
675	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcGmi)
676	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
677	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
678	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
679	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src64Bit)
680	DIS_ARMV8_OP_ALT_DECODE(0x9ac00000, "subp", OP_ARMV8_A64_SUBP, DISOPTYPE_HARMLESS, Reg2SrcSubp),
681	INVALID_OPCODE,
682	DIS_ARMV8_OP( 0x9ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
683	DIS_ARMV8_OP( 0x9ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
684	DIS_ARMV8_OP_ALT_DECODE(0x9ac01000, "irg", OP_ARMV8_A64_IRG, DISOPTYPE_HARMLESS, Reg2SrcIrg),
685	DIS_ARMV8_OP_ALT_DECODE(0x9ac01400, "gmi", OP_ARMV8_A64_GMI, DISOPTYPE_HARMLESS, Reg2SrcGmi),
686	INVALID_OPCODE,
687	INVALID_OPCODE,
688	DIS_ARMV8_OP( 0x9ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
689	DIS_ARMV8_OP( 0x9ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
690	DIS_ARMV8_OP( 0x9ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
691	DIS_ARMV8_OP( 0x9ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
692	INVALID_OPCODE, /** @todo PACGA (FEAT_PAuth). */
693	INVALID_OPCODE,
694	INVALID_OPCODE,
695	INVALID_OPCODE,
696	INVALID_OPCODE,
697	INVALID_OPCODE,
698	INVALID_OPCODE,
699	DIS_ARMV8_OP_ALT_DECODE(0x9ac04c00, "crc32x", OP_ARMV8_A64_CRC32X, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
700	INVALID_OPCODE,
701	INVALID_OPCODE,
702	INVALID_OPCODE,
703	DIS_ARMV8_OP_ALT_DECODE(0x9ac05c00, "crc32cx", OP_ARMV8_A64_CRC32CX, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
704	DIS_ARMV8_OP( 0x9ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
705	DIS_ARMV8_OP( 0x9ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
706	DIS_ARMV8_OP( 0x9ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
707	DIS_ARMV8_OP( 0x9ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS)
708	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src64Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
709	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
710
711
712	/* SUBPS */
713	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Subps)
714	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
715	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
716	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
717	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Subps)
718	DIS_ARMV8_OP(0xbac00000, "subps", OP_ARMV8_A64_SUBPS, DISOPTYPE_HARMLESS),
719	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Subps, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
720	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
721
722
723	/**
724	* C4.1.95 - Data Processing - Register - 2-source
725	*
726	* Differentiate between 32-bit and 64-bit groups based on the SF bit.
727	* Not done as a general decoder step because there are different instructions in each group.
728	*/
729	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src)
730	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src32Bit), /* Data-processing (2-source, 32-bit) */
731	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src64Bit), /* Data-processing (2-source, 64-bit) */
732	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src, 31);
733
734
735	/**
736	* C4.1.95 - Data Processing - Register - 2-source
737	*
738	* Differentiate between SUBPS and the rest based on the S bit.
739	*/
740	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2SrcSubps)
741	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src), /* Data-processing (2-source) */
742	DIS_ARMV8_DECODE_MAP_ENTRY(Subps), /* Subps */
743	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2SrcSubps, 29);
744
745
746	/* RBIT/REV16/REV/CLZ/CLS/CTZ/CNT/ABS/REV32 */
747	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg1SrcInsn)
748	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
749	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
750	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
751	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg1SrcInsn)
752	DIS_ARMV8_OP(0x5ac00000, "rbit", OP_ARMV8_A64_RBIT, DISOPTYPE_HARMLESS),
753	DIS_ARMV8_OP(0x5ac00400, "rev16", OP_ARMV8_A64_REV16, DISOPTYPE_HARMLESS),
754	DIS_ARMV8_OP(0x5ac00800, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo REV32 if SF1 is 1 (why must this be so difficult ARM?). */
755	DIS_ARMV8_OP(0x5ac00c00, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo SF must be 1, otherwise unallocated. */
756	DIS_ARMV8_OP(0x5ac01000, "clz", OP_ARMV8_A64_CLZ, DISOPTYPE_HARMLESS),
757	DIS_ARMV8_OP(0x5ac01400, "cls", OP_ARMV8_A64_CLS, DISOPTYPE_HARMLESS),
758	DIS_ARMV8_OP(0x5ac01800, "ctz", OP_ARMV8_A64_CTZ, DISOPTYPE_HARMLESS),
759	DIS_ARMV8_OP(0x5ac01c00, "cnt", OP_ARMV8_A64_CNT, DISOPTYPE_HARMLESS),
760	DIS_ARMV8_OP(0x5ac02000, "abs", OP_ARMV8_A64_ABS, DISOPTYPE_HARMLESS),
761	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg1SrcInsn, 0x7ffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
762	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
763
764
765	/**
766	* C4.1.95 - Data Processing - Register - 1-source
767	*
768	* Differentiate between standard and FEAT_PAuth instructions based on opcode2 field.
769	*/
770	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg1Src)
771	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1SrcInsn), /* Data-processing (1-source) */
772	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data-processing (1-source, FEAT_PAuth) */
773	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg1Src, 16);
774
775
776	/**
777	* C4.1.95 - Data Processing - Register - 2-source / 1-source
778	*
779	* The 2-source and 1-source instruction classes differentiate based on bit 30.
780	*/
781	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src1Src)
782	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2SrcSubps), /* Data-processing (2-source) */
783	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1Src), /* Data-processing (1-source) */
784	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src1Src, 30);
785
786
787	/*
788	* C4.1.95 - Data Processing - Register
789	*
790	* The op1 field is already decoded in the previous step and is 1 when being here,
791	* leaving us with the following possible values:
792	*
793	* Bit 24 23 22 21
794	* +-------------------------------------------
795	* 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
796	* 0 0 0 1 UNALLOC
797	* 0 0 1 0 Conditional compare (register / immediate)
798	* 0 0 1 1 UNALLOC
799	* 0 1 0 0 Conditional select
800	* 0 1 0 1 UNALLOC
801	* 0 1 1 0 Data processing (2-source or 1-source depending on op0).
802	* 0 1 1 1 UNALLOC
803	* 1 x x x Data processing 3-source
804	*/
805	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
806	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract with carry. */
807	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
808	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp),
809	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
810	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional select. */
811	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
812	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src1Src),
813	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
814	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
815	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
816	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
817	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
818	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
819	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
820	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
821	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Data Processing 3-source. */
822	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
823
824
825	/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
826	*
827	* Note: The size,opc bitfields are concatenated to form an index.
828	*/
829	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
830	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
831	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
832	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
833	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
834	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
835	DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
836	DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
837	DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
838	DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
839	DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
840	DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
841	DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
842	DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
843	DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
844	DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
845	DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
846	INVALID_OPCODE,
847	DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
848	DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
849	INVALID_OPCODE, /** @todo PRFM */
850	INVALID_OPCODE,
851	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /fFixedInsn/,
852	kDisArmV8OpcDecodeCollate,
853	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
854
855
856	/*
857	* C4.1.94 - Loads and Stores - Load/Store register variants
858	*
859	* Differentiate further based on the VR field.
860	*
861	* Bit 26
862	* +-------------------------------------------
863	* 0 GPR variants.
864	* 1 SIMD/FP variants
865	*/
866	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
867	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
868	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
869	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
870
871
872	/*
873	* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
874	*
875	* Note: The size,opc bitfields are concatenated to form an index.
876	*/
877	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
878	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
879	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
880	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
881	DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /idxParam/),
882	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /idxParam/),
883	DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /idxParam/),
884	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
885	DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
886	DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
887	DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
888	DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
889	DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
890	DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
891	DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
892	DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
893	DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
894	DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
895	DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
896	INVALID_OPCODE,
897	DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
898	DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
899	INVALID_OPCODE, /** @todo PRFM */
900	INVALID_OPCODE,
901	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /fFixedInsn/,
902	kDisArmV8OpcDecodeCollate,
903	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
904
905
906	/*
907	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
908	*
909	* Differentiate further based on the VR field.
910	*
911	* Bit 26
912	* +-------------------------------------------
913	* 0 GPR variants.
914	* 1 SIMD/FP variants
915	*/
916	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
917	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
918	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
919	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
920
921
922	/*
923	* C4.1.94 - Loads and Stores - Load/Store register variants
924	*
925	* Differentiate further based on the op2<1:0> field.
926	*
927	* Bit 11 10
928	* +-------------------------------------------
929	* 0 0 Atomic memory operations
930	* 0 1 Load/store register (pac)
931	* 1 0 Load/store register (register offset)
932	* 1 1 Load/store register (pac)
933	*/
934	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
935	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
936	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
937	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
938	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
939	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
940
941
942	/*
943	* STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
944	*
945	* Note: The size,opc bitfields are concatenated to form an index.
946	*/
947	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
948	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
949	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
950	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
951	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
952	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
953	DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
954	DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
955	DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
956	DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
957	DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
958	DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
959	DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
960	DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
961	DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
962	DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
963	DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
964	INVALID_OPCODE,
965	DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
966	DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
967	INVALID_OPCODE, /** @todo PRFUM */
968	INVALID_OPCODE,
969	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /fFixedInsn/,
970	kDisArmV8OpcDecodeCollate,
971	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
972
973
974	/*
975	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
976	*
977	* Differentiate further based on the VR field.
978	*
979	* Bit 26
980	* +-------------------------------------------
981	* 0 GPR variants.
982	* 1 SIMD/FP variants
983	*/
984	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
985	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
986	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
987	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
988
989
990	/*
991	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
992	*
993	* Note: The size,opc bitfields are concatenated to form an index.
994	*/
995	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
996	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
997	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
998	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
999	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
1000	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /idxParam/),
1001	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
1002	DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
1003	DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
1004	DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1005	DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1006	DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
1007	DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
1008	DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1009	DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1010	DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
1011	DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
1012	DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1013	INVALID_OPCODE,
1014	DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
1015	DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
1016	INVALID_OPCODE,
1017	INVALID_OPCODE,
1018	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /fFixedInsn/,
1019	kDisArmV8OpcDecodeCollate,
1020	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1021
1022
1023	/*
1024	* C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
1025	*
1026	* Differentiate further based on the VR field.
1027	*
1028	* Bit 26
1029	* +-------------------------------------------
1030	* 0 GPR variants.
1031	* 1 SIMD/FP variants
1032	*/
1033	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
1034	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
1035	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1036	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
1037
1038
1039	/*
1040	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
1041	*
1042	* Note: The size,opc bitfields are concatenated to form an index.
1043	*/
1044	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
1045	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
1046	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1047	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
1048	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
1049	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /idxParam/),
1050	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
1051	DIS_ARMV8_OP(0x38000400, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
1052	DIS_ARMV8_OP(0x38400400, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
1053	DIS_ARMV8_OP_EX(0x38800400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1054	DIS_ARMV8_OP_EX(0x38c00400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1055	DIS_ARMV8_OP(0x78000400, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
1056	DIS_ARMV8_OP(0x78400400, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
1057	DIS_ARMV8_OP_EX(0x78800400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1058	DIS_ARMV8_OP_EX(0x78c00400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1059	DIS_ARMV8_OP(0xb8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
1060	DIS_ARMV8_OP(0xb8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
1061	DIS_ARMV8_OP_EX(0xb8800400, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1062	INVALID_OPCODE,
1063	DIS_ARMV8_OP(0xf8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
1064	DIS_ARMV8_OP(0xf8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
1065	INVALID_OPCODE,
1066	INVALID_OPCODE,
1067	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /fFixedInsn/,
1068	kDisArmV8OpcDecodeCollate,
1069	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1070
1071
1072	/*
1073	* C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
1074	*
1075	* Differentiate further based on the VR field.
1076	*
1077	* Bit 26
1078	* +-------------------------------------------
1079	* 0 GPR variants.
1080	* 1 SIMD/FP variants
1081	*/
1082	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
1083	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
1084	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1085	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
1086
1087
1088	/*
1089	* STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
1090	*
1091	* Note: The size,opc bitfields are concatenated to form an index.
1092	*/
1093	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
1094	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
1095	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1096	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
1097	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
1098	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
1099	DIS_ARMV8_OP(0x38000800, "sttrb", OP_ARMV8_A64_STTRB, DISOPTYPE_HARMLESS),
1100	DIS_ARMV8_OP(0x38400800, "ldtrb", OP_ARMV8_A64_LDTRB, DISOPTYPE_HARMLESS),
1101	DIS_ARMV8_OP_EX(0x38800800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1102	DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1103	DIS_ARMV8_OP(0x78000800, "sttrh", OP_ARMV8_A64_STTRH, DISOPTYPE_HARMLESS),
1104	DIS_ARMV8_OP(0x78400800, "ldtrh", OP_ARMV8_A64_LDTRH, DISOPTYPE_HARMLESS),
1105	DIS_ARMV8_OP_EX(0x78800800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1106	DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1107	DIS_ARMV8_OP(0xb8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
1108	DIS_ARMV8_OP(0xb8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
1109	DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw", OP_ARMV8_A64_LDTRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1110	INVALID_OPCODE,
1111	DIS_ARMV8_OP(0xf8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
1112	DIS_ARMV8_OP(0xf8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
1113	INVALID_OPCODE,
1114	INVALID_OPCODE,
1115	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /fFixedInsn/,
1116	kDisArmV8OpcDecodeCollate,
1117	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1118
1119
1120	/*
1121	* C4.1.94 - Loads and Stores - Load/Store register variants
1122	*
1123	* Differentiate further based on the op2<1:0> field.
1124	*
1125	* Bit 11 10
1126	* +-------------------------------------------
1127	* 0 0 Load/store register (unscaled immediate)
1128	* 0 1 Load/store register (immediate post-indexed)
1129	* 1 0 Load/store register (unprivileged)
1130	* 1 1 Load/store register (immediate pre-indexed)
1131	*/
1132	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
1133	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
1134	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
1135	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv), /* No vector variants. */
1136	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
1137	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) \| RT_BIT_32(11), 10);
1138
1139
1140	/*
1141	* C4.1.94 - Loads and Stores - Load/Store register variants
1142	*
1143	* Differentiate further based on the op2<11> field.
1144	*
1145	* Bit 21
1146	* +-------------------------------------------
1147	* 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
1148	* 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
1149	*/
1150	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
1151	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
1152	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
1153	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
1154
1155
1156	/*
1157	* C4.1.94 - Loads and Stores - Load/Store register variants
1158	*
1159	* Differentiate further based on the op2<14> field.
1160	*
1161	* Bit 24
1162	* +-------------------------------------------
1163	* 0 All the other Load/store register variants and Atomic memory operations.
1164	* 1 Load/store register (unsigned immediate).
1165	*/
1166	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
1167	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
1168	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
1169	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
1170
1171
1172	/*
1173	* STP/LDP/STGP/LDPSW
1174	*
1175	* Note: The opc,L bitfields are concatenated to form an index.
1176	*/
1177	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
1178	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1179	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1180	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1181	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1182	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
1183	DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1184	DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1185	INVALID_OPCODE,
1186	INVALID_OPCODE,
1187	DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1188	DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1189	INVALID_OPCODE,
1190	INVALID_OPCODE,
1191	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /fFixedInsn/,
1192	kDisArmV8OpcDecodeCollate,
1193	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1194
1195
1196	/*
1197	* STP/LDP/STGP/LDPSW - pre-indexed variant.
1198	*
1199	* Note: The opc,L bitfields are concatenated to form an index.
1200	*/
1201	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
1202	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1203	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1204	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1205	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1206	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /idxParam/),
1207	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
1208	DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1209	DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1210	INVALID_OPCODE,
1211	INVALID_OPCODE,
1212	DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1213	DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1214	INVALID_OPCODE,
1215	INVALID_OPCODE,
1216	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /fFixedInsn/,
1217	kDisArmV8OpcDecodeCollate,
1218	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1219
1220
1221	/*
1222	* STP/LDP/STGP/LDPSW - post-indexed variant.
1223	*
1224	* Note: The opc,L bitfields are concatenated to form an index.
1225	*/
1226	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
1227	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
1228	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
1229	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
1230	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
1231	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /idxParam/),
1232	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
1233	DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1234	DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
1235	INVALID_OPCODE,
1236	INVALID_OPCODE,
1237	DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1238	DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
1239	INVALID_OPCODE,
1240	INVALID_OPCODE,
1241	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /fFixedInsn/,
1242	kDisArmV8OpcDecodeCollate,
1243	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
1244
1245
1246	/*
1247	* C4.1.94 - Loads and Stores - Load/Store register pair variants
1248	*
1249	* Differentiate further based on the op2<14:13> field.
1250	*
1251	* Bit 24 23
1252	* +-------------------------------------------
1253	* 0 0 Load/store no-allocate pair (offset)
1254	* 0 1 Load/store register pair (post-indexed)
1255	* 1 0 Load/store register pair (offset).
1256	* 1 1 Load/store register pair (pre-indexed).
1257	*/
1258	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
1259	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1260	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
1261	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
1262	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
1263	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) \| RT_BIT_32(24), 23);
1264
1265
1266	/*
1267	* C4.1.94 - Loads and Stores
1268	*
1269	* Differentiate further based on the op0<1:0> field.
1270	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
1271	*
1272	* Bit 29 28
1273	* +-------------------------------------------
1274	* 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
1275	* Load/store ordered / Compare and swap
1276	* 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
1277	* LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
1278	* 1 0 Load/store no-allocate pair / Load/store register pair /
1279	* 1 1 Load/store register / Atomic memory operations
1280	*/
1281	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
1282	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1283	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
1284	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
1285	DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
1286	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) \| RT_BIT_32(29), 28);
1287
1288
1289	/*
1290	* C4.1 of the ARMv8 architecture reference manual has the following table for the
1291	* topmost decoding level (Level 0 in our terms), x means don't care:
1292	*
1293	* Bit 28 27 26 25
1294	* +-------------------------------------------
1295	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1296	* 0 0 0 1 UNALLOC
1297	* 0 0 1 0 SVE encodings
1298	* 0 0 1 1 UNALLOC
1299	* 1 0 0 x Data processing immediate
1300	* 1 0 1 x Branch, exception generation and system instructions
1301	* x 1 x 0 Loads and stores
1302	* x 1 0 1 Data processing - register
1303	* x 1 1 1 Data processing - SIMD and floating point
1304	*
1305	* In order to save us some fiddling with the don't care bits we blow up the lookup table
1306	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
1307	* lookup table for the next level:
1308	* Bit 28 27 26 25
1309	* +-------------------------------------------
1310	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1311	* 1 0 0 0 1 UNALLOC
1312	* 2 0 0 1 0 SVE encodings
1313	* 3 0 0 1 1 UNALLOC
1314	* 4 0 1 0 0 Loads and stores
1315	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1316	* 6 0 1 1 0 Loads and stores
1317	* 7 0 1 1 1 Data processing - SIMD and floating point
1318	* 8 1 0 0 0 Data processing immediate
1319	* 9 1 0 0 1 Data processing immediate
1320	* 10 1 0 1 0 Branch, exception generation and system instructions
1321	* 11 1 0 1 1 Branch, exception generation and system instructions
1322	* 12 1 1 0 0 Loads and stores
1323	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1324	* 14 1 1 1 0 Loads and stores
1325	* 15 1 1 1 1 Data processing - SIMD and floating point
1326	*/
1327	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
1328	DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
1329	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1330	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
1331	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1332	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1333	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
1334	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1335	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0), /* Data processing (SIMD & FP) (op0<0> 0) */
1336	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1337	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1338	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1339	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1340	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1341	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
1342	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1343	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1) /* Data processing (SIMD & FP) (op0<0> 1). */
1344	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 106686

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