tstAsmLock-2.asm@ 86186

Last change on this file since 86186 was 82968, checked in by vboxsync, 5 years ago
Copyright year updates by scm.
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1	; $Id: tstAsmLock-2.asm 82968 2020-02-04 10:35:17Z vboxsync $
2	;; @file
3	; Disassembly testcase - Invalid invariants.
4	;
5	; The intention is to check in a binary using the --all-invalid mode
6	; of tstDisasm-2.
7	;
8	; There are some regX, reg/memX variations that aren't tested as
9	; they would require db'ing out the instructions (12 /r and 13 /r
10	; for instance).
11	;
12
13	;
14	; Copyright (C) 2008-2020 Oracle Corporation
15	;
16	; This file is part of VirtualBox Open Source Edition (OSE), as
17	; available from http://www.virtualbox.org. This file is free software;
18	; you can redistribute it and/or modify it under the terms of the GNU
19	; General Public License (GPL) as published by the Free Software
20	; Foundation, in version 2 as it comes in the "COPYING" file of the
21	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	;
24
25	%include "tstAsm.mac"
26	%if TEST_BITS == 64
27	; The disassembler doesn't do imm32 right for 64-bit stuff, so disable it for now.
28	; %define WITH_64_BIT_TESTS_IMM32
29	%define WITH_64_BIT_TESTS
30	%endif
31
32	BITS TEST_BITS
33
34	;
35	; ADC
36	;
37	; 14 ib ADC AL, imm8
38	lock adc al, byte 8
39	; 15 i[wd] ADC [ER]AX, immX
40	lock adc ax, word 16
41	lock adc eax, dword 128
42	%ifdef WITH_64_BIT_TESTS_IMM32
43	lock adc rax, dword 256
44	lock adc rax, dword 0cc90cc90h
45	%endif
46	; 80 /2 ib ADC reg/mem8, imm8 - with reg dst
47	lock adc cl, byte 8
48	; 81 /2 i[wd] ADC reg/memX, immX - with reg dst
49	lock adc cx, word 1000h
50	lock adc ecx, dword 100000h
51	%ifdef WITH_64_BIT_TESTS_IMM32
52	lock adc rcx, dword 100000h
53	%endif
54	; 83 /2 ib ADC reg/memX, imm8 - with reg dst
55	lock adc cx, byte 07fh
56	lock adc ecx, byte 07fh
57	%ifdef WITH_64_BIT_TESTS_IMM32
58	lock adc rcx, byte 07fh
59	%endif
60
61	; 10 /r ADC reg/mem8, reg8 - with reg dst
62	lock adc cl, bl
63	; 11 /r ADC reg/memX, regX - with reg dst
64	lock adc cx, bx
65	lock adc ecx, ebx
66	%ifdef WITH_64_BIT_TESTS
67	lock adc rcx, rbx
68	%endif
69	; 12 /r ADC reg8, reg/mem8
70	lock adc cl, [0badh]
71	; 13 /r ADC regX, reg/memX
72	lock adc cx, [0badh]
73	lock adc ecx, [0badh]
74	%ifdef WITH_64_BIT_TESTS
75	lock adc rcx, [0badh]
76	%endif
77
78	;
79	; ADD
80	;
81	; 04 ib ADD AL, imm8
82	lock add al, byte 8
83	; 05 i[wd] ADD [ER]AX, immX
84	lock add ax, word 16
85	lock add eax, dword 128
86	%ifdef WITH_64_BIT_TESTS_IMM32
87	lock add rax, dword 256
88	lock add rax, dword 0cc90cc90h
89	%endif
90	; 80 /0 ib ADD reg/mem8, imm8 - with reg dst
91	lock add cl, byte 8
92	; 81 /0 i[wd] ADD reg/memX, immX - with reg dst
93	lock add cx, word 1000h
94	lock add ecx, dword 100000h
95	%ifdef WITH_64_BIT_TESTS_IMM32
96	lock add rcx, dword 100000h
97	%endif
98	; 83 /0 ib ADD reg/memX, imm8 - with reg dst
99	lock add cx, byte 07fh
100	lock add ecx, byte 07fh
101	%ifdef WITH_64_BIT_TESTS
102	lock add rcx, byte 07fh
103	%endif
104
105	; 00 /r ADD reg/mem8, reg8 - with reg dst
106	lock add cl, bl
107	; 01 /r ADD reg/memX, regX - with reg dst
108	lock add cx, bx
109	lock add ecx, ebx
110	%ifdef WITH_64_BIT_TESTS
111	lock add rcx, rbx
112	%endif
113	; 02 /r ADD reg8, reg/mem8
114	lock add cl, [0badh]
115	; 03 /r ADD regX, reg/memX
116	lock add cx, [0badh]
117	lock add ecx, [0badh]
118	%ifdef WITH_64_BIT_TESTS
119	lock add rcx, [0badh]
120	%endif
121
122	;
123	; AND
124	;
125	; 24 ib AND AL, imm8
126	lock and al, byte 8
127	; 25 i[wd] AND [ER]AX, immX
128	lock and ax, word 16
129	lock and eax, dword 128
130	%ifdef WITH_64_BIT_TESTS_IMM32
131	lock and rax, dword 256
132	lock and rax, dword 0cc90cc90h
133	%endif
134	; 80 /4 ib AND reg/mem8, imm8 - with reg dst
135	lock and cl, byte 8
136	; 81 /4 i[wd] AND reg/memX, immX - with reg dst
137	lock and cx, word 1000h
138	lock and ecx, dword 100000h
139	%ifdef WITH_64_BIT_TESTS_IMM32
140	lock and rcx, dword 100000h
141	%endif
142	; 83 /4 ib AND reg/memX, imm8 - with reg dst
143	lock and cx, byte 07fh
144	lock and ecx, byte 07fh
145	%ifdef WITH_64_BIT_TESTS
146	lock and rcx, byte 07fh
147	%endif
148
149	; 20 /r AND reg/mem8, reg8 - with reg dst
150	lock and cl, bl
151	; 21 /r AND reg/memX, regX - with reg dst
152	lock and cx, bx
153	lock and ecx, ebx
154	%ifdef WITH_64_BIT_TESTS
155	lock and rcx, rbx
156	%endif
157	; 22 /r AND reg8, reg/mem8
158	lock and cl, [0badh]
159	; 23 /r AND regX, reg/memX
160	lock and cx, [0badh]
161	lock and ecx, [0badh]
162	%ifdef WITH_64_BIT_TESTS
163	lock and rcx, [0badh]
164	%endif
165
166	;
167	; BTC
168	;
169	; 0f bb /r BTC reg/memX, regX (X != 8) - with reg dst
170	lock btc cx, bx
171	lock btc ecx, ebx
172	%ifdef WITH_64_BIT_TESTS
173	lock btc rcx, rbx
174	lock btc r8, rbx
175	lock btc r10, r8
176	%endif
177	; 0f ba /7 ib BTC reg/memX, imm8 (X != 8) - with reg dst
178	lock btc cx, 15
179	lock btc ecx, 30
180	%ifdef WITH_64_BIT_TESTS
181	lock btc rcx, 60
182	lock btc r8, 61
183	lock btc r10, 3
184	%endif
185
186	;
187	; BTR
188	;
189	; 0f b3 /r BTR reg/memX, regX (X != 8) - with reg dst
190	lock btr cx, bx
191	lock btr ecx, ebx
192	%ifdef WITH_64_BIT_TESTS
193	lock btr rcx, rbx
194	lock btr r8, rbx
195	lock btr r10, r8
196	%endif
197	; 0f ba /6 ib BTR reg/memX, imm8 (X != 8) - with reg dst
198	lock btr cx, 15
199	lock btr ecx, 30
200	%ifdef WITH_64_BIT_TESTS
201	lock btr rcx, 60
202	lock btr r8, 61
203	lock btr r10, 3
204	%endif
205
206	;
207	; BTS
208	;
209	; 0f ab /r BTS reg/memX, regX (X != 8) - with reg dst
210	lock bts cx, bx
211	lock bts ecx, ebx
212	%ifdef WITH_64_BIT_TESTS
213	lock bts rcx, rbx
214	lock bts r8, rbx
215	lock bts r10, r8
216	%endif
217	; 0f ba /5 ib BTS reg/memX, imm8 (X != 8) - with reg dst
218	lock bts cx, 15
219	lock bts ecx, 30
220	%ifdef WITH_64_BIT_TESTS
221	lock bts rcx, 60
222	lock bts r8, 61
223	lock bts r10, 3
224	%endif
225
226	;
227	; CMPXCHG
228	;
229	; 0f b0 /r CMPXCHG reg8/mem8, regX - with reg dst
230	lock cmpxchg bl, cl
231	; 0f b1 /r CMPXCHG regX/memX, regX - with reg dst
232	lock cmpxchg bx, cx
233	lock cmpxchg ebx, ecx
234	%ifdef WITH_64_BIT_TESTS
235	lock cmpxchg rbx, rcx
236	%endif
237
238	;
239	; CMPXCHG8B
240	; CMPXCHG16B
241	;
242	; all valid.
243
244	;
245	; DEC
246	;
247	; fe /1 DEC reg8/mem8 - with reg dst
248	lock dec bl
249	; ff /1 DEC regX/memX - with reg dst
250
251	%if TEST_BITS != 64 ; cannot force these two in 32 and 16 bit mode.
252	db 066h, 0f0h, 0ffh, 0cbh
253	db 0f0h, 0ffh, 0cbh
254	%else
255	lock dec bx
256	lock dec ebx
257	%ifdef WITH_64_BIT_TESTS
258	lock dec rbx
259	lock dec r8
260	lock dec r14
261	%endif
262	%endif
263	%if TEST_BITS != 64
264	; 48 +rw DEC reg16
265	lock dec dx
266	; 48 +rd DEC reg32
267	lock dec edx
268	%endif
269
270	;
271	; INC
272	;
273	; fe /1 INC reg8/mem8 - with reg dst
274	lock inc bl
275	; ff /1 INC regX/memX - with reg dst
276
277	%if TEST_BITS != 64 ; cannot force these two in 32 and 16 bit mode.
278	db 066h, 0f0h, 0ffh, 0c3h
279	db 0f0h, 0ffh, 0c3h
280	%else
281	lock inc bx
282	lock inc ebx
283	%ifdef WITH_64_BIT_TESTS
284	lock inc rbx
285	lock inc r8
286	lock inc r14
287	%endif
288	%endif
289	%if TEST_BITS != 64
290	; 48 +rw INC reg16
291	lock inc dx
292	; 48 +rd INC reg32
293	lock inc edx
294	%endif
295
296	;
297	; NEG
298	;
299	; f6 /3 NEG reg8/mem8 - with reg dst
300	lock neg bl
301	; f7 /3 NEG regX/memX - with reg dst
302	lock neg bx
303	lock neg ebx
304	%ifdef WITH_64_BIT_TESTS
305	lock neg rbx
306	lock neg r8
307	lock neg r14
308	%endif
309
310	;
311	; NOT
312	;
313	; f6 /2 NOT reg8/mem8 - with reg dst
314	lock not bl
315	; f7 /2 NOT regX/memX - with reg dst
316	lock not bx
317	lock not ebx
318	%ifdef WITH_64_BIT_TESTS
319	lock not rbx
320	lock not r8
321	lock not r14
322	%endif
323
324	;
325	; OR
326	;
327	; 0C ib OR AL, imm8
328	lock or al, byte 8
329	; 0D i[wd] OR [ER]AX, immX
330	lock or ax, word 16
331	lock or eax, dword 128
332	%ifdef WITH_64_BIT_TESTS_IMM32
333	lock or rax, dword 256
334	lock or rax, dword 0cc90cc90h
335	%endif
336	; 80 /1 ib OR reg/mem8, imm8 - with reg dst
337	lock or cl, byte 8
338	; 81 /1 i[wd] OR reg/memX, immX - with reg dst
339	lock or cx, word 1000h
340	lock or ecx, dword 100000h
341	%ifdef WITH_64_BIT_TESTS_IMM32
342	lock or rcx, dword 100000h
343	%endif
344	; 83 /1 ib OR reg/memX, imm8 - with reg dst
345	lock or cx, byte 07fh
346	lock or ecx, byte 07fh
347	%ifdef WITH_64_BIT_TESTS_IMM32
348	lock or rcx, byte 07fh
349	%endif
350	; 08 /r OR reg/mem8, reg8 - with reg dst
351	lock or cl, bl
352	; 09 /r OR reg/memX, regX - with reg dst
353	lock or cx, bx
354	lock or ecx, ebx
355	%ifdef WITH_64_BIT_TESTS
356	lock or rcx, rbx
357	%endif
358	; 0A /r OR reg8, reg/mem8
359	lock or cl, [0badh]
360	; 0B /r OR regX, reg/memX
361	lock or cx, [0badh]
362	lock or ecx, [0badh]
363	%ifdef WITH_64_BIT_TESTS
364	lock or rcx, [0badh]
365	%endif
366
367	;
368	; SBB
369	;
370	; 1C ib SBB AL, imm8
371	lock sbb al, byte 8
372	; 1D i[wd] SBB [ER]AX, immX
373	lock sbb ax, word 16
374	lock sbb eax, dword 128
375	%ifdef WITH_64_BIT_TESTS_IMM32
376	lock sbb rax, dword 256
377	lock sbb rax, dword 0cc90cc90h
378	%endif
379	; 80 /3 ib SBB reg/mem8, imm8 - with reg dst
380	lock sbb cl, byte 8
381	; 81 /3 i[wd] SBB reg/memX, immX - with reg dst
382	lock sbb cx, word 1000h
383	lock sbb ecx, dword 100000h
384	%ifdef WITH_64_BIT_TESTS_IMM32
385	lock sbb rcx, dword 100000h
386	%endif
387	; 83 /3 ib SBB reg/memX, imm8 - with reg dst
388	lock sbb cx, byte 07fh
389	lock sbb ecx, byte 07fh
390	%ifdef WITH_64_BIT_TESTS_IMM32
391	lock sbb rcx, byte 07fh
392	%endif
393	; 18 /r SBB reg/mem8, reg8 - with reg dst
394	lock sbb cl, bl
395	; 19 /r SBB reg/memX, regX - with reg dst
396	lock sbb cx, bx
397	lock sbb ecx, ebx
398	%ifdef WITH_64_BIT_TESTS
399	lock sbb rcx, rbx
400	%endif
401	; 1A /r SBB reg8, reg/mem8
402	lock sbb cl, [0badh]
403	; 1B /r SBB regX, reg/memX
404	lock sbb cx, [0badh]
405	lock sbb ecx, [0badh]
406	%ifdef WITH_64_BIT_TESTS
407	lock sbb rcx, [0badh]
408	%endif
409
410	;
411	; SUB
412	;
413	; 2C ib SUB AL, imm8
414	lock sub al, byte 8
415	; 2D i[wd] SUB [ER]AX, immX
416	lock sub ax, word 16
417	lock sub eax, dword 128
418	%ifdef WITH_64_BIT_TESTS_IMM32
419	lock sub rax, dword 256
420	lock sub rax, dword 0cc90cc90h
421	%endif
422	; 80 /5 ib SUB reg/mem8, imm8 - with reg dst
423	lock sub cl, byte 8
424	; 81 /5 i[wd] SUB reg/memX, immX - with reg dst
425	lock sub cx, word 1000h
426	lock sub ecx, dword 100000h
427	%ifdef WITH_64_BIT_TESTS_IMM32
428	lock sub rcx, dword 100000h
429	%endif
430	; 83 /5 ib SUB reg/memX, imm8 - with reg dst
431	lock sub cx, byte 07fh
432	lock sub ecx, byte 07fh
433	%ifdef WITH_64_BIT_TESTS_IMM32
434	lock sub rcx, byte 07fh
435	%endif
436	; 28 /r SUB reg/mem8, reg8 - with reg dst
437	lock sub cl, bl
438	; 29 /r SUB reg/memX, regX - with reg dst
439	lock sub cx, bx
440	lock sub ecx, ebx
441	%ifdef WITH_64_BIT_TESTS
442	lock sub rcx, rbx
443	%endif
444	; 2A /r SUB reg8, reg/mem8
445	lock sub cl, [0badh]
446	; 2B /r SUB regX, reg/memX
447	lock sub cx, [0badh]
448	lock sub ecx, [0badh]
449	%ifdef WITH_64_BIT_TESTS
450	lock sub rcx, [0badh]
451	%endif
452
453	;
454	; XADD
455	;
456	; 0f c0 /r XADD reg/mem8, reg8 - with reg dst
457	lock xadd al, bl
458	; 0f c1 /r XADD reg/memX, immX - with reg dst
459	lock xadd cx, bx
460	lock xadd ecx, ebx
461	%ifdef WITH_64_BIT_TESTS
462	lock xadd rcx, rbx
463	lock xadd r8, rbx
464	lock xadd r10, r8
465	%endif
466
467	;
468	; XCHG
469	;
470	; Note: The operands can be switched around but the
471	; encoding is the same.
472	;
473	; 90 +r[wdq] XCHG [RE]ax, regX
474	lock xchg ax, bx
475	lock xchg eax, ecx
476	%ifdef WITH_64_BIT_TESTS
477	lock xchg rax, rcx
478	lock xchg rax, r10
479	%endif
480	; 86 /r XCHG reg/mem8, imm8 - with reg dst
481	lock xchg al, bl
482	%ifdef WITH_64_BIT_TESTS
483	lock xchg r10b, cl
484	lock xchg r10b, r15b
485	%endif
486	; 87 /r XCHG reg/memX, immX - with reg dst
487	lock xchg ax, bx
488	lock xchg eax, ebx
489	%ifdef WITH_64_BIT_TESTS_IMM32
490	lock xchg rax, rbx
491	lock xchg r12, rbx
492	lock xchg r14, r8
493	%endif
494
495	;
496	; XOR
497	;
498	; 34 ib XOR AL, imm8
499	lock xor al, byte 8
500	; 35 i[wd] XOR [ER]AX, immX
501	lock xor ax, word 16
502	lock xor eax, dword 128
503	%ifdef WITH_64_BIT_TESTS_IMM32
504	lock xor rax, dword 256
505	lock xor rax, dword 0cc90cc90h
506	%endif
507	; 80 /6 ib XOR reg/mem8, imm8 - with reg dst
508	lock xor cl, byte 8
509	; 81 /6 i[wd] XOR reg/memX, immX - with reg dst
510	lock xor cx, word 1000h
511	lock xor ecx, dword 100000h
512	%ifdef WITH_64_BIT_TESTS_IMM32
513	lock xor rcx, dword 100000h
514	%endif
515	; 83 /6 ib XOR reg/memX, imm8 - with reg dst
516	lock xor cx, byte 07fh
517	lock xor ecx, byte 07fh
518	%ifdef WITH_64_BIT_TESTS_IMM32
519	lock xor rcx, byte 07fh
520	%endif
521	; 30 /r XOR reg/mem8, reg8 - with reg dst
522	lock xor cl, bl
523	; 31 /r XOR reg/memX, regX - with reg dst
524	lock xor cx, bx
525	lock xor ecx, ebx
526	%ifdef WITH_64_BIT_TESTS
527	lock xor rcx, rbx
528	%endif
529	; 32 /r XOR reg8, reg/mem8
530	lock xor cl, [0badh]
531	; 33 /r XOR regX, reg/memX
532	lock xor cx, [0badh]
533	lock xor ecx, [0badh]
534	%ifdef WITH_64_BIT_TESTS
535	lock xor rcx, [0badh]
536	%endif
537

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source: vbox/trunk/src/VBox/Disassembler/testcase/tstAsmLock-2.asm@ 86186

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