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source: vbox/trunk/src/VBox/Disassembler/testcase/tstAsmLock-2.asm@ 8975

Last change on this file since 8975 was 8975, checked in by vboxsync, 17 years ago

NEG & NOT.

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1; $Id: tstAsmLock-2.asm 8975 2008-05-20 19:01:58Z vboxsync $
2;; @file
3; Disassembly testcase - Invalid invariants.
4;
5; The intention is to check in a binary using the --all-invalid mode
6; of tstDisasm-2.
7;
8
9;
10; Copyright (C) 2008 Sun Microsystems, Inc.
11;
12; This file is part of VirtualBox Open Source Edition (OSE), as
13; available from http://www.virtualbox.org. This file is free software;
14; you can redistribute it and/or modify it under the terms of the GNU
15; General Public License (GPL) as published by the Free Software
16; Foundation, in version 2 as it comes in the "COPYING" file of the
17; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19;
20; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
21; Clara, CA 95054 USA or visit http://www.sun.com if you need
22; additional information or have any questions.
23;
24
25%include "tstAsm.mac"
26%if TEST_BITS == 64
27; The disassembler doesn't do imm32 right for 64-bit stuff, so disable it for now.
28; %define WITH_64_BIT_TESTS_IMM32
29 %define WITH_64_BIT_TESTS
30%endif
31
32 BITS TEST_BITS
33
34 ;
35 ; ADC
36 ;
37 ; 14 ib ADC AL, imm8
38 lock adc al, byte 8
39 ; 15 i[wd] ADC [ER]AX, immX
40 lock adc ax, word 16
41 lock adc eax, dword 128
42%ifdef WITH_64_BIT_TESTS_IMM32
43 lock adc rax, dword 256
44 lock adc rax, dword 0cc90cc90h
45%endif
46 ; 80 /2 ib ADC reg/mem8, imm8 - with reg dst
47 lock adc cl, byte 8
48 ; 81 /2 i[wd] ADC reg/memX, immX - with reg dst
49 lock adc cx, word 1000h
50 lock adc ecx, dword 100000h
51%ifdef WITH_64_BIT_TESTS_IMM32
52 lock adc rcx, dword 100000h
53%endif
54 ; 83 /2 ib ADC reg/memX, imm8 - with reg dst
55 lock adc cx, byte 07fh
56 lock adc ecx, byte 07fh
57%ifdef WITH_64_BIT_TESTS_IMM32
58 lock adc rcx, byte 07fh
59%endif
60
61 ; 10 /r ADC reg/mem8, reg8 - with reg dst
62 lock adc cl, bl
63 ; 11 /r ADC reg/memX, regX - with reg dst
64 lock adc cx, bx
65 lock adc ecx, ebx
66%ifdef WITH_64_BIT_TESTS
67 lock adc rcx, rbx
68%endif
69 ; 12 /r ADC reg8, reg/mem8
70 lock adc cl, [0badh]
71 ; 13 /r ADC regX, reg/memX
72 lock adc cx, [0badh]
73 lock adc ecx, [0badh]
74%ifdef WITH_64_BIT_TESTS
75 lock adc rcx, [0badh]
76%endif
77
78 ;
79 ; ADD
80 ;
81 ; 04 ib ADD AL, imm8
82 lock add al, byte 8
83 ; 05 i[wd] ADD [ER]AX, immX
84 lock add ax, word 16
85 lock add eax, dword 128
86%ifdef WITH_64_BIT_TESTS_IMM32
87 lock add rax, dword 256
88 lock add rax, dword 0cc90cc90h
89%endif
90 ; 80 /0 ib ADD reg/mem8, imm8 - with reg dst
91 lock add cl, byte 8
92 ; 81 /0 i[wd] ADD reg/memX, immX - with reg dst
93 lock add cx, word 1000h
94 lock add ecx, dword 100000h
95%ifdef WITH_64_BIT_TESTS_IMM32
96 lock add rcx, dword 100000h
97%endif
98 ; 83 /0 ib ADD reg/memX, imm8 - with reg dst
99 lock add cx, byte 07fh
100 lock add ecx, byte 07fh
101%ifdef WITH_64_BIT_TESTS
102 lock add rcx, byte 07fh
103%endif
104
105 ; 00 /r ADD reg/mem8, reg8 - with reg dst
106 lock add cl, bl
107 ; 01 /r ADD reg/memX, regX - with reg dst
108 lock add cx, bx
109 lock add ecx, ebx
110%ifdef WITH_64_BIT_TESTS
111 lock add rcx, rbx
112%endif
113 ; 02 /r ADD reg8, reg/mem8
114 lock add cl, [0badh]
115 ; 03 /r ADD regX, reg/memX
116 lock add cx, [0badh]
117 lock add ecx, [0badh]
118%ifdef WITH_64_BIT_TESTS
119 lock add rcx, [0badh]
120%endif
121
122 ;
123 ; AND
124 ;
125 ; 24 ib AND AL, imm8
126 lock and al, byte 8
127 ; 25 i[wd] AND [ER]AX, immX
128 lock and ax, word 16
129 lock and eax, dword 128
130%ifdef WITH_64_BIT_TESTS_IMM32
131 lock and rax, dword 256
132 lock and rax, dword 0cc90cc90h
133%endif
134 ; 80 /4 ib AND reg/mem8, imm8 - with reg dst
135 lock and cl, byte 8
136 ; 81 /4 i[wd] AND reg/memX, immX - with reg dst
137 lock and cx, word 1000h
138 lock and ecx, dword 100000h
139%ifdef WITH_64_BIT_TESTS_IMM32
140 lock and rcx, dword 100000h
141%endif
142 ; 83 /4 ib AND reg/memX, imm8 - with reg dst
143 lock and cx, byte 07fh
144 lock and ecx, byte 07fh
145%ifdef WITH_64_BIT_TESTS
146 lock and rcx, byte 07fh
147%endif
148
149 ; 20 /r AND reg/mem8, reg8 - with reg dst
150 lock and cl, bl
151 ; 21 /r AND reg/memX, regX - with reg dst
152 lock and cx, bx
153 lock and ecx, ebx
154%ifdef WITH_64_BIT_TESTS
155 lock and rcx, rbx
156%endif
157 ; 22 /r AND reg8, reg/mem8
158 lock and cl, [0badh]
159 ; 23 /r AND regX, reg/memX
160 lock and cx, [0badh]
161 lock and ecx, [0badh]
162%ifdef WITH_64_BIT_TESTS
163 lock and rcx, [0badh]
164%endif
165
166 ;
167 ; BTC
168 ;
169 ; 0f bb /r BTC reg/memX, regX (X != 8) - with reg dst
170 lock btc cx, bx
171 lock btc ecx, ebx
172%ifdef WITH_64_BIT_TESTS
173 lock btc rcx, rbx
174 lock btc r8, rbx
175 lock btc r10, r8
176%endif
177 ; 0f ba /7 ib BTC reg/memX, imm8 (X != 8) - with reg dst
178 lock btc cx, 15
179 lock btc ecx, 30
180%ifdef WITH_64_BIT_TESTS
181 lock btc rcx, 60
182 lock btc r8, 61
183 lock btc r10, 3
184%endif
185
186 ;
187 ; BTR
188 ;
189 ; 0f b3 /r BTR reg/memX, regX (X != 8) - with reg dst
190 lock btr cx, bx
191 lock btr ecx, ebx
192%ifdef WITH_64_BIT_TESTS
193 lock btr rcx, rbx
194 lock btr r8, rbx
195 lock btr r10, r8
196%endif
197 ; 0f ba /6 ib BTR reg/memX, imm8 (X != 8) - with reg dst
198 lock btr cx, 15
199 lock btr ecx, 30
200%ifdef WITH_64_BIT_TESTS
201 lock btr rcx, 60
202 lock btr r8, 61
203 lock btr r10, 3
204%endif
205
206 ;
207 ; BTS
208 ;
209 ; 0f ab /r BTS reg/memX, regX (X != 8) - with reg dst
210 lock bts cx, bx
211 lock bts ecx, ebx
212%ifdef WITH_64_BIT_TESTS
213 lock bts rcx, rbx
214 lock bts r8, rbx
215 lock bts r10, r8
216%endif
217 ; 0f ba /5 ib BTS reg/memX, imm8 (X != 8) - with reg dst
218 lock bts cx, 15
219 lock bts ecx, 30
220%ifdef WITH_64_BIT_TESTS
221 lock bts rcx, 60
222 lock bts r8, 61
223 lock bts r10, 3
224%endif
225
226 ;
227 ; CMPXCHG
228 ;
229 ; 0f b0 /r CMPXCHG reg8/mem8, regX - with reg dst
230 lock cmpxchg bl, cl
231 ; 0f b1 /r CMPXCHG regX/memX, regX - with reg dst
232 lock cmpxchg bx, cx
233 lock cmpxchg ebx, ecx
234%ifdef WITH_64_BIT_TESTS
235 lock cmpxchg rbx, rcx
236%endif
237
238 ;
239 ; CMPXCHG8B
240 ; CMPXCHG16B
241 ;
242 ; all valid.
243
244 ;
245 ; DEC
246 ;
247 ; fe /1 DEC reg8/mem8 - with reg dst
248 lock dec bl
249 ; ff /1 DEC regX/memX - with reg dst
250
251%if TEST_BITS != 64 ; cannot force these two in 32 and 16 bit mode.
252 db 066h, 0f0h, 0ffh, 0cbh
253 db 0f0h, 0ffh, 0cbh
254%else
255 lock dec bx
256 lock dec ebx
257 %ifdef WITH_64_BIT_TESTS
258 lock dec rbx
259 lock dec r8
260 lock dec r14
261 %endif
262%endif
263%if TEST_BITS != 64
264 ; 48 +rw DEC reg16
265 lock dec dx
266 ; 48 +rd DEC reg32
267 lock dec edx
268%endif
269
270 ;
271 ; INC
272 ;
273 ; fe /1 INC reg8/mem8 - with reg dst
274 lock inc bl
275 ; ff /1 INC regX/memX - with reg dst
276
277%if TEST_BITS != 64 ; cannot force these two in 32 and 16 bit mode.
278 db 066h, 0f0h, 0ffh, 0c3h
279 db 0f0h, 0ffh, 0c3h
280%else
281 lock inc bx
282 lock inc ebx
283 %ifdef WITH_64_BIT_TESTS
284 lock inc rbx
285 lock inc r8
286 lock inc r14
287 %endif
288%endif
289%if TEST_BITS != 64
290 ; 48 +rw INC reg16
291 lock inc dx
292 ; 48 +rd INC reg32
293 lock inc edx
294%endif
295
296 ;
297 ; NEG
298 ;
299 ; f6 /3 NEG reg8/mem8 - with reg dst
300 lock neg bl
301 ; f7 /3 NEG regX/memX - with reg dst
302 lock neg bx
303 lock neg ebx
304%ifdef WITH_64_BIT_TESTS
305 lock neg rbx
306 lock neg r8
307 lock neg r14
308%endif
309
310 ;
311 ; NOT
312 ;
313 ; f6 /2 NOT reg8/mem8 - with reg dst
314 lock not bl
315 ; f7 /2 NOT regX/memX - with reg dst
316 lock not bx
317 lock not ebx
318%ifdef WITH_64_BIT_TESTS
319 lock not rbx
320 lock not r8
321 lock not r14
322%endif
323
324 ; OR
325 ; SBB
326 ; SUB
327 ; XADD
328 ; XCHG
329 ; XOR
330
331
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