| 1 | /* $Id: tstDisasmArmv8-1-asm.S 105815 2024-08-22 12:25:28Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VBox disassembler - Tables for ARMv8 A64.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | .private_extern _TestProcA64
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| 29 | _TestProcA64:
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| 30 | ; Miscellaneous instructions without a parameter
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| 31 | nop
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| 32 | yield
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| 33 | wfe
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| 34 | wfi
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| 35 | sev
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| 36 | sevl
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| 37 | dgh
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| 38 | xpaclri
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| 39 |
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| 40 | ; Control flow instructions
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| 41 | svc #0xfefe
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| 42 | hvc #0xdead
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| 43 | smc #0xcafe
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| 44 | brk #0xd0d0
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| 45 | hlt #0xc0de
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| 46 | ; tcancel #0xd00f Requires FEAT_TME
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| 47 | dcps1 #0xdeca
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| 48 | dcps2 #0xdec0
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| 49 | dcps3 #0xfeed
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| 50 | b #0x100
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| 51 | b #-0x100
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| 52 | bl #0x100
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| 53 | bl #-0x100
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| 54 | b.ne #+0x1000
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| 55 | b.eq #-0x1000
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| 56 | ; bc.ne #+0x1000 Requires FEAT_HBC
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| 57 | ; bc.eq #-0x1000 Requires FEAT_HBC
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| 58 | cbz x0, #+0x100
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| 59 | cbz x0, #-0x100
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| 60 | cbz w0, #+0x100
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| 61 | cbnz x0, #+0x100
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| 62 | cbnz x0, #-0x100
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| 63 | cbnz w0, #+0x100
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| 64 | tbz w0, #13, #+0x100
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| 65 | tbz x0, #63, #-0x100
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| 66 | tbz w0, #8, #+0x100
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| 67 | ret x30
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| 68 | ret x1
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| 69 | ret x2
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| 70 | ret x15
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| 71 | br x15
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| 72 | blr x15
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| 73 |
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| 74 | ; System register access instructions
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| 75 | msr ttbr0_el1, x0
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| 76 | mrs x0, ttbr0_el1
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| 77 |
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| 78 | ; Arithmetic instructions
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| 79 | add x0, x0, #0x0
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| 80 | add x0, x1, #0x10000
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| 81 | add x0, x1, #65536
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| 82 | add x0, x0, x0
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| 83 | add x0, x1, x29
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| 84 | add x0, x1, x28, LSL #1
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| 85 | add x0, x1, x28, LSL #63
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| 86 | add x0, x1, x28, LSR #1
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| 87 | add x0, x1, x28, LSR #63
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| 88 | add x0, x1, x28, ASR #1
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| 89 | add x0, x1, x28, ASR #63
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| 90 | ; ROR is reserved
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| 91 |
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| 92 | add w0, w1, #0x0
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| 93 | add w0, w1, #0x10000
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| 94 | add w0, w1, #65536
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| 95 | add w0, w1, w29
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| 96 | add w0, w1, w28, LSL #1
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| 97 | add w0, w1, w28, LSL #31
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| 98 | add w0, w1, w28, LSR #1
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| 99 | add w0, w1, w28, LSR #31
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| 100 | add w0, w1, w28, ASR #1
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| 101 | add w0, w1, w28, ASR #31
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| 102 | ; ROR is reserved
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| 103 |
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| 104 | adds x0, x0, #0x0
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| 105 | adds x0, x1, #0x10000
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| 106 | adds x0, x1, #65536
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| 107 | adds x0, x0, x0
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| 108 | adds x0, x1, x29
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| 109 | adds x0, x1, x28, LSL #1
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| 110 | adds x0, x1, x28, LSL #63
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| 111 | adds x0, x1, x28, LSR #1
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| 112 | adds x0, x1, x28, LSR #63
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| 113 | adds x0, x1, x28, ASR #1
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| 114 | adds x0, x1, x28, ASR #63
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| 115 | ; ROR is reserved
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| 116 |
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| 117 | adds w0, w1, #0x0
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| 118 | adds w0, w1, #0x10000
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| 119 | adds w0, w1, #65536
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| 120 | adds w0, w1, w29
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| 121 | adds w0, w1, w28, LSL #1
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| 122 | adds w0, w1, w28, LSL #31
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| 123 | adds w0, w1, w28, LSR #1
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| 124 | adds w0, w1, w28, LSR #31
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| 125 | adds w0, w1, w28, ASR #1
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| 126 | adds w0, w1, w28, ASR #31
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| 127 | ; ROR is reserved
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| 128 |
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| 129 | sub x0, x0, #0x0
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| 130 | sub x0, x1, #0x10000
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| 131 | sub x0, x1, #65536
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| 132 | sub x0, x0, x0
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| 133 | sub x0, x1, x29
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| 134 | sub x0, x1, x28, LSL #1
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| 135 | sub x0, x1, x28, LSL #63
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| 136 | sub x0, x1, x28, LSR #1
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| 137 | sub x0, x1, x28, LSR #63
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| 138 | sub x0, x1, x28, ASR #1
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| 139 | sub x0, x1, x28, ASR #63
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| 140 | ; ROR is reserved
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| 141 |
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| 142 | sub w0, w1, #0x0
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| 143 | sub w0, w1, #0x10000
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| 144 | sub w0, w1, #65536
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| 145 | sub w0, w1, w29
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| 146 | sub w0, w1, w28, LSL #1
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| 147 | sub w0, w1, w28, LSL #31
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| 148 | sub w0, w1, w28, LSR #1
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| 149 | sub w0, w1, w28, LSR #31
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| 150 | sub w0, w1, w28, ASR #1
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| 151 | sub w0, w1, w28, ASR #31
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| 152 | ; ROR is reserved
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| 153 |
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| 154 | subs x0, x0, #0x0
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| 155 | subs x0, x1, #0x10000
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| 156 | subs x0, x1, #65536
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| 157 | subs x0, x0, x0
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| 158 | subs x0, x1, x29
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| 159 | subs x0, x1, x28, LSL #1
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| 160 | subs x0, x1, x28, LSL #63
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| 161 | subs x0, x1, x28, LSR #1
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| 162 | subs x0, x1, x28, LSR #63
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| 163 | subs x0, x1, x28, ASR #1
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| 164 | subs x0, x1, x28, ASR #63
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| 165 | ; ROR is reserved
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| 166 |
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| 167 | subs w0, w1, #0x0
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| 168 | subs w0, w1, #0x10000
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| 169 | subs w0, w1, #65536
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| 170 | subs w0, w1, w29
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| 171 | subs w0, w1, w28, LSL #1
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| 172 | subs w0, w1, w28, LSL #31
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| 173 | subs w0, w1, w28, LSR #1
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| 174 | subs w0, w1, w28, LSR #31
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| 175 | subs w0, w1, w28, ASR #1
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| 176 | subs w0, w1, w28, ASR #31
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| 177 | ; ROR is reserved
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| 178 |
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| 179 | ; Aliases of subs -> cmp
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| 180 | cmp x0, x1
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| 181 | cmp w0, w1
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| 182 | cmp x0, x1, LSL #1
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| 183 | cmp w0, w1, LSL #1
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| 184 |
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| 185 | ; Logical instructions
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| 186 | and x0, x0, #0xffff
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| 187 | and w0, wzr, #0xffff
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| 188 |
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| 189 | ands x0, x0, #0x00ffff00
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| 190 | ands w10, w23, #0x55555555
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| 191 |
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| 192 | orr x0, x0, #0xffff
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| 193 | orr w0, wzr, #0xffff
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| 194 |
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| 195 | mov x0, x1 ; Alias of orr
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| 196 | mov w0, w1 ; Alias of orr
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| 197 |
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| 198 | eor x0, x0, #0x00ffff00
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| 199 | eor w10, w23, #0x55555555
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| 200 |
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| 201 | sbfm x0, x0, #0x1, #0x2
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| 202 | sbfm w0, w0, #0xf, #0x9
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| 203 | bfm x0, x0, #0x1, #0x2
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| 204 | bfm w0, w0, #0xf, #0x9
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| 205 | ubfm x0, x0, #0x1, #0x2
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| 206 | ubfm w0, w0, #0xf, #0x9
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| 207 |
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| 208 | movn x0, #0xffff
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| 209 | movn x0, #0xffff, LSL #16
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| 210 | movn w0, #0xffff
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| 211 | movn w0, #0xffff, LSL #16
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| 212 |
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| 213 | movz x0, #0xffff
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| 214 | movz x0, #0xffff, LSL #48
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| 215 | movz w0, #0xffff
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| 216 | movz w0, #0xffff, LSL #16
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| 217 |
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| 218 | movk x0, #0xffff
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| 219 | movk x0, #0xffff, LSL #32
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| 220 | movk w0, #0xffff
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| 221 | movk w0, #0xffff, LSL #16
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| 222 |
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| 223 | ; Logical instructions with a shifted register
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| 224 | and w0, w0, w27
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| 225 | and w0, w1, w28, LSL #1
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| 226 | and w0, w1, w28, LSL #31
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| 227 | and w0, w1, w28, LSR #1
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| 228 | and w0, w1, w28, LSR #31
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| 229 | and w0, w1, w28, ASR #1
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| 230 | and w0, w1, w28, ASR #31
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| 231 | and w0, w1, w28, ROR #1
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| 232 | and w0, w1, w28, ROR #31
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| 233 |
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| 234 | and x0, x0, x27
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| 235 | and x0, x1, x28, LSL #1
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| 236 | and x0, x1, x28, LSL #63
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| 237 | and x0, x1, x28, LSR #1
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| 238 | and x0, x1, x28, LSR #63
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| 239 | and x0, x1, x28, ASR #1
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| 240 | and x0, x1, x28, ASR #63
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| 241 | and x0, x1, x28, ROR #1
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| 242 | and x0, x1, x28, ROR #63
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| 243 |
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| 244 | orr w0, w0, w27
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| 245 | orr w0, w1, w28, LSL #1
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| 246 | orr w0, w1, w28, LSL #31
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| 247 | orr w0, w1, w28, LSR #1
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| 248 | orr w0, w1, w28, LSR #31
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| 249 | orr w0, w1, w28, ASR #1
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| 250 | orr w0, w1, w28, ASR #31
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| 251 | orr w0, w1, w28, ROR #1
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| 252 | orr w0, w1, w28, ROR #31
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| 253 |
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| 254 | orr x0, x0, x27
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| 255 | orr x0, x1, x28, LSL #1
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| 256 | orr x0, x1, x28, LSL #63
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| 257 | orr x0, x1, x28, LSR #1
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| 258 | orr x0, x1, x28, LSR #63
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| 259 | orr x0, x1, x28, ASR #1
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| 260 | orr x0, x1, x28, ASR #63
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| 261 | orr x0, x1, x28, ROR #1
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| 262 | orr x0, x1, x28, ROR #63
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| 263 |
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| 264 | eor w0, w0, w27
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| 265 | eor w0, w1, w28, LSL #1
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| 266 | eor w0, w1, w28, LSL #31
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| 267 | eor w0, w1, w28, LSR #1
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| 268 | eor w0, w1, w28, LSR #31
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| 269 | eor w0, w1, w28, ASR #1
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| 270 | eor w0, w1, w28, ASR #31
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| 271 | eor w0, w1, w28, ROR #1
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| 272 | eor w0, w1, w28, ROR #31
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| 273 |
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| 274 | eor x0, x0, x27
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| 275 | eor x0, x1, x28, LSL #1
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| 276 | eor x0, x1, x28, LSL #63
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| 277 | eor x0, x1, x28, LSR #1
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| 278 | eor x0, x1, x28, LSR #63
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| 279 | eor x0, x1, x28, ASR #1
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| 280 | eor x0, x1, x28, ASR #63
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| 281 | eor x0, x1, x28, ROR #1
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| 282 | eor x0, x1, x28, ROR #63
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| 283 |
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| 284 | ands x0, x0, x27
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| 285 | ands x0, x1, x28, LSL #1
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| 286 | ands x0, x1, x28, LSL #63
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| 287 | ands x0, x1, x28, LSR #1
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| 288 | ands x0, x1, x28, LSR #63
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| 289 | ands x0, x1, x28, ASR #1
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| 290 | ands x0, x1, x28, ASR #63
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| 291 | ands x0, x1, x28, ROR #1
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| 292 | ands x0, x1, x28, ROR #63
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| 293 |
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| 294 | bic w0, w0, w27
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| 295 | bic w0, w1, w28, LSL #1
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| 296 | bic w0, w1, w28, LSL #31
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| 297 | bic w0, w1, w28, LSR #1
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| 298 | bic w0, w1, w28, LSR #31
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| 299 | bic w0, w1, w28, ASR #1
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| 300 | bic w0, w1, w28, ASR #31
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| 301 | bic w0, w1, w28, ROR #1
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| 302 | bic w0, w1, w28, ROR #31
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| 303 |
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| 304 | bic x0, x0, x27
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| 305 | bic x0, x1, x28, LSL #1
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| 306 | bic x0, x1, x28, LSL #63
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| 307 | bic x0, x1, x28, LSR #1
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| 308 | bic x0, x1, x28, LSR #63
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| 309 | bic x0, x1, x28, ASR #1
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| 310 | bic x0, x1, x28, ASR #63
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| 311 | bic x0, x1, x28, ROR #1
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| 312 | bic x0, x1, x28, ROR #63
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| 313 |
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| 314 | orn w0, w0, w27
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| 315 | orn w0, w1, w28, LSL #1
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| 316 | orn w0, w1, w28, LSL #31
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| 317 | orn w0, w1, w28, LSR #1
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| 318 | orn w0, w1, w28, LSR #31
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| 319 | orn w0, w1, w28, ASR #1
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| 320 | orn w0, w1, w28, ASR #31
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| 321 | orn w0, w1, w28, ROR #1
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| 322 | orn w0, w1, w28, ROR #31
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| 323 |
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| 324 | orn x0, x0, x27
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| 325 | orn x0, x1, x28, LSL #1
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| 326 | orn x0, x1, x28, LSL #63
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| 327 | orn x0, x1, x28, LSR #1
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| 328 | orn x0, x1, x28, LSR #63
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| 329 | orn x0, x1, x28, ASR #1
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| 330 | orn x0, x1, x28, ASR #63
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| 331 | orn x0, x1, x28, ROR #1
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| 332 | orn x0, x1, x28, ROR #63
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| 333 |
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| 334 | eon w0, w0, w27
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| 335 | eon w0, w1, w28, LSL #1
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| 336 | eon w0, w1, w28, LSL #31
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| 337 | eon w0, w1, w28, LSR #1
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| 338 | eon w0, w1, w28, LSR #31
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| 339 | eon w0, w1, w28, ASR #1
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| 340 | eon w0, w1, w28, ASR #31
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| 341 | eon w0, w1, w28, ROR #1
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| 342 | eon w0, w1, w28, ROR #31
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| 343 |
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| 344 | eon x0, x0, x27
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| 345 | eon x0, x1, x28, LSL #1
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| 346 | eon x0, x1, x28, LSL #63
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| 347 | eon x0, x1, x28, LSR #1
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| 348 | eon x0, x1, x28, LSR #63
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| 349 | eon x0, x1, x28, ASR #1
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| 350 | eon x0, x1, x28, ASR #63
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| 351 | eon x0, x1, x28, ROR #1
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| 352 | eon x0, x1, x28, ROR #63
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| 353 |
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| 354 | bics w0, w0, w27
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| 355 | bics w0, w1, w28, LSL #1
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| 356 | bics w0, w1, w28, LSL #31
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| 357 | bics w0, w1, w28, LSR #1
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| 358 | bics w0, w1, w28, LSR #31
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| 359 | bics w0, w1, w28, ASR #1
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| 360 | bics w0, w1, w28, ASR #31
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| 361 | bics w0, w1, w28, ROR #1
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| 362 | bics w0, w1, w28, ROR #31
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| 363 |
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| 364 | bics x0, x0, x27
|
|---|
| 365 | bics x0, x1, x28, LSL #1
|
|---|
| 366 | bics x0, x1, x28, LSL #63
|
|---|
| 367 | bics x0, x1, x28, LSR #1
|
|---|
| 368 | bics x0, x1, x28, LSR #63
|
|---|
| 369 | bics x0, x1, x28, ASR #1
|
|---|
| 370 | bics x0, x1, x28, ASR #63
|
|---|
| 371 | bics x0, x1, x28, ROR #1
|
|---|
| 372 | bics x0, x1, x28, ROR #63
|
|---|
| 373 |
|
|---|
| 374 | ; Memory loads
|
|---|
| 375 | ldrb w0, [x28]
|
|---|
| 376 | ldrb w0, [x28, #1]
|
|---|
| 377 | ldrb w0, [x28, #4095]
|
|---|
| 378 |
|
|---|
| 379 | ldrsb w0, [x28]
|
|---|
| 380 | ldrsb w0, [x28, #1]
|
|---|
| 381 | ldrsb w0, [x28, #4095]
|
|---|
| 382 |
|
|---|
| 383 | ldrsb x0, [x28]
|
|---|
| 384 | ldrsb x0, [x28, #1]
|
|---|
| 385 | ldrsb x0, [x28, #4095]
|
|---|
| 386 |
|
|---|
| 387 | ldrh w0, [x28]
|
|---|
| 388 | ldrh w0, [x28, #2]
|
|---|
| 389 | ldrh w0, [x28, #1024]
|
|---|
| 390 |
|
|---|
| 391 | ldrsh w0, [x28]
|
|---|
| 392 | ldrsh w0, [x28, #2]
|
|---|
| 393 | ldrsh w0, [x28, #1024]
|
|---|
| 394 |
|
|---|
| 395 | ldrsh x0, [x28]
|
|---|
| 396 | ldrsh x0, [x28, #2]
|
|---|
| 397 | ldrsh x0, [x28, #1024]
|
|---|
| 398 |
|
|---|
| 399 | ldr x0, [x28]
|
|---|
| 400 | ldr x0, [x28, #8]
|
|---|
| 401 | ldr x0, [x28, #32760]
|
|---|
| 402 |
|
|---|
| 403 | ldr w0, [x28]
|
|---|
| 404 | ldr w0, [x28, #4]
|
|---|
| 405 | ldr w0, [x28, #16380]
|
|---|
| 406 |
|
|---|
| 407 | ldrsw x0, [x28]
|
|---|
| 408 | ldrsw x0, [x28, #4]
|
|---|
| 409 | ldrsw x0, [x28, #16380]
|
|---|
| 410 |
|
|---|
| 411 | ; Memory stores
|
|---|
| 412 | strb w0, [x28]
|
|---|
| 413 | strb w0, [x28, #1]
|
|---|
| 414 | strb w0, [x28, #4095]
|
|---|
| 415 |
|
|---|
| 416 | strh w0, [x28]
|
|---|
| 417 | strh w0, [x28, #2]
|
|---|
| 418 | strh w0, [x28, #1024]
|
|---|
| 419 |
|
|---|
| 420 | str x0, [x28]
|
|---|
| 421 | str x0, [x28, #8]
|
|---|
| 422 | str x0, [x28, #32760]
|
|---|
| 423 |
|
|---|
| 424 | str w0, [x28]
|
|---|
| 425 | str w0, [x28, #4]
|
|---|
| 426 | str w0, [x28, #16380]
|
|---|
| 427 |
|
|---|
| 428 | ; Conditional compare
|
|---|
| 429 | ccmp x0, x1, #0x3, eq
|
|---|
| 430 | ccmp w0, w1, #0xf, eq
|
|---|
| 431 | ccmp x0, x1, #0x3, ne
|
|---|
| 432 | ccmp w0, w1, #0xf, ne
|
|---|
| 433 | ccmp x0, x1, #0x3, cs
|
|---|
| 434 | ccmp w0, w1, #0xf, cc
|
|---|
| 435 | ccmp x0, x1, #0x3, mi
|
|---|
| 436 | ccmp w0, w1, #0xf, mi
|
|---|
| 437 | ccmp x0, x1, #0x3, pl
|
|---|
| 438 | ccmp w0, w1, #0xf, vs
|
|---|
| 439 | ccmp x0, x1, #0x3, vc
|
|---|
| 440 | ccmp w0, w1, #0xf, vc
|
|---|
| 441 | ccmp x0, x1, #0x3, hi
|
|---|
| 442 | ccmp w0, w1, #0xf, hi
|
|---|
| 443 | ccmp x0, x1, #0x3, ls
|
|---|
| 444 | ccmp w0, w1, #0xf, ls
|
|---|
| 445 | ccmp x0, x1, #0x3, ge
|
|---|
| 446 | ccmp w0, w1, #0xf, ge
|
|---|
| 447 | ccmp x0, x1, #0x3, lt
|
|---|
| 448 | ccmp w0, w1, #0xf, lt
|
|---|
| 449 | ccmp x0, x1, #0x3, gt
|
|---|
| 450 | ccmp w0, w1, #0xf, gt
|
|---|
| 451 | ccmp x0, x1, #0x3, le
|
|---|
| 452 | ccmp w0, w1, #0xf, le
|
|---|
| 453 | ccmp x0, x1, #0x3, al
|
|---|
| 454 | ccmp w0, w1, #0xf, al
|
|---|
| 455 |
|
|---|
| 456 | ccmn x0, x1, #0x3, eq
|
|---|
| 457 | ccmn w0, w1, #0xf, eq
|
|---|
| 458 | ccmn x0, x1, #0x3, ne
|
|---|
| 459 | ccmn w0, w1, #0xf, ne
|
|---|
| 460 | ccmn x0, x1, #0x3, cs
|
|---|
| 461 | ccmn w0, w1, #0xf, cc
|
|---|
| 462 | ccmn x0, x1, #0x3, mi
|
|---|
| 463 | ccmn w0, w1, #0xf, mi
|
|---|
| 464 | ccmn x0, x1, #0x3, pl
|
|---|
| 465 | ccmn w0, w1, #0xf, vs
|
|---|
| 466 | ccmn x0, x1, #0x3, vc
|
|---|
| 467 | ccmn w0, w1, #0xf, vc
|
|---|
| 468 | ccmn x0, x1, #0x3, hi
|
|---|
| 469 | ccmn w0, w1, #0xf, hi
|
|---|
| 470 | ccmn x0, x1, #0x3, ls
|
|---|
| 471 | ccmn w0, w1, #0xf, ls
|
|---|
| 472 | ccmn x0, x1, #0x3, ge
|
|---|
| 473 | ccmn w0, w1, #0xf, ge
|
|---|
| 474 | ccmn x0, x1, #0x3, lt
|
|---|
| 475 | ccmn w0, w1, #0xf, lt
|
|---|
| 476 | ccmn x0, x1, #0x3, gt
|
|---|
| 477 | ccmn w0, w1, #0xf, gt
|
|---|
| 478 | ccmn x0, x1, #0x3, le
|
|---|
| 479 | ccmn w0, w1, #0xf, le
|
|---|
| 480 | ccmn x0, x1, #0x3, al
|
|---|
| 481 | ccmn w0, w1, #0xf, al
|
|---|
| 482 |
|
|---|
| 483 | ;
|
|---|
| 484 | ; Keep last so the testcase can catch errors in
|
|---|
| 485 | ; the disassembly of the last instruction.
|
|---|
| 486 | ;
|
|---|
| 487 | nop
|
|---|
| 488 |
|
|---|
| 489 | .private_extern _TestProcA64_EndProc
|
|---|
| 490 | _TestProcA64_EndProc:
|
|---|
