tstDisasmArmv8-1-asm.S@ 105857

Last change on this file since 105857 was 105857, checked in by vboxsync, 3 months ago
Disassembler/ARMv8: Implement decoding of the ldr/str (unscaled immedate) variant instructions and add testcases, bugref:10394
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 16.9 KB

Line
1	/* $Id: tstDisasmArmv8-1-asm.S 105857 2024-08-25 12:22:39Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	.private_extern _TestProcA64
29	_TestProcA64:
30
31	; Miscellaneous instructions without a parameter
32	nop
33	yield
34	wfe
35	wfi
36	sev
37	sevl
38	dgh
39	xpaclri
40
41	; Control flow instructions
42	svc #0xfefe
43	hvc #0xdead
44	smc #0xcafe
45	brk #0xd0d0
46	hlt #0xc0de
47	; tcancel #0xd00f Requires FEAT_TME
48	dcps1 #0xdeca
49	dcps2 #0xdec0
50	dcps3 #0xfeed
51	b #0x100
52	b #-0x100
53	bl #0x100
54	bl #-0x100
55	b.ne #+0x1000
56	b.eq #-0x1000
57	; bc.ne #+0x1000 Requires FEAT_HBC
58	; bc.eq #-0x1000 Requires FEAT_HBC
59	cbz x0, #+0x100
60	cbz x0, #-0x100
61	cbz w0, #+0x100
62	cbnz x0, #+0x100
63	cbnz x0, #-0x100
64	cbnz w0, #+0x100
65	tbz w0, #13, #+0x100
66	tbz x0, #63, #-0x100
67	tbz w0, #8, #+0x100
68	ret x30
69	ret x1
70	ret x2
71	ret x15
72	br x15
73	blr x15
74
75	; System register access instructions
76	msr ttbr0_el1, x0
77	mrs x0, ttbr0_el1
78
79	; Arithmetic instructions
80	add x0, x0, #0x0
81	add x0, x1, #0x10000
82	add x0, x1, #65536
83	add x0, x0, x0
84	add x0, x1, x29
85	add x0, x1, x28, LSL #1
86	add x0, x1, x28, LSL #63
87	add x0, x1, x28, LSR #1
88	add x0, x1, x28, LSR #63
89	add x0, x1, x28, ASR #1
90	add x0, x1, x28, ASR #63
91	; ROR is reserved
92
93	add w0, w1, #0x0
94	add w0, w1, #0x10000
95	add w0, w1, #65536
96	add w0, w1, w29
97	add w0, w1, w28, LSL #1
98	add w0, w1, w28, LSL #31
99	add w0, w1, w28, LSR #1
100	add w0, w1, w28, LSR #31
101	add w0, w1, w28, ASR #1
102	add w0, w1, w28, ASR #31
103	; ROR is reserved
104
105	adds x0, x0, #0x0
106	adds x0, x1, #0x10000
107	adds x0, x1, #65536
108	adds x0, x0, x0
109	adds x0, x1, x29
110	adds x0, x1, x28, LSL #1
111	adds x0, x1, x28, LSL #63
112	adds x0, x1, x28, LSR #1
113	adds x0, x1, x28, LSR #63
114	adds x0, x1, x28, ASR #1
115	adds x0, x1, x28, ASR #63
116	; ROR is reserved
117
118	adds w0, w1, #0x0
119	adds w0, w1, #0x10000
120	adds w0, w1, #65536
121	adds w0, w1, w29
122	adds w0, w1, w28, LSL #1
123	adds w0, w1, w28, LSL #31
124	adds w0, w1, w28, LSR #1
125	adds w0, w1, w28, LSR #31
126	adds w0, w1, w28, ASR #1
127	adds w0, w1, w28, ASR #31
128	; ROR is reserved
129
130	sub x0, x0, #0x0
131	sub x0, x1, #0x10000
132	sub x0, x1, #65536
133	sub x0, x0, x0
134	sub x0, x1, x29
135	sub x0, x1, x28, LSL #1
136	sub x0, x1, x28, LSL #63
137	sub x0, x1, x28, LSR #1
138	sub x0, x1, x28, LSR #63
139	sub x0, x1, x28, ASR #1
140	sub x0, x1, x28, ASR #63
141	; ROR is reserved
142
143	sub w0, w1, #0x0
144	sub w0, w1, #0x10000
145	sub w0, w1, #65536
146	sub w0, w1, w29
147	sub w0, w1, w28, LSL #1
148	sub w0, w1, w28, LSL #31
149	sub w0, w1, w28, LSR #1
150	sub w0, w1, w28, LSR #31
151	sub w0, w1, w28, ASR #1
152	sub w0, w1, w28, ASR #31
153	; ROR is reserved
154
155	subs x0, x0, #0x0
156	subs x0, x1, #0x10000
157	subs x0, x1, #65536
158	subs x0, x0, x0
159	subs x0, x1, x29
160	subs x0, x1, x28, LSL #1
161	subs x0, x1, x28, LSL #63
162	subs x0, x1, x28, LSR #1
163	subs x0, x1, x28, LSR #63
164	subs x0, x1, x28, ASR #1
165	subs x0, x1, x28, ASR #63
166	; ROR is reserved
167
168	subs w0, w1, #0x0
169	subs w0, w1, #0x10000
170	subs w0, w1, #65536
171	subs w0, w1, w29
172	subs w0, w1, w28, LSL #1
173	subs w0, w1, w28, LSL #31
174	subs w0, w1, w28, LSR #1
175	subs w0, w1, w28, LSR #31
176	subs w0, w1, w28, ASR #1
177	subs w0, w1, w28, ASR #31
178	; ROR is reserved
179
180	; Aliases of subs -> cmp
181	cmp x0, x1
182	cmp w0, w1
183	cmp x0, x1, LSL #1
184	cmp w0, w1, LSL #1
185
186	; Logical instructions
187	and x0, x0, #0xffff
188	and w0, wzr, #0xffff
189
190	ands x0, x0, #0x00ffff00
191	ands w10, w23, #0x55555555
192
193	orr x0, x0, #0xffff
194	orr w0, wzr, #0xffff
195
196	mov x0, x1 ; Alias of orr
197	mov w0, w1 ; Alias of orr
198
199	eor x0, x0, #0x00ffff00
200	eor w10, w23, #0x55555555
201
202	sbfm x0, x0, #0x1, #0x2
203	sbfm w0, w0, #0xf, #0x9
204	bfm x0, x0, #0x1, #0x2
205	bfm w0, w0, #0xf, #0x9
206	ubfm x0, x0, #0x1, #0x2
207	ubfm w0, w0, #0xf, #0x9
208
209	movn x0, #0xffff
210	movn x0, #0xffff, LSL #16
211	movn w0, #0xffff
212	movn w0, #0xffff, LSL #16
213
214	movz x0, #0xffff
215	movz x0, #0xffff, LSL #48
216	movz w0, #0xffff
217	movz w0, #0xffff, LSL #16
218
219	movk x0, #0xffff
220	movk x0, #0xffff, LSL #32
221	movk w0, #0xffff
222	movk w0, #0xffff, LSL #16
223
224	; Logical instructions with a shifted register
225	and w0, w0, w27
226	and w0, w1, w28, LSL #1
227	and w0, w1, w28, LSL #31
228	and w0, w1, w28, LSR #1
229	and w0, w1, w28, LSR #31
230	and w0, w1, w28, ASR #1
231	and w0, w1, w28, ASR #31
232	and w0, w1, w28, ROR #1
233	and w0, w1, w28, ROR #31
234
235	and x0, x0, x27
236	and x0, x1, x28, LSL #1
237	and x0, x1, x28, LSL #63
238	and x0, x1, x28, LSR #1
239	and x0, x1, x28, LSR #63
240	and x0, x1, x28, ASR #1
241	and x0, x1, x28, ASR #63
242	and x0, x1, x28, ROR #1
243	and x0, x1, x28, ROR #63
244
245	orr w0, w0, w27
246	orr w0, w1, w28, LSL #1
247	orr w0, w1, w28, LSL #31
248	orr w0, w1, w28, LSR #1
249	orr w0, w1, w28, LSR #31
250	orr w0, w1, w28, ASR #1
251	orr w0, w1, w28, ASR #31
252	orr w0, w1, w28, ROR #1
253	orr w0, w1, w28, ROR #31
254
255	orr x0, x0, x27
256	orr x0, x1, x28, LSL #1
257	orr x0, x1, x28, LSL #63
258	orr x0, x1, x28, LSR #1
259	orr x0, x1, x28, LSR #63
260	orr x0, x1, x28, ASR #1
261	orr x0, x1, x28, ASR #63
262	orr x0, x1, x28, ROR #1
263	orr x0, x1, x28, ROR #63
264
265	eor w0, w0, w27
266	eor w0, w1, w28, LSL #1
267	eor w0, w1, w28, LSL #31
268	eor w0, w1, w28, LSR #1
269	eor w0, w1, w28, LSR #31
270	eor w0, w1, w28, ASR #1
271	eor w0, w1, w28, ASR #31
272	eor w0, w1, w28, ROR #1
273	eor w0, w1, w28, ROR #31
274
275	eor x0, x0, x27
276	eor x0, x1, x28, LSL #1
277	eor x0, x1, x28, LSL #63
278	eor x0, x1, x28, LSR #1
279	eor x0, x1, x28, LSR #63
280	eor x0, x1, x28, ASR #1
281	eor x0, x1, x28, ASR #63
282	eor x0, x1, x28, ROR #1
283	eor x0, x1, x28, ROR #63
284
285	ands x0, x0, x27
286	ands x0, x1, x28, LSL #1
287	ands x0, x1, x28, LSL #63
288	ands x0, x1, x28, LSR #1
289	ands x0, x1, x28, LSR #63
290	ands x0, x1, x28, ASR #1
291	ands x0, x1, x28, ASR #63
292	ands x0, x1, x28, ROR #1
293	ands x0, x1, x28, ROR #63
294
295	bic w0, w0, w27
296	bic w0, w1, w28, LSL #1
297	bic w0, w1, w28, LSL #31
298	bic w0, w1, w28, LSR #1
299	bic w0, w1, w28, LSR #31
300	bic w0, w1, w28, ASR #1
301	bic w0, w1, w28, ASR #31
302	bic w0, w1, w28, ROR #1
303	bic w0, w1, w28, ROR #31
304
305	bic x0, x0, x27
306	bic x0, x1, x28, LSL #1
307	bic x0, x1, x28, LSL #63
308	bic x0, x1, x28, LSR #1
309	bic x0, x1, x28, LSR #63
310	bic x0, x1, x28, ASR #1
311	bic x0, x1, x28, ASR #63
312	bic x0, x1, x28, ROR #1
313	bic x0, x1, x28, ROR #63
314
315	orn w0, w0, w27
316	orn w0, w1, w28, LSL #1
317	orn w0, w1, w28, LSL #31
318	orn w0, w1, w28, LSR #1
319	orn w0, w1, w28, LSR #31
320	orn w0, w1, w28, ASR #1
321	orn w0, w1, w28, ASR #31
322	orn w0, w1, w28, ROR #1
323	orn w0, w1, w28, ROR #31
324
325	orn x0, x0, x27
326	orn x0, x1, x28, LSL #1
327	orn x0, x1, x28, LSL #63
328	orn x0, x1, x28, LSR #1
329	orn x0, x1, x28, LSR #63
330	orn x0, x1, x28, ASR #1
331	orn x0, x1, x28, ASR #63
332	orn x0, x1, x28, ROR #1
333	orn x0, x1, x28, ROR #63
334
335	eon w0, w0, w27
336	eon w0, w1, w28, LSL #1
337	eon w0, w1, w28, LSL #31
338	eon w0, w1, w28, LSR #1
339	eon w0, w1, w28, LSR #31
340	eon w0, w1, w28, ASR #1
341	eon w0, w1, w28, ASR #31
342	eon w0, w1, w28, ROR #1
343	eon w0, w1, w28, ROR #31
344
345	eon x0, x0, x27
346	eon x0, x1, x28, LSL #1
347	eon x0, x1, x28, LSL #63
348	eon x0, x1, x28, LSR #1
349	eon x0, x1, x28, LSR #63
350	eon x0, x1, x28, ASR #1
351	eon x0, x1, x28, ASR #63
352	eon x0, x1, x28, ROR #1
353	eon x0, x1, x28, ROR #63
354
355	bics w0, w0, w27
356	bics w0, w1, w28, LSL #1
357	bics w0, w1, w28, LSL #31
358	bics w0, w1, w28, LSR #1
359	bics w0, w1, w28, LSR #31
360	bics w0, w1, w28, ASR #1
361	bics w0, w1, w28, ASR #31
362	bics w0, w1, w28, ROR #1
363	bics w0, w1, w28, ROR #31
364
365	bics x0, x0, x27
366	bics x0, x1, x28, LSL #1
367	bics x0, x1, x28, LSL #63
368	bics x0, x1, x28, LSR #1
369	bics x0, x1, x28, LSR #63
370	bics x0, x1, x28, ASR #1
371	bics x0, x1, x28, ASR #63
372	bics x0, x1, x28, ROR #1
373	bics x0, x1, x28, ROR #63
374
375	; Memory loads
376	ldrb w0, [x28]
377	ldrb w0, [x28, #1]
378	ldrb w0, [x28, #4095]
379
380	ldrsb w0, [x28]
381	ldrsb w0, [x28, #1]
382	ldrsb w0, [x28, #4095]
383
384	ldrsb x0, [x28]
385	ldrsb x0, [x28, #1]
386	ldrsb x0, [x28, #4095]
387
388	ldrh w0, [x28]
389	ldrh w0, [x28, #2]
390	ldrh w0, [x28, #1024]
391
392	ldrsh w0, [x28]
393	ldrsh w0, [x28, #2]
394	ldrsh w0, [x28, #1024]
395
396	ldrsh x0, [x28]
397	ldrsh x0, [x28, #2]
398	ldrsh x0, [x28, #1024]
399
400	ldr x0, [x28]
401	ldr x0, [x28, #8]
402	ldr x0, [x28, #32760]
403
404	ldr w0, [x28]
405	ldr w0, [x28, #4]
406	ldr w0, [x28, #16380]
407
408	ldrsw x0, [x28]
409	ldrsw x0, [x28, #4]
410	ldrsw x0, [x28, #16380]
411
412	ldurb w0, [x28]
413	ldurb w0, [x28, #-256]
414	ldurb w0, [x28, #255]
415
416	ldursb w0, [x28]
417	ldursb w0, [x28, #-256]
418	ldursb w0, [x28, #255]
419
420	ldursb x0, [x28]
421	ldursb x0, [x28, #-256]
422	ldursb x0, [x28, #255]
423
424	ldurh w0, [x28]
425	ldurh w0, [x28, #-256]
426	ldurh w0, [x28, #255]
427
428	ldursh w0, [x28]
429	ldursh w0, [x28, #-256]
430	ldursh w0, [x28, #255]
431
432	ldursh x0, [x28]
433	ldursh x0, [x28, #-256]
434	ldursh x0, [x28, #255]
435
436	ldur x0, [x28]
437	ldur x0, [x28, #-256]
438	ldur x0, [x28, #255]
439
440	ldur w0, [x28]
441	ldur w0, [x28, #-256]
442	ldur w0, [x28, #255]
443
444	ldursw x0, [x28]
445	ldursw x0, [x28, #-256]
446	ldursw x0, [x28, #255]
447
448	ldp w0, w1, [x28]
449	ldp w0, w1, [x28, #4]
450	ldp w0, w1, [x28, #-256]
451	ldp w0, w1, [x28, #252]
452
453	ldp x0, x1, [x28]
454	ldp x0, x1, [x28, #8]
455	ldp x0, x1, [x28, #-512]
456	ldp x0, x1, [x28, #504]
457
458	ldr x0, [x1, x2]
459	ldr w0, [x1, x2]
460	ldr x0, [x1, x2, SXTX #0]
461	ldr x0, [x1, x2, LSL #3] ; UXTX
462	ldr x0, [x1, x2, SXTX #3]
463	ldr w0, [x1, w2, UXTW #0]
464	ldr w0, [x1, w2, SXTW #0]
465	ldr w0, [x1, w2, UXTW #2]
466	ldr w0, [x1, w2, SXTW #2]
467
468	ldrb w0, [x1, x2]
469	ldrb w0, [x1, x2, LSL #0] ; UXTX
470	ldrb w0, [x1, x2, SXTX #0]
471	ldrb w0, [x1, w2, UXTW #0]
472	ldrb w0, [x1, w2, SXTW #0]
473
474	ldrsb w0, [x1, x2]
475	ldrsb w0, [x1, x2, LSL #0] ; UXTX
476	ldrsb w0, [x1, x2, SXTX #0]
477	ldrsb w0, [x1, w2, UXTW #0]
478	ldrsb w0, [x1, w2, SXTW #0]
479
480	ldrh w0, [x1, x2]
481	;ldrh w0, [x1, x2, LSL #0] ; UXTX
482	ldrh w0, [x1, x2, SXTX #0]
483	ldrh w0, [x1, x2, LSL #1] ; UXTX
484	ldrh w0, [x1, x2, SXTX #1]
485	ldrh w0, [x1, w2, UXTW #0]
486	ldrh w0, [x1, w2, SXTW #0]
487	ldrh w0, [x1, w2, UXTW #1]
488	ldrh w0, [x1, w2, SXTW #1]
489
490	ldrsh w0, [x1, x2]
491	;ldrsh w0, [x1, x2, LSL #0] ; UXTX
492	ldrsh w0, [x1, x2, SXTX #0]
493	ldrsh w0, [x1, x2, LSL #1] ; UXTX
494	ldrsh w0, [x1, x2, SXTX #1]
495	ldrsh w0, [x1, w2, UXTW #0]
496	ldrsh w0, [x1, w2, SXTW #0]
497	ldrsh w0, [x1, w2, UXTW #1]
498	ldrsh w0, [x1, w2, SXTW #1]
499
500	ldrsw x0, [x1, x2]
501	;ldrsw x0, [x1, x2, LSL #0] ; UXTX
502	ldrsw x0, [x1, x2, SXTX #0]
503	ldrsw x0, [x1, x2, LSL #2] ; UXTX
504	ldrsw x0, [x1, x2, SXTX #2]
505	ldrsw x0, [x1, w2, UXTW #0]
506	ldrsw x0, [x1, w2, SXTW #0]
507	ldrsw x0, [x1, w2, UXTW #2]
508	ldrsw x0, [x1, w2, SXTW #2]
509
510	; Memory stores
511	strb w0, [x28]
512	strb w0, [x28, #1]
513	strb w0, [x28, #4095]
514
515	strh w0, [x28]
516	strh w0, [x28, #2]
517	strh w0, [x28, #1024]
518
519	str x0, [x28]
520	str x0, [x28, #8]
521	str x0, [x28, #32760]
522
523	str w0, [x28]
524	str w0, [x28, #4]
525	str w0, [x28, #16380]
526
527
528	sturb w0, [x28]
529	sturb w0, [x28, #-256]
530	sturb w0, [x28, #255]
531
532	sturh w0, [x28]
533	sturh w0, [x28, #-256]
534	sturh w0, [x28, #255]
535
536	stur x0, [x28]
537	stur x0, [x28, #-256]
538	stur x0, [x28, #255]
539
540	stur w0, [x28]
541	stur w0, [x28, #-256]
542	stur w0, [x28, #255]
543
544	stp w0, w1, [x28]
545	stp w0, w1, [x28, #4]
546	stp w0, w1, [x28, #-256]
547	stp w0, w1, [x28, #252]
548
549	stp x0, x1, [x28]
550	stp x0, x1, [x28, #8]
551	stp x0, x1, [x28, #-512]
552	stp x0, x1, [x28, #504]
553
554	str x0, [x1, x2]
555	str w0, [x1, x2]
556	str x0, [x1, x2, SXTX #0]
557	str x0, [x1, x2, LSL #3] ; UXTX
558	str x0, [x1, x2, SXTX #3]
559	str w0, [x1, w2, UXTW #0]
560	str w0, [x1, w2, SXTW #0]
561	str w0, [x1, w2, UXTW #2]
562	str w0, [x1, w2, SXTW #2]
563
564	strb w0, [x1, x2]
565	strb w0, [x1, x2, LSL #0x0]
566	strb w0, [x1, x2, SXTX #0x0]
567	strb w0, [x1, w2, UXTW #0x0]
568	strb w0, [x1, w2, SXTW #0x0]
569
570	strh w0, [x1, x2]
571	;strh w0, [x1, x2, LSL #0x0] ; UXTX
572	strh w0, [x1, x2, SXTX #0x0]
573	strh w0, [x1, x2, LSL #1] ; UXTX
574	strh w0, [x1, x2, SXTX #1]
575	strh w0, [x1, w2, UXTW #0x0]
576	strh w0, [x1, w2, SXTW #0x0]
577	strh w0, [x1, w2, UXTW #1]
578	strh w0, [x1, w2, SXTW #1]
579
580	; Conditional compare
581	ccmp x0, x1, #0x3, eq
582	ccmp w0, w1, #0xf, eq
583	ccmp x0, x1, #0x3, ne
584	ccmp w0, w1, #0xf, ne
585	ccmp x0, x1, #0x3, cs
586	ccmp w0, w1, #0xf, cc
587	ccmp x0, x1, #0x3, mi
588	ccmp w0, w1, #0xf, mi
589	ccmp x0, x1, #0x3, pl
590	ccmp w0, w1, #0xf, vs
591	ccmp x0, x1, #0x3, vc
592	ccmp w0, w1, #0xf, vc
593	ccmp x0, x1, #0x3, hi
594	ccmp w0, w1, #0xf, hi
595	ccmp x0, x1, #0x3, ls
596	ccmp w0, w1, #0xf, ls
597	ccmp x0, x1, #0x3, ge
598	ccmp w0, w1, #0xf, ge
599	ccmp x0, x1, #0x3, lt
600	ccmp w0, w1, #0xf, lt
601	ccmp x0, x1, #0x3, gt
602	ccmp w0, w1, #0xf, gt
603	ccmp x0, x1, #0x3, le
604	ccmp w0, w1, #0xf, le
605	ccmp x0, x1, #0x3, al
606	ccmp w0, w1, #0xf, al
607
608	ccmn x0, x1, #0x3, eq
609	ccmn w0, w1, #0xf, eq
610	ccmn x0, x1, #0x3, ne
611	ccmn w0, w1, #0xf, ne
612	ccmn x0, x1, #0x3, cs
613	ccmn w0, w1, #0xf, cc
614	ccmn x0, x1, #0x3, mi
615	ccmn w0, w1, #0xf, mi
616	ccmn x0, x1, #0x3, pl
617	ccmn w0, w1, #0xf, vs
618	ccmn x0, x1, #0x3, vc
619	ccmn w0, w1, #0xf, vc
620	ccmn x0, x1, #0x3, hi
621	ccmn w0, w1, #0xf, hi
622	ccmn x0, x1, #0x3, ls
623	ccmn w0, w1, #0xf, ls
624	ccmn x0, x1, #0x3, ge
625	ccmn w0, w1, #0xf, ge
626	ccmn x0, x1, #0x3, lt
627	ccmn w0, w1, #0xf, lt
628	ccmn x0, x1, #0x3, gt
629	ccmn w0, w1, #0xf, gt
630	ccmn x0, x1, #0x3, le
631	ccmn w0, w1, #0xf, le
632	ccmn x0, x1, #0x3, al
633	ccmn w0, w1, #0xf, al
634
635	;
636	; Keep last so the testcase can catch errors in
637	; the disassembly of the last instruction.
638	;
639	nop
640
641	.private_extern _TestProcA64_EndProc
642	_TestProcA64_EndProc:

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format