| 1 | /* $Id: tstDisasmArmv8-1-asm.S 106018 2024-09-12 07:14:22Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VBox disassembler - Tables for ARMv8 A64.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | .private_extern _TestProcA64
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| 29 | _TestProcA64:
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| 30 |
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| 31 | ; Miscellaneous instructions without a parameter
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| 32 | nop
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| 33 | yield
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| 34 | wfe
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| 35 | wfi
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| 36 | sev
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| 37 | sevl
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| 38 | dgh
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| 39 | xpaclri
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| 40 |
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| 41 | ; Control flow instructions
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| 42 | svc #0xfefe
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| 43 | hvc #0xdead
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| 44 | smc #0xcafe
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| 45 | brk #0xd0d0
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| 46 | hlt #0xc0de
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| 47 | ; tcancel #0xd00f Requires FEAT_TME
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| 48 | dcps1 #0xdeca
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| 49 | dcps2 #0xdec0
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| 50 | dcps3 #0xfeed
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| 51 | b #0x100
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| 52 | b #-0x100
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| 53 | bl #0x100
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| 54 | bl #-0x100
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| 55 | b.ne #+0x1000
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| 56 | b.eq #-0x1000
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| 57 | ; bc.ne #+0x1000 Requires FEAT_HBC
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| 58 | ; bc.eq #-0x1000 Requires FEAT_HBC
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| 59 | cbz x0, #+0x100
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| 60 | cbz x0, #-0x100
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| 61 | cbz w0, #+0x100
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| 62 | cbnz x0, #+0x100
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| 63 | cbnz x0, #-0x100
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| 64 | cbnz w0, #+0x100
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| 65 | tbz w0, #13, #+0x100
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| 66 | tbz x0, #63, #-0x100
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| 67 | tbz w0, #8, #+0x100
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| 68 | ret x30
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| 69 | ret x1
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| 70 | ret x2
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| 71 | ret x15
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| 72 | br x15
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| 73 | blr x15
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| 74 |
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| 75 | ; System register access instructions
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| 76 | msr ttbr0_el1, x0
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| 77 | mrs x0, ttbr0_el1
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| 78 |
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| 79 | ; Arithmetic instructions
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| 80 | add x0, x0, #0x0
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| 81 | add x0, x1, #0x10000
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| 82 | add x0, x1, #65536
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| 83 | add x0, x0, x0
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| 84 | add x0, x1, x29
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| 85 | add x0, x1, x28, LSL #1
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| 86 | add x0, x1, x28, LSL #63
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| 87 | add x0, x1, x28, LSR #1
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| 88 | add x0, x1, x28, LSR #63
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| 89 | add x0, x1, x28, ASR #1
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| 90 | add x0, x1, x28, ASR #63
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| 91 | ; ROR is reserved
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| 92 |
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| 93 | add w0, w1, #0x0
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| 94 | add w0, w1, #0x10000
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| 95 | add w0, w1, #65536
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| 96 | add w0, w1, w29
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| 97 | add w0, w1, w28, LSL #1
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| 98 | add w0, w1, w28, LSL #31
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| 99 | add w0, w1, w28, LSR #1
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| 100 | add w0, w1, w28, LSR #31
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| 101 | add w0, w1, w28, ASR #1
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| 102 | add w0, w1, w28, ASR #31
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| 103 | ; ROR is reserved
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| 104 |
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| 105 | adds x0, x0, #0x0
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| 106 | adds x0, x1, #0x10000
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| 107 | adds x0, x1, #65536
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| 108 | adds x0, x0, x0
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| 109 | adds x0, x1, x29
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| 110 | adds x0, x1, x28, LSL #1
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| 111 | adds x0, x1, x28, LSL #63
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| 112 | adds x0, x1, x28, LSR #1
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| 113 | adds x0, x1, x28, LSR #63
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| 114 | adds x0, x1, x28, ASR #1
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| 115 | adds x0, x1, x28, ASR #63
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| 116 | ; ROR is reserved
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| 117 |
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| 118 | adds w0, w1, #0x0
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| 119 | adds w0, w1, #0x10000
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| 120 | adds w0, w1, #65536
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| 121 | adds w0, w1, w29
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| 122 | adds w0, w1, w28, LSL #1
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| 123 | adds w0, w1, w28, LSL #31
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| 124 | adds w0, w1, w28, LSR #1
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| 125 | adds w0, w1, w28, LSR #31
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| 126 | adds w0, w1, w28, ASR #1
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| 127 | adds w0, w1, w28, ASR #31
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| 128 | ; ROR is reserved
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| 129 |
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| 130 | sub x0, x0, #0x0
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| 131 | sub x0, x1, #0x10000
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| 132 | sub x0, x1, #65536
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| 133 | sub x0, x0, x0
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| 134 | sub x0, x1, x29
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| 135 | sub x0, x1, x28, LSL #1
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| 136 | sub x0, x1, x28, LSL #63
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| 137 | sub x0, x1, x28, LSR #1
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| 138 | sub x0, x1, x28, LSR #63
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| 139 | sub x0, x1, x28, ASR #1
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| 140 | sub x0, x1, x28, ASR #63
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| 141 | ; ROR is reserved
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| 142 |
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| 143 | sub w0, w1, #0x0
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| 144 | sub w0, w1, #0x10000
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| 145 | sub w0, w1, #65536
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| 146 | sub w0, w1, w29
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| 147 | sub w0, w1, w28, LSL #1
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| 148 | sub w0, w1, w28, LSL #31
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| 149 | sub w0, w1, w28, LSR #1
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| 150 | sub w0, w1, w28, LSR #31
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| 151 | sub w0, w1, w28, ASR #1
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| 152 | sub w0, w1, w28, ASR #31
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| 153 | ; ROR is reserved
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| 154 |
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| 155 | subs x0, x0, #0x0
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| 156 | subs x0, x1, #0x10000
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| 157 | subs x0, x1, #65536
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| 158 | subs x0, x0, x0
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| 159 | subs x0, x1, x29
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| 160 | subs x0, x1, x28, LSL #1
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| 161 | subs x0, x1, x28, LSL #63
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| 162 | subs x0, x1, x28, LSR #1
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| 163 | subs x0, x1, x28, LSR #63
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| 164 | subs x0, x1, x28, ASR #1
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| 165 | subs x0, x1, x28, ASR #63
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| 166 | ; ROR is reserved
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| 167 |
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| 168 | subs w0, w1, #0x0
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| 169 | subs w0, w1, #0x10000
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| 170 | subs w0, w1, #65536
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| 171 | subs w0, w1, w29
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| 172 | subs w0, w1, w28, LSL #1
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| 173 | subs w0, w1, w28, LSL #31
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| 174 | subs w0, w1, w28, LSR #1
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| 175 | subs w0, w1, w28, LSR #31
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| 176 | subs w0, w1, w28, ASR #1
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| 177 | subs w0, w1, w28, ASR #31
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| 178 | ; ROR is reserved
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| 179 |
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| 180 | ; Aliases of subs -> cmp
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| 181 | cmp x0, x1
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| 182 | cmp w0, w1
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| 183 | cmp x0, x1, LSL #1
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| 184 | cmp w0, w1, LSL #1
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| 185 |
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| 186 | ; Logical instructions
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| 187 | and x0, x0, #0xffff
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| 188 | and w0, wzr, #0xffff
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| 189 |
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| 190 | ands x0, x0, #0x00ffff00
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| 191 | ands w10, w23, #0x55555555
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| 192 |
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| 193 | orr x0, x0, #0xffff
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| 194 | orr w0, wzr, #0xffff
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| 195 |
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| 196 | mov x0, x1 ; Alias of orr
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| 197 | mov w0, w1 ; Alias of orr
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| 198 |
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| 199 | eor x0, x0, #0x00ffff00
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| 200 | eor w10, w23, #0x55555555
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| 201 |
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| 202 | sbfm x0, x0, #0x1, #0x2
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| 203 | sbfm w0, w0, #0xf, #0x9
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| 204 | bfm x0, x0, #0x1, #0x2
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| 205 | bfm w0, w0, #0xf, #0x9
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| 206 | ubfm x0, x0, #0x1, #0x2
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| 207 | ubfm w0, w0, #0xf, #0x9
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| 208 |
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| 209 | movn x0, #0xffff
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| 210 | movn x0, #0xffff, LSL #16
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| 211 | movn w0, #0xffff
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| 212 | movn w0, #0xffff, LSL #16
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| 213 |
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| 214 | movz x0, #0xffff
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| 215 | movz x0, #0xffff, LSL #48
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| 216 | movz w0, #0xffff
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| 217 | movz w0, #0xffff, LSL #16
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| 218 |
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| 219 | movk x0, #0xffff
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| 220 | movk x0, #0xffff, LSL #32
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| 221 | movk w0, #0xffff
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| 222 | movk w0, #0xffff, LSL #16
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| 223 |
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| 224 | ; Logical instructions with a shifted register
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| 225 | and w0, w0, w27
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| 226 | and w0, w1, w28, LSL #1
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| 227 | and w0, w1, w28, LSL #31
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| 228 | and w0, w1, w28, LSR #1
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| 229 | and w0, w1, w28, LSR #31
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| 230 | and w0, w1, w28, ASR #1
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| 231 | and w0, w1, w28, ASR #31
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| 232 | and w0, w1, w28, ROR #1
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| 233 | and w0, w1, w28, ROR #31
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| 234 |
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| 235 | and x0, x0, x27
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| 236 | and x0, x1, x28, LSL #1
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| 237 | and x0, x1, x28, LSL #63
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| 238 | and x0, x1, x28, LSR #1
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| 239 | and x0, x1, x28, LSR #63
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| 240 | and x0, x1, x28, ASR #1
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| 241 | and x0, x1, x28, ASR #63
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| 242 | and x0, x1, x28, ROR #1
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| 243 | and x0, x1, x28, ROR #63
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| 244 |
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| 245 | orr w0, w0, w27
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| 246 | orr w0, w1, w28, LSL #1
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| 247 | orr w0, w1, w28, LSL #31
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| 248 | orr w0, w1, w28, LSR #1
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| 249 | orr w0, w1, w28, LSR #31
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| 250 | orr w0, w1, w28, ASR #1
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| 251 | orr w0, w1, w28, ASR #31
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| 252 | orr w0, w1, w28, ROR #1
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| 253 | orr w0, w1, w28, ROR #31
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| 254 |
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| 255 | orr x0, x0, x27
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| 256 | orr x0, x1, x28, LSL #1
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| 257 | orr x0, x1, x28, LSL #63
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| 258 | orr x0, x1, x28, LSR #1
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| 259 | orr x0, x1, x28, LSR #63
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| 260 | orr x0, x1, x28, ASR #1
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| 261 | orr x0, x1, x28, ASR #63
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| 262 | orr x0, x1, x28, ROR #1
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| 263 | orr x0, x1, x28, ROR #63
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| 264 |
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| 265 | eor w0, w0, w27
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| 266 | eor w0, w1, w28, LSL #1
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| 267 | eor w0, w1, w28, LSL #31
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| 268 | eor w0, w1, w28, LSR #1
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| 269 | eor w0, w1, w28, LSR #31
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| 270 | eor w0, w1, w28, ASR #1
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| 271 | eor w0, w1, w28, ASR #31
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| 272 | eor w0, w1, w28, ROR #1
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| 273 | eor w0, w1, w28, ROR #31
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| 274 |
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| 275 | eor x0, x0, x27
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| 276 | eor x0, x1, x28, LSL #1
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| 277 | eor x0, x1, x28, LSL #63
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| 278 | eor x0, x1, x28, LSR #1
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| 279 | eor x0, x1, x28, LSR #63
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| 280 | eor x0, x1, x28, ASR #1
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| 281 | eor x0, x1, x28, ASR #63
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| 282 | eor x0, x1, x28, ROR #1
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| 283 | eor x0, x1, x28, ROR #63
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| 284 |
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| 285 | ands x0, x0, x27
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| 286 | ands x0, x1, x28, LSL #1
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| 287 | ands x0, x1, x28, LSL #63
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| 288 | ands x0, x1, x28, LSR #1
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| 289 | ands x0, x1, x28, LSR #63
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| 290 | ands x0, x1, x28, ASR #1
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| 291 | ands x0, x1, x28, ASR #63
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| 292 | ands x0, x1, x28, ROR #1
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| 293 | ands x0, x1, x28, ROR #63
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| 294 |
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| 295 | bic w0, w0, w27
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| 296 | bic w0, w1, w28, LSL #1
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| 297 | bic w0, w1, w28, LSL #31
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| 298 | bic w0, w1, w28, LSR #1
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| 299 | bic w0, w1, w28, LSR #31
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| 300 | bic w0, w1, w28, ASR #1
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| 301 | bic w0, w1, w28, ASR #31
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| 302 | bic w0, w1, w28, ROR #1
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| 303 | bic w0, w1, w28, ROR #31
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| 304 |
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| 305 | bic x0, x0, x27
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| 306 | bic x0, x1, x28, LSL #1
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| 307 | bic x0, x1, x28, LSL #63
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| 308 | bic x0, x1, x28, LSR #1
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| 309 | bic x0, x1, x28, LSR #63
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| 310 | bic x0, x1, x28, ASR #1
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| 311 | bic x0, x1, x28, ASR #63
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| 312 | bic x0, x1, x28, ROR #1
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| 313 | bic x0, x1, x28, ROR #63
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| 314 |
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| 315 | orn w0, w0, w27
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| 316 | orn w0, w1, w28, LSL #1
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| 317 | orn w0, w1, w28, LSL #31
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| 318 | orn w0, w1, w28, LSR #1
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| 319 | orn w0, w1, w28, LSR #31
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| 320 | orn w0, w1, w28, ASR #1
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| 321 | orn w0, w1, w28, ASR #31
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| 322 | orn w0, w1, w28, ROR #1
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| 323 | orn w0, w1, w28, ROR #31
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| 324 |
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| 325 | orn x0, x0, x27
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| 326 | orn x0, x1, x28, LSL #1
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| 327 | orn x0, x1, x28, LSL #63
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| 328 | orn x0, x1, x28, LSR #1
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| 329 | orn x0, x1, x28, LSR #63
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| 330 | orn x0, x1, x28, ASR #1
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| 331 | orn x0, x1, x28, ASR #63
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| 332 | orn x0, x1, x28, ROR #1
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| 333 | orn x0, x1, x28, ROR #63
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| 334 |
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| 335 | eon w0, w0, w27
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| 336 | eon w0, w1, w28, LSL #1
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| 337 | eon w0, w1, w28, LSL #31
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| 338 | eon w0, w1, w28, LSR #1
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| 339 | eon w0, w1, w28, LSR #31
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| 340 | eon w0, w1, w28, ASR #1
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| 341 | eon w0, w1, w28, ASR #31
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| 342 | eon w0, w1, w28, ROR #1
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| 343 | eon w0, w1, w28, ROR #31
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| 344 |
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| 345 | eon x0, x0, x27
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| 346 | eon x0, x1, x28, LSL #1
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| 347 | eon x0, x1, x28, LSL #63
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| 348 | eon x0, x1, x28, LSR #1
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| 349 | eon x0, x1, x28, LSR #63
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| 350 | eon x0, x1, x28, ASR #1
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| 351 | eon x0, x1, x28, ASR #63
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| 352 | eon x0, x1, x28, ROR #1
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| 353 | eon x0, x1, x28, ROR #63
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| 354 |
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| 355 | bics w0, w0, w27
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| 356 | bics w0, w1, w28, LSL #1
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| 357 | bics w0, w1, w28, LSL #31
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| 358 | bics w0, w1, w28, LSR #1
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| 359 | bics w0, w1, w28, LSR #31
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| 360 | bics w0, w1, w28, ASR #1
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| 361 | bics w0, w1, w28, ASR #31
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| 362 | bics w0, w1, w28, ROR #1
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| 363 | bics w0, w1, w28, ROR #31
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| 364 |
|
|---|
| 365 | bics x0, x0, x27
|
|---|
| 366 | bics x0, x1, x28, LSL #1
|
|---|
| 367 | bics x0, x1, x28, LSL #63
|
|---|
| 368 | bics x0, x1, x28, LSR #1
|
|---|
| 369 | bics x0, x1, x28, LSR #63
|
|---|
| 370 | bics x0, x1, x28, ASR #1
|
|---|
| 371 | bics x0, x1, x28, ASR #63
|
|---|
| 372 | bics x0, x1, x28, ROR #1
|
|---|
| 373 | bics x0, x1, x28, ROR #63
|
|---|
| 374 |
|
|---|
| 375 | ; Memory loads
|
|---|
| 376 | ldrb w0, [x28]
|
|---|
| 377 | ldrb w0, [x28, #1]
|
|---|
| 378 | ldrb w0, [x28, #4095]
|
|---|
| 379 |
|
|---|
| 380 | ldrsb w0, [x28]
|
|---|
| 381 | ldrsb w0, [x28, #1]
|
|---|
| 382 | ldrsb w0, [x28, #4095]
|
|---|
| 383 |
|
|---|
| 384 | ldrsb x0, [x28]
|
|---|
| 385 | ldrsb x0, [x28, #1]
|
|---|
| 386 | ldrsb x0, [x28, #4095]
|
|---|
| 387 |
|
|---|
| 388 | ldrh w0, [x28]
|
|---|
| 389 | ldrh w0, [x28, #2]
|
|---|
| 390 | ldrh w0, [x28, #1024]
|
|---|
| 391 |
|
|---|
| 392 | ldrsh w0, [x28]
|
|---|
| 393 | ldrsh w0, [x28, #2]
|
|---|
| 394 | ldrsh w0, [x28, #1024]
|
|---|
| 395 |
|
|---|
| 396 | ldrsh x0, [x28]
|
|---|
| 397 | ldrsh x0, [x28, #2]
|
|---|
| 398 | ldrsh x0, [x28, #1024]
|
|---|
| 399 |
|
|---|
| 400 | ldr x0, [x28]
|
|---|
| 401 | ldr x0, [x28, #8]
|
|---|
| 402 | ldr x0, [x28, #32760]
|
|---|
| 403 |
|
|---|
| 404 | ldr w0, [x28]
|
|---|
| 405 | ldr w0, [x28, #4]
|
|---|
| 406 | ldr w0, [x28, #16380]
|
|---|
| 407 |
|
|---|
| 408 | ldrsw x0, [x28]
|
|---|
| 409 | ldrsw x0, [x28, #4]
|
|---|
| 410 | ldrsw x0, [x28, #16380]
|
|---|
| 411 |
|
|---|
| 412 | ldurb w0, [x28]
|
|---|
| 413 | ldurb w0, [x28, #-256]
|
|---|
| 414 | ldurb w0, [x28, #255]
|
|---|
| 415 |
|
|---|
| 416 | ldursb w0, [x28]
|
|---|
| 417 | ldursb w0, [x28, #-256]
|
|---|
| 418 | ldursb w0, [x28, #255]
|
|---|
| 419 |
|
|---|
| 420 | ldursb x0, [x28]
|
|---|
| 421 | ldursb x0, [x28, #-256]
|
|---|
| 422 | ldursb x0, [x28, #255]
|
|---|
| 423 |
|
|---|
| 424 | ldurh w0, [x28]
|
|---|
| 425 | ldurh w0, [x28, #-256]
|
|---|
| 426 | ldurh w0, [x28, #255]
|
|---|
| 427 |
|
|---|
| 428 | ldursh w0, [x28]
|
|---|
| 429 | ldursh w0, [x28, #-256]
|
|---|
| 430 | ldursh w0, [x28, #255]
|
|---|
| 431 |
|
|---|
| 432 | ldursh x0, [x28]
|
|---|
| 433 | ldursh x0, [x28, #-256]
|
|---|
| 434 | ldursh x0, [x28, #255]
|
|---|
| 435 |
|
|---|
| 436 | ldur x0, [x28]
|
|---|
| 437 | ldur x0, [x28, #-256]
|
|---|
| 438 | ldur x0, [x28, #255]
|
|---|
| 439 |
|
|---|
| 440 | ldur w0, [x28]
|
|---|
| 441 | ldur w0, [x28, #-256]
|
|---|
| 442 | ldur w0, [x28, #255]
|
|---|
| 443 |
|
|---|
| 444 | ldursw x0, [x28]
|
|---|
| 445 | ldursw x0, [x28, #-256]
|
|---|
| 446 | ldursw x0, [x28, #255]
|
|---|
| 447 |
|
|---|
| 448 | ldp w0, w1, [x28]
|
|---|
| 449 | ldp w0, w1, [x28, #4]
|
|---|
| 450 | ldp w0, w1, [x28, #-256]
|
|---|
| 451 | ldp w0, w1, [x28, #252]
|
|---|
| 452 |
|
|---|
| 453 | ldp x0, x1, [x28]
|
|---|
| 454 | ldp x0, x1, [x28, #8]
|
|---|
| 455 | ldp x0, x1, [x28, #-512]
|
|---|
| 456 | ldp x0, x1, [x28, #504]
|
|---|
| 457 |
|
|---|
| 458 | ldp w0, w1, [x28, #4]!
|
|---|
| 459 | ldp w0, w1, [x28, #-256]!
|
|---|
| 460 | ldp w0, w1, [x28, #252]!
|
|---|
| 461 |
|
|---|
| 462 | ldp x0, x1, [x28, #8]!
|
|---|
| 463 | ldp x0, x1, [x28, #-512]!
|
|---|
| 464 | ldp x0, x1, [x28, #504]!
|
|---|
| 465 |
|
|---|
| 466 | ldp w0, w1, [x28], #4
|
|---|
| 467 | ldp w0, w1, [x28], #-256
|
|---|
| 468 | ldp w0, w1, [x28], #252
|
|---|
| 469 |
|
|---|
| 470 | ldp x0, x1, [x28], #8
|
|---|
| 471 | ldp x0, x1, [x28], #-512
|
|---|
| 472 | ldp x0, x1, [x28], #504
|
|---|
| 473 |
|
|---|
| 474 | ldr x0, [x1, x2]
|
|---|
| 475 | ldr w0, [x1, x2]
|
|---|
| 476 | ldr x0, [x1, x2, SXTX #0]
|
|---|
| 477 | ldr x0, [x1, x2, LSL #3] ; UXTX
|
|---|
| 478 | ldr x0, [x1, x2, SXTX #3]
|
|---|
| 479 | ldr w0, [x1, w2, UXTW #0]
|
|---|
| 480 | ldr w0, [x1, w2, SXTW #0]
|
|---|
| 481 | ldr w0, [x1, w2, UXTW #2]
|
|---|
| 482 | ldr w0, [x1, w2, SXTW #2]
|
|---|
| 483 |
|
|---|
| 484 | ldrb w0, [x1, x2]
|
|---|
| 485 | ldrb w0, [x1, x2, LSL #0] ; UXTX
|
|---|
| 486 | ldrb w0, [x1, x2, SXTX #0]
|
|---|
| 487 | ldrb w0, [x1, w2, UXTW #0]
|
|---|
| 488 | ldrb w0, [x1, w2, SXTW #0]
|
|---|
| 489 |
|
|---|
| 490 | ldrsb w0, [x1, x2]
|
|---|
| 491 | ldrsb w0, [x1, x2, LSL #0] ; UXTX
|
|---|
| 492 | ldrsb w0, [x1, x2, SXTX #0]
|
|---|
| 493 | ldrsb w0, [x1, w2, UXTW #0]
|
|---|
| 494 | ldrsb w0, [x1, w2, SXTW #0]
|
|---|
| 495 |
|
|---|
| 496 | ldrh w0, [x1, x2]
|
|---|
| 497 | ;ldrh w0, [x1, x2, LSL #0] ; UXTX
|
|---|
| 498 | ldrh w0, [x1, x2, SXTX #0]
|
|---|
| 499 | ldrh w0, [x1, x2, LSL #1] ; UXTX
|
|---|
| 500 | ldrh w0, [x1, x2, SXTX #1]
|
|---|
| 501 | ldrh w0, [x1, w2, UXTW #0]
|
|---|
| 502 | ldrh w0, [x1, w2, SXTW #0]
|
|---|
| 503 | ldrh w0, [x1, w2, UXTW #1]
|
|---|
| 504 | ldrh w0, [x1, w2, SXTW #1]
|
|---|
| 505 |
|
|---|
| 506 | ldrsh w0, [x1, x2]
|
|---|
| 507 | ;ldrsh w0, [x1, x2, LSL #0] ; UXTX
|
|---|
| 508 | ldrsh w0, [x1, x2, SXTX #0]
|
|---|
| 509 | ldrsh w0, [x1, x2, LSL #1] ; UXTX
|
|---|
| 510 | ldrsh w0, [x1, x2, SXTX #1]
|
|---|
| 511 | ldrsh w0, [x1, w2, UXTW #0]
|
|---|
| 512 | ldrsh w0, [x1, w2, SXTW #0]
|
|---|
| 513 | ldrsh w0, [x1, w2, UXTW #1]
|
|---|
| 514 | ldrsh w0, [x1, w2, SXTW #1]
|
|---|
| 515 |
|
|---|
| 516 | ldrsw x0, [x1, x2]
|
|---|
| 517 | ;ldrsw x0, [x1, x2, LSL #0] ; UXTX
|
|---|
| 518 | ldrsw x0, [x1, x2, SXTX #0]
|
|---|
| 519 | ldrsw x0, [x1, x2, LSL #2] ; UXTX
|
|---|
| 520 | ldrsw x0, [x1, x2, SXTX #2]
|
|---|
| 521 | ldrsw x0, [x1, w2, UXTW #0]
|
|---|
| 522 | ldrsw x0, [x1, w2, SXTW #0]
|
|---|
| 523 | ldrsw x0, [x1, w2, UXTW #2]
|
|---|
| 524 | ldrsw x0, [x1, w2, SXTW #2]
|
|---|
| 525 |
|
|---|
| 526 | ; Memory stores
|
|---|
| 527 | strb w0, [x28]
|
|---|
| 528 | strb w0, [x28, #1]
|
|---|
| 529 | strb w0, [x28, #4095]
|
|---|
| 530 |
|
|---|
| 531 | strh w0, [x28]
|
|---|
| 532 | strh w0, [x28, #2]
|
|---|
| 533 | strh w0, [x28, #1024]
|
|---|
| 534 |
|
|---|
| 535 | str x0, [x28]
|
|---|
| 536 | str x0, [x28, #8]
|
|---|
| 537 | str x0, [x28, #32760]
|
|---|
| 538 |
|
|---|
| 539 | str w0, [x28]
|
|---|
| 540 | str w0, [x28, #4]
|
|---|
| 541 | str w0, [x28, #16380]
|
|---|
| 542 |
|
|---|
| 543 |
|
|---|
| 544 | sturb w0, [x28]
|
|---|
| 545 | sturb w0, [x28, #-256]
|
|---|
| 546 | sturb w0, [x28, #255]
|
|---|
| 547 |
|
|---|
| 548 | sturh w0, [x28]
|
|---|
| 549 | sturh w0, [x28, #-256]
|
|---|
| 550 | sturh w0, [x28, #255]
|
|---|
| 551 |
|
|---|
| 552 | stur x0, [x28]
|
|---|
| 553 | stur x0, [x28, #-256]
|
|---|
| 554 | stur x0, [x28, #255]
|
|---|
| 555 |
|
|---|
| 556 | stur w0, [x28]
|
|---|
| 557 | stur w0, [x28, #-256]
|
|---|
| 558 | stur w0, [x28, #255]
|
|---|
| 559 |
|
|---|
| 560 | stp w0, w1, [x28]
|
|---|
| 561 | stp w0, w1, [x28, #4]
|
|---|
| 562 | stp w0, w1, [x28, #-256]
|
|---|
| 563 | stp w0, w1, [x28, #252]
|
|---|
| 564 |
|
|---|
| 565 | stp x0, x1, [x28]
|
|---|
| 566 | stp x0, x1, [x28, #8]
|
|---|
| 567 | stp x0, x1, [x28, #-512]
|
|---|
| 568 | stp x0, x1, [x28, #504]
|
|---|
| 569 |
|
|---|
| 570 | stp w0, w1, [x28, #4]!
|
|---|
| 571 | stp w0, w1, [x28, #-256]!
|
|---|
| 572 | stp w0, w1, [x28, #252]!
|
|---|
| 573 |
|
|---|
| 574 | stp x0, x1, [x28, #8]!
|
|---|
| 575 | stp x0, x1, [x28, #-512]!
|
|---|
| 576 | stp x0, x1, [x28, #504]!
|
|---|
| 577 |
|
|---|
| 578 | stp w0, w1, [x28], #4
|
|---|
| 579 | stp w0, w1, [x28], #-256
|
|---|
| 580 | stp w0, w1, [x28], #252
|
|---|
| 581 |
|
|---|
| 582 | stp x0, x1, [x28], #8
|
|---|
| 583 | stp x0, x1, [x28], #-512
|
|---|
| 584 | stp x0, x1, [x28], #504
|
|---|
| 585 |
|
|---|
| 586 | str x0, [x1, x2]
|
|---|
| 587 | str w0, [x1, x2]
|
|---|
| 588 | str x0, [x1, x2, SXTX #0]
|
|---|
| 589 | str x0, [x1, x2, LSL #3] ; UXTX
|
|---|
| 590 | str x0, [x1, x2, SXTX #3]
|
|---|
| 591 | str w0, [x1, w2, UXTW #0]
|
|---|
| 592 | str w0, [x1, w2, SXTW #0]
|
|---|
| 593 | str w0, [x1, w2, UXTW #2]
|
|---|
| 594 | str w0, [x1, w2, SXTW #2]
|
|---|
| 595 |
|
|---|
| 596 | strb w0, [x1, x2]
|
|---|
| 597 | strb w0, [x1, x2, LSL #0x0]
|
|---|
| 598 | strb w0, [x1, x2, SXTX #0x0]
|
|---|
| 599 | strb w0, [x1, w2, UXTW #0x0]
|
|---|
| 600 | strb w0, [x1, w2, SXTW #0x0]
|
|---|
| 601 |
|
|---|
| 602 | strh w0, [x1, x2]
|
|---|
| 603 | ;strh w0, [x1, x2, LSL #0x0] ; UXTX
|
|---|
| 604 | strh w0, [x1, x2, SXTX #0x0]
|
|---|
| 605 | strh w0, [x1, x2, LSL #1] ; UXTX
|
|---|
| 606 | strh w0, [x1, x2, SXTX #1]
|
|---|
| 607 | strh w0, [x1, w2, UXTW #0x0]
|
|---|
| 608 | strh w0, [x1, w2, SXTW #0x0]
|
|---|
| 609 | strh w0, [x1, w2, UXTW #1]
|
|---|
| 610 | strh w0, [x1, w2, SXTW #1]
|
|---|
| 611 |
|
|---|
| 612 | ; Conditional compare
|
|---|
| 613 | ccmp x0, x1, #0x3, eq
|
|---|
| 614 | ccmp w0, w1, #0xf, eq
|
|---|
| 615 | ccmp x0, x1, #0x3, ne
|
|---|
| 616 | ccmp w0, w1, #0xf, ne
|
|---|
| 617 | ccmp x0, x1, #0x3, cs
|
|---|
| 618 | ccmp w0, w1, #0xf, cc
|
|---|
| 619 | ccmp x0, x1, #0x3, mi
|
|---|
| 620 | ccmp w0, w1, #0xf, mi
|
|---|
| 621 | ccmp x0, x1, #0x3, pl
|
|---|
| 622 | ccmp w0, w1, #0xf, vs
|
|---|
| 623 | ccmp x0, x1, #0x3, vc
|
|---|
| 624 | ccmp w0, w1, #0xf, vc
|
|---|
| 625 | ccmp x0, x1, #0x3, hi
|
|---|
| 626 | ccmp w0, w1, #0xf, hi
|
|---|
| 627 | ccmp x0, x1, #0x3, ls
|
|---|
| 628 | ccmp w0, w1, #0xf, ls
|
|---|
| 629 | ccmp x0, x1, #0x3, ge
|
|---|
| 630 | ccmp w0, w1, #0xf, ge
|
|---|
| 631 | ccmp x0, x1, #0x3, lt
|
|---|
| 632 | ccmp w0, w1, #0xf, lt
|
|---|
| 633 | ccmp x0, x1, #0x3, gt
|
|---|
| 634 | ccmp w0, w1, #0xf, gt
|
|---|
| 635 | ccmp x0, x1, #0x3, le
|
|---|
| 636 | ccmp w0, w1, #0xf, le
|
|---|
| 637 | ccmp x0, x1, #0x3, al
|
|---|
| 638 | ccmp w0, w1, #0xf, al
|
|---|
| 639 |
|
|---|
| 640 | ccmn x0, x1, #0x3, eq
|
|---|
| 641 | ccmn w0, w1, #0xf, eq
|
|---|
| 642 | ccmn x0, x1, #0x3, ne
|
|---|
| 643 | ccmn w0, w1, #0xf, ne
|
|---|
| 644 | ccmn x0, x1, #0x3, cs
|
|---|
| 645 | ccmn w0, w1, #0xf, cc
|
|---|
| 646 | ccmn x0, x1, #0x3, mi
|
|---|
| 647 | ccmn w0, w1, #0xf, mi
|
|---|
| 648 | ccmn x0, x1, #0x3, pl
|
|---|
| 649 | ccmn w0, w1, #0xf, vs
|
|---|
| 650 | ccmn x0, x1, #0x3, vc
|
|---|
| 651 | ccmn w0, w1, #0xf, vc
|
|---|
| 652 | ccmn x0, x1, #0x3, hi
|
|---|
| 653 | ccmn w0, w1, #0xf, hi
|
|---|
| 654 | ccmn x0, x1, #0x3, ls
|
|---|
| 655 | ccmn w0, w1, #0xf, ls
|
|---|
| 656 | ccmn x0, x1, #0x3, ge
|
|---|
| 657 | ccmn w0, w1, #0xf, ge
|
|---|
| 658 | ccmn x0, x1, #0x3, lt
|
|---|
| 659 | ccmn w0, w1, #0xf, lt
|
|---|
| 660 | ccmn x0, x1, #0x3, gt
|
|---|
| 661 | ccmn w0, w1, #0xf, gt
|
|---|
| 662 | ccmn x0, x1, #0x3, le
|
|---|
| 663 | ccmn w0, w1, #0xf, le
|
|---|
| 664 | ccmn x0, x1, #0x3, al
|
|---|
| 665 | ccmn w0, w1, #0xf, al
|
|---|
| 666 |
|
|---|
| 667 | msr spsel, #1
|
|---|
| 668 | msr spsel, #0
|
|---|
| 669 | msr daifset, #0
|
|---|
| 670 | msr daifset, #15
|
|---|
| 671 | msr daifclr, #0
|
|---|
| 672 | msr daifclr, #15
|
|---|
| 673 | msr uao, #1
|
|---|
| 674 | msr uao, #0
|
|---|
| 675 | msr pan, #1
|
|---|
| 676 | msr pan, #0
|
|---|
| 677 | ; msr allint, #1 Not supported by the toolchain
|
|---|
| 678 | ; msr allint, #0 Not supported by the toolchain
|
|---|
| 679 | ;msr pm, #1 Not supported by the maca1 toolchain
|
|---|
| 680 | ;msr pm, #0 Not supported by the maca1 toolchain
|
|---|
| 681 | msr ssbs, #1
|
|---|
| 682 | msr ssbs, #0
|
|---|
| 683 | msr dit, #1
|
|---|
| 684 | msr dit, #0
|
|---|
| 685 | ; msr tco, #1 Not supported by the toolchain
|
|---|
| 686 | ; msr tco, #0 Not supported by the toolchain
|
|---|
| 687 | ; msr svcrsm, #1 Not supported by the toolchain
|
|---|
| 688 | ; msr svcrsm, #0 Not supported by the toolchain
|
|---|
| 689 | ; msr svcrza, #1 Not supported by the toolchain
|
|---|
| 690 | ; msr svcrza, #0 Not supported by the toolchain
|
|---|
| 691 | ; msr svcrsma, #1 Not supported by the toolchain
|
|---|
| 692 | ; msr svcrsma, #0 Not supported by the toolchain
|
|---|
| 693 |
|
|---|
| 694 | ; Floating Point instructions.
|
|---|
| 695 | fmadd s0, s1, s3, s31
|
|---|
| 696 | fmadd d0, d1, d3, d31
|
|---|
| 697 | fmadd h0, h1, h3, h31
|
|---|
| 698 |
|
|---|
| 699 | fmsub s0, s1, s3, s31
|
|---|
| 700 | fmsub d0, d1, d3, d31
|
|---|
| 701 | fmsub h0, h1, h3, h31
|
|---|
| 702 |
|
|---|
| 703 | fnmadd s0, s1, s3, s31
|
|---|
| 704 | fnmadd d0, d1, d3, d31
|
|---|
| 705 | fnmadd h0, h1, h3, h31
|
|---|
| 706 |
|
|---|
| 707 | fnmsub s0, s1, s3, s31
|
|---|
| 708 | fnmsub d0, d1, d3, d31
|
|---|
| 709 | fnmsub h0, h1, h3, h31
|
|---|
| 710 |
|
|---|
| 711 | fcvtzu x0, s0, #1
|
|---|
| 712 | fcvtzu x0, s0, #31
|
|---|
| 713 | fcvtzu x0, s0, #63
|
|---|
| 714 | fcvtzu w0, s0, #1
|
|---|
| 715 | fcvtzu w0, s0, #32
|
|---|
| 716 |
|
|---|
| 717 | fcvtzu x0, d0, #1
|
|---|
| 718 | fcvtzu x0, d0, #31
|
|---|
| 719 | fcvtzu x0, d0, #63
|
|---|
| 720 | fcvtzu w0, d0, #1
|
|---|
| 721 | fcvtzu w0, d0, #32
|
|---|
| 722 |
|
|---|
| 723 | fcvtzu x0, h0, #1
|
|---|
| 724 | fcvtzu x0, h0, #31
|
|---|
| 725 | fcvtzu x0, h0, #63
|
|---|
| 726 | fcvtzu w0, h0, #1
|
|---|
| 727 | fcvtzu w0, h0, #32
|
|---|
| 728 |
|
|---|
| 729 | fcvtzs x0, s0, #1
|
|---|
| 730 | fcvtzs x0, s0, #31
|
|---|
| 731 | fcvtzs x0, s0, #63
|
|---|
| 732 | fcvtzs w0, s0, #1
|
|---|
| 733 | fcvtzs w0, s0, #32
|
|---|
| 734 |
|
|---|
| 735 | fcvtzs x0, d0, #1
|
|---|
| 736 | fcvtzs x0, d0, #31
|
|---|
| 737 | fcvtzs x0, d0, #63
|
|---|
| 738 | fcvtzs w0, d0, #1
|
|---|
| 739 | fcvtzs w0, d0, #32
|
|---|
| 740 |
|
|---|
| 741 | fcvtzs x0, h0, #1
|
|---|
| 742 | fcvtzs x0, h0, #31
|
|---|
| 743 | fcvtzs x0, h0, #63
|
|---|
| 744 | fcvtzs w0, h0, #1
|
|---|
| 745 | fcvtzs w0, h0, #32
|
|---|
| 746 |
|
|---|
| 747 | ucvtf s0, x0, #1
|
|---|
| 748 | ucvtf s0, x0, #31
|
|---|
| 749 | ucvtf s0, x0, #63
|
|---|
| 750 | ucvtf s0, w0, #1
|
|---|
| 751 | ucvtf s0, w0, #32
|
|---|
| 752 |
|
|---|
| 753 | ucvtf d0, x0, #1
|
|---|
| 754 | ucvtf d0, x0, #31
|
|---|
| 755 | ucvtf d0, x0, #63
|
|---|
| 756 | ucvtf d0, w0, #1
|
|---|
| 757 | ucvtf d0, w0, #32
|
|---|
| 758 |
|
|---|
| 759 | ucvtf h0, x0, #1
|
|---|
| 760 | ucvtf h0, x0, #31
|
|---|
| 761 | ucvtf h0, x0, #63
|
|---|
| 762 | ucvtf h0, w0, #1
|
|---|
| 763 | ucvtf h0, w0, #32
|
|---|
| 764 |
|
|---|
| 765 | scvtf s0, x0, #1
|
|---|
| 766 | scvtf s0, x0, #31
|
|---|
| 767 | scvtf s0, x0, #63
|
|---|
| 768 | scvtf s0, w0, #1
|
|---|
| 769 | scvtf s0, w0, #32
|
|---|
| 770 |
|
|---|
| 771 | scvtf d0, x0, #1
|
|---|
| 772 | scvtf d0, x0, #31
|
|---|
| 773 | scvtf d0, x0, #63
|
|---|
| 774 | scvtf d0, w0, #1
|
|---|
| 775 | scvtf d0, w0, #32
|
|---|
| 776 |
|
|---|
| 777 | scvtf h0, x0, #1
|
|---|
| 778 | scvtf h0, x0, #31
|
|---|
| 779 | scvtf h0, x0, #63
|
|---|
| 780 | scvtf h0, w0, #1
|
|---|
| 781 | scvtf h0, w0, #32
|
|---|
| 782 |
|
|---|
| 783 | fcsel s0, s1, s2, eq
|
|---|
| 784 | fcsel d0, d1, d2, eq
|
|---|
| 785 | fcsel h0, h1, h2, eq
|
|---|
| 786 |
|
|---|
| 787 | fmul s0, s1, s2
|
|---|
| 788 | fmul d0, d1, d2
|
|---|
| 789 | fmul h0, h1, h2
|
|---|
| 790 |
|
|---|
| 791 | fdiv s0, s1, s2
|
|---|
| 792 | fdiv d0, d1, d2
|
|---|
| 793 | fdiv h0, h1, h2
|
|---|
| 794 |
|
|---|
| 795 | fadd s0, s1, s2
|
|---|
| 796 | fadd d0, d1, d2
|
|---|
| 797 | fadd h0, h1, h2
|
|---|
| 798 |
|
|---|
| 799 | fsub s0, s1, s2
|
|---|
| 800 | fsub d0, d1, d2
|
|---|
| 801 | fsub h0, h1, h2
|
|---|
| 802 |
|
|---|
| 803 | fmax s0, s1, s2
|
|---|
| 804 | fmax d0, d1, d2
|
|---|
| 805 | fmax h0, h1, h2
|
|---|
| 806 |
|
|---|
| 807 | fmin s0, s1, s2
|
|---|
| 808 | fmin d0, d1, d2
|
|---|
| 809 | fmin h0, h1, h2
|
|---|
| 810 |
|
|---|
| 811 | fmaxnm s0, s1, s2
|
|---|
| 812 | fmaxnm d0, d1, d2
|
|---|
| 813 | fmaxnm h0, h1, h2
|
|---|
| 814 |
|
|---|
| 815 | fminnm s0, s1, s2
|
|---|
| 816 | fminnm d0, d1, d2
|
|---|
| 817 | fminnm h0, h1, h2
|
|---|
| 818 |
|
|---|
| 819 | fnmul s0, s1, s2
|
|---|
| 820 | fnmul d0, d1, d2
|
|---|
| 821 | fnmul h0, h1, h2
|
|---|
| 822 |
|
|---|
| 823 | fccmp s0, s1, #0, eq
|
|---|
| 824 | fccmp s0, s1, #15, ne
|
|---|
| 825 | fccmp d0, d1, #0, eq
|
|---|
| 826 | fccmp d0, d1, #15, ne
|
|---|
| 827 | fccmp h0, h1, #0, eq
|
|---|
| 828 | fccmp h0, h1, #15, ne
|
|---|
| 829 |
|
|---|
| 830 | fccmpe s0, s1, #0, eq
|
|---|
| 831 | fccmpe s0, s1, #15, ne
|
|---|
| 832 | fccmpe d0, d1, #0, eq
|
|---|
| 833 | fccmpe d0, d1, #15, ne
|
|---|
| 834 | fccmpe h0, h1, #0, eq
|
|---|
| 835 | fccmpe h0, h1, #15, ne
|
|---|
| 836 |
|
|---|
| 837 | ;fmov s0, #1 @todo Needs FP immediate parsing
|
|---|
| 838 |
|
|---|
| 839 | fcmp s0, s1
|
|---|
| 840 | ;fcmp s0, #0.0
|
|---|
| 841 | fcmp d0, d1
|
|---|
| 842 | ;fcmp d0, #0.0
|
|---|
| 843 | fcmp h0, h1
|
|---|
| 844 | ;fcmp h0, #0.0
|
|---|
| 845 |
|
|---|
| 846 | fcmpe s0, s1
|
|---|
| 847 | ;fcmpe s0, #0.0
|
|---|
| 848 | fcmpe d0, d1
|
|---|
| 849 | ;fcmpe d0, #0.0
|
|---|
| 850 | fcmpe h0, h1
|
|---|
| 851 | ;fcmpe h0, #0.0
|
|---|
| 852 |
|
|---|
| 853 | fmov s0, s1
|
|---|
| 854 | fmov d0, d1
|
|---|
| 855 | fmov h0, h1
|
|---|
| 856 |
|
|---|
| 857 | fabs s0, s1
|
|---|
| 858 | fabs d0, d1
|
|---|
| 859 | fabs h0, h1
|
|---|
| 860 |
|
|---|
| 861 | fneg s0, s1
|
|---|
| 862 | fneg d0, d1
|
|---|
| 863 | fneg h0, h1
|
|---|
| 864 |
|
|---|
| 865 | fsqrt s0, s1
|
|---|
| 866 | fsqrt d0, d1
|
|---|
| 867 | fsqrt h0, h1
|
|---|
| 868 |
|
|---|
| 869 | fcvt s0, d1
|
|---|
| 870 | fcvt s0, h1
|
|---|
| 871 | fcvt d0, s1
|
|---|
| 872 | fcvt d0, h1
|
|---|
| 873 | fcvt h0, s1
|
|---|
| 874 | fcvt h0, d1
|
|---|
| 875 |
|
|---|
| 876 | frintn s0, s1
|
|---|
| 877 | frintn d0, d1
|
|---|
| 878 | frintn h0, h1
|
|---|
| 879 |
|
|---|
| 880 | frintp s0, s1
|
|---|
| 881 | frintp d0, d1
|
|---|
| 882 | frintp h0, h1
|
|---|
| 883 |
|
|---|
| 884 | frintm s0, s1
|
|---|
| 885 | frintm d0, d1
|
|---|
| 886 | frintm h0, h1
|
|---|
| 887 |
|
|---|
| 888 | frintz s0, s1
|
|---|
| 889 | frintz d0, d1
|
|---|
| 890 | frintz h0, h1
|
|---|
| 891 |
|
|---|
| 892 | frinta s0, s1
|
|---|
| 893 | frinta d0, d1
|
|---|
| 894 | frinta h0, h1
|
|---|
| 895 |
|
|---|
| 896 | frintx s0, s1
|
|---|
| 897 | frintx d0, d1
|
|---|
| 898 | frintx h0, h1
|
|---|
| 899 |
|
|---|
| 900 | frinti s0, s1
|
|---|
| 901 | frinti d0, d1
|
|---|
| 902 | frinti h0, h1
|
|---|
| 903 |
|
|---|
| 904 | frint32z s0, s1
|
|---|
| 905 | frint32z d0, d1
|
|---|
| 906 |
|
|---|
| 907 | frint32x s0, s1
|
|---|
| 908 | frint32x d0, d1
|
|---|
| 909 |
|
|---|
| 910 | frint64z s0, s1
|
|---|
| 911 | frint64z d0, d1
|
|---|
| 912 |
|
|---|
| 913 | frint64x s0, s1
|
|---|
| 914 | frint64x d0, d1
|
|---|
| 915 |
|
|---|
| 916 | sshr d0, d1, #1
|
|---|
| 917 | sshr d0, d1, #64
|
|---|
| 918 |
|
|---|
| 919 | ssra d0, d1, #1
|
|---|
| 920 | ssra d0, d1, #64
|
|---|
| 921 |
|
|---|
| 922 | srshr d0, d1, #1
|
|---|
| 923 | srshr d0, d1, #64
|
|---|
| 924 |
|
|---|
| 925 | srsra d0, d1, #1
|
|---|
| 926 | srsra d0, d1, #64
|
|---|
| 927 |
|
|---|
| 928 | ; @todo
|
|---|
| 929 | ;shl d0, d1, #0
|
|---|
| 930 | ;shl d0, d1, #63
|
|---|
| 931 |
|
|---|
| 932 | ;sqshl d0, d1, #0
|
|---|
| 933 | ;sqshl d0, d1, #63
|
|---|
| 934 |
|
|---|
| 935 | ;sqshrn q0, q1, #1
|
|---|
| 936 | ;sqshrn q0, q1, #64
|
|---|
| 937 |
|
|---|
| 938 | ;sqrshrn q0, dq, #1
|
|---|
| 939 | ;sqrshrn q0, q1, #64
|
|---|
| 940 |
|
|---|
| 941 | ;
|
|---|
| 942 | ; Keep last so the testcase can catch errors in
|
|---|
| 943 | ; the disassembly of the last instruction.
|
|---|
| 944 | ;
|
|---|
| 945 | nop
|
|---|
| 946 |
|
|---|
| 947 | .private_extern _TestProcA64_EndProc
|
|---|
| 948 | _TestProcA64_EndProc:
|
|---|
