SUPDrvGip.cpp@ 60700

Last change on this file since 60700 was 60529, checked in by vboxsync, 9 years ago
SUPDrvGip.cpp: Disabled another RTTimerRequestSystemGranularity assertion that triggers on windows 10.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 178.4 KB

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1	/* $Id: SUPDrvGip.cpp 60529 2016-04-18 09:12:25Z vboxsync $ */
2	/** @file
3	* VBoxDrv - The VirtualBox Support Driver - Common code for GIP.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	/*********************************************************************************************************************************
29	* Header Files *
30	*********************************************************************************************************************************/
31	#define LOG_GROUP LOG_GROUP_SUP_DRV
32	#define SUPDRV_AGNOSTIC
33	#include "SUPDrvInternal.h"
34	#ifndef PAGE_SHIFT
35	# include <iprt/param.h>
36	#endif
37	#include <iprt/asm.h>
38	#include <iprt/asm-amd64-x86.h>
39	#include <iprt/asm-math.h>
40	#include <iprt/cpuset.h>
41	#include <iprt/handletable.h>
42	#include <iprt/mem.h>
43	#include <iprt/mp.h>
44	#include <iprt/power.h>
45	#include <iprt/process.h>
46	#include <iprt/semaphore.h>
47	#include <iprt/spinlock.h>
48	#include <iprt/thread.h>
49	#include <iprt/uuid.h>
50	#include <iprt/net.h>
51	#include <iprt/crc.h>
52	#include <iprt/string.h>
53	#include <iprt/timer.h>
54	#if defined(RT_OS_DARWIN) \|\| defined(RT_OS_SOLARIS) \|\| defined(RT_OS_FREEBSD)
55	# include <iprt/rand.h>
56	# include <iprt/path.h>
57	#endif
58	#include <iprt/uint128.h>
59	#include <iprt/x86.h>
60
61	#include <VBox/param.h>
62	#include <VBox/log.h>
63	#include <VBox/err.h>
64
65	#if defined(RT_OS_SOLARIS) \|\| defined(RT_OS_DARWIN)
66	# include "dtrace/SUPDrv.h"
67	#else
68	/* ... */
69	#endif
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** The frequency by which we recalculate the u32UpdateHz and
76	* u32UpdateIntervalNS GIP members. The value must be a power of 2.
77	*
78	* Warning: Bumping this too high might overflow u32UpdateIntervalNS.
79	*/
80	#define GIP_UPDATEHZ_RECALC_FREQ 0x800
81
82	/** A reserved TSC value used for synchronization as well as measurement of
83	* TSC deltas. */
84	#define GIP_TSC_DELTA_RSVD UINT64_MAX
85	/** The number of TSC delta measurement loops in total (includes primer and
86	* read-time loops). */
87	#define GIP_TSC_DELTA_LOOPS 96
88	/** The number of cache primer loops. */
89	#define GIP_TSC_DELTA_PRIMER_LOOPS 4
90	/** The number of loops until we keep computing the minumum read time. */
91	#define GIP_TSC_DELTA_READ_TIME_LOOPS 24
92
93	/** The TSC frequency refinement period in seconds.
94	* The timer fires after 200ms, then every second, this value just says when
95	* to stop it after that. */
96	#define GIP_TSC_REFINE_PERIOD_IN_SECS 12
97	/** The TSC-delta threshold for the SUPGIPUSETSCDELTA_PRACTICALLY_ZERO rating */
98	#define GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO 32
99	/** The TSC-delta threshold for the SUPGIPUSETSCDELTA_ROUGHLY_ZERO rating */
100	#define GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO 448
101	/** The TSC delta value for the initial GIP master - 0 in regular builds.
102	* To test the delta code this can be set to a non-zero value. */
103	#if 0
104	# define GIP_TSC_DELTA_INITIAL_MASTER_VALUE INT64_C(170139095182512) /* 0x00009abd9854acb0 */
105	#else
106	# define GIP_TSC_DELTA_INITIAL_MASTER_VALUE INT64_C(0)
107	#endif
108
109	AssertCompile(GIP_TSC_DELTA_PRIMER_LOOPS < GIP_TSC_DELTA_READ_TIME_LOOPS);
110	AssertCompile(GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS < GIP_TSC_DELTA_LOOPS);
111
112	/** @def VBOX_SVN_REV
113	* The makefile should define this if it can. */
114	#ifndef VBOX_SVN_REV
115	# define VBOX_SVN_REV 0
116	#endif
117
118	#if 0 /* Don't start the GIP timers. Useful when debugging the IPRT timer code. */
119	# define DO_NOT_START_GIP
120	#endif
121
122
123	/*********************************************************************************************************************************
124	* Internal Functions *
125	*********************************************************************************************************************************/
126	static DECLCALLBACK(void) supdrvGipSyncAndInvariantTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick);
127	static DECLCALLBACK(void) supdrvGipAsyncTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick);
128	static int supdrvGipSetFlags(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, uint32_t fOrMask, uint32_t fAndMask);
129	static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz);
130	static void supdrvTscResetSamples(PSUPDRVDEVEXT pDevExt, bool fClearDeltas);
131	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
132	static int supdrvTscDeltaThreadInit(PSUPDRVDEVEXT pDevExt);
133	static void supdrvTscDeltaTerm(PSUPDRVDEVEXT pDevExt);
134	static void supdrvTscDeltaThreadStartMeasurement(PSUPDRVDEVEXT pDevExt, bool fForceAll);
135	#else
136	static int supdrvMeasureInitialTscDeltas(PSUPDRVDEVEXT pDevExt);
137	static int supdrvMeasureTscDeltaOne(PSUPDRVDEVEXT pDevExt, uint32_t idxWorker);
138	#endif
139
140
141	/*********************************************************************************************************************************
142	* Global Variables *
143	*********************************************************************************************************************************/
144	DECLEXPORT(PSUPGLOBALINFOPAGE) g_pSUPGlobalInfoPage = NULL;
145
146
147
148	/*
149	*
150	* Misc Common GIP Code
151	* Misc Common GIP Code
152	* Misc Common GIP Code
153	*
154	*
155	*/
156
157
158	/**
159	* Finds the GIP CPU index corresponding to @a idCpu.
160	*
161	* @returns GIP CPU array index, UINT32_MAX if not found.
162	* @param pGip The GIP.
163	* @param idCpu The CPU ID.
164	*/
165	static uint32_t supdrvGipFindCpuIndexForCpuId(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
166	{
167	uint32_t i;
168	for (i = 0; i < pGip->cCpus; i++)
169	if (pGip->aCPUs[i].idCpu == idCpu)
170	return i;
171	return UINT32_MAX;
172	}
173
174
175
176	/*
177	*
178	* GIP Mapping and Unmapping Related Code.
179	* GIP Mapping and Unmapping Related Code.
180	* GIP Mapping and Unmapping Related Code.
181	*
182	*
183	*/
184
185
186	/**
187	* (Re-)initializes the per-cpu structure prior to starting or resuming the GIP
188	* updating.
189	*
190	* @param pGip Pointer to the GIP.
191	* @param pGipCpu The per CPU structure for this CPU.
192	* @param u64NanoTS The current time.
193	*/
194	static void supdrvGipReInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pGipCpu, uint64_t u64NanoTS)
195	{
196	/*
197	* Here we don't really care about applying the TSC delta. The re-initialization of this
198	* value is not relevant especially while (re)starting the GIP as the first few ones will
199	* be ignored anyway, see supdrvGipDoUpdateCpu().
200	*/
201	pGipCpu->u64TSC = ASMReadTSC() - pGipCpu->u32UpdateIntervalTSC;
202	pGipCpu->u64NanoTS = u64NanoTS;
203	}
204
205
206	/**
207	* Set the current TSC and NanoTS value for the CPU.
208	*
209	* @param idCpu The CPU ID. Unused - we have to use the APIC ID.
210	* @param pvUser1 Pointer to the ring-0 GIP mapping.
211	* @param pvUser2 Pointer to the variable holding the current time.
212	*/
213	static DECLCALLBACK(void) supdrvGipReInitCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
214	{
215	PSUPGLOBALINFOPAGE pGip = (PSUPGLOBALINFOPAGE)pvUser1;
216	unsigned iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
217
218	if (RT_LIKELY(iCpu < pGip->cCpus && pGip->aCPUs[iCpu].idCpu == idCpu))
219	supdrvGipReInitCpu(pGip, &pGip->aCPUs[iCpu], (uint64_t )pvUser2);
220
221	NOREF(pvUser2);
222	NOREF(idCpu);
223	}
224
225
226	/**
227	* State structure for supdrvGipDetectGetGipCpuCallback.
228	*/
229	typedef struct SUPDRVGIPDETECTGETCPU
230	{
231	/** Bitmap of APIC IDs that has been seen (initialized to zero).
232	* Used to detect duplicate APIC IDs (paranoia). */
233	uint8_t volatile bmApicId[256 / 8];
234	/** Mask of supported GIP CPU getter methods (SUPGIPGETCPU_XXX) (all bits set
235	* initially). The callback clears the methods not detected. */
236	uint32_t volatile fSupported;
237	/** The first callback detecting any kind of range issues (initialized to
238	* NIL_RTCPUID). */
239	RTCPUID volatile idCpuProblem;
240	} SUPDRVGIPDETECTGETCPU;
241	/** Pointer to state structure for supdrvGipDetectGetGipCpuCallback. */
242	typedef SUPDRVGIPDETECTGETCPU *PSUPDRVGIPDETECTGETCPU;
243
244
245	/**
246	* Checks for alternative ways of getting the CPU ID.
247	*
248	* This also checks the APIC ID, CPU ID and CPU set index values against the
249	* GIP tables.
250	*
251	* @param idCpu The CPU ID. Unused - we have to use the APIC ID.
252	* @param pvUser1 Pointer to the state structure.
253	* @param pvUser2 Pointer to the GIP.
254	*/
255	static DECLCALLBACK(void) supdrvGipDetectGetGipCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
256	{
257	PSUPDRVGIPDETECTGETCPU pState = (PSUPDRVGIPDETECTGETCPU)pvUser1;
258	PSUPGLOBALINFOPAGE pGip = (PSUPGLOBALINFOPAGE)pvUser2;
259	uint32_t fSupported = 0;
260	uint16_t idApic;
261	int iCpuSet;
262
263	AssertMsg(idCpu == RTMpCpuId(), ("idCpu=%#x RTMpCpuId()=%#x\n", idCpu, RTMpCpuId())); /* paranoia^3 */
264
265	/*
266	* Check that the CPU ID and CPU set index are interchangable.
267	*/
268	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
269	if ((RTCPUID)iCpuSet == idCpu)
270	{
271	AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
272	if ( iCpuSet >= 0
273	&& iCpuSet < RTCPUSET_MAX_CPUS
274	&& RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS))
275	{
276	/*
277	* Check whether the IDTR.LIMIT contains a CPU number.
278	*/
279	#ifdef RT_ARCH_X86
280	uint16_t const cbIdt = sizeof(X86DESC64SYSTEM) * 256;
281	#else
282	uint16_t const cbIdt = sizeof(X86DESCGATE) * 256;
283	#endif
284	RTIDTR Idtr;
285	ASMGetIDTR(&Idtr);
286	if (Idtr.cbIdt >= cbIdt)
287	{
288	uint32_t uTmp = Idtr.cbIdt - cbIdt;
289	uTmp &= RTCPUSET_MAX_CPUS - 1;
290	if (uTmp == idCpu)
291	{
292	RTIDTR Idtr2;
293	ASMGetIDTR(&Idtr2);
294	if (Idtr2.cbIdt == Idtr.cbIdt)
295	fSupported \|= SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS;
296	}
297	}
298
299	/*
300	* Check whether RDTSCP is an option.
301	*/
302	if (ASMHasCpuId())
303	{
304	if ( ASMIsValidExtRange(ASMCpuId_EAX(UINT32_C(0x80000000)))
305	&& (ASMCpuId_EDX(UINT32_C(0x80000001)) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) )
306	{
307	uint32_t uAux;
308	ASMReadTscWithAux(&uAux);
309	if ((uAux & (RTCPUSET_MAX_CPUS - 1)) == idCpu)
310	{
311	ASMNopPause();
312	ASMReadTscWithAux(&uAux);
313	if ((uAux & (RTCPUSET_MAX_CPUS - 1)) == idCpu)
314	fSupported \|= SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS;
315	}
316	}
317	}
318	}
319	}
320
321	/*
322	* Check that the APIC ID is unique.
323	*/
324	idApic = ASMGetApicId();
325	if (RT_LIKELY( idApic < RT_ELEMENTS(pGip->aiCpuFromApicId)
326	&& !ASMAtomicBitTestAndSet(pState->bmApicId, idApic)))
327	fSupported \|= SUPGIPGETCPU_APIC_ID;
328	else
329	{
330	AssertCompile(sizeof(pState->bmApicId) * 8 == RT_ELEMENTS(pGip->aiCpuFromApicId));
331	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
332	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - duplicate APIC ID.\n",
333	idCpu, iCpuSet, idApic));
334	}
335
336	/*
337	* Check that the iCpuSet is within the expected range.
338	*/
339	if (RT_UNLIKELY( iCpuSet < 0
340	\|\| (unsigned)iCpuSet >= RTCPUSET_MAX_CPUS
341	\|\| (unsigned)iCpuSet >= RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
342	{
343	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
344	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - CPU set index is out of range.\n",
345	idCpu, iCpuSet, idApic));
346	}
347	else
348	{
349	RTCPUID idCpu2 = RTMpCpuIdFromSetIndex(iCpuSet);
350	if (RT_UNLIKELY(idCpu2 != idCpu))
351	{
352	ASMAtomicCmpXchgU32(&pState->idCpuProblem, idCpu, NIL_RTCPUID);
353	LogRel(("supdrvGipDetectGetGipCpuCallback: idCpu=%#x iCpuSet=%d idApic=%#x - CPU id/index roundtrip problem: %#x\n",
354	idCpu, iCpuSet, idApic, idCpu2));
355	}
356	}
357
358	/*
359	* Update the supported feature mask before we return.
360	*/
361	ASMAtomicAndU32(&pState->fSupported, fSupported);
362
363	NOREF(pvUser2);
364	}
365
366
367	/**
368	* Increase the timer freqency on hosts where this is possible (NT).
369	*
370	* The idea is that more interrupts is better for us... Also, it's better than
371	* we increase the timer frequence, because we might end up getting inaccurate
372	* callbacks if someone else does it.
373	*
374	* @param pDevExt Sets u32SystemTimerGranularityGrant if increased.
375	*/
376	static void supdrvGipRequestHigherTimerFrequencyFromSystem(PSUPDRVDEVEXT pDevExt)
377	{
378	if (pDevExt->u32SystemTimerGranularityGrant == 0)
379	{
380	uint32_t u32SystemResolution;
381	if ( RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 976563 /* 1024 HZ */, &u32SystemResolution))
382	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 1000000 /* 1000 HZ */, &u32SystemResolution))
383	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 1953125 /* 512 HZ */, &u32SystemResolution))
384	\|\| RT_SUCCESS_NP(RTTimerRequestSystemGranularity( 2000000 /* 500 HZ */, &u32SystemResolution))
385	)
386	{
387	#if 0 /* def VBOX_STRICT - this is somehow triggers bogus assertions on windows 10 */
388	uint32_t u32After = RTTimerGetSystemGranularity();
389	AssertMsg(u32After <= u32SystemResolution, ("u32After=%u u32SystemResolution=%u\n", u32After, u32SystemResolution));
390	#endif
391	pDevExt->u32SystemTimerGranularityGrant = u32SystemResolution;
392	}
393	}
394	}
395
396
397	/**
398	* Undoes supdrvGipRequestHigherTimerFrequencyFromSystem.
399	*
400	* @param pDevExt Clears u32SystemTimerGranularityGrant.
401	*/
402	static void supdrvGipReleaseHigherTimerFrequencyFromSystem(PSUPDRVDEVEXT pDevExt)
403	{
404	if (pDevExt->u32SystemTimerGranularityGrant)
405	{
406	int rc2 = RTTimerReleaseSystemGranularity(pDevExt->u32SystemTimerGranularityGrant);
407	AssertRC(rc2);
408	pDevExt->u32SystemTimerGranularityGrant = 0;
409	}
410	}
411
412
413	/**
414	* Maps the GIP into userspace and/or get the physical address of the GIP.
415	*
416	* @returns IPRT status code.
417	* @param pSession Session to which the GIP mapping should belong.
418	* @param ppGipR3 Where to store the address of the ring-3 mapping. (optional)
419	* @param pHCPhysGip Where to store the physical address. (optional)
420	*
421	* @remark There is no reference counting on the mapping, so one call to this function
422	* count globally as one reference. One call to SUPR0GipUnmap() is will unmap GIP
423	* and remove the session as a GIP user.
424	*/
425	SUPR0DECL(int) SUPR0GipMap(PSUPDRVSESSION pSession, PRTR3PTR ppGipR3, PRTHCPHYS pHCPhysGip)
426	{
427	int rc;
428	PSUPDRVDEVEXT pDevExt = pSession->pDevExt;
429	RTR3PTR pGipR3 = NIL_RTR3PTR;
430	RTHCPHYS HCPhys = NIL_RTHCPHYS;
431	LogFlow(("SUPR0GipMap: pSession=%p ppGipR3=%p pHCPhysGip=%p\n", pSession, ppGipR3, pHCPhysGip));
432
433	/*
434	* Validate
435	*/
436	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
437	AssertPtrNullReturn(ppGipR3, VERR_INVALID_POINTER);
438	AssertPtrNullReturn(pHCPhysGip, VERR_INVALID_POINTER);
439
440	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
441	RTSemMutexRequest(pDevExt->mtxGip, RT_INDEFINITE_WAIT);
442	#else
443	RTSemFastMutexRequest(pDevExt->mtxGip);
444	#endif
445	if (pDevExt->pGip)
446	{
447	/*
448	* Map it?
449	*/
450	rc = VINF_SUCCESS;
451	if (ppGipR3)
452	{
453	if (pSession->GipMapObjR3 == NIL_RTR0MEMOBJ)
454	rc = RTR0MemObjMapUser(&pSession->GipMapObjR3, pDevExt->GipMemObj, (RTR3PTR)-1, 0,
455	RTMEM_PROT_READ, NIL_RTR0PROCESS);
456	if (RT_SUCCESS(rc))
457	pGipR3 = RTR0MemObjAddressR3(pSession->GipMapObjR3);
458	}
459
460	/*
461	* Get physical address.
462	*/
463	if (pHCPhysGip && RT_SUCCESS(rc))
464	HCPhys = pDevExt->HCPhysGip;
465
466	/*
467	* Reference globally.
468	*/
469	if (!pSession->fGipReferenced && RT_SUCCESS(rc))
470	{
471	pSession->fGipReferenced = 1;
472	pDevExt->cGipUsers++;
473	if (pDevExt->cGipUsers == 1)
474	{
475	PSUPGLOBALINFOPAGE pGipR0 = pDevExt->pGip;
476	uint64_t u64NanoTS;
477
478	/*
479	* GIP starts/resumes updating again. On windows we bump the
480	* host timer frequency to make sure we don't get stuck in guest
481	* mode and to get better timer (and possibly clock) accuracy.
482	*/
483	LogFlow(("SUPR0GipMap: Resumes GIP updating\n"));
484
485	supdrvGipRequestHigherTimerFrequencyFromSystem(pDevExt);
486
487	/*
488	* document me
489	*/
490	if (pGipR0->aCPUs[0].u32TransactionId != 2 /* not the first time */)
491	{
492	unsigned i;
493	for (i = 0; i < pGipR0->cCpus; i++)
494	ASMAtomicUoWriteU32(&pGipR0->aCPUs[i].u32TransactionId,
495	(pGipR0->aCPUs[i].u32TransactionId + GIP_UPDATEHZ_RECALC_FREQ * 2)
496	& ~(GIP_UPDATEHZ_RECALC_FREQ * 2 - 1));
497	ASMAtomicWriteU64(&pGipR0->u64NanoTSLastUpdateHz, 0);
498	}
499
500	/*
501	* document me
502	*/
503	u64NanoTS = RTTimeSystemNanoTS() - pGipR0->u32UpdateIntervalNS;
504	if ( pGipR0->u32Mode == SUPGIPMODE_INVARIANT_TSC
505	\|\| pGipR0->u32Mode == SUPGIPMODE_SYNC_TSC
506	\|\| RTMpGetOnlineCount() == 1)
507	supdrvGipReInitCpu(pGipR0, &pGipR0->aCPUs[0], u64NanoTS);
508	else
509	RTMpOnAll(supdrvGipReInitCpuCallback, pGipR0, &u64NanoTS);
510
511	/*
512	* Detect alternative ways to figure the CPU ID in ring-3 and
513	* raw-mode context. Check the sanity of the APIC IDs, CPU IDs,
514	* and CPU set indexes while we're at it.
515	*/
516	if (RT_SUCCESS(rc))
517	{
518	SUPDRVGIPDETECTGETCPU DetectState;
519	RT_BZERO((void *)&DetectState.bmApicId, sizeof(DetectState.bmApicId));
520	DetectState.fSupported = UINT32_MAX;
521	DetectState.idCpuProblem = NIL_RTCPUID;
522	rc = RTMpOnAll(supdrvGipDetectGetGipCpuCallback, &DetectState, pGipR0);
523	if (DetectState.idCpuProblem == NIL_RTCPUID)
524	{
525	if ( DetectState.fSupported != UINT32_MAX
526	&& DetectState.fSupported != 0)
527	{
528	if (pGipR0->fGetGipCpu != DetectState.fSupported)
529	{
530	pGipR0->fGetGipCpu = DetectState.fSupported;
531	LogRel(("SUPR0GipMap: fGetGipCpu=%#x\n", DetectState.fSupported));
532	}
533	}
534	else
535	{
536	LogRel(("SUPR0GipMap: No supported ways of getting the APIC ID or CPU number in ring-3! (%#x)\n",
537	DetectState.fSupported));
538	rc = VERR_UNSUPPORTED_CPU;
539	}
540	}
541	else
542	{
543	LogRel(("SUPR0GipMap: APIC ID, CPU ID or CPU set index problem detected on CPU #%u (%#x)!\n",
544	DetectState.idCpuProblem, DetectState.idCpuProblem));
545	rc = VERR_INVALID_CPU_ID;
546	}
547	}
548
549	/*
550	* Start the GIP timer if all is well..
551	*/
552	if (RT_SUCCESS(rc))
553	{
554	#ifndef DO_NOT_START_GIP
555	rc = RTTimerStart(pDevExt->pGipTimer, 0 /* fire ASAP */); AssertRC(rc);
556	#endif
557	rc = VINF_SUCCESS;
558	}
559
560	/*
561	* Bail out on error.
562	*/
563	if (RT_FAILURE(rc))
564	{
565	LogRel(("SUPR0GipMap: failed rc=%Rrc\n", rc));
566	pDevExt->cGipUsers = 0;
567	pSession->fGipReferenced = 0;
568	if (pSession->GipMapObjR3 != NIL_RTR0MEMOBJ)
569	{
570	int rc2 = RTR0MemObjFree(pSession->GipMapObjR3, false); AssertRC(rc2);
571	if (RT_SUCCESS(rc2))
572	pSession->GipMapObjR3 = NIL_RTR0MEMOBJ;
573	}
574	HCPhys = NIL_RTHCPHYS;
575	pGipR3 = NIL_RTR3PTR;
576	}
577	}
578	}
579	}
580	else
581	{
582	rc = VERR_GENERAL_FAILURE;
583	Log(("SUPR0GipMap: GIP is not available!\n"));
584	}
585	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
586	RTSemMutexRelease(pDevExt->mtxGip);
587	#else
588	RTSemFastMutexRelease(pDevExt->mtxGip);
589	#endif
590
591	/*
592	* Write returns.
593	*/
594	if (pHCPhysGip)
595	*pHCPhysGip = HCPhys;
596	if (ppGipR3)
597	*ppGipR3 = pGipR3;
598
599	#ifdef DEBUG_DARWIN_GIP
600	OSDBGPRINT(("SUPR0GipMap: returns %d pHCPhysGip=%lx pGipR3=%p\n", rc, (unsigned long)HCPhys, (void )pGipR3));
601	#else
602	LogFlow(( "SUPR0GipMap: returns %d pHCPhysGip=%lx pGipR3=%p\n", rc, (unsigned long)HCPhys, (void )pGipR3));
603	#endif
604	return rc;
605	}
606
607
608	/**
609	* Unmaps any user mapping of the GIP and terminates all GIP access
610	* from this session.
611	*
612	* @returns IPRT status code.
613	* @param pSession Session to which the GIP mapping should belong.
614	*/
615	SUPR0DECL(int) SUPR0GipUnmap(PSUPDRVSESSION pSession)
616	{
617	int rc = VINF_SUCCESS;
618	PSUPDRVDEVEXT pDevExt = pSession->pDevExt;
619	#ifdef DEBUG_DARWIN_GIP
620	OSDBGPRINT(("SUPR0GipUnmap: pSession=%p pGip=%p GipMapObjR3=%p\n",
621	pSession,
622	pSession->GipMapObjR3 != NIL_RTR0MEMOBJ ? RTR0MemObjAddress(pSession->GipMapObjR3) : NULL,
623	pSession->GipMapObjR3));
624	#else
625	LogFlow(("SUPR0GipUnmap: pSession=%p\n", pSession));
626	#endif
627	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
628
629	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
630	RTSemMutexRequest(pDevExt->mtxGip, RT_INDEFINITE_WAIT);
631	#else
632	RTSemFastMutexRequest(pDevExt->mtxGip);
633	#endif
634
635	/*
636	* GIP test-mode session?
637	*/
638	if ( pSession->fGipTestMode
639	&& pDevExt->pGip)
640	{
641	supdrvGipSetFlags(pDevExt, pSession, 0, ~SUPGIP_FLAGS_TESTING_ENABLE);
642	Assert(!pSession->fGipTestMode);
643	}
644
645	/*
646	* Unmap anything?
647	*/
648	if (pSession->GipMapObjR3 != NIL_RTR0MEMOBJ)
649	{
650	rc = RTR0MemObjFree(pSession->GipMapObjR3, false);
651	AssertRC(rc);
652	if (RT_SUCCESS(rc))
653	pSession->GipMapObjR3 = NIL_RTR0MEMOBJ;
654	}
655
656	/*
657	* Dereference global GIP.
658	*/
659	if (pSession->fGipReferenced && !rc)
660	{
661	pSession->fGipReferenced = 0;
662	if ( pDevExt->cGipUsers > 0
663	&& !--pDevExt->cGipUsers)
664	{
665	LogFlow(("SUPR0GipUnmap: Suspends GIP updating\n"));
666	#ifndef DO_NOT_START_GIP
667	rc = RTTimerStop(pDevExt->pGipTimer); AssertRC(rc); rc = VINF_SUCCESS;
668	#endif
669	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
670	}
671	}
672
673	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
674	RTSemMutexRelease(pDevExt->mtxGip);
675	#else
676	RTSemFastMutexRelease(pDevExt->mtxGip);
677	#endif
678
679	return rc;
680	}
681
682
683	/**
684	* Gets the GIP pointer.
685	*
686	* @returns Pointer to the GIP or NULL.
687	*/
688	SUPDECL(PSUPGLOBALINFOPAGE) SUPGetGIP(void)
689	{
690	return g_pSUPGlobalInfoPage;
691	}
692
693
694
695
696
697	/*
698	*
699	*
700	* GIP Initialization, Termination and CPU Offline / Online Related Code.
701	* GIP Initialization, Termination and CPU Offline / Online Related Code.
702	* GIP Initialization, Termination and CPU Offline / Online Related Code.
703	*
704	*
705	*/
706
707	/**
708	* Used by supdrvInitRefineInvariantTscFreqTimer and supdrvGipInitMeasureTscFreq
709	* to update the TSC frequency related GIP variables.
710	*
711	* @param pGip The GIP.
712	* @param nsElapsed The number of nanoseconds elapsed.
713	* @param cElapsedTscTicks The corresponding number of TSC ticks.
714	* @param iTick The tick number for debugging.
715	*/
716	static void supdrvGipInitSetCpuFreq(PSUPGLOBALINFOPAGE pGip, uint64_t nsElapsed, uint64_t cElapsedTscTicks, uint32_t iTick)
717	{
718	/*
719	* Calculate the frequency.
720	*/
721	uint64_t uCpuHz;
722	if ( cElapsedTscTicks < UINT64_MAX / RT_NS_1SEC
723	&& nsElapsed < UINT32_MAX)
724	uCpuHz = ASMMultU64ByU32DivByU32(cElapsedTscTicks, RT_NS_1SEC, (uint32_t)nsElapsed);
725	else
726	{
727	RTUINT128U CpuHz, Tmp, Divisor;
728	CpuHz.s.Lo = CpuHz.s.Hi = 0;
729	RTUInt128MulU64ByU64(&Tmp, cElapsedTscTicks, RT_NS_1SEC_64);
730	RTUInt128Div(&CpuHz, &Tmp, RTUInt128AssignU64(&Divisor, nsElapsed));
731	uCpuHz = CpuHz.s.Lo;
732	}
733
734	/*
735	* Update the GIP.
736	*/
737	ASMAtomicWriteU64(&pGip->u64CpuHz, uCpuHz);
738	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
739	{
740	ASMAtomicWriteU64(&pGip->aCPUs[0].u64CpuHz, uCpuHz);
741
742	/* For inspecting the frequency calcs using tstGIP-2, debugger or similar. */
743	if (iTick + 1 < pGip->cCpus)
744	ASMAtomicWriteU64(&pGip->aCPUs[iTick + 1].u64CpuHz, uCpuHz);
745	}
746	}
747
748
749	/**
750	* Timer callback function for TSC frequency refinement in invariant GIP mode.
751	*
752	* This is started during driver init and fires once
753	* GIP_TSC_REFINE_PERIOD_IN_SECS seconds later.
754	*
755	* @param pTimer The timer.
756	* @param pvUser Opaque pointer to the device instance data.
757	* @param iTick The timer tick.
758	*/
759	static DECLCALLBACK(void) supdrvInitRefineInvariantTscFreqTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
760	{
761	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
762	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
763	RTCPUID idCpu;
764	uint64_t cNsElapsed;
765	uint64_t cTscTicksElapsed;
766	uint64_t nsNow;
767	uint64_t uTsc;
768	RTCCUINTREG fEFlags;
769
770	/* Paranoia. */
771	AssertReturnVoid(pGip);
772	AssertReturnVoid(pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC);
773
774	/*
775	* If we got a power event, stop the refinement process.
776	*/
777	if (pDevExt->fInvTscRefinePowerEvent)
778	{
779	int rc = RTTimerStop(pTimer); AssertRC(rc);
780	return;
781	}
782
783	/*
784	* Read the TSC and time, noting which CPU we are on.
785	*
786	* Don't bother spinning until RTTimeSystemNanoTS changes, since on
787	* systems where it matters we're in a context where we cannot waste that
788	* much time (DPC watchdog, called from clock interrupt).
789	*/
790	fEFlags = ASMIntDisableFlags();
791	uTsc = ASMReadTSC();
792	nsNow = RTTimeSystemNanoTS();
793	idCpu = RTMpCpuId();
794	ASMSetFlags(fEFlags);
795
796	cNsElapsed = nsNow - pDevExt->nsStartInvarTscRefine;
797	cTscTicksElapsed = uTsc - pDevExt->uTscStartInvarTscRefine;
798
799	/*
800	* If the above measurement was taken on a different CPU than the one we
801	* started the process on, cTscTicksElapsed will need to be adjusted with
802	* the TSC deltas of both the CPUs.
803	*
804	* We ASSUME that the delta calculation process takes less time than the
805	* TSC frequency refinement timer. If it doesn't, we'll complain and
806	* drop the frequency refinement.
807	*
808	* Note! We cannot entirely trust enmUseTscDelta here because it's
809	* downgraded after each delta calculation.
810	*/
811	if ( idCpu != pDevExt->idCpuInvarTscRefine
812	&& pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
813	{
814	uint32_t iStartCpuSet = RTMpCpuIdToSetIndex(pDevExt->idCpuInvarTscRefine);
815	uint32_t iStopCpuSet = RTMpCpuIdToSetIndex(idCpu);
816	uint16_t iStartGipCpu = iStartCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
817	? pGip->aiCpuFromCpuSetIdx[iStartCpuSet] : UINT16_MAX;
818	uint16_t iStopGipCpu = iStopCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
819	? pGip->aiCpuFromCpuSetIdx[iStopCpuSet] : UINT16_MAX;
820	int64_t iStartTscDelta = iStartGipCpu < pGip->cCpus ? pGip->aCPUs[iStartGipCpu].i64TSCDelta : INT64_MAX;
821	int64_t iStopTscDelta = iStopGipCpu < pGip->cCpus ? pGip->aCPUs[iStopGipCpu].i64TSCDelta : INT64_MAX;
822	if (RT_LIKELY(iStartTscDelta != INT64_MAX && iStopTscDelta != INT64_MAX))
823	{
824	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
825	{
826	/* cTscTicksElapsed = (uTsc - iStopTscDelta) - (pDevExt->uTscStartInvarTscRefine - iStartTscDelta); */
827	cTscTicksElapsed += iStartTscDelta - iStopTscDelta;
828	}
829	}
830	/*
831	* Allow 5 times the refinement period to elapse before we give up on the TSC delta
832	* calculations.
833	*/
834	else if (cNsElapsed > GIP_TSC_REFINE_PERIOD_IN_SECS * 5 * RT_NS_1SEC_64)
835	{
836	SUPR0Printf("vboxdrv: Failed to refine invariant TSC frequency because deltas are unavailable after %u (%u) seconds\n",
837	(uint32_t)(cNsElapsed / RT_NS_1SEC), GIP_TSC_REFINE_PERIOD_IN_SECS);
838	SUPR0Printf("vboxdrv: start: %u, %u, %#llx stop: %u, %u, %#llx\n",
839	iStartCpuSet, iStartGipCpu, iStartTscDelta, iStopCpuSet, iStopGipCpu, iStopTscDelta);
840	int rc = RTTimerStop(pTimer); AssertRC(rc);
841	return;
842	}
843	}
844
845	/*
846	* Calculate and update the CPU frequency variables in GIP.
847	*
848	* If there is a GIP user already and we've already refined the frequency
849	* a couple of times, don't update it as we want a stable frequency value
850	* for all VMs.
851	*/
852	if ( pDevExt->cGipUsers == 0
853	\|\| cNsElapsed < RT_NS_1SEC * 2)
854	{
855	supdrvGipInitSetCpuFreq(pGip, cNsElapsed, cTscTicksElapsed, (uint32_t)iTick);
856
857	/*
858	* Stop the timer once we've reached the defined refinement period.
859	*/
860	if (cNsElapsed > GIP_TSC_REFINE_PERIOD_IN_SECS * RT_NS_1SEC_64)
861	{
862	int rc = RTTimerStop(pTimer);
863	AssertRC(rc);
864	}
865	}
866	else
867	{
868	int rc = RTTimerStop(pTimer);
869	AssertRC(rc);
870	}
871	}
872
873
874	/**
875	* @callback_method_impl{FNRTPOWERNOTIFICATION}
876	*/
877	static DECLCALLBACK(void) supdrvGipPowerNotificationCallback(RTPOWEREVENT enmEvent, void *pvUser)
878	{
879	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
880	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
881
882	/*
883	* If the TSC frequency refinement timer is running, we need to cancel it so it
884	* doesn't screw up the frequency after a long suspend.
885	*
886	* Recalculate all TSC-deltas on host resume as it may have changed, seen
887	* on Windows 7 running on the Dell Optiplex Intel Core i5-3570.
888	*/
889	if (enmEvent == RTPOWEREVENT_RESUME)
890	{
891	ASMAtomicWriteBool(&pDevExt->fInvTscRefinePowerEvent, true);
892	if ( RT_LIKELY(pGip)
893	&& pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED
894	&& !supdrvOSAreCpusOfflinedOnSuspend())
895	{
896	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
897	supdrvTscDeltaThreadStartMeasurement(pDevExt, true /* fForceAll */);
898	#else
899	RTCpuSetCopy(&pDevExt->TscDeltaCpuSet, &pGip->OnlineCpuSet);
900	supdrvMeasureInitialTscDeltas(pDevExt);
901	#endif
902	}
903	}
904	else if (enmEvent == RTPOWEREVENT_SUSPEND)
905	ASMAtomicWriteBool(&pDevExt->fInvTscRefinePowerEvent, true);
906	}
907
908
909	/**
910	* Start the TSC-frequency refinment timer for the invariant TSC GIP mode.
911	*
912	* We cannot use this in the synchronous and asynchronous tsc GIP modes because
913	* the CPU may change the TSC frequence between now and when the timer fires
914	* (supdrvInitAsyncRefineTscTimer).
915	*
916	* @param pDevExt Pointer to the device instance data.
917	* @param pGip Pointer to the GIP.
918	*/
919	static void supdrvGipInitStartTimerForRefiningInvariantTscFreq(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip)
920	{
921	uint64_t u64NanoTS;
922	RTCCUINTREG fEFlags;
923	int rc;
924
925	/*
926	* Register a power management callback.
927	*/
928	pDevExt->fInvTscRefinePowerEvent = false;
929	rc = RTPowerNotificationRegister(supdrvGipPowerNotificationCallback, pDevExt);
930	AssertRC(rc); /* ignore */
931
932	/*
933	* Record the TSC and NanoTS as the starting anchor point for refinement
934	* of the TSC. We try get as close to a clock tick as possible on systems
935	* which does not provide high resolution time.
936	*/
937	u64NanoTS = RTTimeSystemNanoTS();
938	while (RTTimeSystemNanoTS() == u64NanoTS)
939	ASMNopPause();
940
941	fEFlags = ASMIntDisableFlags();
942	pDevExt->uTscStartInvarTscRefine = ASMReadTSC();
943	pDevExt->nsStartInvarTscRefine = RTTimeSystemNanoTS();
944	pDevExt->idCpuInvarTscRefine = RTMpCpuId();
945	ASMSetFlags(fEFlags);
946
947	/*
948	* Create a timer that runs on the same CPU so we won't have a depencency
949	* on the TSC-delta and can run in parallel to it. On systems that does not
950	* implement CPU specific timers we'll apply deltas in the timer callback,
951	* just like we do for CPUs going offline.
952	*
953	* The longer the refinement interval the better the accuracy, at least in
954	* theory. If it's too long though, ring-3 may already be starting its
955	* first VMs before we're done. On most systems we will be loading the
956	* support driver during boot and VMs won't be started for a while yet,
957	* it is really only a problem during development (especially with
958	* on-demand driver starting on windows).
959	*
960	* To avoid wasting time doing a long supdrvGipInitMeasureTscFreq() call
961	* to calculate the frequency during driver loading, the timer is set
962	* to fire after 200 ms the first time. It will then reschedule itself
963	* to fire every second until GIP_TSC_REFINE_PERIOD_IN_SECS has been
964	* reached or it notices that there is a user land client with GIP
965	* mapped (we want a stable frequency for all VMs).
966	*/
967	rc = RTTimerCreateEx(&pDevExt->pInvarTscRefineTimer, RT_NS_1SEC,
968	RTTIMER_FLAGS_CPU(RTMpCpuIdToSetIndex(pDevExt->idCpuInvarTscRefine)),
969	supdrvInitRefineInvariantTscFreqTimer, pDevExt);
970	if (RT_SUCCESS(rc))
971	{
972	rc = RTTimerStart(pDevExt->pInvarTscRefineTimer, 2*RT_NS_100MS);
973	if (RT_SUCCESS(rc))
974	return;
975	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
976	}
977
978	if (rc == VERR_CPU_OFFLINE \|\| rc == VERR_NOT_SUPPORTED)
979	{
980	rc = RTTimerCreateEx(&pDevExt->pInvarTscRefineTimer, RT_NS_1SEC, RTTIMER_FLAGS_CPU_ANY,
981	supdrvInitRefineInvariantTscFreqTimer, pDevExt);
982	if (RT_SUCCESS(rc))
983	{
984	rc = RTTimerStart(pDevExt->pInvarTscRefineTimer, 2*RT_NS_100MS);
985	if (RT_SUCCESS(rc))
986	return;
987	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
988	}
989	}
990
991	pDevExt->pInvarTscRefineTimer = NULL;
992	OSDBGPRINT(("vboxdrv: Failed to create or start TSC frequency refinement timer: rc=%Rrc\n", rc));
993	}
994
995
996	/**
997	* @callback_method_impl{PFNRTMPWORKER,
998	* RTMpOnSpecific callback for reading TSC and time on the CPU we started
999	* the measurements on.}
1000	*/
1001	DECLCALLBACK(void) supdrvGipInitReadTscAndNanoTsOnCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
1002	{
1003	RTCCUINTREG fEFlags = ASMIntDisableFlags();
1004	uint64_t puTscStop = (uint64_t )pvUser1;
1005	uint64_t pnsStop = (uint64_t )pvUser2;
1006
1007	*puTscStop = ASMReadTSC();
1008	*pnsStop = RTTimeSystemNanoTS();
1009
1010	ASMSetFlags(fEFlags);
1011	}
1012
1013
1014	/**
1015	* Measures the TSC frequency of the system.
1016	*
1017	* The TSC frequency can vary on systems which are not reported as invariant.
1018	* On such systems the object of this function is to find out what the nominal,
1019	* maximum TSC frequency under 'normal' CPU operation.
1020	*
1021	* @returns VBox status code.
1022	* @param pDevExt Pointer to the device instance.
1023	* @param pGip Pointer to the GIP.
1024	* @param fRough Set if we're doing the rough calculation that the
1025	* TSC measuring code needs, where accuracy isn't all
1026	* that important (too high is better than too low).
1027	* When clear we try for best accuracy that we can
1028	* achieve in reasonably short time.
1029	*/
1030	static int supdrvGipInitMeasureTscFreq(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, bool fRough)
1031	{
1032	uint32_t nsTimerIncr = RTTimerGetSystemGranularity();
1033	int cTriesLeft = fRough ? 4 : 2;
1034	while (cTriesLeft-- > 0)
1035	{
1036	RTCCUINTREG fEFlags;
1037	uint64_t nsStart;
1038	uint64_t nsStop;
1039	uint64_t uTscStart;
1040	uint64_t uTscStop;
1041	RTCPUID idCpuStart;
1042	RTCPUID idCpuStop;
1043
1044	/*
1045	* Synchronize with the host OS clock tick on systems without high
1046	* resolution time API (older Windows version for example).
1047	*/
1048	nsStart = RTTimeSystemNanoTS();
1049	while (RTTimeSystemNanoTS() == nsStart)
1050	ASMNopPause();
1051
1052	/*
1053	* Read the TSC and current time, noting which CPU we're on.
1054	*/
1055	fEFlags = ASMIntDisableFlags();
1056	uTscStart = ASMReadTSC();
1057	nsStart = RTTimeSystemNanoTS();
1058	idCpuStart = RTMpCpuId();
1059	ASMSetFlags(fEFlags);
1060
1061	/*
1062	* Delay for a while.
1063	*/
1064	if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1065	{
1066	/*
1067	* Sleep-wait since the TSC frequency is constant, it eases host load.
1068	* Shorter interval produces more variance in the frequency (esp. Windows).
1069	*/
1070	uint64_t msElapsed = 0;
1071	uint64_t msDelay = ( ((fRough ? 16 : 200) * RT_NS_1MS + nsTimerIncr - 1) / nsTimerIncr * nsTimerIncr - RT_NS_100US )
1072	/ RT_NS_1MS;
1073	do
1074	{
1075	RTThreadSleep((RTMSINTERVAL)(msDelay - msElapsed));
1076	nsStop = RTTimeSystemNanoTS();
1077	msElapsed = (nsStop - nsStart) / RT_NS_1MS;
1078	} while (msElapsed < msDelay);
1079
1080	while (RTTimeSystemNanoTS() == nsStop)
1081	ASMNopPause();
1082	}
1083	else
1084	{
1085	/*
1086	* Busy-wait keeping the frequency up.
1087	*/
1088	do
1089	{
1090	ASMNopPause();
1091	nsStop = RTTimeSystemNanoTS();
1092	} while (nsStop - nsStart < RT_NS_100MS);
1093	}
1094
1095	/*
1096	* Read the TSC and time again.
1097	*/
1098	fEFlags = ASMIntDisableFlags();
1099	uTscStop = ASMReadTSC();
1100	nsStop = RTTimeSystemNanoTS();
1101	idCpuStop = RTMpCpuId();
1102	ASMSetFlags(fEFlags);
1103
1104	/*
1105	* If the CPU changes, things get a bit complicated and what we
1106	* can get away with depends on the GIP mode / TSC reliability.
1107	*/
1108	if (idCpuStop != idCpuStart)
1109	{
1110	bool fDoXCall = false;
1111
1112	/*
1113	* Synchronous TSC mode: we're probably fine as it's unlikely
1114	* that we were rescheduled because of TSC throttling or power
1115	* management reasons, so just go ahead.
1116	*/
1117	if (pGip->u32Mode == SUPGIPMODE_SYNC_TSC)
1118	{
1119	/* Probably ok, maybe we should retry once?. */
1120	Assert(pGip->enmUseTscDelta == SUPGIPUSETSCDELTA_NOT_APPLICABLE);
1121	}
1122	/*
1123	* If we're just doing the rough measurement, do the cross call and
1124	* get on with things (we don't have deltas!).
1125	*/
1126	else if (fRough)
1127	fDoXCall = true;
1128	/*
1129	* Invariant TSC mode: It doesn't matter if we have delta available
1130	* for both CPUs. That is not something we can assume at this point.
1131	*
1132	* Note! We cannot necessarily trust enmUseTscDelta here because it's
1133	* downgraded after each delta calculation and the delta
1134	* calculations may not be complete yet.
1135	*/
1136	else if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1137	{
1138	/** @todo This section of code is never reached atm, consider dropping it later on... */
1139	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1140	{
1141	uint32_t iStartCpuSet = RTMpCpuIdToSetIndex(idCpuStart);
1142	uint32_t iStopCpuSet = RTMpCpuIdToSetIndex(idCpuStop);
1143	uint16_t iStartGipCpu = iStartCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
1144	? pGip->aiCpuFromCpuSetIdx[iStartCpuSet] : UINT16_MAX;
1145	uint16_t iStopGipCpu = iStopCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
1146	? pGip->aiCpuFromCpuSetIdx[iStopCpuSet] : UINT16_MAX;
1147	int64_t iStartTscDelta = iStartGipCpu < pGip->cCpus ? pGip->aCPUs[iStartGipCpu].i64TSCDelta : INT64_MAX;
1148	int64_t iStopTscDelta = iStopGipCpu < pGip->cCpus ? pGip->aCPUs[iStopGipCpu].i64TSCDelta : INT64_MAX;
1149	if (RT_LIKELY(iStartTscDelta != INT64_MAX && iStopTscDelta != INT64_MAX))
1150	{
1151	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
1152	{
1153	uTscStart -= iStartTscDelta;
1154	uTscStop -= iStopTscDelta;
1155	}
1156	}
1157	/*
1158	* Invalid CPU indexes are not caused by online/offline races, so
1159	* we have to trigger driver load failure if that happens as GIP
1160	* and IPRT assumptions are busted on this system.
1161	*/
1162	else if (iStopGipCpu >= pGip->cCpus \|\| iStartGipCpu >= pGip->cCpus)
1163	{
1164	SUPR0Printf("vboxdrv: Unexpected CPU index in supdrvGipInitMeasureTscFreq.\n");
1165	SUPR0Printf("vboxdrv: start: %u, %u, %#llx stop: %u, %u, %#llx\n",
1166	iStartCpuSet, iStartGipCpu, iStartTscDelta, iStopCpuSet, iStopGipCpu, iStopTscDelta);
1167	return VERR_INVALID_CPU_INDEX;
1168	}
1169	/*
1170	* No valid deltas. We retry, if we're on our last retry
1171	* we do the cross call instead just to get a result. The
1172	* frequency will be refined in a few seconds anyway.
1173	*/
1174	else if (cTriesLeft > 0)
1175	continue;
1176	else
1177	fDoXCall = true;
1178	}
1179	}
1180	/*
1181	* Asynchronous TSC mode: This is bad, as the reason we usually
1182	* use this mode is to deal with variable TSC frequencies and
1183	* deltas. So, we need to get the TSC from the same CPU as
1184	* started it, we also need to keep that CPU busy. So, retry
1185	* and fall back to the cross call on the last attempt.
1186	*/
1187	else
1188	{
1189	Assert(pGip->u32Mode == SUPGIPMODE_ASYNC_TSC);
1190	if (cTriesLeft > 0)
1191	continue;
1192	fDoXCall = true;
1193	}
1194
1195	if (fDoXCall)
1196	{
1197	/*
1198	* Try read the TSC and timestamp on the start CPU.
1199	*/
1200	int rc = RTMpOnSpecific(idCpuStart, supdrvGipInitReadTscAndNanoTsOnCpu, &uTscStop, &nsStop);
1201	if (RT_FAILURE(rc) && (!fRough \|\| cTriesLeft > 0))
1202	continue;
1203	}
1204	}
1205
1206	/*
1207	* Calculate the TSC frequency and update it (shared with the refinement timer).
1208	*/
1209	supdrvGipInitSetCpuFreq(pGip, nsStop - nsStart, uTscStop - uTscStart, 0);
1210	return VINF_SUCCESS;
1211	}
1212
1213	Assert(!fRough);
1214	return VERR_SUPDRV_TSC_FREQ_MEASUREMENT_FAILED;
1215	}
1216
1217
1218	/**
1219	* Finds our (@a idCpu) entry, or allocates a new one if not found.
1220	*
1221	* @returns Index of the CPU in the cache set.
1222	* @param pGip The GIP.
1223	* @param idCpu The CPU ID.
1224	*/
1225	static uint32_t supdrvGipFindOrAllocCpuIndexForCpuId(PSUPGLOBALINFOPAGE pGip, RTCPUID idCpu)
1226	{
1227	uint32_t i, cTries;
1228
1229	/*
1230	* ASSUMES that CPU IDs are constant.
1231	*/
1232	for (i = 0; i < pGip->cCpus; i++)
1233	if (pGip->aCPUs[i].idCpu == idCpu)
1234	return i;
1235
1236	cTries = 0;
1237	do
1238	{
1239	for (i = 0; i < pGip->cCpus; i++)
1240	{
1241	bool fRc;
1242	ASMAtomicCmpXchgSize(&pGip->aCPUs[i].idCpu, idCpu, NIL_RTCPUID, fRc);
1243	if (fRc)
1244	return i;
1245	}
1246	} while (cTries++ < 32);
1247	AssertReleaseFailed();
1248	return i - 1;
1249	}
1250
1251
1252	/**
1253	* The calling CPU should be accounted as online, update GIP accordingly.
1254	*
1255	* This is used by supdrvGipCreate() as well as supdrvGipMpEvent().
1256	*
1257	* @param pDevExt The device extension.
1258	* @param idCpu The CPU ID.
1259	*/
1260	static void supdrvGipMpEventOnlineOrInitOnCpu(PSUPDRVDEVEXT pDevExt, RTCPUID idCpu)
1261	{
1262	int iCpuSet = 0;
1263	uint16_t idApic = UINT16_MAX;
1264	uint32_t i = 0;
1265	uint64_t u64NanoTS = 0;
1266	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1267
1268	AssertPtrReturnVoid(pGip);
1269	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1270	AssertRelease(idCpu == RTMpCpuId());
1271	Assert(pGip->cPossibleCpus == RTMpGetCount());
1272
1273	/*
1274	* Do this behind a spinlock with interrupts disabled as this can fire
1275	* on all CPUs simultaneously, see @bugref{6110}.
1276	*/
1277	RTSpinlockAcquire(pDevExt->hGipSpinlock);
1278
1279	/*
1280	* Update the globals.
1281	*/
1282	ASMAtomicWriteU16(&pGip->cPresentCpus, RTMpGetPresentCount());
1283	ASMAtomicWriteU16(&pGip->cOnlineCpus, RTMpGetOnlineCount());
1284	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
1285	if (iCpuSet >= 0)
1286	{
1287	Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
1288	RTCpuSetAddByIndex(&pGip->OnlineCpuSet, iCpuSet);
1289	RTCpuSetAddByIndex(&pGip->PresentCpuSet, iCpuSet);
1290	}
1291
1292	/*
1293	* Update the entry.
1294	*/
1295	u64NanoTS = RTTimeSystemNanoTS() - pGip->u32UpdateIntervalNS;
1296	i = supdrvGipFindOrAllocCpuIndexForCpuId(pGip, idCpu);
1297
1298	supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS, pGip->u64CpuHz);
1299
1300	idApic = ASMGetApicId();
1301	ASMAtomicWriteU16(&pGip->aCPUs[i].idApic, idApic);
1302	ASMAtomicWriteS16(&pGip->aCPUs[i].iCpuSet, (int16_t)iCpuSet);
1303	ASMAtomicWriteSize(&pGip->aCPUs[i].idCpu, idCpu);
1304
1305	/*
1306	* Update the APIC ID and CPU set index mappings.
1307	*/
1308	ASMAtomicWriteU16(&pGip->aiCpuFromApicId[idApic], i);
1309	ASMAtomicWriteU16(&pGip->aiCpuFromCpuSetIdx[iCpuSet], i);
1310
1311	/* Add this CPU to this set of CPUs we need to calculate the TSC-delta for. */
1312	RTCpuSetAddByIndex(&pDevExt->TscDeltaCpuSet, RTMpCpuIdToSetIndex(idCpu));
1313
1314	/* Update the Mp online/offline counter. */
1315	ASMAtomicIncU32(&pDevExt->cMpOnOffEvents);
1316
1317	/* Commit it. */
1318	ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_ONLINE);
1319
1320	RTSpinlockRelease(pDevExt->hGipSpinlock);
1321	}
1322
1323
1324	/**
1325	* RTMpOnSpecific callback wrapper for supdrvGipMpEventOnlineOrInitOnCpu().
1326	*
1327	* @param idCpu The CPU ID we are running on.
1328	* @param pvUser1 Opaque pointer to the device instance data.
1329	* @param pvUser2 Not used.
1330	*/
1331	static DECLCALLBACK(void) supdrvGipMpEventOnlineCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1332	{
1333	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser1;
1334	NOREF(pvUser2);
1335	supdrvGipMpEventOnlineOrInitOnCpu(pDevExt, idCpu);
1336	}
1337
1338
1339	/**
1340	* The CPU should be accounted as offline, update the GIP accordingly.
1341	*
1342	* This is used by supdrvGipMpEvent.
1343	*
1344	* @param pDevExt The device extension.
1345	* @param idCpu The CPU ID.
1346	*/
1347	static void supdrvGipMpEventOffline(PSUPDRVDEVEXT pDevExt, RTCPUID idCpu)
1348	{
1349	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1350	int iCpuSet;
1351	unsigned i;
1352
1353	AssertPtrReturnVoid(pGip);
1354	RTSpinlockAcquire(pDevExt->hGipSpinlock);
1355
1356	iCpuSet = RTMpCpuIdToSetIndex(idCpu);
1357	AssertReturnVoid(iCpuSet >= 0);
1358
1359	i = pGip->aiCpuFromCpuSetIdx[iCpuSet];
1360	AssertReturnVoid(i < pGip->cCpus);
1361	AssertReturnVoid(pGip->aCPUs[i].idCpu == idCpu);
1362
1363	Assert(RTCpuSetIsMemberByIndex(&pGip->PossibleCpuSet, iCpuSet));
1364	RTCpuSetDelByIndex(&pGip->OnlineCpuSet, iCpuSet);
1365
1366	/* Update the Mp online/offline counter. */
1367	ASMAtomicIncU32(&pDevExt->cMpOnOffEvents);
1368
1369	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1370	{
1371	/* Reset the TSC delta, we will recalculate it lazily. */
1372	ASMAtomicWriteS64(&pGip->aCPUs[i].i64TSCDelta, INT64_MAX);
1373	/* Remove this CPU from the set of CPUs that we have obtained the TSC deltas. */
1374	RTCpuSetDelByIndex(&pDevExt->TscDeltaObtainedCpuSet, iCpuSet);
1375	}
1376
1377	/* Commit it. */
1378	ASMAtomicWriteSize(&pGip->aCPUs[i].enmState, SUPGIPCPUSTATE_OFFLINE);
1379
1380	RTSpinlockRelease(pDevExt->hGipSpinlock);
1381	}
1382
1383
1384	/**
1385	* Multiprocessor event notification callback.
1386	*
1387	* This is used to make sure that the GIP master gets passed on to
1388	* another CPU. It also updates the associated CPU data.
1389	*
1390	* @param enmEvent The event.
1391	* @param idCpu The cpu it applies to.
1392	* @param pvUser Pointer to the device extension.
1393	*/
1394	static DECLCALLBACK(void) supdrvGipMpEvent(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvUser)
1395	{
1396	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
1397	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
1398
1399	if (pGip)
1400	{
1401	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1402	switch (enmEvent)
1403	{
1404	case RTMPEVENT_ONLINE:
1405	{
1406	RTThreadPreemptDisable(&PreemptState);
1407	if (idCpu == RTMpCpuId())
1408	{
1409	supdrvGipMpEventOnlineOrInitOnCpu(pDevExt, idCpu);
1410	RTThreadPreemptRestore(&PreemptState);
1411	}
1412	else
1413	{
1414	RTThreadPreemptRestore(&PreemptState);
1415	RTMpOnSpecific(idCpu, supdrvGipMpEventOnlineCallback, pDevExt, NULL /* pvUser2 */);
1416	}
1417
1418	/*
1419	* Recompute TSC-delta for the newly online'd CPU.
1420	*/
1421	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1422	{
1423	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1424	supdrvTscDeltaThreadStartMeasurement(pDevExt, false /* fForceAll */);
1425	#else
1426	uint32_t iCpu = supdrvGipFindOrAllocCpuIndexForCpuId(pGip, idCpu);
1427	supdrvMeasureTscDeltaOne(pDevExt, iCpu);
1428	#endif
1429	}
1430	break;
1431	}
1432
1433	case RTMPEVENT_OFFLINE:
1434	supdrvGipMpEventOffline(pDevExt, idCpu);
1435	break;
1436	}
1437	}
1438
1439	/*
1440	* Make sure there is a master GIP.
1441	*/
1442	if (enmEvent == RTMPEVENT_OFFLINE)
1443	{
1444	RTCPUID idGipMaster = ASMAtomicReadU32(&pDevExt->idGipMaster);
1445	if (idGipMaster == idCpu)
1446	{
1447	/*
1448	* The GIP master is going offline, find a new one.
1449	*/
1450	bool fIgnored;
1451	unsigned i;
1452	RTCPUID idNewGipMaster = NIL_RTCPUID;
1453	RTCPUSET OnlineCpus;
1454	RTMpGetOnlineSet(&OnlineCpus);
1455
1456	for (i = 0; i < RTCPUSET_MAX_CPUS; i++)
1457	if (RTCpuSetIsMemberByIndex(&OnlineCpus, i))
1458	{
1459	RTCPUID idCurCpu = RTMpCpuIdFromSetIndex(i);
1460	if (idCurCpu != idGipMaster)
1461	{
1462	idNewGipMaster = idCurCpu;
1463	break;
1464	}
1465	}
1466
1467	Log(("supdrvGipMpEvent: Gip master %#lx -> %#lx\n", (long)idGipMaster, (long)idNewGipMaster));
1468	ASMAtomicCmpXchgSize(&pDevExt->idGipMaster, idNewGipMaster, idGipMaster, fIgnored);
1469	NOREF(fIgnored);
1470	}
1471	}
1472	}
1473
1474
1475	/**
1476	* On CPU initialization callback for RTMpOnAll.
1477	*
1478	* @param idCpu The CPU ID.
1479	* @param pvUser1 The device extension.
1480	* @param pvUser2 The GIP.
1481	*/
1482	static DECLCALLBACK(void) supdrvGipInitOnCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
1483	{
1484	/* This is good enough, even though it will update some of the globals a
1485	bit to much. */
1486	supdrvGipMpEventOnlineOrInitOnCpu((PSUPDRVDEVEXT)pvUser1, idCpu);
1487	}
1488
1489
1490	/**
1491	* Callback used by supdrvDetermineAsyncTSC to read the TSC on a CPU.
1492	*
1493	* @param idCpu Ignored.
1494	* @param pvUser1 Where to put the TSC.
1495	* @param pvUser2 Ignored.
1496	*/
1497	static DECLCALLBACK(void) supdrvGipInitDetermineAsyncTscWorker(RTCPUID idCpu, void pvUser1, void pvUser2)
1498	{
1499	Assert(RTMpCpuIdToSetIndex(idCpu) == (intptr_t)pvUser2);
1500	ASMAtomicWriteU64((uint64_t volatile *)pvUser1, ASMReadTSC());
1501	}
1502
1503
1504	/**
1505	* Determine if Async GIP mode is required because of TSC drift.
1506	*
1507	* When using the default/normal timer code it is essential that the time stamp counter
1508	* (TSC) runs never backwards, that is, a read operation to the counter should return
1509	* a bigger value than any previous read operation. This is guaranteed by the latest
1510	* AMD CPUs and by newer Intel CPUs which never enter the C2 state (P4). In any other
1511	* case we have to choose the asynchronous timer mode.
1512	*
1513	* @param poffMin Pointer to the determined difference between different
1514	* cores (optional, can be NULL).
1515	* @return false if the time stamp counters appear to be synchronized, true otherwise.
1516	*/
1517	static bool supdrvGipInitDetermineAsyncTsc(uint64_t *poffMin)
1518	{
1519	/*
1520	* Just iterate all the cpus 8 times and make sure that the TSC is
1521	* ever increasing. We don't bother taking TSC rollover into account.
1522	*/
1523	int iEndCpu = RTMpGetArraySize();
1524	int iCpu;
1525	int cLoops = 8;
1526	bool fAsync = false;
1527	int rc = VINF_SUCCESS;
1528	uint64_t offMax = 0;
1529	uint64_t offMin = ~(uint64_t)0;
1530	uint64_t PrevTsc = ASMReadTSC();
1531
1532	while (cLoops-- > 0)
1533	{
1534	for (iCpu = 0; iCpu < iEndCpu; iCpu++)
1535	{
1536	uint64_t CurTsc;
1537	rc = RTMpOnSpecific(RTMpCpuIdFromSetIndex(iCpu), supdrvGipInitDetermineAsyncTscWorker,
1538	&CurTsc, (void *)(uintptr_t)iCpu);
1539	if (RT_SUCCESS(rc))
1540	{
1541	if (CurTsc <= PrevTsc)
1542	{
1543	fAsync = true;
1544	offMin = offMax = PrevTsc - CurTsc;
1545	Log(("supdrvGipInitDetermineAsyncTsc: iCpu=%d cLoops=%d CurTsc=%llx PrevTsc=%llx\n",
1546	iCpu, cLoops, CurTsc, PrevTsc));
1547	break;
1548	}
1549
1550	/* Gather statistics (except the first time). */
1551	if (iCpu != 0 \|\| cLoops != 7)
1552	{
1553	uint64_t off = CurTsc - PrevTsc;
1554	if (off < offMin)
1555	offMin = off;
1556	if (off > offMax)
1557	offMax = off;
1558	Log2(("%d/%d: off=%llx\n", cLoops, iCpu, off));
1559	}
1560
1561	/* Next */
1562	PrevTsc = CurTsc;
1563	}
1564	else if (rc == VERR_NOT_SUPPORTED)
1565	break;
1566	else
1567	AssertMsg(rc == VERR_CPU_NOT_FOUND \|\| rc == VERR_CPU_OFFLINE, ("%d\n", rc));
1568	}
1569
1570	/* broke out of the loop. */
1571	if (iCpu < iEndCpu)
1572	break;
1573	}
1574
1575	if (poffMin)
1576	poffMin = offMin; / Almost RTMpOnSpecific profiling. */
1577	Log(("supdrvGipInitDetermineAsyncTsc: returns %d; iEndCpu=%d rc=%d offMin=%llx offMax=%llx\n",
1578	fAsync, iEndCpu, rc, offMin, offMax));
1579	#if !defined(RT_OS_SOLARIS) && !defined(RT_OS_OS2) && !defined(RT_OS_WINDOWS)
1580	OSDBGPRINT(("vboxdrv: fAsync=%d offMin=%#lx offMax=%#lx\n", fAsync, (long)offMin, (long)offMax));
1581	#endif
1582	return fAsync;
1583	}
1584
1585
1586	/**
1587	* supdrvGipInit() worker that determines the GIP TSC mode.
1588	*
1589	* @returns The most suitable TSC mode.
1590	* @param pDevExt Pointer to the device instance data.
1591	*/
1592	static SUPGIPMODE supdrvGipInitDetermineTscMode(PSUPDRVDEVEXT pDevExt)
1593	{
1594	uint64_t u64DiffCoresIgnored;
1595	uint32_t uEAX, uEBX, uECX, uEDX;
1596
1597	/*
1598	* Establish whether the CPU advertises TSC as invariant, we need that in
1599	* a couple of places below.
1600	*/
1601	bool fInvariantTsc = false;
1602	if (ASMHasCpuId())
1603	{
1604	uEAX = ASMCpuId_EAX(0x80000000);
1605	if (ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)
1606	{
1607	uEDX = ASMCpuId_EDX(0x80000007);
1608	if (uEDX & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
1609	fInvariantTsc = true;
1610	}
1611	}
1612
1613	/*
1614	* On single CPU systems, we don't need to consider ASYNC mode.
1615	*/
1616	if (RTMpGetCount() <= 1)
1617	return fInvariantTsc ? SUPGIPMODE_INVARIANT_TSC : SUPGIPMODE_SYNC_TSC;
1618
1619	/*
1620	* Allow the user and/or OS specific bits to force async mode.
1621	*/
1622	if (supdrvOSGetForcedAsyncTscMode(pDevExt))
1623	return SUPGIPMODE_ASYNC_TSC;
1624
1625	/*
1626	* Use invariant mode if the CPU says TSC is invariant.
1627	*/
1628	if (fInvariantTsc)
1629	return SUPGIPMODE_INVARIANT_TSC;
1630
1631	/*
1632	* TSC is not invariant and we're on SMP, this presents two problems:
1633	*
1634	* (1) There might be a skew between the CPU, so that cpu0
1635	* returns a TSC that is slightly different from cpu1.
1636	* This screw may be due to (2), bad TSC initialization
1637	* or slightly different TSC rates.
1638	*
1639	* (2) Power management (and other things) may cause the TSC
1640	* to run at a non-constant speed, and cause the speed
1641	* to be different on the cpus. This will result in (1).
1642	*
1643	* If any of the above is detected, we will have to use ASYNC mode.
1644	*/
1645	/* (1). Try check for current differences between the cpus. */
1646	if (supdrvGipInitDetermineAsyncTsc(&u64DiffCoresIgnored))
1647	return SUPGIPMODE_ASYNC_TSC;
1648
1649	/* (2) If it's an AMD CPU with power management, we won't trust its TSC. */
1650	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1651	if ( ASMIsValidStdRange(uEAX)
1652	&& ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1653	{
1654	/* Check for APM support. */
1655	uEAX = ASMCpuId_EAX(0x80000000);
1656	if (ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)
1657	{
1658	uEDX = ASMCpuId_EDX(0x80000007);
1659	if (uEDX & 0x3e) /* STC\|TM\|THERMTRIP\|VID\|FID. Ignore TS. */
1660	return SUPGIPMODE_ASYNC_TSC;
1661	}
1662	}
1663
1664	return SUPGIPMODE_SYNC_TSC;
1665	}
1666
1667
1668	/**
1669	* Initializes per-CPU GIP information.
1670	*
1671	* @param pGip Pointer to the GIP.
1672	* @param pCpu Pointer to which GIP CPU to initialize.
1673	* @param u64NanoTS The current nanosecond timestamp.
1674	* @param uCpuHz The CPU frequency to set, 0 if the caller doesn't know.
1675	*/
1676	static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz)
1677	{
1678	pCpu->u32TransactionId = 2;
1679	pCpu->u64NanoTS = u64NanoTS;
1680	pCpu->u64TSC = ASMReadTSC();
1681	pCpu->u64TSCSample = GIP_TSC_DELTA_RSVD;
1682	pCpu->i64TSCDelta = pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED ? INT64_MAX : 0;
1683
1684	ASMAtomicWriteSize(&pCpu->enmState, SUPGIPCPUSTATE_INVALID);
1685	ASMAtomicWriteSize(&pCpu->idCpu, NIL_RTCPUID);
1686	ASMAtomicWriteS16(&pCpu->iCpuSet, -1);
1687	ASMAtomicWriteU16(&pCpu->idApic, UINT16_MAX);
1688
1689	/*
1690	* The first time we're called, we don't have a CPU frequency handy,
1691	* so pretend it's a 4 GHz CPU. On CPUs that are online, we'll get
1692	* called again and at that point we have a more plausible CPU frequency
1693	* value handy. The frequency history will also be adjusted again on
1694	* the 2nd timer callout (maybe we can skip that now?).
1695	*/
1696	if (!uCpuHz)
1697	{
1698	pCpu->u64CpuHz = _4G - 1;
1699	pCpu->u32UpdateIntervalTSC = (uint32_t)((_4G - 1) / pGip->u32UpdateHz);
1700	}
1701	else
1702	{
1703	pCpu->u64CpuHz = uCpuHz;
1704	pCpu->u32UpdateIntervalTSC = (uint32_t)(uCpuHz / pGip->u32UpdateHz);
1705	}
1706	pCpu->au32TSCHistory[0]
1707	= pCpu->au32TSCHistory[1]
1708	= pCpu->au32TSCHistory[2]
1709	= pCpu->au32TSCHistory[3]
1710	= pCpu->au32TSCHistory[4]
1711	= pCpu->au32TSCHistory[5]
1712	= pCpu->au32TSCHistory[6]
1713	= pCpu->au32TSCHistory[7]
1714	= pCpu->u32UpdateIntervalTSC;
1715	}
1716
1717
1718	/**
1719	* Initializes the GIP data.
1720	*
1721	* @param pDevExt Pointer to the device instance data.
1722	* @param pGip Pointer to the read-write kernel mapping of the GIP.
1723	* @param HCPhys The physical address of the GIP.
1724	* @param u64NanoTS The current nanosecond timestamp.
1725	* @param uUpdateHz The update frequency.
1726	* @param uUpdateIntervalNS The update interval in nanoseconds.
1727	* @param cCpus The CPU count.
1728	*/
1729	static void supdrvGipInit(PSUPDRVDEVEXT pDevExt, PSUPGLOBALINFOPAGE pGip, RTHCPHYS HCPhys,
1730	uint64_t u64NanoTS, unsigned uUpdateHz, unsigned uUpdateIntervalNS, unsigned cCpus)
1731	{
1732	size_t const cbGip = RT_ALIGN_Z(RT_OFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), PAGE_SIZE);
1733	unsigned i;
1734	#ifdef DEBUG_DARWIN_GIP
1735	OSDBGPRINT(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
1736	#else
1737	LogFlow(("supdrvGipInit: pGip=%p HCPhys=%lx u64NanoTS=%llu uUpdateHz=%d cCpus=%u\n", pGip, (long)HCPhys, u64NanoTS, uUpdateHz, cCpus));
1738	#endif
1739
1740	/*
1741	* Initialize the structure.
1742	*/
1743	memset(pGip, 0, cbGip);
1744
1745	pGip->u32Magic = SUPGLOBALINFOPAGE_MAGIC;
1746	pGip->u32Version = SUPGLOBALINFOPAGE_VERSION;
1747	pGip->u32Mode = supdrvGipInitDetermineTscMode(pDevExt);
1748	if ( pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC
1749	/\|\| pGip->u32Mode == SUPGIPMODE_SYNC_TSC /)
1750	pGip->enmUseTscDelta = supdrvOSAreTscDeltasInSync() /* Allow OS override (windows). */
1751	? SUPGIPUSETSCDELTA_ZERO_CLAIMED : SUPGIPUSETSCDELTA_PRACTICALLY_ZERO /* downgrade later */;
1752	else
1753	pGip->enmUseTscDelta = SUPGIPUSETSCDELTA_NOT_APPLICABLE;
1754	pGip->cCpus = (uint16_t)cCpus;
1755	pGip->cPages = (uint16_t)(cbGip / PAGE_SIZE);
1756	pGip->u32UpdateHz = uUpdateHz;
1757	pGip->u32UpdateIntervalNS = uUpdateIntervalNS;
1758	pGip->fGetGipCpu = SUPGIPGETCPU_APIC_ID;
1759	RTCpuSetEmpty(&pGip->OnlineCpuSet);
1760	RTCpuSetEmpty(&pGip->PresentCpuSet);
1761	RTMpGetSet(&pGip->PossibleCpuSet);
1762	pGip->cOnlineCpus = RTMpGetOnlineCount();
1763	pGip->cPresentCpus = RTMpGetPresentCount();
1764	pGip->cPossibleCpus = RTMpGetCount();
1765	pGip->idCpuMax = RTMpGetMaxCpuId();
1766	for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromApicId); i++)
1767	pGip->aiCpuFromApicId[i] = UINT16_MAX;
1768	for (i = 0; i < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx); i++)
1769	pGip->aiCpuFromCpuSetIdx[i] = UINT16_MAX;
1770	for (i = 0; i < cCpus; i++)
1771	supdrvGipInitCpu(pGip, &pGip->aCPUs[i], u64NanoTS, 0 /uCpuHz/);
1772
1773	/*
1774	* Link it to the device extension.
1775	*/
1776	pDevExt->pGip = pGip;
1777	pDevExt->HCPhysGip = HCPhys;
1778	pDevExt->cGipUsers = 0;
1779	}
1780
1781
1782	/**
1783	* Creates the GIP.
1784	*
1785	* @returns VBox status code.
1786	* @param pDevExt Instance data. GIP stuff may be updated.
1787	*/
1788	int VBOXCALL supdrvGipCreate(PSUPDRVDEVEXT pDevExt)
1789	{
1790	PSUPGLOBALINFOPAGE pGip;
1791	RTHCPHYS HCPhysGip;
1792	uint32_t u32SystemResolution;
1793	uint32_t u32Interval;
1794	uint32_t u32MinInterval;
1795	uint32_t uMod;
1796	unsigned cCpus;
1797	int rc;
1798
1799	LogFlow(("supdrvGipCreate:\n"));
1800
1801	/*
1802	* Assert order.
1803	*/
1804	Assert(pDevExt->u32SystemTimerGranularityGrant == 0);
1805	Assert(pDevExt->GipMemObj == NIL_RTR0MEMOBJ);
1806	Assert(!pDevExt->pGipTimer);
1807	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
1808	Assert(pDevExt->mtxGip != NIL_RTSEMMUTEX);
1809	Assert(pDevExt->mtxTscDelta != NIL_RTSEMMUTEX);
1810	#else
1811	Assert(pDevExt->mtxGip != NIL_RTSEMFASTMUTEX);
1812	Assert(pDevExt->mtxTscDelta != NIL_RTSEMFASTMUTEX);
1813	#endif
1814
1815	/*
1816	* Check the CPU count.
1817	*/
1818	cCpus = RTMpGetArraySize();
1819	if ( cCpus > RTCPUSET_MAX_CPUS
1820	\|\| cCpus > 256 /* ApicId is used for the mappings */)
1821	{
1822	SUPR0Printf("VBoxDrv: Too many CPUs (%u) for the GIP (max %u)\n", cCpus, RT_MIN(RTCPUSET_MAX_CPUS, 256));
1823	return VERR_TOO_MANY_CPUS;
1824	}
1825
1826	/*
1827	* Allocate a contiguous set of pages with a default kernel mapping.
1828	*/
1829	rc = RTR0MemObjAllocCont(&pDevExt->GipMemObj, RT_UOFFSETOF(SUPGLOBALINFOPAGE, aCPUs[cCpus]), false /fExecutable/);
1830	if (RT_FAILURE(rc))
1831	{
1832	OSDBGPRINT(("supdrvGipCreate: failed to allocate the GIP page. rc=%d\n", rc));
1833	return rc;
1834	}
1835	pGip = (PSUPGLOBALINFOPAGE)RTR0MemObjAddress(pDevExt->GipMemObj); AssertPtr(pGip);
1836	HCPhysGip = RTR0MemObjGetPagePhysAddr(pDevExt->GipMemObj, 0); Assert(HCPhysGip != NIL_RTHCPHYS);
1837
1838	/*
1839	* Find a reasonable update interval and initialize the structure.
1840	*/
1841	supdrvGipRequestHigherTimerFrequencyFromSystem(pDevExt);
1842	/** @todo figure out why using a 100Ms interval upsets timekeeping in VMs.
1843	* See @bugref{6710}. */
1844	u32MinInterval = RT_NS_10MS;
1845	u32SystemResolution = RTTimerGetSystemGranularity();
1846	u32Interval = u32MinInterval;
1847	uMod = u32MinInterval % u32SystemResolution;
1848	if (uMod)
1849	u32Interval += u32SystemResolution - uMod;
1850
1851	supdrvGipInit(pDevExt, pGip, HCPhysGip, RTTimeSystemNanoTS(), RT_NS_1SEC / u32Interval /=Hz/, u32Interval, cCpus);
1852
1853	/*
1854	* Important sanity check...
1855	*/
1856	if (RT_UNLIKELY( pGip->enmUseTscDelta == SUPGIPUSETSCDELTA_ZERO_CLAIMED
1857	&& pGip->u32Mode == SUPGIPMODE_ASYNC_TSC
1858	&& !supdrvOSGetForcedAsyncTscMode(pDevExt)))
1859	{
1860	OSDBGPRINT(("supdrvGipCreate: Host-OS/user claims the TSC-deltas are zero but we detected async. TSC! Bad.\n"));
1861	return VERR_INTERNAL_ERROR_2;
1862	}
1863
1864	/* It doesn't make sense to do TSC-delta detection on systems we detect as async. */
1865	AssertReturn( pGip->u32Mode != SUPGIPMODE_ASYNC_TSC
1866	\|\| pGip->enmUseTscDelta <= SUPGIPUSETSCDELTA_ZERO_CLAIMED, VERR_INTERNAL_ERROR_3);
1867
1868	/*
1869	* Do the TSC frequency measurements.
1870	*
1871	* If we're in invariant TSC mode, just to a quick preliminary measurement
1872	* that the TSC-delta measurement code can use to yield cross calls.
1873	*
1874	* If we're in any of the other two modes, neither which require MP init,
1875	* notifications or deltas for the job, do the full measurement now so
1876	* that supdrvGipInitOnCpu() can populate the TSC interval and history
1877	* array with more reasonable values.
1878	*/
1879	if (pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC)
1880	{
1881	rc = supdrvGipInitMeasureTscFreq(pDevExt, pGip, true /fRough/); /* cannot fail */
1882	supdrvGipInitStartTimerForRefiningInvariantTscFreq(pDevExt, pGip);
1883	}
1884	else
1885	rc = supdrvGipInitMeasureTscFreq(pDevExt, pGip, false /fRough/);
1886	if (RT_SUCCESS(rc))
1887	{
1888	/*
1889	* Start TSC-delta measurement thread before we start getting MP
1890	* events that will try kick it into action (includes the
1891	* RTMpOnAll/supdrvGipInitOnCpu call below).
1892	*/
1893	RTCpuSetEmpty(&pDevExt->TscDeltaCpuSet);
1894	RTCpuSetEmpty(&pDevExt->TscDeltaObtainedCpuSet);
1895	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1896	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1897	rc = supdrvTscDeltaThreadInit(pDevExt);
1898	#endif
1899	if (RT_SUCCESS(rc))
1900	{
1901	rc = RTMpNotificationRegister(supdrvGipMpEvent, pDevExt);
1902	if (RT_SUCCESS(rc))
1903	{
1904	/*
1905	* Do GIP initialization on all online CPUs. Wake up the
1906	* TSC-delta thread afterwards.
1907	*/
1908	rc = RTMpOnAll(supdrvGipInitOnCpu, pDevExt, pGip);
1909	if (RT_SUCCESS(rc))
1910	{
1911	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
1912	supdrvTscDeltaThreadStartMeasurement(pDevExt, true /* fForceAll */);
1913	#else
1914	uint16_t iCpu;
1915	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
1916	{
1917	/*
1918	* Measure the TSC deltas now that we have MP notifications.
1919	*/
1920	int cTries = 5;
1921	do
1922	{
1923	rc = supdrvMeasureInitialTscDeltas(pDevExt);
1924	if ( rc != VERR_TRY_AGAIN
1925	&& rc != VERR_CPU_OFFLINE)
1926	break;
1927	} while (--cTries > 0);
1928	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
1929	Log(("supdrvTscDeltaInit: cpu[%u] delta %lld\n", iCpu, pGip->aCPUs[iCpu].i64TSCDelta));
1930	}
1931	else
1932	{
1933	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
1934	AssertMsg(!pGip->aCPUs[iCpu].i64TSCDelta, ("iCpu=%u %lld mode=%d\n", iCpu, pGip->aCPUs[iCpu].i64TSCDelta, pGip->u32Mode));
1935	}
1936	if (RT_SUCCESS(rc))
1937	#endif
1938	{
1939	/*
1940	* Create the timer.
1941	* If CPU_ALL isn't supported we'll have to fall back to synchronous mode.
1942	*/
1943	if (pGip->u32Mode == SUPGIPMODE_ASYNC_TSC)
1944	{
1945	rc = RTTimerCreateEx(&pDevExt->pGipTimer, u32Interval, RTTIMER_FLAGS_CPU_ALL,
1946	supdrvGipAsyncTimer, pDevExt);
1947	if (rc == VERR_NOT_SUPPORTED)
1948	{
1949	OSDBGPRINT(("supdrvGipCreate: omni timer not supported, falling back to synchronous mode\n"));
1950	pGip->u32Mode = SUPGIPMODE_SYNC_TSC;
1951	}
1952	}
1953	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
1954	rc = RTTimerCreateEx(&pDevExt->pGipTimer, u32Interval, 0 /* fFlags */,
1955	supdrvGipSyncAndInvariantTimer, pDevExt);
1956	if (RT_SUCCESS(rc))
1957	{
1958	/*
1959	* We're good.
1960	*/
1961	Log(("supdrvGipCreate: %u ns interval.\n", u32Interval));
1962	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
1963
1964	g_pSUPGlobalInfoPage = pGip;
1965	return VINF_SUCCESS;
1966	}
1967
1968	OSDBGPRINT(("supdrvGipCreate: failed create GIP timer at %u ns interval. rc=%Rrc\n", u32Interval, rc));
1969	Assert(!pDevExt->pGipTimer);
1970	}
1971	}
1972	else
1973	OSDBGPRINT(("supdrvGipCreate: RTMpOnAll failed. rc=%Rrc\n", rc));
1974	}
1975	else
1976	OSDBGPRINT(("supdrvGipCreate: failed to register MP event notfication. rc=%Rrc\n", rc));
1977	}
1978	else
1979	OSDBGPRINT(("supdrvGipCreate: supdrvTscDeltaInit failed. rc=%Rrc\n", rc));
1980	}
1981	else
1982	OSDBGPRINT(("supdrvGipCreate: supdrvMeasureInitialTscDeltas failed. rc=%Rrc\n", rc));
1983
1984	/* Releases timer frequency increase too. */
1985	supdrvGipDestroy(pDevExt);
1986	return rc;
1987	}
1988
1989
1990	/**
1991	* Invalidates the GIP data upon termination.
1992	*
1993	* @param pGip Pointer to the read-write kernel mapping of the GIP.
1994	*/
1995	static void supdrvGipTerm(PSUPGLOBALINFOPAGE pGip)
1996	{
1997	unsigned i;
1998	pGip->u32Magic = 0;
1999	for (i = 0; i < pGip->cCpus; i++)
2000	{
2001	pGip->aCPUs[i].u64NanoTS = 0;
2002	pGip->aCPUs[i].u64TSC = 0;
2003	pGip->aCPUs[i].iTSCHistoryHead = 0;
2004	pGip->aCPUs[i].u64TSCSample = 0;
2005	pGip->aCPUs[i].i64TSCDelta = INT64_MAX;
2006	}
2007	}
2008
2009
2010	/**
2011	* Terminates the GIP.
2012	*
2013	* @param pDevExt Instance data. GIP stuff may be updated.
2014	*/
2015	void VBOXCALL supdrvGipDestroy(PSUPDRVDEVEXT pDevExt)
2016	{
2017	int rc;
2018	#ifdef DEBUG_DARWIN_GIP
2019	OSDBGPRINT(("supdrvGipDestroy: pDevExt=%p pGip=%p pGipTimer=%p GipMemObj=%p\n", pDevExt,
2020	pDevExt->GipMemObj != NIL_RTR0MEMOBJ ? RTR0MemObjAddress(pDevExt->GipMemObj) : NULL,
2021	pDevExt->pGipTimer, pDevExt->GipMemObj));
2022	#endif
2023
2024	/*
2025	* Stop receiving MP notifications before tearing anything else down.
2026	*/
2027	RTMpNotificationDeregister(supdrvGipMpEvent, pDevExt);
2028
2029	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
2030	/*
2031	* Terminate the TSC-delta measurement thread and resources.
2032	*/
2033	supdrvTscDeltaTerm(pDevExt);
2034	#endif
2035
2036	/*
2037	* Destroy the TSC-refinement timer.
2038	*/
2039	if (pDevExt->pInvarTscRefineTimer)
2040	{
2041	RTTimerDestroy(pDevExt->pInvarTscRefineTimer);
2042	pDevExt->pInvarTscRefineTimer = NULL;
2043	}
2044
2045	/*
2046	* Invalid the GIP data.
2047	*/
2048	if (pDevExt->pGip)
2049	{
2050	supdrvGipTerm(pDevExt->pGip);
2051	pDevExt->pGip = NULL;
2052	}
2053	g_pSUPGlobalInfoPage = NULL;
2054
2055	/*
2056	* Destroy the timer and free the GIP memory object.
2057	*/
2058	if (pDevExt->pGipTimer)
2059	{
2060	rc = RTTimerDestroy(pDevExt->pGipTimer); AssertRC(rc);
2061	pDevExt->pGipTimer = NULL;
2062	}
2063
2064	if (pDevExt->GipMemObj != NIL_RTR0MEMOBJ)
2065	{
2066	rc = RTR0MemObjFree(pDevExt->GipMemObj, true /* free mappings */); AssertRC(rc);
2067	pDevExt->GipMemObj = NIL_RTR0MEMOBJ;
2068	}
2069
2070	/*
2071	* Finally, make sure we've release the system timer resolution request
2072	* if one actually succeeded and is still pending.
2073	*/
2074	supdrvGipReleaseHigherTimerFrequencyFromSystem(pDevExt);
2075	}
2076
2077
2078
2079
2080	/*
2081	*
2082	*
2083	* GIP Update Timer Related Code
2084	* GIP Update Timer Related Code
2085	* GIP Update Timer Related Code
2086	*
2087	*
2088	*/
2089
2090
2091	/**
2092	* Worker routine for supdrvGipUpdate() and supdrvGipUpdatePerCpu() that
2093	* updates all the per cpu data except the transaction id.
2094	*
2095	* @param pDevExt The device extension.
2096	* @param pGipCpu Pointer to the per cpu data.
2097	* @param u64NanoTS The current time stamp.
2098	* @param u64TSC The current TSC.
2099	* @param iTick The current timer tick.
2100	*
2101	* @remarks Can be called with interrupts disabled!
2102	*/
2103	static void supdrvGipDoUpdateCpu(PSUPDRVDEVEXT pDevExt, PSUPGIPCPU pGipCpu, uint64_t u64NanoTS, uint64_t u64TSC, uint64_t iTick)
2104	{
2105	uint64_t u64TSCDelta;
2106	bool fUpdateCpuHz;
2107	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2108	AssertPtrReturnVoid(pGip);
2109
2110	/* Delta between this and the previous update. */
2111	ASMAtomicUoWriteU32(&pGipCpu->u32PrevUpdateIntervalNS, (uint32_t)(u64NanoTS - pGipCpu->u64NanoTS));
2112
2113	/*
2114	* Update the NanoTS.
2115	*/
2116	ASMAtomicWriteU64(&pGipCpu->u64NanoTS, u64NanoTS);
2117
2118	/*
2119	* Calc TSC delta.
2120	*/
2121	u64TSCDelta = u64TSC - pGipCpu->u64TSC;
2122	ASMAtomicWriteU64(&pGipCpu->u64TSC, u64TSC);
2123
2124	/*
2125	* Determine if we need to update the CPU (TSC) frequency calculation.
2126	*
2127	* We don't need to keep recalculating the frequency when it's invariant,
2128	* unless the special tstGIP-2 testing mode is enabled.
2129	*/
2130	fUpdateCpuHz = pGip->u32Mode != SUPGIPMODE_INVARIANT_TSC;
2131	if (!(pGip->fFlags & SUPGIP_FLAGS_TESTING))
2132	{ /* likely*/ }
2133	else
2134	{
2135	uint32_t fGipFlags = pGip->fFlags;
2136	if (fGipFlags & (SUPGIP_FLAGS_TESTING_ENABLE \| SUPGIP_FLAGS_TESTING_START))
2137	{
2138	if (fGipFlags & SUPGIP_FLAGS_TESTING_START)
2139	{
2140	/* Cache the TSC frequency before forcing updates due to test mode. */
2141	if (!fUpdateCpuHz)
2142	pDevExt->uGipTestModeInvariantCpuHz = pGip->aCPUs[0].u64CpuHz;
2143	ASMAtomicAndU32(&pGip->fFlags, ~SUPGIP_FLAGS_TESTING_START);
2144	}
2145	fUpdateCpuHz = true;
2146	}
2147	else if (fGipFlags & SUPGIP_FLAGS_TESTING_STOP)
2148	{
2149	/* Restore the cached TSC frequency if any. */
2150	if (!fUpdateCpuHz)
2151	{
2152	Assert(pDevExt->uGipTestModeInvariantCpuHz);
2153	ASMAtomicWriteU64(&pGip->aCPUs[0].u64CpuHz, pDevExt->uGipTestModeInvariantCpuHz);
2154	}
2155	ASMAtomicAndU32(&pGip->fFlags, ~(SUPGIP_FLAGS_TESTING_STOP \| SUPGIP_FLAGS_TESTING));
2156	}
2157	}
2158
2159	/*
2160	* Calculate the CPU (TSC) frequency if necessary.
2161	*/
2162	if (fUpdateCpuHz)
2163	{
2164	uint64_t u64CpuHz;
2165	uint32_t u32UpdateIntervalTSC;
2166	uint32_t u32UpdateIntervalTSCSlack;
2167	uint32_t u32TransactionId;
2168	unsigned iTSCHistoryHead;
2169
2170	if (u64TSCDelta >> 32)
2171	{
2172	u64TSCDelta = pGipCpu->u32UpdateIntervalTSC;
2173	pGipCpu->cErrors++;
2174	}
2175
2176	/*
2177	* On the 2nd and 3rd callout, reset the history with the current TSC
2178	* interval since the values entered by supdrvGipInit are totally off.
2179	* The interval on the 1st callout completely unreliable, the 2nd is a bit
2180	* better, while the 3rd should be most reliable.
2181	*/
2182	/** @todo Could we drop this now that we initializes the history
2183	* with nominal TSC frequency values? */
2184	u32TransactionId = pGipCpu->u32TransactionId;
2185	if (RT_UNLIKELY( ( u32TransactionId == 5
2186	\|\| u32TransactionId == 7)
2187	&& ( iTick == 2
2188	\|\| iTick == 3) ))
2189	{
2190	unsigned i;
2191	for (i = 0; i < RT_ELEMENTS(pGipCpu->au32TSCHistory); i++)
2192	ASMAtomicUoWriteU32(&pGipCpu->au32TSCHistory[i], (uint32_t)u64TSCDelta);
2193	}
2194
2195	/*
2196	* Validate the NanoTS deltas between timer fires with an arbitrary threshold of 0.5%.
2197	* Wait until we have at least one full history since the above history reset. The
2198	* assumption is that the majority of the previous history values will be tolerable.
2199	* See @bugref{6710#c67}.
2200	*/
2201	/** @todo Could we drop the fudging there now that we initializes the history
2202	* with nominal TSC frequency values? */
2203	if ( u32TransactionId > 23 /* 7 + (8 * 2) */
2204	&& pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
2205	{
2206	uint32_t uNanoTsThreshold = pGip->u32UpdateIntervalNS / 200;
2207	if ( pGipCpu->u32PrevUpdateIntervalNS > pGip->u32UpdateIntervalNS + uNanoTsThreshold
2208	\|\| pGipCpu->u32PrevUpdateIntervalNS < pGip->u32UpdateIntervalNS - uNanoTsThreshold)
2209	{
2210	uint32_t u32;
2211	u32 = pGipCpu->au32TSCHistory[0];
2212	u32 += pGipCpu->au32TSCHistory[1];
2213	u32 += pGipCpu->au32TSCHistory[2];
2214	u32 += pGipCpu->au32TSCHistory[3];
2215	u32 >>= 2;
2216	u64TSCDelta = pGipCpu->au32TSCHistory[4];
2217	u64TSCDelta += pGipCpu->au32TSCHistory[5];
2218	u64TSCDelta += pGipCpu->au32TSCHistory[6];
2219	u64TSCDelta += pGipCpu->au32TSCHistory[7];
2220	u64TSCDelta >>= 2;
2221	u64TSCDelta += u32;
2222	u64TSCDelta >>= 1;
2223	}
2224	}
2225
2226	/*
2227	* TSC History.
2228	*/
2229	Assert(RT_ELEMENTS(pGipCpu->au32TSCHistory) == 8);
2230	iTSCHistoryHead = (pGipCpu->iTSCHistoryHead + 1) & 7;
2231	ASMAtomicWriteU32(&pGipCpu->iTSCHistoryHead, iTSCHistoryHead);
2232	ASMAtomicWriteU32(&pGipCpu->au32TSCHistory[iTSCHistoryHead], (uint32_t)u64TSCDelta);
2233
2234	/*
2235	* UpdateIntervalTSC = average of last 8,2,1 intervals depending on update HZ.
2236	*
2237	* On Windows, we have an occasional (but recurring) sour value that messed up
2238	* the history but taking only 1 interval reduces the precision overall.
2239	*/
2240	if ( pGip->u32Mode == SUPGIPMODE_INVARIANT_TSC
2241	\|\| pGip->u32UpdateHz >= 1000)
2242	{
2243	uint32_t u32;
2244	u32 = pGipCpu->au32TSCHistory[0];
2245	u32 += pGipCpu->au32TSCHistory[1];
2246	u32 += pGipCpu->au32TSCHistory[2];
2247	u32 += pGipCpu->au32TSCHistory[3];
2248	u32 >>= 2;
2249	u32UpdateIntervalTSC = pGipCpu->au32TSCHistory[4];
2250	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[5];
2251	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[6];
2252	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[7];
2253	u32UpdateIntervalTSC >>= 2;
2254	u32UpdateIntervalTSC += u32;
2255	u32UpdateIntervalTSC >>= 1;
2256
2257	/* Value chosen for a 2GHz Athlon64 running linux 2.6.10/11. */
2258	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 14;
2259	}
2260	else if (pGip->u32UpdateHz >= 90)
2261	{
2262	u32UpdateIntervalTSC = (uint32_t)u64TSCDelta;
2263	u32UpdateIntervalTSC += pGipCpu->au32TSCHistory[(iTSCHistoryHead - 1) & 7];
2264	u32UpdateIntervalTSC >>= 1;
2265
2266	/* value chosen on a 2GHz thinkpad running windows */
2267	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 7;
2268	}
2269	else
2270	{
2271	u32UpdateIntervalTSC = (uint32_t)u64TSCDelta;
2272
2273	/* This value hasn't be checked yet.. waiting for OS/2 and 33Hz timers.. :-) */
2274	u32UpdateIntervalTSCSlack = u32UpdateIntervalTSC >> 6;
2275	}
2276	ASMAtomicWriteU32(&pGipCpu->u32UpdateIntervalTSC, u32UpdateIntervalTSC + u32UpdateIntervalTSCSlack);
2277
2278	/*
2279	* CpuHz.
2280	*/
2281	u64CpuHz = ASMMult2xU32RetU64(u32UpdateIntervalTSC, RT_NS_1SEC);
2282	u64CpuHz /= pGip->u32UpdateIntervalNS;
2283	ASMAtomicWriteU64(&pGipCpu->u64CpuHz, u64CpuHz);
2284	}
2285	}
2286
2287
2288	/**
2289	* Updates the GIP.
2290	*
2291	* @param pDevExt The device extension.
2292	* @param u64NanoTS The current nanosecond timestamp.
2293	* @param u64TSC The current TSC timestamp.
2294	* @param idCpu The CPU ID.
2295	* @param iTick The current timer tick.
2296	*
2297	* @remarks Can be called with interrupts disabled!
2298	*/
2299	static void supdrvGipUpdate(PSUPDRVDEVEXT pDevExt, uint64_t u64NanoTS, uint64_t u64TSC, RTCPUID idCpu, uint64_t iTick)
2300	{
2301	/*
2302	* Determine the relevant CPU data.
2303	*/
2304	PSUPGIPCPU pGipCpu;
2305	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2306	AssertPtrReturnVoid(pGip);
2307
2308	if (pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
2309	pGipCpu = &pGip->aCPUs[0];
2310	else
2311	{
2312	unsigned iCpu = pGip->aiCpuFromApicId[ASMGetApicId()];
2313	if (RT_UNLIKELY(iCpu >= pGip->cCpus))
2314	return;
2315	pGipCpu = &pGip->aCPUs[iCpu];
2316	if (RT_UNLIKELY(pGipCpu->idCpu != idCpu))
2317	return;
2318	}
2319
2320	/*
2321	* Start update transaction.
2322	*/
2323	if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
2324	{
2325	/* this can happen on win32 if we're taking to long and there are more CPUs around. shouldn't happen though. */
2326	AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
2327	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2328	pGipCpu->cErrors++;
2329	return;
2330	}
2331
2332	/*
2333	* Recalc the update frequency every 0x800th time.
2334	*/
2335	if ( pGip->u32Mode != SUPGIPMODE_INVARIANT_TSC /* cuz we're not recalculating the frequency on invariant hosts. */
2336	&& !(pGipCpu->u32TransactionId & (GIP_UPDATEHZ_RECALC_FREQ * 2 - 2)))
2337	{
2338	if (pGip->u64NanoTSLastUpdateHz)
2339	{
2340	#ifdef RT_ARCH_AMD64 /** @todo fix 64-bit div here to work on x86 linux. */
2341	uint64_t u64Delta = u64NanoTS - pGip->u64NanoTSLastUpdateHz;
2342	uint32_t u32UpdateHz = (uint32_t)((RT_NS_1SEC_64 * GIP_UPDATEHZ_RECALC_FREQ) / u64Delta);
2343	if (u32UpdateHz <= 2000 && u32UpdateHz >= 30)
2344	{
2345	/** @todo r=ramshankar: Changing u32UpdateHz might screw up TSC frequency
2346	* calculation on non-invariant hosts if it changes the history decision
2347	* taken in supdrvGipDoUpdateCpu(). */
2348	uint64_t u64Interval = u64Delta / GIP_UPDATEHZ_RECALC_FREQ;
2349	ASMAtomicWriteU32(&pGip->u32UpdateHz, u32UpdateHz);
2350	ASMAtomicWriteU32(&pGip->u32UpdateIntervalNS, (uint32_t)u64Interval);
2351	}
2352	#endif
2353	}
2354	ASMAtomicWriteU64(&pGip->u64NanoTSLastUpdateHz, u64NanoTS \| 1);
2355	}
2356
2357	/*
2358	* Update the data.
2359	*/
2360	supdrvGipDoUpdateCpu(pDevExt, pGipCpu, u64NanoTS, u64TSC, iTick);
2361
2362	/*
2363	* Complete transaction.
2364	*/
2365	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2366	}
2367
2368
2369	/**
2370	* Updates the per cpu GIP data for the calling cpu.
2371	*
2372	* @param pDevExt The device extension.
2373	* @param u64NanoTS The current nanosecond timestamp.
2374	* @param u64TSC The current TSC timesaver.
2375	* @param idCpu The CPU ID.
2376	* @param idApic The APIC id for the CPU index.
2377	* @param iTick The current timer tick.
2378	*
2379	* @remarks Can be called with interrupts disabled!
2380	*/
2381	static void supdrvGipUpdatePerCpu(PSUPDRVDEVEXT pDevExt, uint64_t u64NanoTS, uint64_t u64TSC,
2382	RTCPUID idCpu, uint8_t idApic, uint64_t iTick)
2383	{
2384	uint32_t iCpu;
2385	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2386
2387	/*
2388	* Avoid a potential race when a CPU online notification doesn't fire on
2389	* the onlined CPU but the tick creeps in before the event notification is
2390	* run.
2391	*/
2392	if (RT_UNLIKELY(iTick == 1))
2393	{
2394	iCpu = supdrvGipFindOrAllocCpuIndexForCpuId(pGip, idCpu);
2395	if (pGip->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_OFFLINE)
2396	supdrvGipMpEventOnlineOrInitOnCpu(pDevExt, idCpu);
2397	}
2398
2399	iCpu = pGip->aiCpuFromApicId[idApic];
2400	if (RT_LIKELY(iCpu < pGip->cCpus))
2401	{
2402	PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
2403	if (pGipCpu->idCpu == idCpu)
2404	{
2405	/*
2406	* Start update transaction.
2407	*/
2408	if (!(ASMAtomicIncU32(&pGipCpu->u32TransactionId) & 1))
2409	{
2410	AssertMsgFailed(("Invalid transaction id, %#x, not odd!\n", pGipCpu->u32TransactionId));
2411	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2412	pGipCpu->cErrors++;
2413	return;
2414	}
2415
2416	/*
2417	* Update the data.
2418	*/
2419	supdrvGipDoUpdateCpu(pDevExt, pGipCpu, u64NanoTS, u64TSC, iTick);
2420
2421	/*
2422	* Complete transaction.
2423	*/
2424	ASMAtomicIncU32(&pGipCpu->u32TransactionId);
2425	}
2426	}
2427	}
2428
2429
2430	/**
2431	* Timer callback function for the sync and invariant GIP modes.
2432	*
2433	* @param pTimer The timer.
2434	* @param pvUser Opaque pointer to the device extension.
2435	* @param iTick The timer tick.
2436	*/
2437	static DECLCALLBACK(void) supdrvGipSyncAndInvariantTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
2438	{
2439	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
2440	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
2441	RTCCUINTREG fEFlags = ASMIntDisableFlags(); /* No interruptions please (real problem on S10). */
2442	uint64_t u64TSC = ASMReadTSC();
2443	uint64_t u64NanoTS = RTTimeSystemNanoTS();
2444
2445	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO)
2446	{
2447	/*
2448	* The calculations in supdrvGipUpdate() is somewhat timing sensitive,
2449	* missing timer ticks is not an option for GIP because the GIP users
2450	* will end up incrementing the time in 1ns per time getter call until
2451	* there is a complete timer update. So, if the delta has yet to be
2452	* calculated, we just pretend it is zero for now (the GIP users
2453	* probably won't have it for a wee while either and will do the same).
2454	*
2455	* We could maybe on some platforms try cross calling a CPU with a
2456	* working delta here, but it's not worth the hassle since the
2457	* likelihood of this happening is really low. On Windows, Linux, and
2458	* Solaris timers fire on the CPU they were registered/started on.
2459	* Darwin timers doesn't necessarily (they are high priority threads).
2460	*/
2461	uint32_t iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
2462	uint16_t iGipCpu = RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx))
2463	? pGip->aiCpuFromCpuSetIdx[iCpuSet] : UINT16_MAX;
2464	Assert(!ASMIntAreEnabled());
2465	if (RT_LIKELY(iGipCpu < pGip->cCpus))
2466	{
2467	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
2468	if (iTscDelta != INT64_MAX)
2469	u64TSC -= iTscDelta;
2470	}
2471	}
2472
2473	supdrvGipUpdate(pDevExt, u64NanoTS, u64TSC, NIL_RTCPUID, iTick);
2474
2475	ASMSetFlags(fEFlags);
2476	}
2477
2478
2479	/**
2480	* Timer callback function for async GIP mode.
2481	* @param pTimer The timer.
2482	* @param pvUser Opaque pointer to the device extension.
2483	* @param iTick The timer tick.
2484	*/
2485	static DECLCALLBACK(void) supdrvGipAsyncTimer(PRTTIMER pTimer, void *pvUser, uint64_t iTick)
2486	{
2487	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
2488	RTCCUINTREG fEFlags = ASMIntDisableFlags(); /* No interruptions please (real problem on S10). */
2489	RTCPUID idCpu = RTMpCpuId();
2490	uint64_t u64TSC = ASMReadTSC();
2491	uint64_t NanoTS = RTTimeSystemNanoTS();
2492
2493	/** @todo reset the transaction number and whatnot when iTick == 1. */
2494	if (pDevExt->idGipMaster == idCpu)
2495	supdrvGipUpdate(pDevExt, NanoTS, u64TSC, idCpu, iTick);
2496	else
2497	supdrvGipUpdatePerCpu(pDevExt, NanoTS, u64TSC, idCpu, ASMGetApicId(), iTick);
2498
2499	ASMSetFlags(fEFlags);
2500	}
2501
2502
2503
2504
2505	/*
2506	*
2507	*
2508	* TSC Delta Measurements And Related Code
2509	* TSC Delta Measurements And Related Code
2510	* TSC Delta Measurements And Related Code
2511	*
2512	*
2513	*/
2514
2515
2516	/*
2517	* Select TSC delta measurement algorithm.
2518	*/
2519	#if 0
2520	# define GIP_TSC_DELTA_METHOD_1
2521	#else
2522	# define GIP_TSC_DELTA_METHOD_2
2523	#endif
2524
2525	/** For padding variables to keep them away from other cache lines. Better too
2526	* large than too small!
2527	* @remarks Current AMD64 and x86 CPUs seems to use 64 bytes. There are claims
2528	* that NetBurst had 128 byte cache lines while the 486 thru Pentium
2529	* III had 32 bytes cache lines. */
2530	#define GIP_TSC_DELTA_CACHE_LINE_SIZE 128
2531
2532
2533	/**
2534	* TSC delta measurement algorithm \#2 result entry.
2535	*/
2536	typedef struct SUPDRVTSCDELTAMETHOD2ENTRY
2537	{
2538	uint32_t iSeqMine;
2539	uint32_t iSeqOther;
2540	uint64_t uTsc;
2541	} SUPDRVTSCDELTAMETHOD2ENTRY;
2542
2543	/**
2544	* TSC delta measurement algorithm \#2 Data.
2545	*/
2546	typedef struct SUPDRVTSCDELTAMETHOD2
2547	{
2548	/** Padding to make sure the iCurSeqNo is in its own cache line. */
2549	uint64_t au64CacheLinePaddingBefore[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2550	/** The current sequence number of this worker. */
2551	uint32_t volatile iCurSeqNo;
2552	/** Padding to make sure the iCurSeqNo is in its own cache line. */
2553	uint32_t au64CacheLinePaddingAfter[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint32_t) - 1];
2554	/** Result table. */
2555	SUPDRVTSCDELTAMETHOD2ENTRY aResults[64];
2556	} SUPDRVTSCDELTAMETHOD2;
2557	/** Pointer to the data for TSC delta measurement algorithm \#2 .*/
2558	typedef SUPDRVTSCDELTAMETHOD2 *PSUPDRVTSCDELTAMETHOD2;
2559
2560
2561	/**
2562	* The TSC delta synchronization struct, version 2.
2563	*
2564	* The synchronization variable is completely isolated in its own cache line
2565	* (provided our max cache line size estimate is correct).
2566	*/
2567	typedef struct SUPTSCDELTASYNC2
2568	{
2569	/** Padding to make sure the uVar1 is in its own cache line. */
2570	uint64_t au64CacheLinePaddingBefore[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2571
2572	/** The synchronization variable, holds values GIP_TSC_DELTA_SYNC_. /
2573	volatile uint32_t uSyncVar;
2574	/** Sequence synchronizing variable used for post 'GO' synchronization. */
2575	volatile uint32_t uSyncSeq;
2576
2577	/** Padding to make sure the uVar1 is in its own cache line. */
2578	uint64_t au64CacheLinePaddingAfter[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t) - 2];
2579
2580	/** Start RDTSC value. Put here mainly to save stack space. */
2581	uint64_t uTscStart;
2582	/** Copy of SUPDRVGIPTSCDELTARGS::cMaxTscTicks. */
2583	uint64_t cMaxTscTicks;
2584	} SUPTSCDELTASYNC2;
2585	AssertCompileSize(SUPTSCDELTASYNC2, GIP_TSC_DELTA_CACHE_LINE_SIZE * 2 + sizeof(uint64_t));
2586	typedef SUPTSCDELTASYNC2 *PSUPTSCDELTASYNC2;
2587
2588	/** Prestart wait. */
2589	#define GIP_TSC_DELTA_SYNC2_PRESTART_WAIT UINT32_C(0x0ffe)
2590	/** Prestart aborted. */
2591	#define GIP_TSC_DELTA_SYNC2_PRESTART_ABORT UINT32_C(0x0fff)
2592	/** Ready (on your mark). */
2593	#define GIP_TSC_DELTA_SYNC2_READY UINT32_C(0x1000)
2594	/** Steady (get set). */
2595	#define GIP_TSC_DELTA_SYNC2_STEADY UINT32_C(0x1001)
2596	/** Go! */
2597	#define GIP_TSC_DELTA_SYNC2_GO UINT32_C(0x1002)
2598	/** Used by the verification test. */
2599	#define GIP_TSC_DELTA_SYNC2_GO_GO UINT32_C(0x1003)
2600
2601	/** We reached the time limit. */
2602	#define GIP_TSC_DELTA_SYNC2_TIMEOUT UINT32_C(0x1ffe)
2603	/** The other party won't touch the sync struct ever again. */
2604	#define GIP_TSC_DELTA_SYNC2_FINAL UINT32_C(0x1fff)
2605
2606
2607	/**
2608	* Argument package/state passed by supdrvMeasureTscDeltaOne() to the RTMpOn
2609	* callback worker.
2610	* @todo add
2611	*/
2612	typedef struct SUPDRVGIPTSCDELTARGS
2613	{
2614	/** The device extension. */
2615	PSUPDRVDEVEXT pDevExt;
2616	/** Pointer to the GIP CPU array entry for the worker. */
2617	PSUPGIPCPU pWorker;
2618	/** Pointer to the GIP CPU array entry for the master. */
2619	PSUPGIPCPU pMaster;
2620	/** The maximum number of ticks to spend in supdrvMeasureTscDeltaCallback.
2621	* (This is what we need a rough TSC frequency for.) */
2622	uint64_t cMaxTscTicks;
2623	/** Used to abort synchronization setup. */
2624	bool volatile fAbortSetup;
2625
2626	/** Padding to make sure the master variables live in its own cache lines. */
2627	uint64_t au64CacheLinePaddingBefore[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2628
2629	/** @name Master
2630	* @{ */
2631	/** The time the master spent in the MP worker. */
2632	uint64_t cElapsedMasterTscTicks;
2633	/** The iTry value when stopped at. */
2634	uint32_t iTry;
2635	/** Set if the run timed out. */
2636	bool volatile fTimedOut;
2637	/** Pointer to the master's synchronization struct (on stack). */
2638	PSUPTSCDELTASYNC2 volatile pSyncMaster;
2639	/** Master data union. */
2640	union
2641	{
2642	/** Data (master) for delta verification. */
2643	struct
2644	{
2645	/** Verification test TSC values for the master. */
2646	uint64_t volatile auTscs[32];
2647	} Verify;
2648	/** Data (master) for measurement method \#2. */
2649	struct
2650	{
2651	/** Data and sequence number. */
2652	SUPDRVTSCDELTAMETHOD2 Data;
2653	/** The lag setting for the next run. */
2654	bool fLag;
2655	/** Number of hits. */
2656	uint32_t cHits;
2657	} M2;
2658	} uMaster;
2659	/** The verifier verdict, VINF_SUCCESS if ok, VERR_OUT_OF_RANGE if not,
2660	* VERR_TRY_AGAIN on timeout. */
2661	int32_t rcVerify;
2662	#ifdef TSCDELTA_VERIFY_WITH_STATS
2663	/** The maximum difference between TSC read during delta verification. */
2664	int64_t cMaxVerifyTscTicks;
2665	/** The minimum difference between two TSC reads during verification. */
2666	int64_t cMinVerifyTscTicks;
2667	/** The bad TSC diff, worker relative to master (= worker - master).
2668	* Negative value means the worker is behind the master. */
2669	int64_t iVerifyBadTscDiff;
2670	#endif
2671	/** @} */
2672
2673	/** Padding to make sure the worker variables live is in its own cache line. */
2674	uint64_t au64CacheLinePaddingBetween[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2675
2676	/** @name Proletarian
2677	* @{ */
2678	/** Pointer to the worker's synchronization struct (on stack). */
2679	PSUPTSCDELTASYNC2 volatile pSyncWorker;
2680	/** The time the worker spent in the MP worker. */
2681	uint64_t cElapsedWorkerTscTicks;
2682	/** Worker data union. */
2683	union
2684	{
2685	/** Data (worker) for delta verification. */
2686	struct
2687	{
2688	/** Verification test TSC values for the worker. */
2689	uint64_t volatile auTscs[32];
2690	} Verify;
2691	/** Data (worker) for measurement method \#2. */
2692	struct
2693	{
2694	/** Data and sequence number. */
2695	SUPDRVTSCDELTAMETHOD2 Data;
2696	/** The lag setting for the next run (set by master). */
2697	bool fLag;
2698	} M2;
2699	} uWorker;
2700	/** @} */
2701
2702	/** Padding to make sure the above is in its own cache line. */
2703	uint64_t au64CacheLinePaddingAfter[GIP_TSC_DELTA_CACHE_LINE_SIZE / sizeof(uint64_t)];
2704	} SUPDRVGIPTSCDELTARGS;
2705	typedef SUPDRVGIPTSCDELTARGS *PSUPDRVGIPTSCDELTARGS;
2706
2707
2708	/** @name Macros that implements the basic synchronization steps common to
2709	* the algorithms.
2710	*
2711	* Must be used from loop as the timeouts are implemented via 'break' statements
2712	* at the moment.
2713	*
2714	* @{
2715	*/
2716	#if defined(DEBUG_bird) /* \|\| defined(VBOX_STRICT) */
2717	# define TSCDELTA_DBG_VARS() uint32_t iDbgCounter
2718	# define TSCDELTA_DBG_START_LOOP() do { iDbgCounter = 0; } while (0)
2719	# define TSCDELTA_DBG_CHECK_LOOP() \
2720	do { iDbgCounter++; if ((iDbgCounter & UINT32_C(0x01ffffff)) == 0) RT_BREAKPOINT(); } while (0)
2721	#else
2722	# define TSCDELTA_DBG_VARS() ((void)0)
2723	# define TSCDELTA_DBG_START_LOOP() ((void)0)
2724	# define TSCDELTA_DBG_CHECK_LOOP() ((void)0)
2725	#endif
2726	#if 0
2727	# define TSCDELTA_DBG_SYNC_MSG(a_Args) SUPR0Printf a_Args
2728	#else
2729	# define TSCDELTA_DBG_SYNC_MSG(a_Args) ((void)0)
2730	#endif
2731	#if 0
2732	# define TSCDELTA_DBG_SYNC_MSG2(a_Args) SUPR0Printf a_Args
2733	#else
2734	# define TSCDELTA_DBG_SYNC_MSG2(a_Args) ((void)0)
2735	#endif
2736	#if 0
2737	# define TSCDELTA_DBG_SYNC_MSG9(a_Args) SUPR0Printf a_Args
2738	#else
2739	# define TSCDELTA_DBG_SYNC_MSG9(a_Args) ((void)0)
2740	#endif
2741
2742
2743	static bool supdrvTscDeltaSync2_Before(PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync,
2744	bool fIsMaster, PRTCCUINTREG pfEFlags, PSUPDRVGIPTSCDELTARGS pArgs)
2745	{
2746	uint32_t iMySeq = fIsMaster ? 0 : 256;
2747	uint32_t const iMaxSeq = iMySeq + 16; /* For the last loop, darn linux/freebsd C-ishness. */
2748	uint32_t u32Tmp;
2749	uint32_t iSync2Loops = 0;
2750	RTCCUINTREG fEFlags;
2751	TSCDELTA_DBG_VARS();
2752
2753	pfEFlags = X86_EFL_IF \| X86_EFL_1; / should shut up most nagging compilers. */
2754
2755	/*
2756	* The master tells the worker to get on it's mark.
2757	*/
2758	if (fIsMaster)
2759	{
2760	if (RT_LIKELY(ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_STEADY, GIP_TSC_DELTA_SYNC2_READY)))
2761	{ /* likely*/ }
2762	else
2763	{
2764	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #1 uSyncVar=%#x\n", fIsMaster ? "master" : "worker", pOtherSync->uSyncVar));
2765	return false;
2766	}
2767	}
2768
2769	/*
2770	* Wait for the on your mark signal (ack in the master case). We process timeouts here.
2771	*/
2772	ASMAtomicWriteU32(&(pMySync)->uSyncSeq, 0);
2773	for (;;)
2774	{
2775	fEFlags = ASMIntDisableFlags();
2776	u32Tmp = ASMAtomicReadU32(&pMySync->uSyncVar);
2777	if (u32Tmp == GIP_TSC_DELTA_SYNC2_STEADY)
2778	break;
2779	ASMSetFlags(fEFlags);
2780	ASMNopPause();
2781
2782	/* Abort? */
2783	if (u32Tmp != GIP_TSC_DELTA_SYNC2_READY)
2784	{
2785	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #2 u32Tmp=%#x\n", fIsMaster ? "master" : "worker", u32Tmp));
2786	return false;
2787	}
2788
2789	/* Check for timeouts every so often (not every loop in case RDTSC is
2790	trapping or something). Must check the first time around. */
2791	#if 0 /* For debugging the timeout paths. */
2792	static uint32_t volatile xxx;
2793	#endif
2794	if ( ( (iSync2Loops & 0x3ff) == 0
2795	&& ASMReadTSC() - pMySync->uTscStart > pMySync->cMaxTscTicks)
2796	#if 0 /* This is crazy, I know, but enable this code and the results are markedly better when enabled on the 1.4GHz AMD (debug). */
2797	\|\| (!fIsMaster && (++xxx & 0xf) == 0)
2798	#endif
2799	)
2800	{
2801	/* Try switch our own state into timeout mode so the master cannot tell us to 'GO',
2802	ignore the timeout if we've got the go ahead already (simpler). */
2803	if (ASMAtomicCmpXchgU32(&pMySync->uSyncVar, GIP_TSC_DELTA_SYNC2_TIMEOUT, GIP_TSC_DELTA_SYNC2_READY))
2804	{
2805	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: timeout\n", fIsMaster ? "master" : "worker"));
2806	ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_TIMEOUT, GIP_TSC_DELTA_SYNC2_STEADY);
2807	ASMAtomicWriteBool(&pArgs->fTimedOut, true);
2808	return false;
2809	}
2810	}
2811	iSync2Loops++;
2812	}
2813
2814	/*
2815	* Interrupts are now disabled and will remain disabled until we do
2816	* TSCDELTA_MASTER_SYNC_AFTER / TSCDELTA_OTHER_SYNC_AFTER.
2817	*/
2818	*pfEFlags = fEFlags;
2819
2820	/*
2821	* The worker tells the master that it is on its mark and that the master
2822	* need to get into position as well.
2823	*/
2824	if (!fIsMaster)
2825	{
2826	if (RT_LIKELY(ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_STEADY, GIP_TSC_DELTA_SYNC2_READY)))
2827	{ /* likely */ }
2828	else
2829	{
2830	ASMSetFlags(fEFlags);
2831	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #3 uSyncVar=%#x\n", fIsMaster ? "master" : "worker", pOtherSync->uSyncVar));
2832	return false;
2833	}
2834	}
2835
2836	/*
2837	* The master sends the 'go' to the worker and wait for ACK.
2838	*/
2839	if (fIsMaster)
2840	{
2841	if (RT_LIKELY(ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO, GIP_TSC_DELTA_SYNC2_STEADY)))
2842	{ /* likely */ }
2843	else
2844	{
2845	ASMSetFlags(fEFlags);
2846	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #4 uSyncVar=%#x\n", fIsMaster ? "master" : "worker", pOtherSync->uSyncVar));
2847	return false;
2848	}
2849	}
2850
2851	/*
2852	* Wait for the 'go' signal (ack in the master case).
2853	*/
2854	TSCDELTA_DBG_START_LOOP();
2855	for (;;)
2856	{
2857	u32Tmp = ASMAtomicReadU32(&pMySync->uSyncVar);
2858	if (u32Tmp == GIP_TSC_DELTA_SYNC2_GO)
2859	break;
2860	if (RT_LIKELY(u32Tmp == GIP_TSC_DELTA_SYNC2_STEADY))
2861	{ /* likely */ }
2862	else
2863	{
2864	ASMSetFlags(fEFlags);
2865	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #5 u32Tmp=%#x\n", fIsMaster ? "master" : "worker", u32Tmp));
2866	return false;
2867	}
2868
2869	TSCDELTA_DBG_CHECK_LOOP();
2870	ASMNopPause();
2871	}
2872
2873	/*
2874	* The worker acks the 'go' (shouldn't fail).
2875	*/
2876	if (!fIsMaster)
2877	{
2878	if (RT_LIKELY(ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO, GIP_TSC_DELTA_SYNC2_STEADY)))
2879	{ /* likely */ }
2880	else
2881	{
2882	ASMSetFlags(fEFlags);
2883	TSCDELTA_DBG_SYNC_MSG(("sync/before/%s: #6 uSyncVar=%#x\n", fIsMaster ? "master" : "worker", pOtherSync->uSyncVar));
2884	return false;
2885	}
2886	}
2887
2888	/*
2889	* Try enter mostly lockstep execution with it.
2890	*/
2891	for (;;)
2892	{
2893	uint32_t iOtherSeq1, iOtherSeq2;
2894	ASMCompilerBarrier();
2895	ASMSerializeInstruction();
2896
2897	ASMAtomicWriteU32(&pMySync->uSyncSeq, iMySeq);
2898	ASMNopPause();
2899	iOtherSeq1 = ASMAtomicXchgU32(&pOtherSync->uSyncSeq, iMySeq);
2900	ASMNopPause();
2901	iOtherSeq2 = ASMAtomicReadU32(&pMySync->uSyncSeq);
2902
2903	ASMCompilerBarrier();
2904	if (iOtherSeq1 == iOtherSeq2)
2905	return true;
2906
2907	/* Did the other guy give up? Should we give up? */
2908	if ( iOtherSeq1 == UINT32_MAX
2909	\|\| iOtherSeq2 == UINT32_MAX)
2910	return true;
2911	if (++iMySeq >= iMaxSeq)
2912	{
2913	ASMAtomicWriteU32(&pMySync->uSyncSeq, UINT32_MAX);
2914	return true;
2915	}
2916	ASMNopPause();
2917	}
2918	}
2919
2920	#define TSCDELTA_MASTER_SYNC_BEFORE(a_pMySync, a_pOtherSync, a_pfEFlags, a_pArgs) \
2921	if (RT_LIKELY(supdrvTscDeltaSync2_Before(a_pMySync, a_pOtherSync, true /fIsMaster/, a_pfEFlags, a_pArgs))) \
2922	{ /likely/ } \
2923	else if (true) \
2924	{ \
2925	TSCDELTA_DBG_SYNC_MSG9(("sync/before/master: #89\n")); \
2926	break; \
2927	} else do {} while (0)
2928	#define TSCDELTA_OTHER_SYNC_BEFORE(a_pMySync, a_pOtherSync, a_pfEFlags, a_pArgs) \
2929	if (RT_LIKELY(supdrvTscDeltaSync2_Before(a_pMySync, a_pOtherSync, false /fIsMaster/, a_pfEFlags, a_pArgs))) \
2930	{ /likely/ } \
2931	else if (true) \
2932	{ \
2933	TSCDELTA_DBG_SYNC_MSG9(("sync/before/other: #89\n")); \
2934	break; \
2935	} else do {} while (0)
2936
2937
2938	static bool supdrvTscDeltaSync2_After(PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync,
2939	bool fIsMaster, RTCCUINTREG fEFlags)
2940	{
2941	TSCDELTA_DBG_VARS();
2942
2943	/*
2944	* Wait for the 'ready' signal. In the master's case, this means the
2945	* worker has completed its data collection, while in the worker's case it
2946	* means the master is done processing the data and it's time for the next
2947	* loop iteration (or whatever).
2948	*/
2949	ASMSetFlags(fEFlags);
2950	TSCDELTA_DBG_START_LOOP();
2951	for (;;)
2952	{
2953	uint32_t u32Tmp = ASMAtomicReadU32(&pMySync->uSyncVar);
2954	if ( u32Tmp == GIP_TSC_DELTA_SYNC2_READY
2955	\|\| (u32Tmp == GIP_TSC_DELTA_SYNC2_STEADY && !fIsMaster) /* kicked twice => race */ )
2956	return true;
2957	ASMNopPause();
2958	if (RT_LIKELY(u32Tmp == GIP_TSC_DELTA_SYNC2_GO))
2959	{ /* likely */}
2960	else
2961	{
2962	TSCDELTA_DBG_SYNC_MSG(("sync/after/other: #1 u32Tmp=%#x\n", u32Tmp));
2963	return false; /* shouldn't ever happen! */
2964	}
2965	TSCDELTA_DBG_CHECK_LOOP();
2966	ASMNopPause();
2967	}
2968	}
2969
2970	#define TSCDELTA_MASTER_SYNC_AFTER(a_pMySync, a_pOtherSync, a_fEFlags) \
2971	if (RT_LIKELY(supdrvTscDeltaSync2_After(a_pMySync, a_pOtherSync, true /fIsMaster/, a_fEFlags))) \
2972	{ /* likely */ } \
2973	else if (true) \
2974	{ \
2975	TSCDELTA_DBG_SYNC_MSG9(("sync/after/master: #97\n")); \
2976	break; \
2977	} else do {} while (0)
2978
2979	#define TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(a_pMySync, a_pOtherSync) \
2980	/* \
2981	* Tell the worker that we're done processing the data and ready for the next round. \
2982	*/ \
2983	if (RT_LIKELY(ASMAtomicCmpXchgU32(&(a_pOtherSync)->uSyncVar, GIP_TSC_DELTA_SYNC2_READY, GIP_TSC_DELTA_SYNC2_GO))) \
2984	{ /* likely */ } \
2985	else if (true)\
2986	{ \
2987	TSCDELTA_DBG_SYNC_MSG(("sync/after/master: #99 uSyncVar=%#x\n", (a_pOtherSync)->uSyncVar)); \
2988	break; \
2989	} else do {} while (0)
2990
2991	#define TSCDELTA_OTHER_SYNC_AFTER(a_pMySync, a_pOtherSync, a_fEFlags) \
2992	if (true) { \
2993	/* \
2994	* Tell the master that we're done collecting data and wait for the next round to start. \
2995	*/ \
2996	if (RT_LIKELY(ASMAtomicCmpXchgU32(&(a_pOtherSync)->uSyncVar, GIP_TSC_DELTA_SYNC2_READY, GIP_TSC_DELTA_SYNC2_GO))) \
2997	{ /* likely */ } \
2998	else \
2999	{ \
3000	ASMSetFlags(a_fEFlags); \
3001	TSCDELTA_DBG_SYNC_MSG(("sync/after/other: #0 uSyncVar=%#x\n", (a_pOtherSync)->uSyncVar)); \
3002	break; \
3003	} \
3004	if (RT_LIKELY(supdrvTscDeltaSync2_After(a_pMySync, a_pOtherSync, false /fIsMaster/, a_fEFlags))) \
3005	{ /* likely */ } \
3006	else \
3007	{ \
3008	TSCDELTA_DBG_SYNC_MSG9(("sync/after/other: #98\n")); \
3009	break; \
3010	} \
3011	} else do {} while (0)
3012	/** @} */
3013
3014
3015	#ifdef GIP_TSC_DELTA_METHOD_1
3016	/**
3017	* TSC delta measurement algorithm \#1 (GIP_TSC_DELTA_METHOD_1).
3018	*
3019	*
3020	* We ignore the first few runs of the loop in order to prime the
3021	* cache. Also, we need to be careful about using 'pause' instruction
3022	* in critical busy-wait loops in this code - it can cause undesired
3023	* behaviour with hyperthreading.
3024	*
3025	* We try to minimize the measurement error by computing the minimum
3026	* read time of the compare statement in the worker by taking TSC
3027	* measurements across it.
3028	*
3029	* It must be noted that the computed minimum read time is mostly to
3030	* eliminate huge deltas when the worker is too early and doesn't by
3031	* itself help produce more accurate deltas. We allow two times the
3032	* computed minimum as an arbitrary acceptable threshold. Therefore,
3033	* it is still possible to get negative deltas where there are none
3034	* when the worker is earlier. As long as these occasional negative
3035	* deltas are lower than the time it takes to exit guest-context and
3036	* the OS to reschedule EMT on a different CPU, we won't expose a TSC
3037	* that jumped backwards. It is due to the existence of the negative
3038	* deltas that we don't recompute the delta with the master and
3039	* worker interchanged to eliminate the remaining measurement error.
3040	*
3041	*
3042	* @param pArgs The argument/state data.
3043	* @param pMySync My synchronization structure.
3044	* @param pOtherSync My partner's synchronization structure.
3045	* @param fIsMaster Set if master, clear if worker.
3046	* @param iTry The attempt number.
3047	*/
3048	static void supdrvTscDeltaMethod1Loop(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync,
3049	bool fIsMaster, uint32_t iTry)
3050	{
3051	PSUPGIPCPU pGipCpuWorker = pArgs->pWorker;
3052	PSUPGIPCPU pGipCpuMaster = pArgs->pMaster;
3053	uint64_t uMinCmpReadTime = UINT64_MAX;
3054	unsigned iLoop;
3055	NOREF(iTry);
3056
3057	for (iLoop = 0; iLoop < GIP_TSC_DELTA_LOOPS; iLoop++)
3058	{
3059	RTCCUINTREG fEFlags;
3060	if (fIsMaster)
3061	{
3062	/*
3063	* The master.
3064	*/
3065	AssertMsg(pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD,
3066	("%#llx idMaster=%#x idWorker=%#x (idGipMaster=%#x)\n",
3067	pGipCpuMaster->u64TSCSample, pGipCpuMaster->idCpu, pGipCpuWorker->idCpu, pArgs->pDevExt->idGipMaster));
3068	TSCDELTA_MASTER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3069
3070	do
3071	{
3072	ASMSerializeInstruction();
3073	ASMAtomicWriteU64(&pGipCpuMaster->u64TSCSample, ASMReadTSC());
3074	} while (pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD);
3075
3076	TSCDELTA_MASTER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3077
3078	/* Process the data. */
3079	if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS)
3080	{
3081	if (pGipCpuWorker->u64TSCSample != GIP_TSC_DELTA_RSVD)
3082	{
3083	int64_t iDelta = pGipCpuWorker->u64TSCSample
3084	- (pGipCpuMaster->u64TSCSample - pGipCpuMaster->i64TSCDelta);
3085	if ( iDelta >= GIP_TSC_DELTA_INITIAL_MASTER_VALUE
3086	? iDelta < pGipCpuWorker->i64TSCDelta
3087	: iDelta > pGipCpuWorker->i64TSCDelta \|\| pGipCpuWorker->i64TSCDelta == INT64_MAX)
3088	pGipCpuWorker->i64TSCDelta = iDelta;
3089	}
3090	}
3091
3092	/* Reset our TSC sample and tell the worker to move on. */
3093	ASMAtomicWriteU64(&pGipCpuMaster->u64TSCSample, GIP_TSC_DELTA_RSVD);
3094	TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(pMySync, pOtherSync);
3095	}
3096	else
3097	{
3098	/*
3099	* The worker.
3100	*/
3101	uint64_t uTscWorker;
3102	uint64_t uTscWorkerFlushed;
3103	uint64_t uCmpReadTime;
3104
3105	ASMAtomicReadU64(&pGipCpuMaster->u64TSCSample); /* Warm the cache line. */
3106	TSCDELTA_OTHER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3107
3108	/*
3109	* Keep reading the TSC until we notice that the master has read his. Reading
3110	* the TSC -after- the master has updated the memory is way too late. We thus
3111	* compensate by trying to measure how long it took for the worker to notice
3112	* the memory flushed from the master.
3113	*/
3114	do
3115	{
3116	ASMSerializeInstruction();
3117	uTscWorker = ASMReadTSC();
3118	} while (pGipCpuMaster->u64TSCSample == GIP_TSC_DELTA_RSVD);
3119	ASMSerializeInstruction();
3120	uTscWorkerFlushed = ASMReadTSC();
3121
3122	uCmpReadTime = uTscWorkerFlushed - uTscWorker;
3123	if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS + GIP_TSC_DELTA_READ_TIME_LOOPS)
3124	{
3125	/* This is totally arbitrary a.k.a I don't like it but I have no better ideas for now. */
3126	if (uCmpReadTime < (uMinCmpReadTime << 1))
3127	{
3128	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, uTscWorker);
3129	if (uCmpReadTime < uMinCmpReadTime)
3130	uMinCmpReadTime = uCmpReadTime;
3131	}
3132	else
3133	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, GIP_TSC_DELTA_RSVD);
3134	}
3135	else if (iLoop > GIP_TSC_DELTA_PRIMER_LOOPS)
3136	{
3137	if (uCmpReadTime < uMinCmpReadTime)
3138	uMinCmpReadTime = uCmpReadTime;
3139	}
3140
3141	TSCDELTA_OTHER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3142	}
3143	}
3144
3145	TSCDELTA_DBG_SYNC_MSG9(("sync/method1loop/%s: #92 iLoop=%u MyState=%#x\n", fIsMaster ? "master" : "worker", iLoop,
3146	pMySync->uSyncVar));
3147
3148	/*
3149	* We must reset the worker TSC sample value in case it gets picked as a
3150	* GIP master later on (it's trashed above, naturally).
3151	*/
3152	if (!fIsMaster)
3153	ASMAtomicWriteU64(&pGipCpuWorker->u64TSCSample, GIP_TSC_DELTA_RSVD);
3154	}
3155	#endif /* GIP_TSC_DELTA_METHOD_1 */
3156
3157
3158	#ifdef GIP_TSC_DELTA_METHOD_2
3159	/*
3160	* TSC delta measurement algorithm \#2 configuration and code - Experimental!!
3161	*/
3162
3163	# define GIP_TSC_DELTA_M2_LOOPS (7 + GIP_TSC_DELTA_M2_PRIMER_LOOPS)
3164	# define GIP_TSC_DELTA_M2_PRIMER_LOOPS 0
3165
3166
3167	static void supdrvTscDeltaMethod2ProcessDataOnMaster(PSUPDRVGIPTSCDELTARGS pArgs, uint32_t iLoop)
3168	{
3169	int64_t iMasterTscDelta = pArgs->pMaster->i64TSCDelta;
3170	int64_t iBestDelta = pArgs->pWorker->i64TSCDelta;
3171	uint32_t idxResult;
3172	uint32_t cHits = 0;
3173
3174	/*
3175	* Look for matching entries in the master and worker tables.
3176	*/
3177	for (idxResult = 0; idxResult < RT_ELEMENTS(pArgs->uMaster.M2.Data.aResults); idxResult++)
3178	{
3179	uint32_t idxOther = pArgs->uMaster.M2.Data.aResults[idxResult].iSeqOther;
3180	if (idxOther & 1)
3181	{
3182	idxOther >>= 1;
3183	if (idxOther < RT_ELEMENTS(pArgs->uWorker.M2.Data.aResults))
3184	{
3185	if (pArgs->uWorker.M2.Data.aResults[idxOther].iSeqOther == pArgs->uMaster.M2.Data.aResults[idxResult].iSeqMine)
3186	{
3187	int64_t iDelta;
3188	iDelta = pArgs->uWorker.M2.Data.aResults[idxOther].uTsc
3189	- (pArgs->uMaster.M2.Data.aResults[idxResult].uTsc - iMasterTscDelta);
3190	if ( iDelta >= GIP_TSC_DELTA_INITIAL_MASTER_VALUE
3191	? iDelta < iBestDelta
3192	: iDelta > iBestDelta \|\| iBestDelta == INT64_MAX)
3193	iBestDelta = iDelta;
3194	cHits++;
3195	}
3196	}
3197	}
3198	}
3199
3200	/*
3201	* Save the results.
3202	*/
3203	if (cHits > 2)
3204	pArgs->pWorker->i64TSCDelta = iBestDelta;
3205	pArgs->uMaster.M2.cHits += cHits;
3206	}
3207
3208
3209	/**
3210	* The core function of the 2nd TSC delta measurement algorithm.
3211	*
3212	* The idea here is that we have the two CPUs execute the exact same code
3213	* collecting a largish set of TSC samples. The code has one data dependency on
3214	* the other CPU which intention it is to synchronize the execution as well as
3215	* help cross references the two sets of TSC samples (the sequence numbers).
3216	*
3217	* The @a fLag parameter is used to modify the execution a tiny bit on one or
3218	* both of the CPUs. When @a fLag differs between the CPUs, it is thought that
3219	* it will help with making the CPUs enter lock step execution occasionally.
3220	*
3221	*/
3222	static void supdrvTscDeltaMethod2CollectData(PSUPDRVTSCDELTAMETHOD2 pMyData, uint32_t volatile *piOtherSeqNo, bool fLag)
3223	{
3224	SUPDRVTSCDELTAMETHOD2ENTRY *pEntry = &pMyData->aResults[0];
3225	uint32_t cLeft = RT_ELEMENTS(pMyData->aResults);
3226
3227	ASMAtomicWriteU32(&pMyData->iCurSeqNo, 0);
3228	ASMSerializeInstruction();
3229	while (cLeft-- > 0)
3230	{
3231	uint64_t uTsc;
3232	uint32_t iSeqMine = ASMAtomicIncU32(&pMyData->iCurSeqNo);
3233	uint32_t iSeqOther = ASMAtomicReadU32(piOtherSeqNo);
3234	ASMCompilerBarrier();
3235	ASMSerializeInstruction(); /* Way better result than with ASMMemoryFenceSSE2() in this position! */
3236	uTsc = ASMReadTSC();
3237	ASMAtomicIncU32(&pMyData->iCurSeqNo);
3238	ASMCompilerBarrier();
3239	ASMSerializeInstruction();
3240	pEntry->iSeqMine = iSeqMine;
3241	pEntry->iSeqOther = iSeqOther;
3242	pEntry->uTsc = uTsc;
3243	pEntry++;
3244	ASMSerializeInstruction();
3245	if (fLag)
3246	ASMNopPause();
3247	}
3248	}
3249
3250
3251	/**
3252	* TSC delta measurement algorithm \#2 (GIP_TSC_DELTA_METHOD_2).
3253	*
3254	* See supdrvTscDeltaMethod2CollectData for algorithm details.
3255	*
3256	* @param pArgs The argument/state data.
3257	* @param pMySync My synchronization structure.
3258	* @param pOtherSync My partner's synchronization structure.
3259	* @param fIsMaster Set if master, clear if worker.
3260	* @param iTry The attempt number.
3261	*/
3262	static void supdrvTscDeltaMethod2Loop(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC2 pMySync, PSUPTSCDELTASYNC2 pOtherSync,
3263	bool fIsMaster, uint32_t iTry)
3264	{
3265	unsigned iLoop;
3266
3267	for (iLoop = 0; iLoop < GIP_TSC_DELTA_M2_LOOPS; iLoop++)
3268	{
3269	RTCCUINTREG fEFlags;
3270	if (fIsMaster)
3271	{
3272	/*
3273	* Adjust the loop lag fudge.
3274	*/
3275	# if GIP_TSC_DELTA_M2_PRIMER_LOOPS > 0
3276	if (iLoop < GIP_TSC_DELTA_M2_PRIMER_LOOPS)
3277	{
3278	/* Lag during the priming to be nice to everyone.. */
3279	pArgs->uMaster.M2.fLag = true;
3280	pArgs->uWorker.M2.fLag = true;
3281	}
3282	else
3283	# endif
3284	if (iLoop < (GIP_TSC_DELTA_M2_LOOPS - GIP_TSC_DELTA_M2_PRIMER_LOOPS) / 4)
3285	{
3286	/* 25 % of the body without lagging. */
3287	pArgs->uMaster.M2.fLag = false;
3288	pArgs->uWorker.M2.fLag = false;
3289	}
3290	else if (iLoop < (GIP_TSC_DELTA_M2_LOOPS - GIP_TSC_DELTA_M2_PRIMER_LOOPS) / 4 * 2)
3291	{
3292	/* 25 % of the body with both lagging. */
3293	pArgs->uMaster.M2.fLag = true;
3294	pArgs->uWorker.M2.fLag = true;
3295	}
3296	else
3297	{
3298	/* 50% of the body with alternating lag. */
3299	pArgs->uMaster.M2.fLag = (iLoop & 1) == 0;
3300	pArgs->uWorker.M2.fLag= (iLoop & 1) == 1;
3301	}
3302
3303	/*
3304	* Sync up with the worker and collect data.
3305	*/
3306	TSCDELTA_MASTER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3307	supdrvTscDeltaMethod2CollectData(&pArgs->uMaster.M2.Data, &pArgs->uWorker.M2.Data.iCurSeqNo, pArgs->uMaster.M2.fLag);
3308	TSCDELTA_MASTER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3309
3310	/*
3311	* Process the data.
3312	*/
3313	# if GIP_TSC_DELTA_M2_PRIMER_LOOPS > 0
3314	if (iLoop >= GIP_TSC_DELTA_M2_PRIMER_LOOPS)
3315	# endif
3316	supdrvTscDeltaMethod2ProcessDataOnMaster(pArgs, iLoop);
3317
3318	TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(pMySync, pOtherSync);
3319	}
3320	else
3321	{
3322	/*
3323	* The worker.
3324	*/
3325	TSCDELTA_OTHER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3326	supdrvTscDeltaMethod2CollectData(&pArgs->uWorker.M2.Data, &pArgs->uMaster.M2.Data.iCurSeqNo, pArgs->uWorker.M2.fLag);
3327	TSCDELTA_OTHER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3328	}
3329	}
3330	}
3331
3332	#endif /* GIP_TSC_DELTA_METHOD_2 */
3333
3334
3335
3336	static int supdrvTscDeltaVerify(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC2 pMySync,
3337	PSUPTSCDELTASYNC2 pOtherSync, bool fIsMaster, int64_t iWorkerTscDelta)
3338	{
3339	/PSUPGIPCPU pGipCpuWorker = pArgs->pWorker; - unused /
3340	PSUPGIPCPU pGipCpuMaster = pArgs->pMaster;
3341	uint32_t i;
3342	TSCDELTA_DBG_VARS();
3343
3344	for (;;)
3345	{
3346	RTCCUINTREG fEFlags;
3347	AssertCompile((RT_ELEMENTS(pArgs->uMaster.Verify.auTscs) & 1) == 0);
3348	AssertCompile(RT_ELEMENTS(pArgs->uMaster.Verify.auTscs) == RT_ELEMENTS(pArgs->uWorker.Verify.auTscs));
3349
3350	if (fIsMaster)
3351	{
3352	uint64_t uTscWorker;
3353	TSCDELTA_MASTER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3354
3355	/*
3356	* Collect TSC, master goes first.
3357	*/
3358	for (i = 0; i < RT_ELEMENTS(pArgs->uMaster.Verify.auTscs); i += 2)
3359	{
3360	/* Read, kick & wait #1. */
3361	uint64_t register uTsc = ASMReadTSC();
3362	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO_GO);
3363	ASMSerializeInstruction();
3364	pArgs->uMaster.Verify.auTscs[i] = uTsc;
3365	TSCDELTA_DBG_START_LOOP();
3366	while (ASMAtomicReadU32(&pMySync->uSyncVar) == GIP_TSC_DELTA_SYNC2_GO)
3367	{
3368	TSCDELTA_DBG_CHECK_LOOP();
3369	ASMNopPause();
3370	}
3371
3372	/* Read, kick & wait #2. */
3373	uTsc = ASMReadTSC();
3374	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO);
3375	ASMSerializeInstruction();
3376	pArgs->uMaster.Verify.auTscs[i + 1] = uTsc;
3377	TSCDELTA_DBG_START_LOOP();
3378	while (ASMAtomicReadU32(&pMySync->uSyncVar) == GIP_TSC_DELTA_SYNC2_GO_GO)
3379	{
3380	TSCDELTA_DBG_CHECK_LOOP();
3381	ASMNopPause();
3382	}
3383	}
3384
3385	TSCDELTA_MASTER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3386
3387	/*
3388	* Process the data.
3389	*/
3390	#ifdef TSCDELTA_VERIFY_WITH_STATS
3391	pArgs->cMaxVerifyTscTicks = INT64_MIN;
3392	pArgs->cMinVerifyTscTicks = INT64_MAX;
3393	pArgs->iVerifyBadTscDiff = 0;
3394	#endif
3395	ASMAtomicWriteS32(&pArgs->rcVerify, VINF_SUCCESS);
3396	uTscWorker = 0;
3397	for (i = 0; i < RT_ELEMENTS(pArgs->uMaster.Verify.auTscs); i++)
3398	{
3399	/* Master vs previous worker entry. */
3400	uint64_t uTscMaster = pArgs->uMaster.Verify.auTscs[i] - pGipCpuMaster->i64TSCDelta;
3401	int64_t iDiff;
3402	if (i > 0)
3403	{
3404	iDiff = uTscMaster - uTscWorker;
3405	#ifdef TSCDELTA_VERIFY_WITH_STATS
3406	if (iDiff > pArgs->cMaxVerifyTscTicks)
3407	pArgs->cMaxVerifyTscTicks = iDiff;
3408	if (iDiff < pArgs->cMinVerifyTscTicks)
3409	pArgs->cMinVerifyTscTicks = iDiff;
3410	#endif
3411	if (iDiff < 0)
3412	{
3413	#ifdef TSCDELTA_VERIFY_WITH_STATS
3414	pArgs->iVerifyBadTscDiff = -iDiff;
3415	#endif
3416	ASMAtomicWriteS32(&pArgs->rcVerify, VERR_OUT_OF_RANGE);
3417	break;
3418	}
3419	}
3420
3421	/* Worker vs master. */
3422	uTscWorker = pArgs->uWorker.Verify.auTscs[i] - iWorkerTscDelta;
3423	iDiff = uTscWorker - uTscMaster;
3424	#ifdef TSCDELTA_VERIFY_WITH_STATS
3425	if (iDiff > pArgs->cMaxVerifyTscTicks)
3426	pArgs->cMaxVerifyTscTicks = iDiff;
3427	if (iDiff < pArgs->cMinVerifyTscTicks)
3428	pArgs->cMinVerifyTscTicks = iDiff;
3429	#endif
3430	if (iDiff < 0)
3431	{
3432	#ifdef TSCDELTA_VERIFY_WITH_STATS
3433	pArgs->iVerifyBadTscDiff = iDiff;
3434	#endif
3435	ASMAtomicWriteS32(&pArgs->rcVerify, VERR_OUT_OF_RANGE);
3436	break;
3437	}
3438	}
3439
3440	/* Done. */
3441	TSCDELTA_MASTER_KICK_OTHER_OUT_OF_AFTER(pMySync, pOtherSync);
3442	}
3443	else
3444	{
3445	/*
3446	* The worker, master leads.
3447	*/
3448	TSCDELTA_OTHER_SYNC_BEFORE(pMySync, pOtherSync, &fEFlags, pArgs);
3449
3450	for (i = 0; i < RT_ELEMENTS(pArgs->uWorker.Verify.auTscs); i += 2)
3451	{
3452	uint64_t register uTsc;
3453
3454	/* Wait, Read and Kick #1. */
3455	TSCDELTA_DBG_START_LOOP();
3456	while (ASMAtomicReadU32(&pMySync->uSyncVar) == GIP_TSC_DELTA_SYNC2_GO)
3457	{
3458	TSCDELTA_DBG_CHECK_LOOP();
3459	ASMNopPause();
3460	}
3461	uTsc = ASMReadTSC();
3462	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO_GO);
3463	ASMSerializeInstruction();
3464	pArgs->uWorker.Verify.auTscs[i] = uTsc;
3465
3466	/* Wait, Read and Kick #2. */
3467	TSCDELTA_DBG_START_LOOP();
3468	while (ASMAtomicReadU32(&pMySync->uSyncVar) == GIP_TSC_DELTA_SYNC2_GO_GO)
3469	{
3470	TSCDELTA_DBG_CHECK_LOOP();
3471	ASMNopPause();
3472	}
3473	uTsc = ASMReadTSC();
3474	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_GO);
3475	ASMSerializeInstruction();
3476	pArgs->uWorker.Verify.auTscs[i + 1] = uTsc;
3477	}
3478
3479	TSCDELTA_OTHER_SYNC_AFTER(pMySync, pOtherSync, fEFlags);
3480	}
3481	return pArgs->rcVerify;
3482	}
3483
3484	/*
3485	* Timed out, please retry.
3486	*/
3487	ASMAtomicWriteS32(&pArgs->rcVerify, VERR_TRY_AGAIN);
3488	return VERR_TIMEOUT;
3489	}
3490
3491
3492
3493	/**
3494	* Handles the special abort procedure during synchronization setup in
3495	* supdrvMeasureTscDeltaCallbackUnwrapped().
3496	*
3497	* @returns 0 (dummy, ignored)
3498	* @param pArgs Pointer to argument/state data.
3499	* @param pMySync Pointer to my sync structure.
3500	* @param fIsMaster Set if we're the master, clear if worker.
3501	* @param fTimeout Set if it's a timeout.
3502	*/
3503	DECL_NO_INLINE(static, int)
3504	supdrvMeasureTscDeltaCallbackAbortSyncSetup(PSUPDRVGIPTSCDELTARGS pArgs, PSUPTSCDELTASYNC2 pMySync, bool fIsMaster, bool fTimeout)
3505	{
3506	PSUPTSCDELTASYNC2 volatile *ppMySync = fIsMaster ? &pArgs->pSyncMaster : &pArgs->pSyncWorker;
3507	PSUPTSCDELTASYNC2 volatile *ppOtherSync = fIsMaster ? &pArgs->pSyncWorker : &pArgs->pSyncMaster;
3508	TSCDELTA_DBG_VARS();
3509
3510	/*
3511	* Clear our sync pointer and make sure the abort flag is set.
3512	*/
3513	ASMAtomicWriteNullPtr(ppMySync);
3514	ASMAtomicWriteBool(&pArgs->fAbortSetup, true);
3515	if (fTimeout)
3516	ASMAtomicWriteBool(&pArgs->fTimedOut, true);
3517
3518	/*
3519	* Make sure the other party is out of there and won't be touching our
3520	* sync state again (would cause stack corruption).
3521	*/
3522	TSCDELTA_DBG_START_LOOP();
3523	while (ASMAtomicReadPtrT(ppOtherSync, PSUPTSCDELTASYNC2) != NULL)
3524	{
3525	ASMNopPause();
3526	ASMNopPause();
3527	ASMNopPause();
3528	TSCDELTA_DBG_CHECK_LOOP();
3529	}
3530
3531	return 0;
3532	}
3533
3534
3535	/**
3536	* This is used by supdrvMeasureInitialTscDeltas() to read the TSC on two CPUs
3537	* and compute the delta between them.
3538	*
3539	* To reduce code size a good when timeout handling was added, a dummy return
3540	* value had to be added (saves 1-3 lines per timeout case), thus this
3541	* 'Unwrapped' function and the dummy 0 return value.
3542	*
3543	* @returns 0 (dummy, ignored)
3544	* @param idCpu The CPU we are current scheduled on.
3545	* @param pArgs Pointer to a parameter package.
3546	*
3547	* @remarks Measuring TSC deltas between the CPUs is tricky because we need to
3548	* read the TSC at exactly the same time on both the master and the
3549	* worker CPUs. Due to DMA, bus arbitration, cache locality,
3550	* contention, SMI, pipelining etc. there is no guaranteed way of
3551	* doing this on x86 CPUs.
3552	*/
3553	static int supdrvMeasureTscDeltaCallbackUnwrapped(RTCPUID idCpu, PSUPDRVGIPTSCDELTARGS pArgs)
3554	{
3555	PSUPDRVDEVEXT pDevExt = pArgs->pDevExt;
3556	PSUPGIPCPU pGipCpuWorker = pArgs->pWorker;
3557	PSUPGIPCPU pGipCpuMaster = pArgs->pMaster;
3558	bool const fIsMaster = idCpu == pGipCpuMaster->idCpu;
3559	uint32_t iTry;
3560	PSUPTSCDELTASYNC2 volatile *ppMySync = fIsMaster ? &pArgs->pSyncMaster : &pArgs->pSyncWorker;
3561	PSUPTSCDELTASYNC2 volatile *ppOtherSync = fIsMaster ? &pArgs->pSyncWorker : &pArgs->pSyncMaster;
3562	SUPTSCDELTASYNC2 MySync;
3563	PSUPTSCDELTASYNC2 pOtherSync;
3564	int rc;
3565	TSCDELTA_DBG_VARS();
3566
3567	/* A bit of paranoia first. */
3568	if (!pGipCpuMaster \|\| !pGipCpuWorker)
3569	return 0;
3570
3571	/*
3572	* If the CPU isn't part of the measurement, return immediately.
3573	*/
3574	if ( !fIsMaster
3575	&& idCpu != pGipCpuWorker->idCpu)
3576	return 0;
3577
3578	/*
3579	* Set up my synchronization stuff and wait for the other party to show up.
3580	*
3581	* We don't wait forever since the other party may be off fishing (offline,
3582	* spinning with ints disables, whatever), we must play nice to the rest of
3583	* the system as this context generally isn't one in which we will get
3584	* preempted and we may hold up a number of lower priority interrupts.
3585	*/
3586	ASMAtomicWriteU32(&MySync.uSyncVar, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT);
3587	ASMAtomicWritePtr(ppMySync, &MySync);
3588	MySync.uTscStart = ASMReadTSC();
3589	MySync.cMaxTscTicks = pArgs->cMaxTscTicks;
3590
3591	/* Look for the partner, might not be here yet... Special abort considerations. */
3592	iTry = 0;
3593	TSCDELTA_DBG_START_LOOP();
3594	while ((pOtherSync = ASMAtomicReadPtrT(ppOtherSync, PSUPTSCDELTASYNC2)) == NULL)
3595	{
3596	ASMNopPause();
3597	if ( ASMAtomicReadBool(&pArgs->fAbortSetup)
3598	\|\| !RTMpIsCpuOnline(fIsMaster ? pGipCpuWorker->idCpu : pGipCpuWorker->idCpu) )
3599	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3600	if ( (iTry++ & 0xff) == 0
3601	&& ASMReadTSC() - MySync.uTscStart > pArgs->cMaxTscTicks)
3602	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, true /fTimeout/);
3603	TSCDELTA_DBG_CHECK_LOOP();
3604	ASMNopPause();
3605	}
3606
3607	/* I found my partner, waiting to be found... Special abort considerations. */
3608	if (fIsMaster)
3609	if (!ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_READY, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)) /* parnaoia */
3610	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3611
3612	iTry = 0;
3613	TSCDELTA_DBG_START_LOOP();
3614	while (ASMAtomicReadU32(&MySync.uSyncVar) == GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)
3615	{
3616	ASMNopPause();
3617	if (ASMAtomicReadBool(&pArgs->fAbortSetup))
3618	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3619	if ( (iTry++ & 0xff) == 0
3620	&& ASMReadTSC() - MySync.uTscStart > pArgs->cMaxTscTicks)
3621	{
3622	if ( fIsMaster
3623	&& !ASMAtomicCmpXchgU32(&MySync.uSyncVar, GIP_TSC_DELTA_SYNC2_PRESTART_ABORT, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT))
3624	break; /* race #1: slave has moved on, handle timeout in loop instead. */
3625	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, true /fTimeout/);
3626	}
3627	TSCDELTA_DBG_CHECK_LOOP();
3628	}
3629
3630	if (!fIsMaster)
3631	if (!ASMAtomicCmpXchgU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_READY, GIP_TSC_DELTA_SYNC2_PRESTART_WAIT)) /* race #1 */
3632	return supdrvMeasureTscDeltaCallbackAbortSyncSetup(pArgs, &MySync, fIsMaster, false /fTimeout/);
3633
3634	/** @todo Add a resumable state to pArgs so we don't waste time if we time
3635	* out or something. Timeouts are legit, any of the two CPUs may get
3636	* interrupted. */
3637
3638	/*
3639	* Start by seeing if we have a zero delta between the two CPUs.
3640	* This should normally be the case.
3641	*/
3642	rc = supdrvTscDeltaVerify(pArgs, &MySync, pOtherSync, fIsMaster, GIP_TSC_DELTA_INITIAL_MASTER_VALUE);
3643	if (RT_SUCCESS(rc))
3644	{
3645	if (fIsMaster)
3646	{
3647	ASMAtomicWriteS64(&pGipCpuWorker->i64TSCDelta, GIP_TSC_DELTA_INITIAL_MASTER_VALUE);
3648	RTCpuSetDelByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet);
3649	RTCpuSetAddByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpuWorker->iCpuSet);
3650	}
3651	}
3652	/*
3653	* If the verification didn't time out, do regular delta measurements.
3654	* We retry this until we get a reasonable value.
3655	*/
3656	else if (rc != VERR_TIMEOUT)
3657	{
3658	Assert(pGipCpuWorker->i64TSCDelta == INT64_MAX);
3659	for (iTry = 0; iTry < 12; iTry++)
3660	{
3661	/*
3662	* Check the state before we start.
3663	*/
3664	uint32_t u32Tmp = ASMAtomicReadU32(&MySync.uSyncVar);
3665	if ( u32Tmp != GIP_TSC_DELTA_SYNC2_READY
3666	&& (fIsMaster \|\| u32Tmp != GIP_TSC_DELTA_SYNC2_STEADY) /* worker may be late prepping for the next round */ )
3667	{
3668	TSCDELTA_DBG_SYNC_MSG(("sync/loop/%s: #0 iTry=%u MyState=%#x\n", fIsMaster ? "master" : "worker", iTry, u32Tmp));
3669	break;
3670	}
3671
3672	/*
3673	* Do the measurements.
3674	*/
3675	#ifdef GIP_TSC_DELTA_METHOD_1
3676	supdrvTscDeltaMethod1Loop(pArgs, &MySync, pOtherSync, fIsMaster, iTry);
3677	#elif defined(GIP_TSC_DELTA_METHOD_2)
3678	supdrvTscDeltaMethod2Loop(pArgs, &MySync, pOtherSync, fIsMaster, iTry);
3679	#else
3680	# error "huh??"
3681	#endif
3682
3683	/*
3684	* Check the state.
3685	*/
3686	u32Tmp = ASMAtomicReadU32(&MySync.uSyncVar);
3687	if ( u32Tmp != GIP_TSC_DELTA_SYNC2_READY
3688	&& (fIsMaster \|\| u32Tmp != GIP_TSC_DELTA_SYNC2_STEADY) /* worker may be late prepping for the next round */ )
3689	{
3690	if (fIsMaster)
3691	TSCDELTA_DBG_SYNC_MSG(("sync/loop/master: #1 iTry=%u MyState=%#x\n", iTry, u32Tmp));
3692	else
3693	TSCDELTA_DBG_SYNC_MSG2(("sync/loop/worker: #1 iTry=%u MyState=%#x\n", iTry, u32Tmp));
3694	break;
3695	}
3696
3697	/*
3698	* Success? If so, stop trying. Master decides.
3699	*/
3700	if (fIsMaster)
3701	{
3702	if (pGipCpuWorker->i64TSCDelta != INT64_MAX)
3703	{
3704	RTCpuSetDelByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet);
3705	RTCpuSetAddByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpuWorker->iCpuSet);
3706	TSCDELTA_DBG_SYNC_MSG2(("sync/loop/master: #9 iTry=%u MyState=%#x\n", iTry, MySync.uSyncVar));
3707	break;
3708	}
3709	}
3710	}
3711	if (fIsMaster)
3712	pArgs->iTry = iTry;
3713	}
3714
3715	/*
3716	* End the synchronization dance. We tell the other that we're done,
3717	* then wait for the same kind of reply.
3718	*/
3719	ASMAtomicWriteU32(&pOtherSync->uSyncVar, GIP_TSC_DELTA_SYNC2_FINAL);
3720	ASMAtomicWriteNullPtr(ppMySync);
3721	iTry = 0;
3722	TSCDELTA_DBG_START_LOOP();
3723	while (ASMAtomicReadU32(&MySync.uSyncVar) != GIP_TSC_DELTA_SYNC2_FINAL)
3724	{
3725	iTry++;
3726	if ( iTry == 0
3727	&& !RTMpIsCpuOnline(fIsMaster ? pGipCpuWorker->idCpu : pGipCpuWorker->idCpu))
3728	break; /* this really shouldn't happen. */
3729	TSCDELTA_DBG_CHECK_LOOP();
3730	ASMNopPause();
3731	}
3732
3733	/*
3734	* Collect some runtime stats.
3735	*/
3736	if (fIsMaster)
3737	pArgs->cElapsedMasterTscTicks = ASMReadTSC() - MySync.uTscStart;
3738	else
3739	pArgs->cElapsedWorkerTscTicks = ASMReadTSC() - MySync.uTscStart;
3740	return 0;
3741	}
3742
3743	/**
3744	* Callback used by supdrvMeasureInitialTscDeltas() to read the TSC on two CPUs
3745	* and compute the delta between them.
3746	*
3747	* @param idCpu The CPU we are current scheduled on.
3748	* @param pvUser1 Pointer to a parameter package (SUPDRVGIPTSCDELTARGS).
3749	* @param pvUser2 Unused.
3750	*/
3751	static DECLCALLBACK(void) supdrvMeasureTscDeltaCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
3752	{
3753	supdrvMeasureTscDeltaCallbackUnwrapped(idCpu, (PSUPDRVGIPTSCDELTARGS)pvUser1);
3754	}
3755
3756
3757	/**
3758	* Measures the TSC delta between the master GIP CPU and one specified worker
3759	* CPU.
3760	*
3761	* @returns VBox status code.
3762	* @retval VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED on pure measurement
3763	* failure.
3764	* @param pDevExt Pointer to the device instance data.
3765	* @param idxWorker The index of the worker CPU from the GIP's array of
3766	* CPUs.
3767	*
3768	* @remarks This must be called with preemption enabled!
3769	*/
3770	static int supdrvMeasureTscDeltaOne(PSUPDRVDEVEXT pDevExt, uint32_t idxWorker)
3771	{
3772	int rc;
3773	int rc2;
3774	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3775	RTCPUID idMaster = pDevExt->idGipMaster;
3776	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[idxWorker];
3777	PSUPGIPCPU pGipCpuMaster;
3778	uint32_t iGipCpuMaster;
3779	uint32_t u32Tmp;
3780
3781	/* Validate input a bit. */
3782	AssertReturn(pGip, VERR_INVALID_PARAMETER);
3783	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
3784	Assert(RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3785
3786	/*
3787	* Don't attempt measuring the delta for the GIP master.
3788	*/
3789	if (pGipCpuWorker->idCpu == idMaster)
3790	{
3791	if (pGipCpuWorker->i64TSCDelta == INT64_MAX) /* This shouldn't happen, but just in case. */
3792	ASMAtomicWriteS64(&pGipCpuWorker->i64TSCDelta, GIP_TSC_DELTA_INITIAL_MASTER_VALUE);
3793	return VINF_SUCCESS;
3794	}
3795
3796	/*
3797	* One measurement at a time, at least for now. We might be using
3798	* broadcast IPIs so, so be nice to the rest of the system.
3799	*/
3800	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
3801	rc = RTSemMutexRequest(pDevExt->mtxTscDelta, RT_INDEFINITE_WAIT);
3802	#else
3803	rc = RTSemFastMutexRequest(pDevExt->mtxTscDelta);
3804	#endif
3805	if (RT_FAILURE(rc))
3806	return rc;
3807
3808	/*
3809	* If the CPU has hyper-threading and the APIC IDs of the master and worker are adjacent,
3810	* try pick a different master. (This fudge only works with multi core systems.)
3811	* ASSUMES related threads have adjacent APIC IDs. ASSUMES two threads per core.
3812	*
3813	* We skip this on AMDs for now as their HTT is different from Intel's and
3814	* it doesn't seem to have any favorable effect on the results.
3815	*
3816	* If the master is offline, we need a new master too, so share the code.
3817	*/
3818	iGipCpuMaster = supdrvGipFindCpuIndexForCpuId(pGip, idMaster);
3819	AssertReturn(iGipCpuMaster < pGip->cCpus, VERR_INVALID_CPU_ID);
3820	pGipCpuMaster = &pGip->aCPUs[iGipCpuMaster];
3821	if ( ( (pGipCpuMaster->idApic & ~1) == (pGipCpuWorker->idApic & ~1)
3822	&& pGip->cOnlineCpus > 2
3823	&& ASMHasCpuId()
3824	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
3825	&& (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_HTT)
3826	&& ( !ASMIsAmdCpu()
3827	\|\| ASMGetCpuFamily(u32Tmp = ASMCpuId_EAX(1)) > 0x15
3828	\|\| ( ASMGetCpuFamily(u32Tmp) == 0x15 /* Piledriver+, not bulldozer (FX-4150 didn't like it). */
3829	&& ASMGetCpuModelAMD(u32Tmp) >= 0x02) ) )
3830	\|\| !RTMpIsCpuOnline(idMaster) )
3831	{
3832	uint32_t i;
3833	for (i = 0; i < pGip->cCpus; i++)
3834	if ( i != iGipCpuMaster
3835	&& i != idxWorker
3836	&& pGip->aCPUs[i].enmState == SUPGIPCPUSTATE_ONLINE
3837	&& pGip->aCPUs[i].i64TSCDelta != INT64_MAX
3838	&& pGip->aCPUs[i].idCpu != NIL_RTCPUID
3839	&& pGip->aCPUs[i].idCpu != idMaster /* paranoia starts here... */
3840	&& pGip->aCPUs[i].idCpu != pGipCpuWorker->idCpu
3841	&& pGip->aCPUs[i].idApic != pGipCpuWorker->idApic
3842	&& pGip->aCPUs[i].idApic != pGipCpuMaster->idApic
3843	&& RTMpIsCpuOnline(pGip->aCPUs[i].idCpu))
3844	{
3845	iGipCpuMaster = i;
3846	pGipCpuMaster = &pGip->aCPUs[i];
3847	idMaster = pGipCpuMaster->idCpu;
3848	break;
3849	}
3850	}
3851
3852	if (RTCpuSetIsMemberByIndex(&pGip->OnlineCpuSet, pGipCpuWorker->iCpuSet))
3853	{
3854	/*
3855	* Initialize data package for the RTMpOnPair callback.
3856	*/
3857	PSUPDRVGIPTSCDELTARGS pArgs = (PSUPDRVGIPTSCDELTARGS)RTMemAllocZ(sizeof(*pArgs));
3858	if (pArgs)
3859	{
3860	pArgs->pWorker = pGipCpuWorker;
3861	pArgs->pMaster = pGipCpuMaster;
3862	pArgs->pDevExt = pDevExt;
3863	pArgs->pSyncMaster = NULL;
3864	pArgs->pSyncWorker = NULL;
3865	pArgs->cMaxTscTicks = ASMAtomicReadU64(&pGip->u64CpuHz) / 512; /* 1953 us */
3866
3867	/*
3868	* Do the RTMpOnPair call. We reset i64TSCDelta first so we
3869	* and supdrvMeasureTscDeltaCallback can use it as a success check.
3870	*/
3871	/** @todo Store the i64TSCDelta result in pArgs first? Perhaps deals with
3872	* that when doing the restart loop reorg. */
3873	ASMAtomicWriteS64(&pGipCpuWorker->i64TSCDelta, INT64_MAX);
3874	rc = RTMpOnPair(pGipCpuMaster->idCpu, pGipCpuWorker->idCpu, RTMPON_F_CONCURRENT_EXEC,
3875	supdrvMeasureTscDeltaCallback, pArgs, NULL);
3876	if (RT_SUCCESS(rc))
3877	{
3878	#if 0
3879	SUPR0Printf("mponpair ticks: %9llu %9llu max: %9llu iTry: %u%s\n", pArgs->cElapsedMasterTscTicks,
3880	pArgs->cElapsedWorkerTscTicks, pArgs->cMaxTscTicks, pArgs->iTry,
3881	pArgs->fTimedOut ? " timed out" :"");
3882	#endif
3883	#if 0
3884	SUPR0Printf("rcVerify=%d iVerifyBadTscDiff=%lld cMinVerifyTscTicks=%lld cMaxVerifyTscTicks=%lld\n",
3885	pArgs->rcVerify, pArgs->iVerifyBadTscDiff, pArgs->cMinVerifyTscTicks, pArgs->cMaxVerifyTscTicks);
3886	#endif
3887	if (RT_LIKELY(pGipCpuWorker->i64TSCDelta != INT64_MAX))
3888	{
3889	/*
3890	* Work the TSC delta applicability rating. It starts
3891	* optimistic in supdrvGipInit, we downgrade it here.
3892	*/
3893	SUPGIPUSETSCDELTA enmRating;
3894	if ( pGipCpuWorker->i64TSCDelta > GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO
3895	\|\| pGipCpuWorker->i64TSCDelta < -GIP_TSC_DELTA_THRESHOLD_ROUGHLY_ZERO)
3896	enmRating = SUPGIPUSETSCDELTA_NOT_ZERO;
3897	else if ( pGipCpuWorker->i64TSCDelta > GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO
3898	\|\| pGipCpuWorker->i64TSCDelta < -GIP_TSC_DELTA_THRESHOLD_PRACTICALLY_ZERO)
3899	enmRating = SUPGIPUSETSCDELTA_ROUGHLY_ZERO;
3900	else
3901	enmRating = SUPGIPUSETSCDELTA_PRACTICALLY_ZERO;
3902	if (pGip->enmUseTscDelta < enmRating)
3903	{
3904	AssertCompile(sizeof(pGip->enmUseTscDelta) == sizeof(uint32_t));
3905	ASMAtomicWriteU32((uint32_t volatile *)&pGip->enmUseTscDelta, enmRating);
3906	}
3907	}
3908	else
3909	rc = VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED;
3910	}
3911	/** @todo return try-again if we get an offline CPU error. */
3912
3913	RTMemFree(pArgs);
3914	}
3915	else
3916	rc = VERR_NO_MEMORY;
3917	}
3918	else
3919	rc = VERR_CPU_OFFLINE;
3920
3921	/*
3922	* We're done now.
3923	*/
3924	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
3925	rc2 = RTSemMutexRelease(pDevExt->mtxTscDelta); AssertRC(rc2);
3926	#else
3927	rc2 = RTSemFastMutexRelease(pDevExt->mtxTscDelta); AssertRC(rc2);
3928	#endif
3929	return rc;
3930	}
3931
3932
3933	/**
3934	* Resets the TSC-delta related TSC samples and optionally the deltas
3935	* themselves.
3936	*
3937	* @param pDevExt Pointer to the device instance data.
3938	* @param fResetTscDeltas Whether the TSC-deltas are also to be reset.
3939	*
3940	* @remarks This might be called while holding a spinlock!
3941	*/
3942	static void supdrvTscResetSamples(PSUPDRVDEVEXT pDevExt, bool fResetTscDeltas)
3943	{
3944	unsigned iCpu;
3945	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3946	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
3947	{
3948	PSUPGIPCPU pGipCpu = &pGip->aCPUs[iCpu];
3949	ASMAtomicWriteU64(&pGipCpu->u64TSCSample, GIP_TSC_DELTA_RSVD);
3950	if (fResetTscDeltas)
3951	{
3952	RTCpuSetDelByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpu->iCpuSet);
3953	ASMAtomicWriteS64(&pGipCpu->i64TSCDelta, INT64_MAX);
3954	}
3955	}
3956	}
3957
3958
3959	/**
3960	* Picks an online CPU as the master TSC for TSC-delta computations.
3961	*
3962	* @returns VBox status code.
3963	* @param pDevExt Pointer to the device instance data.
3964	* @param pidxMaster Where to store the CPU array index of the chosen
3965	* master. Optional, can be NULL.
3966	*/
3967	static int supdrvTscPickMaster(PSUPDRVDEVEXT pDevExt, uint32_t *pidxMaster)
3968	{
3969	/*
3970	* Pick the first CPU online as the master TSC and make it the new GIP master based
3971	* on the APIC ID.
3972	*
3973	* Technically we can simply use "idGipMaster" but doing this gives us master as CPU 0
3974	* in most cases making it nicer/easier for comparisons. It is safe to update the GIP
3975	* master as this point since the sync/async timer isn't created yet.
3976	*/
3977	unsigned iCpu;
3978	uint32_t idxMaster = UINT32_MAX;
3979	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
3980	for (iCpu = 0; iCpu < RT_ELEMENTS(pGip->aiCpuFromApicId); iCpu++)
3981	{
3982	uint16_t idxCpu = pGip->aiCpuFromApicId[iCpu];
3983	if (idxCpu != UINT16_MAX)
3984	{
3985	PSUPGIPCPU pGipCpu = &pGip->aCPUs[idxCpu];
3986	if (RTCpuSetIsMemberByIndex(&pGip->OnlineCpuSet, pGipCpu->iCpuSet))
3987	{
3988	idxMaster = idxCpu;
3989	pGipCpu->i64TSCDelta = GIP_TSC_DELTA_INITIAL_MASTER_VALUE;
3990	ASMAtomicWriteSize(&pDevExt->idGipMaster, pGipCpu->idCpu);
3991	if (pidxMaster)
3992	*pidxMaster = idxMaster;
3993	return VINF_SUCCESS;
3994	}
3995	}
3996	}
3997	return VERR_CPU_OFFLINE;
3998	}
3999
4000
4001	/**
4002	* Performs the initial measurements of the TSC deltas between CPUs.
4003	*
4004	* This is called by supdrvGipCreate(), supdrvGipPowerNotificationCallback() or
4005	* triggered by it if threaded.
4006	*
4007	* @returns VBox status code.
4008	* @param pDevExt Pointer to the device instance data.
4009	*
4010	* @remarks Must be called only after supdrvGipInitOnCpu() as this function uses
4011	* idCpu, GIP's online CPU set which are populated in
4012	* supdrvGipInitOnCpu().
4013	*/
4014	static int supdrvMeasureInitialTscDeltas(PSUPDRVDEVEXT pDevExt)
4015	{
4016	PSUPGIPCPU pGipCpuMaster;
4017	unsigned iCpu;
4018	unsigned iOddEven;
4019	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
4020	uint32_t idxMaster = UINT32_MAX;
4021	uint32_t cMpOnOffEvents = ASMAtomicReadU32(&pDevExt->cMpOnOffEvents);
4022
4023	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
4024	supdrvTscResetSamples(pDevExt, true /* fClearDeltas */);
4025	int rc = supdrvTscPickMaster(pDevExt, &idxMaster);
4026	if (RT_FAILURE(rc))
4027	{
4028	SUPR0Printf("Failed to pick a CPU master for TSC-delta measurements rc=%Rrc\n", rc);
4029	return rc;
4030	}
4031	AssertReturn(idxMaster < pGip->cCpus, VERR_INVALID_CPU_INDEX);
4032	pGipCpuMaster = &pGip->aCPUs[idxMaster];
4033	Assert(pDevExt->idGipMaster == pGipCpuMaster->idCpu);
4034
4035	/*
4036	* If there is only a single CPU online we have nothing to do.
4037	*/
4038	if (pGip->cOnlineCpus <= 1)
4039	{
4040	AssertReturn(pGip->cOnlineCpus > 0, VERR_INTERNAL_ERROR_5);
4041	return VINF_SUCCESS;
4042	}
4043
4044	/*
4045	* Loop thru the GIP CPU array and get deltas for each CPU (except the
4046	* master). We do the CPUs with the even numbered APIC IDs first so that
4047	* we've got alternative master CPUs to pick from on hyper-threaded systems.
4048	*/
4049	for (iOddEven = 0; iOddEven < 2; iOddEven++)
4050	{
4051	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
4052	{
4053	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[iCpu];
4054	if ( iCpu != idxMaster
4055	&& (iOddEven > 0 \|\| (pGipCpuWorker->idApic & 1) == 0)
4056	&& RTCpuSetIsMemberByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet))
4057	{
4058	rc = supdrvMeasureTscDeltaOne(pDevExt, iCpu);
4059	if (RT_FAILURE(rc))
4060	{
4061	SUPR0Printf("supdrvMeasureTscDeltaOne failed. rc=%d CPU[%u].idCpu=%u Master[%u].idCpu=%u\n", rc, iCpu,
4062	pGipCpuWorker->idCpu, idxMaster, pDevExt->idGipMaster, pGipCpuMaster->idCpu);
4063	break;
4064	}
4065
4066	if (ASMAtomicReadU32(&pDevExt->cMpOnOffEvents) != cMpOnOffEvents)
4067	{
4068	SUPR0Printf("One or more CPUs transitioned between online & offline states. I'm confused, retry...\n");
4069	rc = VERR_TRY_AGAIN;
4070	break;
4071	}
4072	}
4073	}
4074	}
4075
4076	return rc;
4077	}
4078
4079
4080	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
4081
4082	/**
4083	* Switches the TSC-delta measurement thread into the butchered state.
4084	*
4085	* @returns VBox status code.
4086	* @param pDevExt Pointer to the device instance data.
4087	* @param fSpinlockHeld Whether the TSC-delta spinlock is held or not.
4088	* @param pszFailed An error message to log.
4089	* @param rcFailed The error code to exit the thread with.
4090	*/
4091	static int supdrvTscDeltaThreadButchered(PSUPDRVDEVEXT pDevExt, bool fSpinlockHeld, const char *pszFailed, int rcFailed)
4092	{
4093	if (!fSpinlockHeld)
4094	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4095
4096	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Butchered;
4097	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4098	OSDBGPRINT(("supdrvTscDeltaThreadButchered: %s. rc=%Rrc\n", pszFailed, rcFailed));
4099	return rcFailed;
4100	}
4101
4102
4103	/**
4104	* The TSC-delta measurement thread.
4105	*
4106	* @returns VBox status code.
4107	* @param hThread The thread handle.
4108	* @param pvUser Opaque pointer to the device instance data.
4109	*/
4110	static DECLCALLBACK(int) supdrvTscDeltaThread(RTTHREAD hThread, void *pvUser)
4111	{
4112	PSUPDRVDEVEXT pDevExt = (PSUPDRVDEVEXT)pvUser;
4113	uint32_t cConsecutiveTimeouts = 0;
4114	int rc = VERR_INTERNAL_ERROR_2;
4115	for (;;)
4116	{
4117	/*
4118	* Switch on the current state.
4119	*/
4120	SUPDRVTSCDELTATHREADSTATE enmState;
4121	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4122	enmState = pDevExt->enmTscDeltaThreadState;
4123	switch (enmState)
4124	{
4125	case kTscDeltaThreadState_Creating:
4126	{
4127	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Listening;
4128	rc = RTSemEventSignal(pDevExt->hTscDeltaEvent);
4129	if (RT_FAILURE(rc))
4130	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "RTSemEventSignal", rc);
4131	/* fall thru */
4132	}
4133
4134	case kTscDeltaThreadState_Listening:
4135	{
4136	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4137
4138	/*
4139	* Linux counts uninterruptible sleeps as load, hence we shall do a
4140	* regular, interruptible sleep here and ignore wake ups due to signals.
4141	* See task_contributes_to_load() in include/linux/sched.h in the Linux sources.
4142	*/
4143	rc = RTThreadUserWaitNoResume(hThread, pDevExt->cMsTscDeltaTimeout);
4144	if ( RT_FAILURE(rc)
4145	&& rc != VERR_TIMEOUT
4146	&& rc != VERR_INTERRUPTED)
4147	return supdrvTscDeltaThreadButchered(pDevExt, false /* fSpinlockHeld */, "RTThreadUserWait", rc);
4148	RTThreadUserReset(hThread);
4149	break;
4150	}
4151
4152	case kTscDeltaThreadState_WaitAndMeasure:
4153	{
4154	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Measuring;
4155	rc = RTSemEventSignal(pDevExt->hTscDeltaEvent); /* (Safe on windows as long as spinlock isn't IRQ safe.) */
4156	if (RT_FAILURE(rc))
4157	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "RTSemEventSignal", rc);
4158	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4159	RTThreadSleep(1);
4160	/* fall thru */
4161	}
4162
4163	case kTscDeltaThreadState_Measuring:
4164	{
4165	cConsecutiveTimeouts = 0;
4166	if (pDevExt->fTscThreadRecomputeAllDeltas)
4167	{
4168	int cTries = 8;
4169	int cMsWaitPerTry = 10;
4170	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
4171	Assert(pGip);
4172	do
4173	{
4174	RTCpuSetCopy(&pDevExt->TscDeltaCpuSet, &pGip->OnlineCpuSet);
4175	rc = supdrvMeasureInitialTscDeltas(pDevExt);
4176	if ( RT_SUCCESS(rc)
4177	\|\| ( RT_FAILURE(rc)
4178	&& rc != VERR_TRY_AGAIN
4179	&& rc != VERR_CPU_OFFLINE))
4180	{
4181	break;
4182	}
4183	RTThreadSleep(cMsWaitPerTry);
4184	} while (cTries-- > 0);
4185	pDevExt->fTscThreadRecomputeAllDeltas = false;
4186	}
4187	else
4188	{
4189	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
4190	unsigned iCpu;
4191
4192	/* Measure TSC-deltas only for the CPUs that are in the set. */
4193	rc = VINF_SUCCESS;
4194	for (iCpu = 0; iCpu < pGip->cCpus; iCpu++)
4195	{
4196	PSUPGIPCPU pGipCpuWorker = &pGip->aCPUs[iCpu];
4197	if (RTCpuSetIsMemberByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet))
4198	{
4199	if (pGipCpuWorker->i64TSCDelta == INT64_MAX)
4200	{
4201	int rc2 = supdrvMeasureTscDeltaOne(pDevExt, iCpu);
4202	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4203	rc = rc2;
4204	}
4205	else
4206	{
4207	/*
4208	* The thread/someone must've called SUPR0TscDeltaMeasureBySetIndex(),
4209	* mark the delta as fine to get the timer thread off our back.
4210	*/
4211	RTCpuSetDelByIndex(&pDevExt->TscDeltaCpuSet, pGipCpuWorker->iCpuSet);
4212	RTCpuSetAddByIndex(&pDevExt->TscDeltaObtainedCpuSet, pGipCpuWorker->iCpuSet);
4213	}
4214	}
4215	}
4216	}
4217	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4218	if (pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
4219	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Listening;
4220	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4221	Assert(rc != VERR_NOT_AVAILABLE); /* VERR_NOT_AVAILABLE is used as init value, see supdrvTscDeltaThreadInit(). */
4222	ASMAtomicWriteS32(&pDevExt->rcTscDelta, rc);
4223	break;
4224	}
4225
4226	case kTscDeltaThreadState_Terminating:
4227	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Destroyed;
4228	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4229	return VINF_SUCCESS;
4230
4231	case kTscDeltaThreadState_Butchered:
4232	default:
4233	return supdrvTscDeltaThreadButchered(pDevExt, true /* fSpinlockHeld */, "Invalid state", VERR_INVALID_STATE);
4234	}
4235	}
4236
4237	return rc;
4238	}
4239
4240
4241	/**
4242	* Waits for the TSC-delta measurement thread to respond to a state change.
4243	*
4244	* @returns VINF_SUCCESS on success, VERR_TIMEOUT if it doesn't respond in time,
4245	* other error code on internal error.
4246	*
4247	* @param pDevExt The device instance data.
4248	* @param enmCurState The current state.
4249	* @param enmNewState The new state we're waiting for it to enter.
4250	*/
4251	static int supdrvTscDeltaThreadWait(PSUPDRVDEVEXT pDevExt, SUPDRVTSCDELTATHREADSTATE enmCurState,
4252	SUPDRVTSCDELTATHREADSTATE enmNewState)
4253	{
4254	SUPDRVTSCDELTATHREADSTATE enmActualState;
4255	int rc;
4256
4257	/*
4258	* Wait a short while for the expected state transition.
4259	*/
4260	RTSemEventWait(pDevExt->hTscDeltaEvent, RT_MS_1SEC);
4261	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4262	enmActualState = pDevExt->enmTscDeltaThreadState;
4263	if (enmActualState == enmNewState)
4264	{
4265	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4266	rc = VINF_SUCCESS;
4267	}
4268	else if (enmActualState == enmCurState)
4269	{
4270	/*
4271	* Wait longer if the state has not yet transitioned to the one we want.
4272	*/
4273	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4274	rc = RTSemEventWait(pDevExt->hTscDeltaEvent, 50 * RT_MS_1SEC);
4275	if ( RT_SUCCESS(rc)
4276	\|\| rc == VERR_TIMEOUT)
4277	{
4278	/*
4279	* Check the state whether we've succeeded.
4280	*/
4281	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4282	enmActualState = pDevExt->enmTscDeltaThreadState;
4283	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4284	if (enmActualState == enmNewState)
4285	rc = VINF_SUCCESS;
4286	else if (enmActualState == enmCurState)
4287	{
4288	rc = VERR_TIMEOUT;
4289	OSDBGPRINT(("supdrvTscDeltaThreadWait: timed out state transition. enmActualState=%d enmNewState=%d\n",
4290	enmActualState, enmNewState));
4291	}
4292	else
4293	{
4294	rc = VERR_INTERNAL_ERROR;
4295	OSDBGPRINT(("supdrvTscDeltaThreadWait: invalid state transition from %d to %d, expected %d\n", enmCurState,
4296	enmActualState, enmNewState));
4297	}
4298	}
4299	else
4300	OSDBGPRINT(("supdrvTscDeltaThreadWait: RTSemEventWait failed. rc=%Rrc\n", rc));
4301	}
4302	else
4303	{
4304	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4305	OSDBGPRINT(("supdrvTscDeltaThreadWait: invalid state %d when transitioning from %d to %d\n",
4306	enmActualState, enmCurState, enmNewState));
4307	rc = VERR_INTERNAL_ERROR;
4308	}
4309
4310	return rc;
4311	}
4312
4313
4314	/**
4315	* Signals the TSC-delta thread to start measuring TSC-deltas.
4316	*
4317	* @param pDevExt Pointer to the device instance data.
4318	* @param fForceAll Force re-calculating TSC-deltas on all CPUs.
4319	*/
4320	static void supdrvTscDeltaThreadStartMeasurement(PSUPDRVDEVEXT pDevExt, bool fForceAll)
4321	{
4322	if (pDevExt->hTscDeltaThread != NIL_RTTHREAD)
4323	{
4324	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4325	if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Listening
4326	\|\| pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
4327	{
4328	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_WaitAndMeasure;
4329	if (fForceAll)
4330	pDevExt->fTscThreadRecomputeAllDeltas = true;
4331	}
4332	else if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_WaitAndMeasure
4333	&& fForceAll)
4334	pDevExt->fTscThreadRecomputeAllDeltas = true;
4335	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4336	RTThreadUserSignal(pDevExt->hTscDeltaThread);
4337	}
4338	}
4339
4340
4341	/**
4342	* Terminates the actual thread running supdrvTscDeltaThread().
4343	*
4344	* This is an internal worker function for supdrvTscDeltaThreadInit() and
4345	* supdrvTscDeltaTerm().
4346	*
4347	* @param pDevExt Pointer to the device instance data.
4348	*/
4349	static void supdrvTscDeltaThreadTerminate(PSUPDRVDEVEXT pDevExt)
4350	{
4351	int rc;
4352	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4353	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Terminating;
4354	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4355	RTThreadUserSignal(pDevExt->hTscDeltaThread);
4356	rc = RTThreadWait(pDevExt->hTscDeltaThread, 50 * RT_MS_1SEC, NULL /* prc */);
4357	if (RT_FAILURE(rc))
4358	{
4359	/* Signal a few more times before giving up. */
4360	int cTriesLeft = 5;
4361	while (--cTriesLeft > 0)
4362	{
4363	RTThreadUserSignal(pDevExt->hTscDeltaThread);
4364	rc = RTThreadWait(pDevExt->hTscDeltaThread, 2 * RT_MS_1SEC, NULL /* prc */);
4365	if (rc != VERR_TIMEOUT)
4366	break;
4367	}
4368	}
4369	}
4370
4371
4372	/**
4373	* Initializes and spawns the TSC-delta measurement thread.
4374	*
4375	* A thread is required for servicing re-measurement requests from events like
4376	* CPUs coming online, suspend/resume etc. as it cannot be done synchronously
4377	* under all contexts on all OSs.
4378	*
4379	* @returns VBox status code.
4380	* @param pDevExt Pointer to the device instance data.
4381	*
4382	* @remarks Must only be called -after- initializing GIP and setting up MP
4383	* notifications!
4384	*/
4385	static int supdrvTscDeltaThreadInit(PSUPDRVDEVEXT pDevExt)
4386	{
4387	int rc;
4388	Assert(pDevExt->pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED);
4389	rc = RTSpinlockCreate(&pDevExt->hTscDeltaSpinlock, RTSPINLOCK_FLAGS_INTERRUPT_UNSAFE, "VBoxTscSpnLck");
4390	if (RT_SUCCESS(rc))
4391	{
4392	rc = RTSemEventCreate(&pDevExt->hTscDeltaEvent);
4393	if (RT_SUCCESS(rc))
4394	{
4395	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_Creating;
4396	pDevExt->cMsTscDeltaTimeout = 60000;
4397	rc = RTThreadCreate(&pDevExt->hTscDeltaThread, supdrvTscDeltaThread, pDevExt, 0 /* cbStack */,
4398	RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "VBoxTscThread");
4399	if (RT_SUCCESS(rc))
4400	{
4401	rc = supdrvTscDeltaThreadWait(pDevExt, kTscDeltaThreadState_Creating, kTscDeltaThreadState_Listening);
4402	if (RT_SUCCESS(rc))
4403	{
4404	ASMAtomicWriteS32(&pDevExt->rcTscDelta, VERR_NOT_AVAILABLE);
4405	return rc;
4406	}
4407
4408	OSDBGPRINT(("supdrvTscDeltaInit: supdrvTscDeltaThreadWait failed. rc=%Rrc\n", rc));
4409	supdrvTscDeltaThreadTerminate(pDevExt);
4410	}
4411	else
4412	OSDBGPRINT(("supdrvTscDeltaInit: RTThreadCreate failed. rc=%Rrc\n", rc));
4413	RTSemEventDestroy(pDevExt->hTscDeltaEvent);
4414	pDevExt->hTscDeltaEvent = NIL_RTSEMEVENT;
4415	}
4416	else
4417	OSDBGPRINT(("supdrvTscDeltaInit: RTSemEventCreate failed. rc=%Rrc\n", rc));
4418	RTSpinlockDestroy(pDevExt->hTscDeltaSpinlock);
4419	pDevExt->hTscDeltaSpinlock = NIL_RTSPINLOCK;
4420	}
4421	else
4422	OSDBGPRINT(("supdrvTscDeltaInit: RTSpinlockCreate failed. rc=%Rrc\n", rc));
4423
4424	return rc;
4425	}
4426
4427
4428	/**
4429	* Terminates the TSC-delta measurement thread and cleanup.
4430	*
4431	* @param pDevExt Pointer to the device instance data.
4432	*/
4433	static void supdrvTscDeltaTerm(PSUPDRVDEVEXT pDevExt)
4434	{
4435	if ( pDevExt->hTscDeltaSpinlock != NIL_RTSPINLOCK
4436	&& pDevExt->hTscDeltaEvent != NIL_RTSEMEVENT)
4437	{
4438	supdrvTscDeltaThreadTerminate(pDevExt);
4439	}
4440
4441	if (pDevExt->hTscDeltaSpinlock != NIL_RTSPINLOCK)
4442	{
4443	RTSpinlockDestroy(pDevExt->hTscDeltaSpinlock);
4444	pDevExt->hTscDeltaSpinlock = NIL_RTSPINLOCK;
4445	}
4446
4447	if (pDevExt->hTscDeltaEvent != NIL_RTSEMEVENT)
4448	{
4449	RTSemEventDestroy(pDevExt->hTscDeltaEvent);
4450	pDevExt->hTscDeltaEvent = NIL_RTSEMEVENT;
4451	}
4452
4453	ASMAtomicWriteS32(&pDevExt->rcTscDelta, VERR_NOT_AVAILABLE);
4454	}
4455
4456	#endif /* SUPDRV_USE_TSC_DELTA_THREAD */
4457
4458	/**
4459	* Measure the TSC delta for the CPU given by its CPU set index.
4460	*
4461	* @returns VBox status code.
4462	* @retval VERR_INTERRUPTED if interrupted while waiting.
4463	* @retval VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED if we were unable to get a
4464	* measurement.
4465	* @retval VERR_CPU_OFFLINE if the specified CPU is offline.
4466	*
4467	* @param pSession The caller's session. GIP must've been mapped.
4468	* @param iCpuSet The CPU set index of the CPU to measure.
4469	* @param fFlags Flags, SUP_TSCDELTA_MEASURE_F_XXX.
4470	* @param cMsWaitRetry Number of milliseconds to wait between each retry.
4471	* @param cMsWaitThread Number of milliseconds to wait for the thread to get
4472	* ready.
4473	* @param cTries Number of times to try, pass 0 for the default.
4474	*/
4475	SUPR0DECL(int) SUPR0TscDeltaMeasureBySetIndex(PSUPDRVSESSION pSession, uint32_t iCpuSet, uint32_t fFlags,
4476	RTMSINTERVAL cMsWaitRetry, RTMSINTERVAL cMsWaitThread, uint32_t cTries)
4477	{
4478	PSUPDRVDEVEXT pDevExt;
4479	PSUPGLOBALINFOPAGE pGip;
4480	uint16_t iGipCpu;
4481	int rc;
4482	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
4483	uint64_t msTsStartWait;
4484	uint32_t iWaitLoop;
4485	#endif
4486
4487	/*
4488	* Validate and adjust the input.
4489	*/
4490	AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER);
4491	if (!pSession->fGipReferenced)
4492	return VERR_WRONG_ORDER;
4493
4494	pDevExt = pSession->pDevExt;
4495	AssertReturn(SUP_IS_DEVEXT_VALID(pDevExt), VERR_INVALID_PARAMETER);
4496
4497	pGip = pDevExt->pGip;
4498	AssertPtrReturn(pGip, VERR_INTERNAL_ERROR_2);
4499
4500	AssertReturn(iCpuSet < RTCPUSET_MAX_CPUS, VERR_INVALID_CPU_INDEX);
4501	AssertReturn(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx), VERR_INVALID_CPU_INDEX);
4502	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
4503	AssertReturn(iGipCpu < pGip->cCpus, VERR_INVALID_CPU_INDEX);
4504
4505	if (fFlags & ~SUP_TSCDELTA_MEASURE_F_VALID_MASK)
4506	return VERR_INVALID_FLAGS;
4507
4508	/*
4509	* The request is a noop if the TSC delta isn't being used.
4510	*/
4511	if (pGip->enmUseTscDelta <= SUPGIPUSETSCDELTA_ZERO_CLAIMED)
4512	return VINF_SUCCESS;
4513
4514	if (cTries == 0)
4515	cTries = 12;
4516	else if (cTries > 256)
4517	cTries = 256;
4518
4519	if (cMsWaitRetry == 0)
4520	cMsWaitRetry = 2;
4521	else if (cMsWaitRetry > 1000)
4522	cMsWaitRetry = 1000;
4523
4524	#ifdef SUPDRV_USE_TSC_DELTA_THREAD
4525	/*
4526	* Has the TSC already been measured and we're not forced to redo it?
4527	*/
4528	if ( pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX
4529	&& !(fFlags & SUP_TSCDELTA_MEASURE_F_FORCE))
4530	return VINF_SUCCESS;
4531
4532	/*
4533	* Asynchronous request? Forward it to the thread, no waiting.
4534	*/
4535	if (fFlags & SUP_TSCDELTA_MEASURE_F_ASYNC)
4536	{
4537	/** @todo Async. doesn't implement options like retries, waiting. We'll need
4538	* to pass those options to the thread somehow and implement it in the
4539	* thread. Check if anyone uses/needs fAsync before implementing this. */
4540	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4541	RTCpuSetAddByIndex(&pDevExt->TscDeltaCpuSet, iCpuSet);
4542	if ( pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Listening
4543	\|\| pDevExt->enmTscDeltaThreadState == kTscDeltaThreadState_Measuring)
4544	{
4545	pDevExt->enmTscDeltaThreadState = kTscDeltaThreadState_WaitAndMeasure;
4546	rc = VINF_SUCCESS;
4547	}
4548	else if (pDevExt->enmTscDeltaThreadState != kTscDeltaThreadState_WaitAndMeasure)
4549	rc = VERR_THREAD_IS_DEAD;
4550	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4551	RTThreadUserSignal(pDevExt->hTscDeltaThread);
4552	return VINF_SUCCESS;
4553	}
4554
4555	/*
4556	* If a TSC-delta measurement request is already being serviced by the thread,
4557	* wait 'cTries' times if a retry-timeout is provided, otherwise bail as busy.
4558	*/
4559	msTsStartWait = RTTimeSystemMilliTS();
4560	for (iWaitLoop = 0;; iWaitLoop++)
4561	{
4562	uint64_t cMsElapsed;
4563	SUPDRVTSCDELTATHREADSTATE enmState;
4564	RTSpinlockAcquire(pDevExt->hTscDeltaSpinlock);
4565	enmState = pDevExt->enmTscDeltaThreadState;
4566	RTSpinlockRelease(pDevExt->hTscDeltaSpinlock);
4567
4568	if (enmState == kTscDeltaThreadState_Measuring)
4569	{ /* Must wait, the thread is busy. */ }
4570	else if (enmState == kTscDeltaThreadState_WaitAndMeasure)
4571	{ /* Must wait, this state only says what will happen next. */ }
4572	else if (enmState == kTscDeltaThreadState_Terminating)
4573	{ /* Must wait, this state only says what should happen next. */ }
4574	else
4575	break; /* All other states, the thread is either idly listening or dead. */
4576
4577	/* Wait or fail. */
4578	if (cMsWaitThread == 0)
4579	return VERR_SUPDRV_TSC_DELTA_MEASUREMENT_BUSY;
4580	cMsElapsed = RTTimeSystemMilliTS() - msTsStartWait;
4581	if (cMsElapsed >= cMsWaitThread)
4582	return VERR_SUPDRV_TSC_DELTA_MEASUREMENT_BUSY;
4583
4584	rc = RTThreadSleep(RT_MIN((RTMSINTERVAL)(cMsWaitThread - cMsElapsed), RT_MIN(iWaitLoop + 1, 10)));
4585	if (rc == VERR_INTERRUPTED)
4586	return rc;
4587	}
4588	#endif /* SUPDRV_USE_TSC_DELTA_THREAD */
4589
4590	/*
4591	* Try measure the TSC delta the given number of times.
4592	*/
4593	for (;;)
4594	{
4595	/* Unless we're forced to measure the delta, check whether it's done already. */
4596	if ( !(fFlags & SUP_TSCDELTA_MEASURE_F_FORCE)
4597	&& pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX)
4598	{
4599	rc = VINF_SUCCESS;
4600	break;
4601	}
4602
4603	/* Measure it. */
4604	rc = supdrvMeasureTscDeltaOne(pDevExt, iGipCpu);
4605	if (rc != VERR_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED)
4606	{
4607	Assert(pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX \|\| RT_FAILURE_NP(rc));
4608	break;
4609	}
4610
4611	/* Retry? */
4612	if (cTries <= 1)
4613	break;
4614	cTries--;
4615
4616	/* Always delay between retries (be nice to the rest of the system
4617	and avoid the BSOD hounds). */
4618	rc = RTThreadSleep(cMsWaitRetry);
4619	if (rc == VERR_INTERRUPTED)
4620	break;
4621	}
4622
4623	return rc;
4624	}
4625
4626
4627	/**
4628	* Service a TSC-delta measurement request.
4629	*
4630	* @returns VBox status code.
4631	* @param pDevExt Pointer to the device instance data.
4632	* @param pSession The support driver session.
4633	* @param pReq Pointer to the TSC-delta measurement request.
4634	*/
4635	int VBOXCALL supdrvIOCtl_TscDeltaMeasure(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, PSUPTSCDELTAMEASURE pReq)
4636	{
4637	uint32_t cTries;
4638	uint32_t iCpuSet;
4639	uint32_t fFlags;
4640	RTMSINTERVAL cMsWaitRetry;
4641
4642	/*
4643	* Validate and adjust/resolve the input so they can be passed onto SUPR0TscDeltaMeasureBySetIndex.
4644	*/
4645	AssertPtr(pDevExt); AssertPtr(pSession); AssertPtr(pReq); /* paranoia^2 */
4646
4647	if (pReq->u.In.idCpu == NIL_RTCPUID)
4648	return VERR_INVALID_CPU_ID;
4649	iCpuSet = RTMpCpuIdToSetIndex(pReq->u.In.idCpu);
4650	if (iCpuSet >= RTCPUSET_MAX_CPUS)
4651	return VERR_INVALID_CPU_ID;
4652
4653	cTries = pReq->u.In.cRetries == 0 ? 0 : (uint32_t)pReq->u.In.cRetries + 1;
4654
4655	cMsWaitRetry = RT_MAX(pReq->u.In.cMsWaitRetry, 5);
4656
4657	fFlags = 0;
4658	if (pReq->u.In.fAsync)
4659	fFlags \|= SUP_TSCDELTA_MEASURE_F_ASYNC;
4660	if (pReq->u.In.fForce)
4661	fFlags \|= SUP_TSCDELTA_MEASURE_F_FORCE;
4662
4663	return SUPR0TscDeltaMeasureBySetIndex(pSession, iCpuSet, fFlags, cMsWaitRetry,
4664	cTries == 0 ? 5 * RT_MS_1SEC : cMsWaitRetry * cTries /cMsWaitThread/,
4665	cTries);
4666	}
4667
4668
4669	/**
4670	* Reads TSC with delta applied.
4671	*
4672	* Will try to resolve delta value INT64_MAX before applying it. This is the
4673	* main purpose of this function, to handle the case where the delta needs to be
4674	* determined.
4675	*
4676	* @returns VBox status code.
4677	* @param pDevExt Pointer to the device instance data.
4678	* @param pSession The support driver session.
4679	* @param pReq Pointer to the TSC-read request.
4680	*/
4681	int VBOXCALL supdrvIOCtl_TscRead(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, PSUPTSCREAD pReq)
4682	{
4683	PSUPGLOBALINFOPAGE pGip;
4684	int rc;
4685
4686	/*
4687	* Validate. We require the client to have mapped GIP (no asserting on
4688	* ring-3 preconditions).
4689	*/
4690	AssertPtr(pDevExt); AssertPtr(pReq); AssertPtr(pSession); /* paranoia^2 */
4691	if (pSession->GipMapObjR3 == NIL_RTR0MEMOBJ)
4692	return VERR_WRONG_ORDER;
4693	pGip = pDevExt->pGip;
4694	AssertReturn(pGip, VERR_INTERNAL_ERROR_2);
4695
4696	/*
4697	* We're usually here because we need to apply delta, but we shouldn't be
4698	* upset if the GIP is some different mode.
4699	*/
4700	if (pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED)
4701	{
4702	uint32_t cTries = 0;
4703	for (;;)
4704	{
4705	/*
4706	* Start by gathering the data, using CLI for disabling preemption
4707	* while we do that.
4708	*/
4709	RTCCUINTREG fEFlags = ASMIntDisableFlags();
4710	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
4711	int iGipCpu;
4712	if (RT_LIKELY( (unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
4713	&& (iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet]) < pGip->cCpus ))
4714	{
4715	int64_t i64Delta = pGip->aCPUs[iGipCpu].i64TSCDelta;
4716	pReq->u.Out.idApic = pGip->aCPUs[iGipCpu].idApic;
4717	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4718	ASMSetFlags(fEFlags);
4719
4720	/*
4721	* If we're lucky we've got a delta, but no predictions here
4722	* as this I/O control is normally only used when the TSC delta
4723	* is set to INT64_MAX.
4724	*/
4725	if (i64Delta != INT64_MAX)
4726	{
4727	pReq->u.Out.u64AdjustedTsc -= i64Delta;
4728	rc = VINF_SUCCESS;
4729	break;
4730	}
4731
4732	/* Give up after a few times. */
4733	if (cTries >= 4)
4734	{
4735	rc = VWRN_SUPDRV_TSC_DELTA_MEASUREMENT_FAILED;
4736	break;
4737	}
4738
4739	/* Need to measure the delta an try again. */
4740	rc = supdrvMeasureTscDeltaOne(pDevExt, iGipCpu);
4741	Assert(pGip->aCPUs[iGipCpu].i64TSCDelta != INT64_MAX \|\| RT_FAILURE_NP(rc));
4742	/** @todo should probably delay on failure... dpc watchdogs */
4743	}
4744	else
4745	{
4746	/* This really shouldn't happen. */
4747	AssertMsgFailed(("idCpu=%#x iCpuSet=%#x (%d)\n", RTMpCpuId(), iCpuSet, iCpuSet));
4748	pReq->u.Out.idApic = ASMGetApicId();
4749	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4750	ASMSetFlags(fEFlags);
4751	rc = VERR_INTERNAL_ERROR_5; /** @todo change to warning. */
4752	break;
4753	}
4754	}
4755	}
4756	else
4757	{
4758	/*
4759	* No delta to apply. Easy. Deal with preemption the lazy way.
4760	*/
4761	RTCCUINTREG fEFlags = ASMIntDisableFlags();
4762	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
4763	int iGipCpu;
4764	if (RT_LIKELY( (unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)
4765	&& (iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet]) < pGip->cCpus ))
4766	pReq->u.Out.idApic = pGip->aCPUs[iGipCpu].idApic;
4767	else
4768	pReq->u.Out.idApic = ASMGetApicId();
4769	pReq->u.Out.u64AdjustedTsc = ASMReadTSC();
4770	ASMSetFlags(fEFlags);
4771	rc = VINF_SUCCESS;
4772	}
4773
4774	return rc;
4775	}
4776
4777
4778	/**
4779	* Worker for supdrvIOCtl_GipSetFlags.
4780	*
4781	* @returns VBox status code.
4782	* @retval VERR_WRONG_ORDER if an enable-once-per-session flag is set again for
4783	* a session.
4784	*
4785	* @param pDevExt Pointer to the device instance data.
4786	* @param pSession The support driver session.
4787	* @param fOrMask The OR mask of the GIP flags, see SUPGIP_FLAGS_XXX.
4788	* @param fAndMask The AND mask of the GIP flags, see SUPGIP_FLAGS_XXX.
4789	*
4790	* @remarks Caller must own the GIP mutex.
4791	*
4792	* @remarks This function doesn't validate any of the flags.
4793	*/
4794	static int supdrvGipSetFlags(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, uint32_t fOrMask, uint32_t fAndMask)
4795	{
4796	uint32_t cRefs;
4797	PSUPGLOBALINFOPAGE pGip = pDevExt->pGip;
4798	AssertMsg((fOrMask & fAndMask) == fOrMask, ("%#x & %#x\n", fOrMask, fAndMask)); /* ASSUMED by code below */
4799
4800	/*
4801	* Compute GIP test-mode flags.
4802	*/
4803	if (fOrMask & SUPGIP_FLAGS_TESTING_ENABLE)
4804	{
4805	if (!pSession->fGipTestMode)
4806	{
4807	Assert(pDevExt->cGipTestModeRefs < _64K);
4808	pSession->fGipTestMode = true;
4809	cRefs = ++pDevExt->cGipTestModeRefs;
4810	if (cRefs == 1)
4811	{
4812	fOrMask \|= SUPGIP_FLAGS_TESTING \| SUPGIP_FLAGS_TESTING_START;
4813	fAndMask &= ~SUPGIP_FLAGS_TESTING_STOP;
4814	}
4815	}
4816	else
4817	{
4818	LogRelMax(10, ("supdrvGipSetFlags: SUPGIP_FLAGS_TESTING_ENABLE already set for this session\n"));
4819	return VERR_WRONG_ORDER;
4820	}
4821	}
4822	else if ( !(fAndMask & SUPGIP_FLAGS_TESTING_ENABLE)
4823	&& pSession->fGipTestMode)
4824	{
4825	Assert(pDevExt->cGipTestModeRefs > 0);
4826	Assert(pDevExt->cGipTestModeRefs < _64K);
4827	pSession->fGipTestMode = false;
4828	cRefs = --pDevExt->cGipTestModeRefs;
4829	if (!cRefs)
4830	fOrMask \|= SUPGIP_FLAGS_TESTING_STOP;
4831	else
4832	fAndMask \|= SUPGIP_FLAGS_TESTING_ENABLE;
4833	}
4834
4835	/*
4836	* Commit the flags. This should be done as atomically as possible
4837	* since the flag consumers won't be holding the GIP mutex.
4838	*/
4839	ASMAtomicOrU32(&pGip->fFlags, fOrMask);
4840	ASMAtomicAndU32(&pGip->fFlags, fAndMask);
4841
4842	return VINF_SUCCESS;
4843	}
4844
4845
4846	/**
4847	* Sets GIP test mode parameters.
4848	*
4849	* @returns VBox status code.
4850	* @param pDevExt Pointer to the device instance data.
4851	* @param pSession The support driver session.
4852	* @param fOrMask The OR mask of the GIP flags, see SUPGIP_FLAGS_XXX.
4853	* @param fAndMask The AND mask of the GIP flags, see SUPGIP_FLAGS_XXX.
4854	*/
4855	int VBOXCALL supdrvIOCtl_GipSetFlags(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, uint32_t fOrMask, uint32_t fAndMask)
4856	{
4857	PSUPGLOBALINFOPAGE pGip;
4858	int rc;
4859
4860	/*
4861	* Validate. We require the client to have mapped GIP (no asserting on
4862	* ring-3 preconditions).
4863	*/
4864	AssertPtr(pDevExt); AssertPtr(pSession); /* paranoia^2 */
4865	if (pSession->GipMapObjR3 == NIL_RTR0MEMOBJ)
4866	return VERR_WRONG_ORDER;
4867	pGip = pDevExt->pGip;
4868	AssertReturn(pGip, VERR_INTERNAL_ERROR_3);
4869
4870	if (fOrMask & ~SUPGIP_FLAGS_VALID_MASK)
4871	return VERR_INVALID_PARAMETER;
4872	if ((fAndMask & ~SUPGIP_FLAGS_VALID_MASK) != ~SUPGIP_FLAGS_VALID_MASK)
4873	return VERR_INVALID_PARAMETER;
4874
4875	/*
4876	* Don't confuse supdrvGipSetFlags or anyone else by both setting
4877	* and clearing the same flags. AND takes precedence.
4878	*/
4879	fOrMask &= fAndMask;
4880
4881	/*
4882	* Take the loader lock to avoid having to think about races between two
4883	* clients changing the flags at the same time (state is not simple).
4884	*/
4885	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
4886	RTSemMutexRequest(pDevExt->mtxGip, RT_INDEFINITE_WAIT);
4887	#else
4888	RTSemFastMutexRequest(pDevExt->mtxGip);
4889	#endif
4890
4891	rc = supdrvGipSetFlags(pDevExt, pSession, fOrMask, fAndMask);
4892
4893	#ifdef SUPDRV_USE_MUTEX_FOR_GIP
4894	RTSemMutexRelease(pDevExt->mtxGip);
4895	#else
4896	RTSemFastMutexRelease(pDevExt->mtxGip);
4897	#endif
4898	return rc;
4899	}
4900

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source: vbox/trunk/src/VBox/HostDrivers/Support/SUPDrvGip.cpp@ 60700

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