SUPLibAll.cpp@ 82963

Last change on this file since 82963 was 81071, checked in by vboxsync, 5 years ago
SUPDrv,IPRT,VMM: Support host APIC ID above 256 in GIP. (Only tested on 4 core intel.) bugref:9501
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1	/* $Id: SUPLibAll.cpp 81071 2019-09-30 10:17:28Z vboxsync $ */
2	/** @file
3	* VirtualBox Support Library - All Contexts Code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	/*********************************************************************************************************************************
29	* Header Files *
30	*********************************************************************************************************************************/
31	#include <VBox/sup.h>
32	#ifdef IN_RC
33	# include <VBox/vmm/vm.h>
34	# include <VBox/vmm/vmm.h>
35	#endif
36	#ifdef IN_RING0
37	# include <iprt/mp.h>
38	#endif
39	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
40	# include <iprt/asm-amd64-x86.h>
41	#endif
42	#include <iprt/errcore.h>
43
44
45	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
46
47	/**
48	* The slow case for SUPReadTsc where we need to apply deltas.
49	*
50	* Must only be called when deltas are applicable, so please do not call it
51	* directly.
52	*
53	* @returns TSC with delta applied.
54	* @param pGip Pointer to the GIP.
55	*
56	* @remarks May be called with interrupts disabled in ring-0! This is why the
57	* ring-0 code doesn't attempt to figure the delta.
58	*
59	* @internal
60	*/
61	SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
62	{
63	uint64_t uTsc;
64	uint16_t iGipCpu;
65	AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
66	AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
67	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
68
69	/*
70	* Read the TSC and get the corresponding aCPUs index.
71	*/
72	#ifdef IN_RING3
73	if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
74	{
75	/* RDTSCP gives us all we need, no loops/cli. */
76	uint32_t iCpuSet;
77	uTsc = ASMReadTscWithAux(&iCpuSet);
78	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
79	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
80	}
81	else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
82	{
83	/* Storing the IDTR is normally very quick, but we need to loop. */
84	uint32_t cTries = 0;
85	for (;;)
86	{
87	uint16_t cbLim = ASMGetIdtrLimit();
88	uTsc = ASMReadTSC();
89	if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
90	{
91	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
92	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
93	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
94	break;
95	}
96	if (cTries >= 16)
97	{
98	iGipCpu = UINT16_MAX;
99	break;
100	}
101	cTries++;
102	}
103	}
104	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
105	{
106	/* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
107	uint32_t cTries = 0;
108	for (;;)
109	{
110	uint32_t idApic = ASMGetApicIdExt0B();
111	uTsc = ASMReadTSC();
112	if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
113	{
114	iGipCpu = pGip->aiCpuFromApicId[idApic];
115	break;
116	}
117	if (cTries >= 16)
118	{
119	iGipCpu = UINT16_MAX;
120	break;
121	}
122	cTries++;
123	}
124	}
125	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
126	{
127	/* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
128	uint32_t cTries = 0;
129	for (;;)
130	{
131	uint32_t idApic = ASMGetApicIdExt8000001E();
132	uTsc = ASMReadTSC();
133	if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
134	{
135	iGipCpu = pGip->aiCpuFromApicId[idApic];
136	break;
137	}
138	if (cTries >= 16)
139	{
140	iGipCpu = UINT16_MAX;
141	break;
142	}
143	cTries++;
144	}
145	}
146	else
147	{
148	/* Get APIC ID via the slow CPUID instruction, requires looping. */
149	uint32_t cTries = 0;
150	for (;;)
151	{
152	uint8_t idApic = ASMGetApicId();
153	uTsc = ASMReadTSC();
154	if (RT_LIKELY(ASMGetApicId() == idApic))
155	{
156	iGipCpu = pGip->aiCpuFromApicId[idApic];
157	break;
158	}
159	if (cTries >= 16)
160	{
161	iGipCpu = UINT16_MAX;
162	break;
163	}
164	cTries++;
165	}
166	}
167	#elif defined(IN_RING0)
168	/* Ring-0: Use use RTMpCpuId(), no loops. */
169	RTCCUINTREG uFlags = ASMIntDisableFlags();
170	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
171	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
172	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
173	else
174	iGipCpu = UINT16_MAX;
175	uTsc = ASMReadTSC();
176	ASMSetFlags(uFlags);
177
178	# elif defined(IN_RC)
179	/* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
180	RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
181	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
182	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
183	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
184	else
185	iGipCpu = UINT16_MAX;
186	uTsc = ASMReadTSC();
187	ASMSetFlags(uFlags);
188	#else
189	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
190	#endif
191
192	/*
193	* If the delta is valid, apply it.
194	*/
195	if (RT_LIKELY(iGipCpu < pGip->cCpus))
196	{
197	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
198	if (RT_LIKELY(iTscDelta != INT64_MAX))
199	return uTsc - iTscDelta;
200
201	# ifdef IN_RING3
202	/*
203	* The delta needs calculating, call supdrv to get the TSC.
204	*/
205	int rc = SUPR3ReadTsc(&uTsc, NULL);
206	if (RT_SUCCESS(rc))
207	return uTsc;
208	AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
209	uTsc = ASMReadTSC();
210	# endif /* IN_RING3 */
211	}
212
213	/*
214	* This shouldn't happen, especially not in ring-3 and raw-mode context.
215	* But if it does, return something that's half useful.
216	*/
217	AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
218	return uTsc;
219	}
220
221
222	/**
223	* Internal worker for getting the GIP CPU array index for the calling CPU.
224	*
225	* @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
226	* @param pGip The GIP.
227	*/
228	DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
229	{
230	uint16_t iGipCpu;
231	#ifdef IN_RING3
232	if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
233	{
234	/* Storing the IDTR is normally very fast. */
235	uint16_t cbLim = ASMGetIdtrLimit();
236	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
237	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
238	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
239	}
240	else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
241	{
242	/* RDTSCP gives us what need need and more. */
243	uint32_t iCpuSet;
244	ASMReadTscWithAux(&iCpuSet);
245	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
246	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
247	}
248	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
249	{
250	/* Get APIC ID via the slow CPUID/0000000B instruction. */
251	uint32_t idApic = ASMGetApicIdExt0B();
252	iGipCpu = pGip->aiCpuFromApicId[idApic];
253	}
254	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
255	{
256	/* Get APIC ID via the slow CPUID/8000001E instruction. */
257	uint32_t idApic = ASMGetApicIdExt8000001E();
258	iGipCpu = pGip->aiCpuFromApicId[idApic];
259	}
260	else
261	{
262	/* Get APIC ID via the slow CPUID instruction. */
263	uint8_t idApic = ASMGetApicId();
264	iGipCpu = pGip->aiCpuFromApicId[idApic];
265	}
266	#elif defined(IN_RING0)
267	/* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
268	RTCCUINTREG uFlags = ASMIntDisableFlags();
269	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
270	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
271	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
272	else
273	iGipCpu = UINT16_MAX;
274	ASMSetFlags(uFlags);
275
276	# elif defined(IN_RC)
277	/* Raw-mode context: We can get the host CPU set index via VMCPU. */
278	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
279	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
280	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
281	else
282	iGipCpu = UINT16_MAX;
283	#else
284	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
285	#endif
286	return iGipCpu;
287	}
288
289
290	/**
291	* Slow path in SUPGetTscDelta, don't call directly.
292	*
293	* @returns See SUPGetTscDelta.
294	* @param pGip The GIP.
295	* @internal
296	*/
297	SUPDECL(uint64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
298	{
299	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
300	if (RT_LIKELY(iGipCpu < pGip->cCpus))
301	{
302	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
303	if (iTscDelta != INT64_MAX)
304	return iTscDelta;
305	}
306	AssertFailed();
307	return 0;
308	}
309
310
311	/**
312	* Slow path in SUPGetCpuHzFromGip, don't call directly.
313	*
314	* @returns See SUPGetCpuHzFromGip.
315	* @param pGip The GIP.
316	* @internal
317	*/
318	SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
319	{
320	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
321	if (RT_LIKELY(iGipCpu < pGip->cCpus))
322	return pGip->aCPUs[iGipCpu].u64CpuHz;
323	AssertFailed();
324	return pGip->u64CpuHz;
325	}
326
327
328	/**
329	* Worker for SUPIsTscFreqCompatible().
330	*
331	* @returns true if it's compatible, false otherwise.
332	* @param uBaseCpuHz The reference CPU frequency of the system.
333	* @param uCpuHz The CPU frequency to compare with the base.
334	* @param fRelax Whether to use a more relaxed threshold (like
335	* for when running in a virtualized environment).
336	*
337	* @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
338	* to be used by tstGIP-2 or the like.
339	*/
340	SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
341	{
342	if (uBaseCpuHz != uCpuHz)
343	{
344	/* Arbitrary tolerance threshold, tweak later if required, perhaps
345	more tolerance on lower frequencies and less tolerance on higher. */
346	uint16_t uFact = !fRelax ? 666 /* 0.15% / : 125 / 0.8% */;
347	uint64_t uThr = uBaseCpuHz / uFact;
348	uint64_t uLo = uBaseCpuHz - uThr;
349	uint64_t uHi = uBaseCpuHz + uThr;
350	if ( uCpuHz < uLo
351	\|\| uCpuHz > uHi)
352	return false;
353	}
354	return true;
355	}
356
357
358	/**
359	* Checks if the provided TSC frequency is close enough to the computed TSC
360	* frequency of the host.
361	*
362	* @returns true if it's compatible, false otherwise.
363	* @param uCpuHz The TSC frequency to check.
364	* @param puGipCpuHz Where to store the GIP TSC frequency used
365	* during the compatibility test - optional.
366	* @param fRelax Whether to use a more relaxed threshold (like
367	* for when running in a virtualized environment).
368	*/
369	SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
370	{
371	PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
372	bool fCompat = false;
373	uint64_t uGipCpuHz = 0;
374	if ( pGip
375	&& pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
376	{
377	uGipCpuHz = pGip->u64CpuHz;
378	fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
379	}
380	if (puGipCpuHz)
381	*puGipCpuHz = uGipCpuHz;
382	return fCompat;
383	}
384
385	#endif /* RT_ARCH_AMD64 \|\| RT_ARCH_X86 */
386

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source: vbox/trunk/src/VBox/HostDrivers/Support/SUPLibAll.cpp@ 82963

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