VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 57218

Last change on this file since 57218 was 57218, checked in by vboxsync, 9 years ago

SUPDrv, tstGIP-2: Add support for GIP flags and testing TSC frequency compatibility.
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1/* $Id: tstGIP-2.cpp 57218 2015-08-06 14:53:27Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27/*******************************************************************************
28* Header Files *
29*******************************************************************************/
30#include <VBox/sup.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/thread.h>
37#include <iprt/stream.h>
38#include <iprt/string.h>
39#include <iprt/initterm.h>
40#include <iprt/getopt.h>
41#include <iprt/x86.h>
42
43int main(int argc, char **argv)
44{
45 RTR3InitExe(argc, &argv, 0);
46
47 /*
48 * Parse args
49 */
50 static const RTGETOPTDEF g_aOptions[] =
51 {
52 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
53 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
54 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
55 { "--spin", 's', RTGETOPT_REQ_NOTHING },
56 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
57 * CpuHz deviation in a separate column. */
58 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
59 * implies updating GIP CpuHz even when invariant) */
60 };
61
62 uint32_t cIterations = 40;
63 bool fHex = true;
64 bool fSpin = false;
65 bool fCompat = true;
66 bool fTestMode = true;
67 int ch;
68 uint64_t uCpuHzRef = UINT64_MAX;
69 uint64_t uCpuHzOverallDeviation = 0;
70 uint32_t cCpuHzNotCompat = 0;
71 int64_t iCpuHzMaxDeviation = 0;
72 int32_t cCpuHzOverallDevCnt = 0;
73 RTGETOPTUNION ValueUnion;
74 RTGETOPTSTATE GetState;
75 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
76 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
77 {
78 switch (ch)
79 {
80 case 'i':
81 cIterations = ValueUnion.u32;
82 break;
83
84 case 'd':
85 fHex = false;
86 break;
87
88 case 'h':
89 fHex = true;
90 break;
91
92 case 's':
93 fSpin = true;
94 break;
95
96 case 'r':
97 uCpuHzRef = ValueUnion.u64;
98 break;
99
100 case 't':
101 fTestMode = false;
102 break;
103
104 default:
105 return RTGetOptPrintError(ch, &ValueUnion);
106 }
107 }
108
109 /*
110 * Init
111 */
112 PSUPDRVSESSION pSession = NIL_RTR0PTR;
113 int rc = SUPR3Init(&pSession);
114 if (RT_SUCCESS(rc))
115 {
116 if (g_pSUPGlobalInfoPage)
117 {
118 /* Pick current CpuHz as the reference if none was specified. */
119 if (uCpuHzRef == UINT64_MAX)
120 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
121
122 if ( fTestMode
123 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
124 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
125
126 RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64 u32Mode=%d (%s) u32Version=%#x\n",
127 g_pSUPGlobalInfoPage->cCpus,
128 g_pSUPGlobalInfoPage->u32UpdateHz,
129 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
130 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
131 g_pSUPGlobalInfoPage->u64CpuHz,
132 uCpuHzRef,
133 g_pSUPGlobalInfoPage->u32Mode,
134 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
135 g_pSUPGlobalInfoPage->u32Version);
136 RTPrintf(fHex
137 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
138 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
139 uCpuHzRef ? " CpuHz deviation Compat " : "");
140 static SUPGIPCPU s_aaCPUs[2][256];
141
142 for (uint32_t i = 0; i < cIterations; i++)
143 {
144 /* copy the data */
145 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
146
147 /* display it & find something to spin on. */
148 uint32_t u32TransactionId = 0;
149 uint32_t volatile *pu32TransactionId = NULL;
150 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
151 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
152 {
153 char szCpuHzDeviation[32];
154 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
155 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
156 if (uCpuHzRef)
157 {
158 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
159 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
160 if (uCpuHzDeviation > 999999999)
161 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s ", "?");
162 else
163 {
164 /* Wait until the history validation code takes effect. */
165 bool fCurHzCompat = true;
166 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
167 {
168 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
169 iCpuHzMaxDeviation = iCpuHzDeviation;
170 uCpuHzOverallDeviation += uCpuHzDeviation;
171 cCpuHzOverallDevCnt++;
172 fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /* fRelax */);
173 }
174 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
175 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
176 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
177 if (!fCurHzCompat)
178 ++cCpuHzNotCompat;
179 fCompat &= fCurHzCompat;
180 }
181 }
182 else
183 szCpuHzDeviation[0] = '\0';
184 RTPrintf(fHex
185 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
186 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
187 i, iCpu,
188 pCpu->u64NanoTS,
189 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
190 pCpu->u64TSC,
191 pCpu->u32UpdateIntervalTSC,
192 pCpu->iTSCHistoryHead,
193 pCpu->u32TransactionId,
194 pCpu->u64CpuHz,
195 szCpuHzDeviation,
196 pCpu->au32TSCHistory[0],
197 pCpu->au32TSCHistory[1],
198 pCpu->au32TSCHistory[2],
199 pCpu->au32TSCHistory[3],
200 pCpu->au32TSCHistory[4],
201 pCpu->au32TSCHistory[5],
202 pCpu->au32TSCHistory[6],
203 pCpu->au32TSCHistory[7],
204 pCpu->cErrors);
205 if (!pu32TransactionId)
206 {
207 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
208 u32TransactionId = pCpu->u32TransactionId;
209 }
210 }
211
212 /* wait a bit / spin */
213 if (!fSpin)
214 RTThreadSleep(9);
215 else
216 {
217 if (pu32TransactionId)
218 {
219 uint32_t uTmp;
220 while ( u32TransactionId == (uTmp = *pu32TransactionId)
221 || (uTmp & 1))
222 ASMNopPause();
223 }
224 else
225 RTThreadSleep(1);
226 }
227 }
228
229 /*
230 * Display TSC deltas.
231 *
232 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
233 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
234 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
235 */
236 RTPrintf("tstGIP-2: TSC deltas:\n");
237 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
238 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
239 {
240 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
241 if (iCpu != UINT16_MAX)
242 {
243 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
244 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
245 }
246 }
247
248 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
249 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
250 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
251
252 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
253 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
254 if ( uCpuHzRef
255 && cCpuHzOverallDevCnt)
256 {
257 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
258 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
259 uPct / 1000, (uPct % 1000) / 10);
260
261 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
262 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
263 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
264
265 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz)\n", fCompat,
266 cCpuHzNotCompat, cIterations * g_pSUPGlobalInfoPage->cCpus, uCpuHzRef);
267
268 if ( !fCompat
269 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
270 rc = -1;
271 }
272
273 /* Disable GIP test mode. */
274 if (fTestMode)
275 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
276 }
277 else
278 {
279 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
280 rc = -1;
281 }
282
283 SUPR3Term(false /*fForced*/);
284 }
285 else
286 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
287 return !!rc;
288}
289
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