VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 57349

Last change on this file since 57349 was 57349, checked in by vboxsync, 10 years ago

tstGIP-2: Only validate data that actually gets updated for invariant and sync modes, output fixes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 13.9 KB
Line 
1/* $Id: tstGIP-2.cpp 57349 2015-08-14 14:02:42Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27/*******************************************************************************
28* Header Files *
29*******************************************************************************/
30#include <VBox/sup.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/thread.h>
37#include <iprt/stream.h>
38#include <iprt/string.h>
39#include <iprt/initterm.h>
40#include <iprt/getopt.h>
41#include <iprt/x86.h>
42
43int main(int argc, char **argv)
44{
45 RTR3InitExe(argc, &argv, 0);
46
47 /*
48 * Parse args
49 */
50 static const RTGETOPTDEF g_aOptions[] =
51 {
52 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
53 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
54 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
55 { "--spin", 's', RTGETOPT_REQ_NOTHING },
56 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
57 * CpuHz deviation in a separate column. */
58 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
59 * implies updating GIP CpuHz even when invariant) */
60 };
61
62 bool fHex = true;
63 bool fSpin = false;
64 bool fCompat = true;
65 bool fTestMode = true;
66 int ch;
67 uint32_t cIterations = 40;
68 uint64_t uCpuHzRef = UINT64_MAX;
69 RTGETOPTUNION ValueUnion;
70 RTGETOPTSTATE GetState;
71 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
72 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
73 {
74 switch (ch)
75 {
76 case 'i':
77 cIterations = ValueUnion.u32;
78 break;
79
80 case 'd':
81 fHex = false;
82 break;
83
84 case 'h':
85 fHex = true;
86 break;
87
88 case 's':
89 fSpin = true;
90 break;
91
92 case 'r':
93 uCpuHzRef = ValueUnion.u64;
94 break;
95
96 case 't':
97 fTestMode = false;
98 break;
99
100 default:
101 return RTGetOptPrintError(ch, &ValueUnion);
102 }
103 }
104
105 /*
106 * Init
107 */
108 PSUPDRVSESSION pSession = NIL_RTR0PTR;
109 int rc = SUPR3Init(&pSession);
110 if (RT_SUCCESS(rc))
111 {
112 if (g_pSUPGlobalInfoPage)
113 {
114 uint64_t uCpuHzOverallDeviation = 0;
115 uint32_t cCpuHzNotCompat = 0;
116 int64_t iCpuHzMaxDeviation = 0;
117 int32_t cCpuHzOverallDevCnt = 0;
118 uint32_t cCpuHzChecked = 0;
119
120 /* Pick current CpuHz as the reference if none was specified. */
121 if (uCpuHzRef == UINT64_MAX)
122 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
123
124 if ( fTestMode
125 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
126 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
127
128 RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64 u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x\n",
129 g_pSUPGlobalInfoPage->cCpus,
130 g_pSUPGlobalInfoPage->u32UpdateHz,
131 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
132 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
133 g_pSUPGlobalInfoPage->u64CpuHz,
134 uCpuHzRef,
135 g_pSUPGlobalInfoPage->u32Mode,
136 fTestMode,
137 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
138 g_pSUPGlobalInfoPage->u32Version);
139 RTPrintf(fHex
140 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
141 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
142 uCpuHzRef ? " CpuHz deviation Compat " : "");
143 static SUPGIPCPU s_aaCPUs[2][256];
144 for (uint32_t i = 0; i < cIterations; i++)
145 {
146 /* Copy the data. */
147 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
148
149 /* Display it & find something to spin on. */
150 uint32_t u32TransactionId = 0;
151 uint32_t volatile *pu32TransactionId = NULL;
152 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
153 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
154 {
155 char szCpuHzDeviation[32];
156 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
157 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
158 if (uCpuHzRef)
159 {
160 /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
161 if ( iCpu == 0
162 || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
163 {
164 /* Wait until the history validation code takes effect. */
165 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
166 {
167 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
168 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
169 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
170 if (uCpuHzDeviation <= 999999999)
171 {
172 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
173 iCpuHzMaxDeviation = iCpuHzDeviation;
174 uCpuHzOverallDeviation += uCpuHzDeviation;
175 cCpuHzOverallDevCnt++;
176 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
177 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
178 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
179 }
180 else
181 {
182 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
183 fCurHzCompat);
184 }
185
186 if (!fCurHzCompat)
187 ++cCpuHzNotCompat;
188 fCompat &= fCurHzCompat;
189 ++cCpuHzChecked;
190 }
191 else
192 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
193 }
194 else
195 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
196 }
197 else
198 szCpuHzDeviation[0] = '\0';
199 RTPrintf(fHex
200 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
201 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
202 i, iCpu,
203 pCpu->u64NanoTS,
204 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
205 pCpu->u64TSC,
206 pCpu->u32UpdateIntervalTSC,
207 pCpu->iTSCHistoryHead,
208 pCpu->u32TransactionId,
209 pCpu->u64CpuHz,
210 szCpuHzDeviation,
211 pCpu->au32TSCHistory[0],
212 pCpu->au32TSCHistory[1],
213 pCpu->au32TSCHistory[2],
214 pCpu->au32TSCHistory[3],
215 pCpu->au32TSCHistory[4],
216 pCpu->au32TSCHistory[5],
217 pCpu->au32TSCHistory[6],
218 pCpu->au32TSCHistory[7],
219 pCpu->cErrors);
220 if (!pu32TransactionId)
221 {
222 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
223 u32TransactionId = pCpu->u32TransactionId;
224 }
225 }
226
227 /* Wait a bit / spin. */
228 if (!fSpin)
229 RTThreadSleep(9);
230 else
231 {
232 if (pu32TransactionId)
233 {
234 uint32_t uTmp;
235 while ( u32TransactionId == (uTmp = *pu32TransactionId)
236 || (uTmp & 1))
237 ASMNopPause();
238 }
239 else
240 RTThreadSleep(1);
241 }
242 }
243
244 /*
245 * Display TSC deltas.
246 *
247 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
248 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
249 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
250 */
251 RTPrintf("tstGIP-2: TSC deltas:\n");
252 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
253 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
254 {
255 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
256 if (iCpu != UINT16_MAX)
257 {
258 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
259 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
260 }
261 }
262
263 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
264 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
265 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
266
267 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
268 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
269 if (uCpuHzRef)
270 {
271 if (cCpuHzOverallDevCnt)
272 {
273 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
274 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
275 uPct / 1000, (uPct % 1000) / 10);
276
277 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
278 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
279 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
280 }
281 else
282 {
283 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
284 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
285 }
286
287 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
288 cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
289
290 if ( !fCompat
291 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
292 rc = -1;
293 }
294
295 /* Disable GIP test mode. */
296 if (fTestMode)
297 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
298 }
299 else
300 {
301 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
302 rc = -1;
303 }
304
305 SUPR3Term(false /*fForced*/);
306 }
307 else
308 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
309 return !!rc;
310}
311
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette