VirtualBox

source: vbox/trunk/src/VBox/Main/BusAssignmentManager.cpp@ 34079

Last change on this file since 34079 was 34044, checked in by vboxsync, 14 years ago

Main: refcounting bug
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1/* $Id: BusAssignmentManager.cpp 34044 2010-11-12 19:05:42Z vboxsync $ */
2
3/** @file
4 *
5 * VirtualBox bus slots assignment manager
6 */
7
8/*
9 * Copyright (C) 2010 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19#include "BusAssignmentManager.h"
20
21#include <iprt/asm.h>
22
23#include <VBox/cfgm.h>
24
25#include <map>
26#include <vector>
27#include <algorithm>
28
29struct DeviceAssignmentRule
30{
31 const char* pszName;
32 int iBus;
33 int iDevice;
34 int iFn;
35 int iPriority;
36};
37
38struct DeviceAliasRule
39{
40 const char* pszDevName;
41 const char* pszDevAlias;
42};
43
44/* Those rules define PCI slots assignment */
45
46/* Device Bus Device Function Priority */
47
48/* Generic rules */
49static const DeviceAssignmentRule aGenericRules[] =
50{
51 /* VGA controller */
52 {"vga", 0, 2, 0, 0},
53
54 /* VMM device */
55 {"VMMDev", 0, 4, 0, 0},
56
57 /* Audio controllers */
58 {"ichac97", 0, 5, 0, 0},
59 {"hda", 0, 5, 0, 0},
60
61 /* Storage controllers */
62 {"ahci", 0, 13, 0, 1},
63 {"lsilogic", 0, 20, 0, 1},
64 {"buslogic", 0, 21, 0, 1},
65 {"lsilogicsas", 0, 22, 0, 1},
66
67 /* USB controllers */
68 {"usb-ohci", 0, 6, 0, 0},
69 {"usb-ehci", 0, 11, 0, 0},
70
71 /* ACPI controller */
72 {"acpi", 0, 7, 0, 0},
73
74 /* Network controllers */
75 /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
76 * next 4 get 16..19. */
77 {"nic", 0, 3, 0, 1},
78 {"nic", 0, 8, 0, 1},
79 {"nic", 0, 9, 0, 1},
80 {"nic", 0, 10, 0, 1},
81 {"nic", 0, 16, 0, 1},
82 {"nic", 0, 17, 0, 1},
83 {"nic", 0, 18, 0, 1},
84 {"nic", 0, 19, 0, 1},
85 /* VMWare assigns first NIC to slot 11 */
86 {"nic-vmware", 0, 11, 0, 1},
87
88 /* ISA/LPC controller */
89 {"lpc", 0, 31, 0, 0},
90
91 { NULL, -1, -1, -1, 0}
92};
93
94/* PIIX3 chipset rules */
95static const DeviceAssignmentRule aPiix3Rules[] =
96{
97 {"piix3ide", 0, 1, 1, 0},
98 {"pcibridge", 0, 24, 0, 0},
99 {"pcibridge", 0, 25, 0, 0},
100 { NULL, -1, -1, -1, 0}
101};
102
103
104/* ICH9 chipset rules */
105static const DeviceAssignmentRule aIch9Rules[] =
106{
107 /* Host Controller */
108 {"i82801", 0, 30, 0, 0},
109
110 /* Those are functions of LPC at 00:1e:00 */
111 /**
112 * Please note, that for devices being functions, like we do here, device 0
113 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
114 * Alternative approach is to assign separate slot to each device.
115 */
116 {"piix3ide", 0, 31, 1, 1},
117 {"ahci", 0, 31, 2, 1},
118 {"smbus", 0, 31, 3, 1},
119 {"usb-ohci", 0, 31, 4, 1},
120 {"usb-ehci", 0, 31, 5, 1},
121 {"thermal", 0, 31, 6, 1},
122
123 /* to make sure rule never used before rules assigning devices on it */
124 {"ich9pcibridge", 0, 24, 0, 10},
125 {"ich9pcibridge", 0, 25, 0, 10},
126 {"ich9pcibridge", 1, 24, 0, 9},
127 {"ich9pcibridge", 1, 25, 0, 9},
128 {"ich9pcibridge", 2, 24, 0, 8},
129 {"ich9pcibridge", 2, 25, 0, 8},
130 {"ich9pcibridge", 3, 24, 0, 7},
131 {"ich9pcibridge", 3, 25, 0, 7},
132 {"ich9pcibridge", 4, 24, 0, 6},
133 {"ich9pcibridge", 4, 25, 0, 6},
134 {"ich9pcibridge", 5, 24, 0, 5},
135 {"ich9pcibridge", 5, 25, 0, 5},
136
137 /* Storage controllers */
138 {"ahci", 1, 0, 0, 0},
139 {"ahci", 1, 1, 0, 0},
140 {"ahci", 1, 2, 0, 0},
141 {"ahci", 1, 3, 0, 0},
142 {"ahci", 1, 4, 0, 0},
143 {"ahci", 1, 5, 0, 0},
144 {"ahci", 1, 6, 0, 0},
145 {"lsilogic", 1, 7, 0, 0},
146 {"lsilogic", 1, 8, 0, 0},
147 {"lsilogic", 1, 9, 0, 0},
148 {"lsilogic", 1, 10, 0, 0},
149 {"lsilogic", 1, 11, 0, 0},
150 {"lsilogic", 1, 12, 0, 0},
151 {"lsilogic", 1, 13, 0, 0},
152 {"buslogic", 1, 14, 0, 0},
153 {"buslogic", 1, 15, 0, 0},
154 {"buslogic", 1, 16, 0, 0},
155 {"buslogic", 1, 17, 0, 0},
156 {"buslogic", 1, 18, 0, 0},
157 {"buslogic", 1, 19, 0, 0},
158 {"buslogic", 1, 20, 0, 0},
159 {"lsilogicsas", 1, 21, 0, 0},
160 {"lsilogicsas", 1, 26, 0, 0},
161 {"lsilogicsas", 1, 27, 0, 0},
162 {"lsilogicsas", 1, 28, 0, 0},
163 {"lsilogicsas", 1, 29, 0, 0},
164 {"lsilogicsas", 1, 30, 0, 0},
165 {"lsilogicsas", 1, 31, 0, 0},
166
167 /* NICs */
168 {"nic", 2, 0, 0, 0},
169 {"nic", 2, 1, 0, 0},
170 {"nic", 2, 2, 0, 0},
171 {"nic", 2, 3, 0, 0},
172 {"nic", 2, 4, 0, 0},
173 {"nic", 2, 5, 0, 0},
174 {"nic", 2, 6, 0, 0},
175 {"nic", 2, 7, 0, 0},
176 {"nic", 2, 8, 0, 0},
177 {"nic", 2, 9, 0, 0},
178 {"nic", 2, 10, 0, 0},
179 {"nic", 2, 11, 0, 0},
180 {"nic", 2, 12, 0, 0},
181 {"nic", 2, 13, 0, 0},
182 {"nic", 2, 14, 0, 0},
183 {"nic", 2, 15, 0, 0},
184 {"nic", 2, 16, 0, 0},
185 {"nic", 2, 17, 0, 0},
186 {"nic", 2, 18, 0, 0},
187 {"nic", 2, 19, 0, 0},
188 {"nic", 2, 20, 0, 0},
189 {"nic", 2, 21, 0, 0},
190 {"nic", 2, 26, 0, 0},
191 {"nic", 2, 27, 0, 0},
192 {"nic", 2, 28, 0, 0},
193 {"nic", 2, 29, 0, 0},
194 {"nic", 2, 30, 0, 0},
195 {"nic", 2, 31, 0, 0},
196
197 { NULL, -1, -1, -1, 0}
198};
199
200/* Aliasing rules */
201static const DeviceAliasRule aDeviceAliases[] =
202{
203 {"e1000", "nic"},
204 {"pcnet", "nic"},
205 {"virtio-net", "nic"},
206 {"ahci", "storage"},
207 {"lsilogic", "storage"},
208 {"buslogic", "storage"},
209 {"lsilogicsas", "storage"}
210};
211
212struct BusAssignmentManager::State
213{
214 struct PciDeviceRecord
215 {
216 char szDevName[16];
217
218 PciDeviceRecord(const char* pszName)
219 {
220 ::strncpy(szDevName, pszName, sizeof(szDevName));
221 }
222
223 bool operator<(const PciDeviceRecord &a) const
224 {
225 return ::strcmp(szDevName, a.szDevName) < 0;
226 }
227
228 bool operator==(const PciDeviceRecord &a) const
229 {
230 return ::strcmp(szDevName, a.szDevName) == 0;
231 }
232 };
233
234 typedef std::map <PciBusAddress,PciDeviceRecord > PciMap;
235 typedef std::vector<PciBusAddress> PciAddrList;
236 typedef std::vector<const DeviceAssignmentRule*> PciRulesList;
237 typedef std::map <PciDeviceRecord,PciAddrList > ReversePciMap;
238
239 volatile int32_t cRefCnt;
240 ChipsetType_T mChipsetType;
241 PciMap mPciMap;
242 ReversePciMap mReversePciMap;
243
244 State()
245 : cRefCnt(1), mChipsetType(ChipsetType_Null)
246 {}
247 ~State()
248 {}
249
250 HRESULT init(ChipsetType_T chipsetType);
251
252 HRESULT record(const char* pszName, PciBusAddress& Address);
253 HRESULT autoAssign(const char* pszName, PciBusAddress& Address);
254 bool checkAvailable(PciBusAddress& Address);
255 bool findPciAddress(const char* pszDevName, int iInstance, PciBusAddress& Address);
256
257 const char* findAlias(const char* pszName);
258 void addMatchingRules(const char* pszName, PciRulesList& aList);
259};
260
261HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
262{
263 mChipsetType = chipsetType;
264 return S_OK;
265}
266
267HRESULT BusAssignmentManager::State::record(const char* pszName, PciBusAddress& Address)
268{
269 PciDeviceRecord devRec(pszName);
270
271 /* Remember address -> device mapping */
272 mPciMap.insert(PciMap::value_type(Address, devRec));
273
274 ReversePciMap::iterator it = mReversePciMap.find(devRec);
275 if (it == mReversePciMap.end())
276 {
277 mReversePciMap.insert(ReversePciMap::value_type(devRec, PciAddrList()));
278 it = mReversePciMap.find(devRec);
279 }
280
281 /* Remember device name -> addresses mapping */
282 it->second.push_back(Address);
283
284 return S_OK;
285}
286
287bool BusAssignmentManager::State::findPciAddress(const char* pszDevName, int iInstance, PciBusAddress& Address)
288{
289 PciDeviceRecord devRec(pszDevName);
290
291 ReversePciMap::iterator it = mReversePciMap.find(devRec);
292 if (it == mReversePciMap.end())
293 return false;
294
295 if (iInstance >= (int)it->second.size())
296 return false;
297
298 Address = it->second[iInstance];
299 return true;
300}
301
302void BusAssignmentManager::State::addMatchingRules(const char* pszName, PciRulesList& aList)
303{
304 size_t iRuleset, iRule;
305 const DeviceAssignmentRule* aArrays[2] = {aGenericRules, NULL};
306
307 switch (mChipsetType)
308 {
309 case ChipsetType_PIIX3:
310 aArrays[1] = aPiix3Rules;
311 break;
312 case ChipsetType_ICH9:
313 aArrays[1] = aIch9Rules;
314 break;
315 default:
316 Assert(false);
317 break;
318 }
319
320 for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
321 {
322 if (aArrays[iRuleset] == NULL)
323 continue;
324
325 for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
326 {
327 if (strcmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
328 aList.push_back(&aArrays[iRuleset][iRule]);
329 }
330 }
331}
332
333const char* BusAssignmentManager::State::findAlias(const char* pszDev)
334{
335 for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
336 {
337 if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
338 return aDeviceAliases[iAlias].pszDevAlias;
339 }
340 return NULL;
341}
342
343static bool RuleComparator(const DeviceAssignmentRule* r1, const DeviceAssignmentRule* r2)
344{
345 return (r1->iPriority > r2->iPriority);
346}
347
348HRESULT BusAssignmentManager::State::autoAssign(const char* pszName, PciBusAddress& Address)
349{
350 PciRulesList matchingRules;
351
352 addMatchingRules(pszName, matchingRules);
353 const char* pszAlias = findAlias(pszName);
354 if (pszAlias)
355 addMatchingRules(pszAlias, matchingRules);
356
357 AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
358
359 sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
360
361 for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
362 {
363 const DeviceAssignmentRule* rule = matchingRules[iRule];
364
365 Address.iBus = rule->iBus;
366 Address.iDevice = rule->iDevice;
367 Address.iFn = rule->iFn;
368
369 if (checkAvailable(Address))
370 return S_OK;
371 }
372 AssertMsg(false, ("All possible candidate positions for %s exhausted\n", pszName));
373
374 return E_INVALIDARG;
375}
376
377bool BusAssignmentManager::State::checkAvailable(PciBusAddress& Address)
378{
379 PciMap::const_iterator it = mPciMap.find(Address);
380
381 return (it == mPciMap.end());
382}
383
384BusAssignmentManager::BusAssignmentManager()
385 : pState(NULL)
386{
387 pState = new State();
388 Assert(pState);
389}
390
391BusAssignmentManager::~BusAssignmentManager()
392{
393 if (pState)
394 {
395 delete pState;
396 pState = NULL;
397 }
398}
399
400
401BusAssignmentManager* BusAssignmentManager::pInstance = NULL;
402
403BusAssignmentManager* BusAssignmentManager::getInstance(ChipsetType_T chipsetType)
404{
405 if (pInstance == NULL)
406 {
407 pInstance = new BusAssignmentManager();
408 pInstance->pState->init(chipsetType);
409 Assert(pInstance);
410 return pInstance;
411 }
412
413 pInstance->AddRef();
414 return pInstance;
415}
416
417void BusAssignmentManager::AddRef()
418{
419 ASMAtomicIncS32(&pState->cRefCnt);
420}
421void BusAssignmentManager::Release()
422{
423 if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
424 delete this;
425}
426
427DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char* pszName, uint64_t u64)
428{
429 int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
430 if (RT_FAILURE(vrc))
431 return E_INVALIDARG;
432
433 return S_OK;
434}
435
436HRESULT BusAssignmentManager::assignPciDevice(const char* pszDevName, PCFGMNODE pCfg,
437 PciBusAddress& Address, bool fAddressRequired)
438{
439 HRESULT rc = S_OK;
440
441 if (!Address.valid())
442 rc = pState->autoAssign(pszDevName, Address);
443 else
444 {
445 bool fAvailable = pState->checkAvailable(Address);
446
447 if (!fAvailable)
448 {
449 if (fAddressRequired)
450 rc = E_ACCESSDENIED;
451 else
452 rc = pState->autoAssign(pszDevName, Address);
453 }
454 }
455
456 if (FAILED(rc))
457 return rc;
458
459 Assert(Address.valid() && pState->checkAvailable(Address));
460
461 rc = pState->record(pszDevName, Address);
462 if (FAILED(rc))
463 return rc;
464
465 rc = InsertConfigInteger(pCfg, "PCIBusNo", Address.iBus);
466 if (FAILED(rc))
467 return rc;
468 rc = InsertConfigInteger(pCfg, "PCIDeviceNo", Address.iDevice);
469 if (FAILED(rc))
470 return rc;
471 rc = InsertConfigInteger(pCfg, "PCIFunctionNo", Address.iFn);
472 if (FAILED(rc))
473 return rc;
474
475 return S_OK;
476}
477
478
479bool BusAssignmentManager::findPciAddress(const char* pszDevName, int iInstance, PciBusAddress& Address)
480{
481 return pState->findPciAddress(pszDevName, iInstance, Address);
482}
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