VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 85959

Last change on this file since 85959 was 85011, checked in by vboxsync, 4 years ago

Main/BusAssignmentManager: Prepend global variables with "g_".
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1/* $Id: BusAssignmentManager.cpp 85011 2020-06-30 17:28:26Z vboxsync $ */
2/** @file
3 * VirtualBox bus slots assignment manager
4 */
5
6/*
7 * Copyright (C) 2010-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#define LOG_GROUP LOG_GROUP_MAIN
19#include "LoggingNew.h"
20
21#include "BusAssignmentManager.h"
22
23#include <iprt/asm.h>
24#include <iprt/string.h>
25
26#include <VBox/vmm/cfgm.h>
27#include <VBox/com/array.h>
28
29#include <map>
30#include <vector>
31#include <algorithm>
32
33struct DeviceAssignmentRule
34{
35 const char *pszName;
36 int iBus;
37 int iDevice;
38 int iFn;
39 int iPriority;
40};
41
42struct DeviceAliasRule
43{
44 const char *pszDevName;
45 const char *pszDevAlias;
46};
47
48/* Those rules define PCI slots assignment */
49/** @note
50 * The EFI takes assumptions about PCI slot assignments which are different
51 * from the following tables in certain cases, for example the IDE device
52 * is assumed to be 00:01.1! */
53
54/* Device Bus Device Function Priority */
55
56/* Generic rules */
57static const DeviceAssignmentRule g_aGenericRules[] =
58{
59 /* VGA controller */
60 {"vga", 0, 2, 0, 0},
61
62 /* VMM device */
63 {"VMMDev", 0, 4, 0, 0},
64
65 /* Audio controllers */
66 {"ichac97", 0, 5, 0, 0},
67 {"hda", 0, 5, 0, 0},
68
69 /* Storage controllers */
70 {"buslogic", 0, 21, 0, 1},
71 {"lsilogicsas", 0, 22, 0, 1},
72 {"nvme", 0, 14, 0, 1},
73 {"virtio-scsi", 0, 15, 0, 1},
74
75 /* USB controllers */
76 {"usb-ohci", 0, 6, 0, 0},
77 {"usb-ehci", 0, 11, 0, 0},
78 {"usb-xhci", 0, 12, 0, 0},
79
80 /* ACPI controller */
81#if 0
82 // It really should be this for 440FX chipset (part of PIIX4 actually)
83 {"acpi", 0, 1, 3, 0},
84#else
85 {"acpi", 0, 7, 0, 0},
86#endif
87
88 /* Network controllers */
89 /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
90 * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
91 * swap places, i.e. the first card goes to ID 17=0x11. */
92 {"nic", 0, 3, 0, 1},
93 {"nic", 0, 8, 0, 1},
94 {"nic", 0, 9, 0, 1},
95 {"nic", 0, 10, 0, 1},
96 {"nic", 0, 16, 0, 1},
97 {"nic", 0, 17, 0, 1},
98 {"nic", 0, 18, 0, 1},
99 {"nic", 0, 19, 0, 1},
100
101 /* ISA/LPC controller */
102 {"lpc", 0, 31, 0, 0},
103
104 { NULL, -1, -1, -1, 0}
105};
106
107/* PIIX3 chipset rules */
108static const DeviceAssignmentRule g_aPiix3Rules[] =
109{
110 {"piix3ide", 0, 1, 1, 0},
111 {"ahci", 0, 13, 0, 1},
112 {"lsilogic", 0, 20, 0, 1},
113 {"pcibridge", 0, 24, 0, 0},
114 {"pcibridge", 0, 25, 0, 0},
115 { NULL, -1, -1, -1, 0}
116};
117
118
119/* ICH9 chipset rules */
120static const DeviceAssignmentRule g_aIch9Rules[] =
121{
122 /* Host Controller */
123 {"i82801", 0, 30, 0, 0},
124
125 /* Those are functions of LPC at 00:1e:00 */
126 /**
127 * Please note, that for devices being functions, like we do here, device 0
128 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
129 * Alternative approach is to assign separate slot to each device.
130 */
131 {"piix3ide", 0, 31, 1, 2},
132 {"ahci", 0, 31, 2, 2},
133 {"smbus", 0, 31, 3, 2},
134 {"usb-ohci", 0, 31, 4, 2},
135 {"usb-ehci", 0, 31, 5, 2},
136 {"thermal", 0, 31, 6, 2},
137
138 /* to make sure rule never used before rules assigning devices on it */
139 {"ich9pcibridge", 0, 24, 0, 10},
140 {"ich9pcibridge", 0, 25, 0, 10},
141 {"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
142 {"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
143 {"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
144 {"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
145 {"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
146 {"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
147 {"ich9pcibridge", 8, 24, 0, 6},
148 {"ich9pcibridge", 8, 25, 0, 6},
149 {"ich9pcibridge", 10, 24, 0, 5},
150 {"ich9pcibridge", 10, 25, 0, 5},
151
152 /* Storage controllers */
153 {"ahci", 1, 0, 0, 0},
154 {"ahci", 1, 1, 0, 0},
155 {"ahci", 1, 2, 0, 0},
156 {"ahci", 1, 3, 0, 0},
157 {"ahci", 1, 4, 0, 0},
158 {"ahci", 1, 5, 0, 0},
159 {"ahci", 1, 6, 0, 0},
160 {"lsilogic", 1, 7, 0, 0},
161 {"lsilogic", 1, 8, 0, 0},
162 {"lsilogic", 1, 9, 0, 0},
163 {"lsilogic", 1, 10, 0, 0},
164 {"lsilogic", 1, 11, 0, 0},
165 {"lsilogic", 1, 12, 0, 0},
166 {"lsilogic", 1, 13, 0, 0},
167 {"buslogic", 1, 14, 0, 0},
168 {"buslogic", 1, 15, 0, 0},
169 {"buslogic", 1, 16, 0, 0},
170 {"buslogic", 1, 17, 0, 0},
171 {"buslogic", 1, 18, 0, 0},
172 {"buslogic", 1, 19, 0, 0},
173 {"buslogic", 1, 20, 0, 0},
174 {"lsilogicsas", 1, 21, 0, 0},
175 {"lsilogicsas", 1, 26, 0, 0},
176 {"lsilogicsas", 1, 27, 0, 0},
177 {"lsilogicsas", 1, 28, 0, 0},
178 {"lsilogicsas", 1, 29, 0, 0},
179 {"lsilogicsas", 1, 30, 0, 0},
180 {"lsilogicsas", 1, 31, 0, 0},
181
182 /* NICs */
183 {"nic", 2, 0, 0, 0},
184 {"nic", 2, 1, 0, 0},
185 {"nic", 2, 2, 0, 0},
186 {"nic", 2, 3, 0, 0},
187 {"nic", 2, 4, 0, 0},
188 {"nic", 2, 5, 0, 0},
189 {"nic", 2, 6, 0, 0},
190 {"nic", 2, 7, 0, 0},
191 {"nic", 2, 8, 0, 0},
192 {"nic", 2, 9, 0, 0},
193 {"nic", 2, 10, 0, 0},
194 {"nic", 2, 11, 0, 0},
195 {"nic", 2, 12, 0, 0},
196 {"nic", 2, 13, 0, 0},
197 {"nic", 2, 14, 0, 0},
198 {"nic", 2, 15, 0, 0},
199 {"nic", 2, 16, 0, 0},
200 {"nic", 2, 17, 0, 0},
201 {"nic", 2, 18, 0, 0},
202 {"nic", 2, 19, 0, 0},
203 {"nic", 2, 20, 0, 0},
204 {"nic", 2, 21, 0, 0},
205 {"nic", 2, 26, 0, 0},
206 {"nic", 2, 27, 0, 0},
207 {"nic", 2, 28, 0, 0},
208 {"nic", 2, 29, 0, 0},
209 {"nic", 2, 30, 0, 0},
210 {"nic", 2, 31, 0, 0},
211
212 /* Storage controller #2 (NVMe, virtio-scsi) */
213 {"nvme", 3, 0, 0, 0},
214 {"nvme", 3, 1, 0, 0},
215 {"nvme", 3, 2, 0, 0},
216 {"nvme", 3, 3, 0, 0},
217 {"nvme", 3, 4, 0, 0},
218 {"nvme", 3, 5, 0, 0},
219 {"nvme", 3, 6, 0, 0},
220 {"virtio-scsi", 3, 7, 0, 0},
221 {"virtio-scsi", 3, 8, 0, 0},
222 {"virtio-scsi", 3, 9, 0, 0},
223 {"virtio-scsi", 3, 10, 0, 0},
224 {"virtio-scsi", 3, 11, 0, 0},
225 {"virtio-scsi", 3, 12, 0, 0},
226 {"virtio-scsi", 3, 13, 0, 0},
227
228 { NULL, -1, -1, -1, 0}
229};
230
231
232#ifdef VBOX_WITH_IOMMU_AMD
233/*
234 * AMD IOMMU and LSI Logic controller rules.
235 *
236 * Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
237 * conflicts with the SB I/O APIC, we assign the LSI Logic controller
238 * to device number 23 when the VM is configured for an AMD IOMMU.
239 */
240static const DeviceAssignmentRule g_aIch9IommuLsiRules[] =
241{
242 /* AMD IOMMU. */
243 {"iommu-amd", 0, 0, 2, 0},
244 /* AMD IOMMU: Reserved for southbridge I/O APIC. */
245 {"sb-ioapic", 0, 20, 0, 0},
246
247 /* Storage controller */
248 {"lsilogic", 0, 23, 0, 1},
249 { NULL, -1, -1, -1, 0}
250};
251#endif
252
253/* LSI Logic Controller. */
254static const DeviceAssignmentRule g_aIch9LsiRules[] =
255{
256 /* Storage controller */
257 {"lsilogic", 0, 20, 0, 1},
258 { NULL, -1, -1, -1, 0}
259};
260
261/* Aliasing rules */
262static const DeviceAliasRule g_aDeviceAliases[] =
263{
264 {"e1000", "nic"},
265 {"pcnet", "nic"},
266 {"virtio-net", "nic"},
267 {"ahci", "storage"},
268 {"lsilogic", "storage"},
269 {"buslogic", "storage"},
270 {"lsilogicsas", "storage"},
271 {"nvme", "storage"},
272 {"virtio-scsi", "storage"}
273};
274
275struct BusAssignmentManager::State
276{
277 struct PCIDeviceRecord
278 {
279 char szDevName[32];
280 PCIBusAddress HostAddress;
281
282 PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
283 {
284 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
285 this->HostAddress = aHostAddress;
286 }
287
288 PCIDeviceRecord(const char *pszName)
289 {
290 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
291 }
292
293 bool operator<(const PCIDeviceRecord &a) const
294 {
295 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
296 }
297
298 bool operator==(const PCIDeviceRecord &a) const
299 {
300 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
301 }
302 };
303
304 typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
305 typedef std::vector<PCIBusAddress> PCIAddrList;
306 typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
307 typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
308
309 volatile int32_t cRefCnt;
310 ChipsetType_T mChipsetType;
311 const char * mpszBridgeName;
312 bool mfIommu;
313 PCIMap mPCIMap;
314 ReversePCIMap mReversePCIMap;
315
316 State()
317 : cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge")
318 {}
319 ~State()
320 {}
321
322 HRESULT init(ChipsetType_T chipsetType, bool fIommu);
323
324 HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
325 HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
326 bool checkAvailable(PCIBusAddress& Address);
327 bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
328
329 const char *findAlias(const char *pszName);
330 void addMatchingRules(const char *pszName, PCIRulesList& aList);
331 void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
332};
333
334HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType, bool fIommu)
335{
336 mChipsetType = chipsetType;
337 mfIommu = fIommu;
338 switch (chipsetType)
339 {
340 case ChipsetType_PIIX3:
341 mpszBridgeName = "pcibridge";
342 break;
343 case ChipsetType_ICH9:
344 mpszBridgeName = "ich9pcibridge";
345 break;
346 default:
347 mpszBridgeName = "unknownbridge";
348 AssertFailed();
349 break;
350 }
351 return S_OK;
352}
353
354HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
355{
356 PCIDeviceRecord devRec(pszName, HostAddress);
357
358 /* Remember address -> device mapping */
359 mPCIMap.insert(PCIMap::value_type(Address, devRec));
360
361 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
362 if (it == mReversePCIMap.end())
363 {
364 mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
365 it = mReversePCIMap.find(devRec);
366 }
367
368 /* Remember device name -> addresses mapping */
369 it->second.push_back(Address);
370
371 return S_OK;
372}
373
374bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
375{
376 PCIDeviceRecord devRec(pszDevName);
377
378 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
379 if (it == mReversePCIMap.end())
380 return false;
381
382 if (iInstance >= (int)it->second.size())
383 return false;
384
385 Address = it->second[iInstance];
386 return true;
387}
388
389void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
390{
391 size_t iRuleset, iRule;
392 const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
393
394 switch (mChipsetType)
395 {
396 case ChipsetType_PIIX3:
397 aArrays[1] = g_aPiix3Rules;
398 break;
399 case ChipsetType_ICH9:
400 {
401 aArrays[1] = g_aIch9Rules;
402#ifdef VBOX_WITH_IOMMU_AMD
403 if (mfIommu)
404 aArrays[2] = g_aIch9IommuLsiRules;
405 else
406#endif
407 {
408 aArrays[2] = g_aIch9LsiRules;
409 }
410 break;
411 }
412 default:
413 AssertFailed();
414 break;
415 }
416
417 for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
418 {
419 if (aArrays[iRuleset] == NULL)
420 continue;
421
422 for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
423 {
424 if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
425 aList.push_back(&aArrays[iRuleset][iRule]);
426 }
427 }
428}
429
430const char *BusAssignmentManager::State::findAlias(const char *pszDev)
431{
432 for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
433 {
434 if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
435 return g_aDeviceAliases[iAlias].pszDevAlias;
436 }
437 return NULL;
438}
439
440static bool RuleComparator(const DeviceAssignmentRule *r1, const DeviceAssignmentRule *r2)
441{
442 return (r1->iPriority > r2->iPriority);
443}
444
445HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
446{
447 PCIRulesList matchingRules;
448
449 addMatchingRules(pszName, matchingRules);
450 const char *pszAlias = findAlias(pszName);
451 if (pszAlias)
452 addMatchingRules(pszAlias, matchingRules);
453
454 AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
455
456 stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
457
458 for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
459 {
460 const DeviceAssignmentRule *rule = matchingRules[iRule];
461
462 Address.miBus = rule->iBus;
463 Address.miDevice = rule->iDevice;
464 Address.miFn = rule->iFn;
465
466 if (checkAvailable(Address))
467 return S_OK;
468 }
469 AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
470
471 return E_INVALIDARG;
472}
473
474bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
475{
476 PCIMap::const_iterator it = mPCIMap.find(Address);
477
478 return (it == mPCIMap.end());
479}
480
481void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
482{
483 aAttached.resize(mPCIMap.size());
484
485 size_t i = 0;
486 PCIDeviceInfo dev;
487 for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
488 {
489 dev.strDeviceName = it->second.szDevName;
490 dev.guestAddress = it->first;
491 dev.hostAddress = it->second.HostAddress;
492 aAttached[i] = dev;
493 }
494}
495
496BusAssignmentManager::BusAssignmentManager()
497 : pState(NULL)
498{
499 pState = new State();
500 Assert(pState);
501}
502
503BusAssignmentManager::~BusAssignmentManager()
504{
505 if (pState)
506 {
507 delete pState;
508 pState = NULL;
509 }
510}
511
512BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType, bool fIommu)
513{
514 BusAssignmentManager *pInstance = new BusAssignmentManager();
515 pInstance->pState->init(chipsetType, fIommu);
516 Assert(pInstance);
517 return pInstance;
518}
519
520void BusAssignmentManager::AddRef()
521{
522 ASMAtomicIncS32(&pState->cRefCnt);
523}
524void BusAssignmentManager::Release()
525{
526 if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
527 delete this;
528}
529
530DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char *pszName, uint64_t u64)
531{
532 int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
533 if (RT_FAILURE(vrc))
534 return E_INVALIDARG;
535
536 return S_OK;
537}
538
539DECLINLINE(HRESULT) InsertConfigNode(PCFGMNODE pNode, const char *pcszName, PCFGMNODE *ppChild)
540{
541 int vrc = CFGMR3InsertNode(pNode, pcszName, ppChild);
542 if (RT_FAILURE(vrc))
543 return E_INVALIDARG;
544
545 return S_OK;
546}
547
548
549HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
550 PCFGMNODE pCfg,
551 PCIBusAddress& GuestAddress,
552 PCIBusAddress HostAddress,
553 bool fGuestAddressRequired)
554{
555 HRESULT rc = S_OK;
556
557 if (!GuestAddress.valid())
558 rc = pState->autoAssign(pszDevName, GuestAddress);
559 else
560 {
561 bool fAvailable = pState->checkAvailable(GuestAddress);
562
563 if (!fAvailable)
564 {
565 if (fGuestAddressRequired)
566 rc = E_ACCESSDENIED;
567 else
568 rc = pState->autoAssign(pszDevName, GuestAddress);
569 }
570 }
571
572 if (FAILED(rc))
573 return rc;
574
575 Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
576
577 rc = pState->record(pszDevName, GuestAddress, HostAddress);
578 if (FAILED(rc))
579 return rc;
580
581 if (pCfg)
582 {
583 rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
584 if (FAILED(rc))
585 return rc;
586 rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
587 if (FAILED(rc))
588 return rc;
589 rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
590 if (FAILED(rc))
591 return rc;
592 }
593
594 /* Check if the bus is still unknown, i.e. the bridge to it is missing */
595 if ( GuestAddress.miBus > 0
596 && !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
597 {
598 PCFGMNODE pDevices = CFGMR3GetParent(CFGMR3GetParent(pCfg));
599 AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
600 PCFGMNODE pBridges = CFGMR3GetChild(pDevices, "ich9pcibridge");
601 AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
602
603 /* Device should be on a not yet existing bus, add it automatically */
604 for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
605 {
606 if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
607 {
608 PCIBusAddress BridgeGuestAddress;
609 rc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
610 if (FAILED(rc))
611 return rc;
612 if (BridgeGuestAddress.miBus > iBridge)
613 AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
614
615 PCFGMNODE pInst;
616 InsertConfigNode(pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
617 InsertConfigInteger(pInst, "Trusted", 1);
618 rc = assignPCIDevice(pState->mpszBridgeName, pInst);
619 if (FAILED(rc))
620 return rc;
621 }
622 }
623 }
624
625 return S_OK;
626}
627
628
629bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
630{
631 return pState->findPCIAddress(pszDevName, iInstance, Address);
632}
633void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
634{
635 pState->listAttachedPCIDevices(aAttached);
636}
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