BusAssignmentManager.cpp@ 88382

Last change on this file since 88382 was 88333, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 ACPI, BusAssignmentManager and ConsoleImpl2 changes for VT-d PCI device.
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1	/* $Id: BusAssignmentManager.cpp 88333 2021-03-31 16:29:39Z vboxsync $ */
2	/** @file
3	* VirtualBox bus slots assignment manager
4	*/
5
6	/*
7	* Copyright (C) 2010-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#define LOG_GROUP LOG_GROUP_MAIN
19	#include "LoggingNew.h"
20
21	#include "BusAssignmentManager.h"
22
23	#include <iprt/asm.h>
24	#include <iprt/string.h>
25
26	#include <VBox/vmm/cfgm.h>
27	#include <VBox/com/array.h>
28
29	#include <map>
30	#include <vector>
31	#include <algorithm>
32
33	struct DeviceAssignmentRule
34	{
35	const char *pszName;
36	int iBus;
37	int iDevice;
38	int iFn;
39	int iPriority;
40	};
41
42	struct DeviceAliasRule
43	{
44	const char *pszDevName;
45	const char *pszDevAlias;
46	};
47
48	/* Those rules define PCI slots assignment */
49	/** @note
50	* The EFI takes assumptions about PCI slot assignments which are different
51	* from the following tables in certain cases, for example the IDE device
52	* is assumed to be 00:01.1! */
53
54	/* Device Bus Device Function Priority */
55
56	/* Generic rules */
57	static const DeviceAssignmentRule g_aGenericRules[] =
58	{
59	/* VGA controller */
60	{"vga", 0, 2, 0, 0},
61
62	/* VMM device */
63	{"VMMDev", 0, 4, 0, 0},
64
65	/* Audio controllers */
66	{"ichac97", 0, 5, 0, 0},
67	{"hda", 0, 5, 0, 0},
68
69	/* Storage controllers */
70	{"buslogic", 0, 21, 0, 1},
71	{"lsilogicsas", 0, 22, 0, 1},
72	{"nvme", 0, 14, 0, 1},
73	{"virtio-scsi", 0, 15, 0, 1},
74
75	/* USB controllers */
76	{"usb-ohci", 0, 6, 0, 0},
77	{"usb-ehci", 0, 11, 0, 0},
78	{"usb-xhci", 0, 12, 0, 0},
79
80	/* ACPI controller */
81	#if 0
82	// It really should be this for 440FX chipset (part of PIIX4 actually)
83	{"acpi", 0, 1, 3, 0},
84	#else
85	{"acpi", 0, 7, 0, 0},
86	#endif
87
88	/* Network controllers */
89	/* the first network card gets the PCI ID 3, the next 3 gets 8..10,
90	* next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
91	* swap places, i.e. the first card goes to ID 17=0x11. */
92	{"nic", 0, 3, 0, 1},
93	{"nic", 0, 8, 0, 1},
94	{"nic", 0, 9, 0, 1},
95	{"nic", 0, 10, 0, 1},
96	{"nic", 0, 16, 0, 1},
97	{"nic", 0, 17, 0, 1},
98	{"nic", 0, 18, 0, 1},
99	{"nic", 0, 19, 0, 1},
100
101	/* ISA/LPC controller */
102	{"lpc", 0, 31, 0, 0},
103
104	{ NULL, -1, -1, -1, 0}
105	};
106
107	/* PIIX3 chipset rules */
108	static const DeviceAssignmentRule g_aPiix3Rules[] =
109	{
110	{"piix3ide", 0, 1, 1, 0},
111	{"ahci", 0, 13, 0, 1},
112	{"lsilogic", 0, 20, 0, 1},
113	{"pcibridge", 0, 24, 0, 0},
114	{"pcibridge", 0, 25, 0, 0},
115	{ NULL, -1, -1, -1, 0}
116	};
117
118
119	/* ICH9 chipset rules */
120	static const DeviceAssignmentRule g_aIch9Rules[] =
121	{
122	/* Host Controller */
123	{"i82801", 0, 30, 0, 0},
124
125	/* Those are functions of LPC at 00:1e:00 */
126	/**
127	* Please note, that for devices being functions, like we do here, device 0
128	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
129	* Alternative approach is to assign separate slot to each device.
130	*/
131	{"piix3ide", 0, 31, 1, 2},
132	{"ahci", 0, 31, 2, 2},
133	{"smbus", 0, 31, 3, 2},
134	{"usb-ohci", 0, 31, 4, 2},
135	{"usb-ehci", 0, 31, 5, 2},
136	{"thermal", 0, 31, 6, 2},
137
138	/* to make sure rule never used before rules assigning devices on it */
139	{"ich9pcibridge", 0, 24, 0, 10},
140	{"ich9pcibridge", 0, 25, 0, 10},
141	{"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
142	{"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
143	{"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
144	{"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
145	{"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
146	{"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
147	{"ich9pcibridge", 8, 24, 0, 6},
148	{"ich9pcibridge", 8, 25, 0, 6},
149	{"ich9pcibridge", 10, 24, 0, 5},
150	{"ich9pcibridge", 10, 25, 0, 5},
151
152	/* Storage controllers */
153	{"ahci", 1, 0, 0, 0},
154	{"ahci", 1, 1, 0, 0},
155	{"ahci", 1, 2, 0, 0},
156	{"ahci", 1, 3, 0, 0},
157	{"ahci", 1, 4, 0, 0},
158	{"ahci", 1, 5, 0, 0},
159	{"ahci", 1, 6, 0, 0},
160	{"lsilogic", 1, 7, 0, 0},
161	{"lsilogic", 1, 8, 0, 0},
162	{"lsilogic", 1, 9, 0, 0},
163	{"lsilogic", 1, 10, 0, 0},
164	{"lsilogic", 1, 11, 0, 0},
165	{"lsilogic", 1, 12, 0, 0},
166	{"lsilogic", 1, 13, 0, 0},
167	{"buslogic", 1, 14, 0, 0},
168	{"buslogic", 1, 15, 0, 0},
169	{"buslogic", 1, 16, 0, 0},
170	{"buslogic", 1, 17, 0, 0},
171	{"buslogic", 1, 18, 0, 0},
172	{"buslogic", 1, 19, 0, 0},
173	{"buslogic", 1, 20, 0, 0},
174	{"lsilogicsas", 1, 21, 0, 0},
175	{"lsilogicsas", 1, 26, 0, 0},
176	{"lsilogicsas", 1, 27, 0, 0},
177	{"lsilogicsas", 1, 28, 0, 0},
178	{"lsilogicsas", 1, 29, 0, 0},
179	{"lsilogicsas", 1, 30, 0, 0},
180	{"lsilogicsas", 1, 31, 0, 0},
181
182	/* NICs */
183	{"nic", 2, 0, 0, 0},
184	{"nic", 2, 1, 0, 0},
185	{"nic", 2, 2, 0, 0},
186	{"nic", 2, 3, 0, 0},
187	{"nic", 2, 4, 0, 0},
188	{"nic", 2, 5, 0, 0},
189	{"nic", 2, 6, 0, 0},
190	{"nic", 2, 7, 0, 0},
191	{"nic", 2, 8, 0, 0},
192	{"nic", 2, 9, 0, 0},
193	{"nic", 2, 10, 0, 0},
194	{"nic", 2, 11, 0, 0},
195	{"nic", 2, 12, 0, 0},
196	{"nic", 2, 13, 0, 0},
197	{"nic", 2, 14, 0, 0},
198	{"nic", 2, 15, 0, 0},
199	{"nic", 2, 16, 0, 0},
200	{"nic", 2, 17, 0, 0},
201	{"nic", 2, 18, 0, 0},
202	{"nic", 2, 19, 0, 0},
203	{"nic", 2, 20, 0, 0},
204	{"nic", 2, 21, 0, 0},
205	{"nic", 2, 26, 0, 0},
206	{"nic", 2, 27, 0, 0},
207	{"nic", 2, 28, 0, 0},
208	{"nic", 2, 29, 0, 0},
209	{"nic", 2, 30, 0, 0},
210	{"nic", 2, 31, 0, 0},
211
212	/* Storage controller #2 (NVMe, virtio-scsi) */
213	{"nvme", 3, 0, 0, 0},
214	{"nvme", 3, 1, 0, 0},
215	{"nvme", 3, 2, 0, 0},
216	{"nvme", 3, 3, 0, 0},
217	{"nvme", 3, 4, 0, 0},
218	{"nvme", 3, 5, 0, 0},
219	{"nvme", 3, 6, 0, 0},
220	{"virtio-scsi", 3, 7, 0, 0},
221	{"virtio-scsi", 3, 8, 0, 0},
222	{"virtio-scsi", 3, 9, 0, 0},
223	{"virtio-scsi", 3, 10, 0, 0},
224	{"virtio-scsi", 3, 11, 0, 0},
225	{"virtio-scsi", 3, 12, 0, 0},
226	{"virtio-scsi", 3, 13, 0, 0},
227
228	{ NULL, -1, -1, -1, 0}
229	};
230
231
232	#ifdef VBOX_WITH_IOMMU_AMD
233	/*
234	* AMD IOMMU and LSI Logic controller rules.
235	*
236	* Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
237	* conflicts with the SB I/O APIC, we assign the LSI Logic controller
238	* to device number 23 when the VM is configured for an AMD IOMMU.
239	*/
240	static const DeviceAssignmentRule g_aIch9IommuAmdRules[] =
241	{
242	/* AMD IOMMU. */
243	{"iommu-amd", 0, 0, 0, 0},
244	/* AMD IOMMU: Reserved for southbridge I/O APIC. */
245	{"sb-ioapic", 0, 20, 0, 0},
246
247	/* Storage controller */
248	{"lsilogic", 0, 23, 0, 1},
249	{ NULL, -1, -1, -1, 0}
250	};
251	#endif
252
253	#ifdef VBOX_WITH_IOMMU_INTEL
254	/*
255	* Intel IOMMU.
256	* The VT-d misc, address remapping, system management device is
257	* located at BDF 00:5:0 on real hardware so we mimick the same.
258	* LSI logic remains at 0:20:0.
259	*/
260	static const DeviceAssignmentRule g_aIch9IommuIntelRules[] =
261	{
262	/* Intel IOMMU. */
263	{"iommu-intel", 0, 5, 0, 0},
264
265	/* Storage controller */
266	{"lsilogic", 0, 20, 0, 1},
267	{ NULL, -1, -1, -1, 0}
268	};
269	#endif
270
271	/* LSI Logic Controller. */
272	static const DeviceAssignmentRule g_aIch9LsiRules[] =
273	{
274	/* Storage controller */
275	{"lsilogic", 0, 20, 0, 1},
276	{ NULL, -1, -1, -1, 0}
277	};
278
279	/* Aliasing rules */
280	static const DeviceAliasRule g_aDeviceAliases[] =
281	{
282	{"e1000", "nic"},
283	{"pcnet", "nic"},
284	{"virtio-net", "nic"},
285	{"ahci", "storage"},
286	{"lsilogic", "storage"},
287	{"buslogic", "storage"},
288	{"lsilogicsas", "storage"},
289	{"nvme", "storage"},
290	{"virtio-scsi", "storage"}
291	};
292
293	struct BusAssignmentManager::State
294	{
295	struct PCIDeviceRecord
296	{
297	char szDevName[32];
298	PCIBusAddress HostAddress;
299
300	PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
301	{
302	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
303	this->HostAddress = aHostAddress;
304	}
305
306	PCIDeviceRecord(const char *pszName)
307	{
308	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
309	}
310
311	bool operator<(const PCIDeviceRecord &a) const
312	{
313	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
314	}
315
316	bool operator==(const PCIDeviceRecord &a) const
317	{
318	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
319	}
320	};
321
322	typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
323	typedef std::vector<PCIBusAddress> PCIAddrList;
324	typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
325	typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
326
327	volatile int32_t cRefCnt;
328	ChipsetType_T mChipsetType;
329	const char * mpszBridgeName;
330	IommuType_T mIommuType;
331	PCIMap mPCIMap;
332	ReversePCIMap mReversePCIMap;
333
334	State()
335	: cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge")
336	{}
337	~State()
338	{}
339
340	HRESULT init(ChipsetType_T chipsetType, IommuType_T iommuType);
341
342	HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
343	HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
344	bool checkAvailable(PCIBusAddress& Address);
345	bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
346
347	const char findAlias(const char pszName);
348	void addMatchingRules(const char *pszName, PCIRulesList& aList);
349	void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
350	};
351
352	HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType, IommuType_T iommuType)
353	{
354	if (iommuType != IommuType_None)
355	{
356	#if defined(VBOX_WITH_IOMMU_AMD) && defined(VBOX_WITH_IOMMU_INTEL)
357	Assert(iommuType == IommuType_AMD \|\| iommuType == IommuType_Intel);
358	#elif defined(VBOX_WITH_IOMMU_AMD)
359	Assert(iommuType == IommuType_AMD);
360	#elif defined(VBOX_WITH_IOMMU_INTEL)
361	Assert(iommuType == IommuType_Intel);
362	#endif
363	}
364
365	mChipsetType = chipsetType;
366	mIommuType = iommuType;
367	switch (chipsetType)
368	{
369	case ChipsetType_PIIX3:
370	mpszBridgeName = "pcibridge";
371	break;
372	case ChipsetType_ICH9:
373	mpszBridgeName = "ich9pcibridge";
374	break;
375	default:
376	mpszBridgeName = "unknownbridge";
377	AssertFailed();
378	break;
379	}
380	return S_OK;
381	}
382
383	HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
384	{
385	PCIDeviceRecord devRec(pszName, HostAddress);
386
387	/* Remember address -> device mapping */
388	mPCIMap.insert(PCIMap::value_type(Address, devRec));
389
390	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
391	if (it == mReversePCIMap.end())
392	{
393	mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
394	it = mReversePCIMap.find(devRec);
395	}
396
397	/* Remember device name -> addresses mapping */
398	it->second.push_back(Address);
399
400	return S_OK;
401	}
402
403	bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
404	{
405	PCIDeviceRecord devRec(pszDevName);
406
407	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
408	if (it == mReversePCIMap.end())
409	return false;
410
411	if (iInstance >= (int)it->second.size())
412	return false;
413
414	Address = it->second[iInstance];
415	return true;
416	}
417
418	void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
419	{
420	size_t iRuleset, iRule;
421	const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
422
423	switch (mChipsetType)
424	{
425	case ChipsetType_PIIX3:
426	aArrays[1] = g_aPiix3Rules;
427	break;
428	case ChipsetType_ICH9:
429	{
430	aArrays[1] = g_aIch9Rules;
431	#ifdef VBOX_WITH_IOMMU_AMD
432	if (mIommuType == IommuType_AMD)
433	aArrays[2] = g_aIch9IommuAmdRules;
434	else
435	#endif
436	#ifdef VBOX_WITH_IOMMU_INTEL
437	if (mIommuType == IommuType_Intel)
438	aArrays[2] = g_aIch9IommuIntelRules;
439	else
440	#endif
441	{
442	aArrays[2] = g_aIch9LsiRules;
443	}
444	break;
445	}
446	default:
447	AssertFailed();
448	break;
449	}
450
451	for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
452	{
453	if (aArrays[iRuleset] == NULL)
454	continue;
455
456	for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
457	{
458	if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
459	aList.push_back(&aArrays[iRuleset][iRule]);
460	}
461	}
462	}
463
464	const char BusAssignmentManager::State::findAlias(const char pszDev)
465	{
466	for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
467	{
468	if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
469	return g_aDeviceAliases[iAlias].pszDevAlias;
470	}
471	return NULL;
472	}
473
474	static bool RuleComparator(const DeviceAssignmentRule r1, const DeviceAssignmentRule r2)
475	{
476	return (r1->iPriority > r2->iPriority);
477	}
478
479	HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
480	{
481	PCIRulesList matchingRules;
482
483	addMatchingRules(pszName, matchingRules);
484	const char *pszAlias = findAlias(pszName);
485	if (pszAlias)
486	addMatchingRules(pszAlias, matchingRules);
487
488	AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
489
490	stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
491
492	for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
493	{
494	const DeviceAssignmentRule *rule = matchingRules[iRule];
495
496	Address.miBus = rule->iBus;
497	Address.miDevice = rule->iDevice;
498	Address.miFn = rule->iFn;
499
500	if (checkAvailable(Address))
501	return S_OK;
502	}
503	AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
504
505	return E_INVALIDARG;
506	}
507
508	bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
509	{
510	PCIMap::const_iterator it = mPCIMap.find(Address);
511
512	return (it == mPCIMap.end());
513	}
514
515	void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
516	{
517	aAttached.resize(mPCIMap.size());
518
519	size_t i = 0;
520	PCIDeviceInfo dev;
521	for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
522	{
523	dev.strDeviceName = it->second.szDevName;
524	dev.guestAddress = it->first;
525	dev.hostAddress = it->second.HostAddress;
526	aAttached[i] = dev;
527	}
528	}
529
530	BusAssignmentManager::BusAssignmentManager()
531	: pState(NULL)
532	{
533	pState = new State();
534	Assert(pState);
535	}
536
537	BusAssignmentManager::~BusAssignmentManager()
538	{
539	if (pState)
540	{
541	delete pState;
542	pState = NULL;
543	}
544	}
545
546	BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType, IommuType_T iommuType)
547	{
548	BusAssignmentManager *pInstance = new BusAssignmentManager();
549	pInstance->pState->init(chipsetType, iommuType);
550	Assert(pInstance);
551	return pInstance;
552	}
553
554	void BusAssignmentManager::AddRef()
555	{
556	ASMAtomicIncS32(&pState->cRefCnt);
557	}
558	void BusAssignmentManager::Release()
559	{
560	if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
561	delete this;
562	}
563
564	DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char *pszName, uint64_t u64)
565	{
566	int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
567	if (RT_FAILURE(vrc))
568	return E_INVALIDARG;
569
570	return S_OK;
571	}
572
573	DECLINLINE(HRESULT) InsertConfigNode(PCFGMNODE pNode, const char pcszName, PCFGMNODE ppChild)
574	{
575	int vrc = CFGMR3InsertNode(pNode, pcszName, ppChild);
576	if (RT_FAILURE(vrc))
577	return E_INVALIDARG;
578
579	return S_OK;
580	}
581
582
583	HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
584	PCFGMNODE pCfg,
585	PCIBusAddress& GuestAddress,
586	PCIBusAddress HostAddress,
587	bool fGuestAddressRequired)
588	{
589	HRESULT rc = S_OK;
590
591	if (!GuestAddress.valid())
592	rc = pState->autoAssign(pszDevName, GuestAddress);
593	else
594	{
595	bool fAvailable = pState->checkAvailable(GuestAddress);
596
597	if (!fAvailable)
598	{
599	if (fGuestAddressRequired)
600	rc = E_ACCESSDENIED;
601	else
602	rc = pState->autoAssign(pszDevName, GuestAddress);
603	}
604	}
605
606	if (FAILED(rc))
607	return rc;
608
609	Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
610
611	rc = pState->record(pszDevName, GuestAddress, HostAddress);
612	if (FAILED(rc))
613	return rc;
614
615	if (pCfg)
616	{
617	rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
618	if (FAILED(rc))
619	return rc;
620	rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
621	if (FAILED(rc))
622	return rc;
623	rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
624	if (FAILED(rc))
625	return rc;
626	}
627
628	/* Check if the bus is still unknown, i.e. the bridge to it is missing */
629	if ( GuestAddress.miBus > 0
630	&& !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
631	{
632	PCFGMNODE pDevices = CFGMR3GetParent(CFGMR3GetParent(pCfg));
633	AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
634	PCFGMNODE pBridges = CFGMR3GetChild(pDevices, "ich9pcibridge");
635	AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
636
637	/* Device should be on a not yet existing bus, add it automatically */
638	for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
639	{
640	if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
641	{
642	PCIBusAddress BridgeGuestAddress;
643	rc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
644	if (FAILED(rc))
645	return rc;
646	if (BridgeGuestAddress.miBus > iBridge)
647	AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
648
649	PCFGMNODE pInst;
650	InsertConfigNode(pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
651	InsertConfigInteger(pInst, "Trusted", 1);
652	rc = assignPCIDevice(pState->mpszBridgeName, pInst);
653	if (FAILED(rc))
654	return rc;
655	}
656	}
657	}
658
659	return S_OK;
660	}
661
662
663	bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
664	{
665	return pState->findPCIAddress(pszDevName, iInstance, Address);
666	}
667	void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
668	{
669	pState->listAttachedPCIDevices(aAttached);
670	}

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source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 88382

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