BusAssignmentManager.cpp@ 107491

Last change on this file since 107491 was 107491, checked in by vboxsync, 12 days ago
Main/src-client/BusAssignmentManager.cpp: Missing field initialiser, bugref:3409
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1	/* $Id: BusAssignmentManager.cpp 107491 2025-01-08 10:09:53Z vboxsync $ */
2	/** @file
3	* VirtualBox bus slots assignment manager
4	*/
5
6	/*
7	* Copyright (C) 2010-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN
33	#include "LoggingNew.h"
34
35	#include "BusAssignmentManager.h"
36
37	#include <iprt/asm.h>
38	#include <iprt/string.h>
39
40	#include <VBox/vmm/cfgm.h>
41	#include <VBox/vmm/vmmr3vtable.h>
42	#include <VBox/com/array.h>
43
44	#include <map>
45	#include <vector>
46	#include <algorithm>
47
48
49	/*********************************************************************************************************************************
50	* Structures and Typedefs *
51	*********************************************************************************************************************************/
52	struct DeviceAssignmentRule
53	{
54	const char *pszName;
55	int iBus;
56	int iDevice;
57	int iFn;
58	int iPriority;
59	};
60
61	struct DeviceAliasRule
62	{
63	const char *pszDevName;
64	const char *pszDevAlias;
65	};
66
67
68	/*********************************************************************************************************************************
69	* Global Variables *
70	*********************************************************************************************************************************/
71	/* Those rules define PCI slots assignment */
72	/** @note
73	* The EFI takes assumptions about PCI slot assignments which are different
74	* from the following tables in certain cases, for example the IDE device
75	* is assumed to be 00:01.1! */
76
77	/* Device Bus Device Function Priority */
78
79	/* Generic rules */
80	static const DeviceAssignmentRule g_aGenericRules[] =
81	{
82	/* VGA controller */
83	{"vga", 0, 2, 0, 0},
84
85	/* VMM device */
86	{"VMMDev", 0, 4, 0, 0},
87
88	/* Audio controllers */
89	{"ichac97", 0, 5, 0, 0},
90	{"hda", 0, 5, 0, 0},
91
92	/* Storage controllers */
93	{"buslogic", 0, 21, 0, 1},
94	{"lsilogicsas", 0, 22, 0, 1},
95	{"nvme", 0, 14, 0, 1},
96	{"virtio-scsi", 0, 15, 0, 1},
97
98	/* USB controllers */
99	{"usb-ohci", 0, 6, 0, 0},
100	{"usb-ehci", 0, 11, 0, 0},
101	{"usb-xhci", 0, 12, 0, 0},
102
103	/* ACPI controller */
104	#if 0
105	// It really should be this for 440FX chipset (part of PIIX4 actually)
106	{"acpi", 0, 1, 3, 0},
107	#else
108	{"acpi", 0, 7, 0, 0},
109	#endif
110
111	/* Network controllers */
112	/* the first network card gets the PCI ID 3, the next 3 gets 8..10,
113	* next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
114	* swap places, i.e. the first card goes to ID 17=0x11. */
115	{"nic", 0, 3, 0, 1},
116	{"nic", 0, 8, 0, 1},
117	{"nic", 0, 9, 0, 1},
118	{"nic", 0, 10, 0, 1},
119	{"nic", 0, 16, 0, 1},
120	{"nic", 0, 17, 0, 1},
121	{"nic", 0, 18, 0, 1},
122	{"nic", 0, 19, 0, 1},
123
124	/* ISA/LPC controller */
125	{"lpc", 0, 31, 0, 0},
126
127	{ NULL, -1, -1, -1, 0}
128	};
129
130	/* PIIX3 chipset rules */
131	static const DeviceAssignmentRule g_aPiix3Rules[] =
132	{
133	{"piix3ide", 0, 1, 1, 0},
134	{"ahci", 0, 13, 0, 1},
135	{"lsilogic", 0, 20, 0, 1},
136	{"pcibridge", 0, 24, 0, 0},
137	{"pcibridge", 0, 25, 0, 0},
138	{ NULL, -1, -1, -1, 0}
139	};
140
141
142	/* ICH9 chipset rules */
143	static const DeviceAssignmentRule g_aIch9Rules[] =
144	{
145	/* Host Controller */
146	{"i82801", 0, 30, 0, 0},
147
148	/* Those are functions of LPC at 00:1e:00 */
149	/**
150	* Please note, that for devices being functions, like we do here, device 0
151	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
152	* Alternative approach is to assign separate slot to each device.
153	*/
154	{"piix3ide", 0, 31, 1, 2},
155	{"ahci", 0, 31, 2, 2},
156	{"smbus", 0, 31, 3, 2},
157	{"usb-ohci", 0, 31, 4, 2},
158	{"usb-ehci", 0, 31, 5, 2},
159	{"thermal", 0, 31, 6, 2},
160
161	/* to make sure rule never used before rules assigning devices on it */
162	{"ich9pcibridge", 0, 24, 0, 10},
163	{"ich9pcibridge", 0, 25, 0, 10},
164	{"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
165	{"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
166	{"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
167	{"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
168	{"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
169	{"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
170	{"ich9pcibridge", 8, 24, 0, 6},
171	{"ich9pcibridge", 8, 25, 0, 6},
172	{"ich9pcibridge", 10, 24, 0, 5},
173	{"ich9pcibridge", 10, 25, 0, 5},
174
175	/* Storage controllers */
176	{"ahci", 1, 0, 0, 0},
177	{"ahci", 1, 1, 0, 0},
178	{"ahci", 1, 2, 0, 0},
179	{"ahci", 1, 3, 0, 0},
180	{"ahci", 1, 4, 0, 0},
181	{"ahci", 1, 5, 0, 0},
182	{"ahci", 1, 6, 0, 0},
183	{"lsilogic", 1, 7, 0, 0},
184	{"lsilogic", 1, 8, 0, 0},
185	{"lsilogic", 1, 9, 0, 0},
186	{"lsilogic", 1, 10, 0, 0},
187	{"lsilogic", 1, 11, 0, 0},
188	{"lsilogic", 1, 12, 0, 0},
189	{"lsilogic", 1, 13, 0, 0},
190	{"buslogic", 1, 14, 0, 0},
191	{"buslogic", 1, 15, 0, 0},
192	{"buslogic", 1, 16, 0, 0},
193	{"buslogic", 1, 17, 0, 0},
194	{"buslogic", 1, 18, 0, 0},
195	{"buslogic", 1, 19, 0, 0},
196	{"buslogic", 1, 20, 0, 0},
197	{"lsilogicsas", 1, 21, 0, 0},
198	{"lsilogicsas", 1, 26, 0, 0},
199	{"lsilogicsas", 1, 27, 0, 0},
200	{"lsilogicsas", 1, 28, 0, 0},
201	{"lsilogicsas", 1, 29, 0, 0},
202	{"lsilogicsas", 1, 30, 0, 0},
203	{"lsilogicsas", 1, 31, 0, 0},
204
205	/* NICs */
206	{"nic", 2, 0, 0, 0},
207	{"nic", 2, 1, 0, 0},
208	{"nic", 2, 2, 0, 0},
209	{"nic", 2, 3, 0, 0},
210	{"nic", 2, 4, 0, 0},
211	{"nic", 2, 5, 0, 0},
212	{"nic", 2, 6, 0, 0},
213	{"nic", 2, 7, 0, 0},
214	{"nic", 2, 8, 0, 0},
215	{"nic", 2, 9, 0, 0},
216	{"nic", 2, 10, 0, 0},
217	{"nic", 2, 11, 0, 0},
218	{"nic", 2, 12, 0, 0},
219	{"nic", 2, 13, 0, 0},
220	{"nic", 2, 14, 0, 0},
221	{"nic", 2, 15, 0, 0},
222	{"nic", 2, 16, 0, 0},
223	{"nic", 2, 17, 0, 0},
224	{"nic", 2, 18, 0, 0},
225	{"nic", 2, 19, 0, 0},
226	{"nic", 2, 20, 0, 0},
227	{"nic", 2, 21, 0, 0},
228	{"nic", 2, 26, 0, 0},
229	{"nic", 2, 27, 0, 0},
230	{"nic", 2, 28, 0, 0},
231	{"nic", 2, 29, 0, 0},
232	{"nic", 2, 30, 0, 0},
233	{"nic", 2, 31, 0, 0},
234
235	/* Storage controller #2 (NVMe, virtio-scsi) */
236	{"nvme", 3, 0, 0, 0},
237	{"nvme", 3, 1, 0, 0},
238	{"nvme", 3, 2, 0, 0},
239	{"nvme", 3, 3, 0, 0},
240	{"nvme", 3, 4, 0, 0},
241	{"nvme", 3, 5, 0, 0},
242	{"nvme", 3, 6, 0, 0},
243	{"virtio-scsi", 3, 7, 0, 0},
244	{"virtio-scsi", 3, 8, 0, 0},
245	{"virtio-scsi", 3, 9, 0, 0},
246	{"virtio-scsi", 3, 10, 0, 0},
247	{"virtio-scsi", 3, 11, 0, 0},
248	{"virtio-scsi", 3, 12, 0, 0},
249	{"virtio-scsi", 3, 13, 0, 0},
250
251	{ NULL, -1, -1, -1, 0}
252	};
253
254
255	/* Virtual Armv8 platform chipset rules */
256	static const DeviceAssignmentRule g_aArmv8Rules[] =
257	{
258	/* VGA controller */
259	{"vga", 0, 0, 0, 0},
260
261	/* VMM device */
262	{"VMMDev", 0, 1, 0, 0},
263
264	/* Audio controllers */
265	{"ichac97", 0, 2, 0, 0},
266	{"hda", 0, 2, 0, 0},
267
268	/* Storage controllers */
269	{"virtio-scsi", 0, 3, 0, 1},
270	{"nvme", 0, 4, 0, 1},
271	{"ahci", 0, 16, 0, 1},
272	{"lsilogicsas", 0, 17, 0, 1},
273
274	/* USB controllers */
275	{"usb-ehci", 0, 5, 0, 0},
276	{"usb-xhci", 0, 6, 0, 0},
277	{"usb-ohci", 0, 7, 0, 0},
278
279	/* Network controllers */
280	{"nic", 0, 8, 0, 1},
281	{"nic", 0, 9, 0, 1},
282	{"nic", 0, 10, 0, 1},
283	{"nic", 0, 11, 0, 1},
284	{"nic", 0, 12, 0, 1},
285	{"nic", 0, 13, 0, 1},
286	{"nic", 0, 14, 0, 1},
287	{"nic", 0, 15, 0, 1},
288
289	/* to make sure rule never used before rules assigning devices on it */
290	{"pci-generic-ecam-bridge", 0, 24, 0, 10},
291	{"pci-generic-ecam-bridge", 0, 25, 0, 10},
292	{"pci-generic-ecam-bridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
293	{"pci-generic-ecam-bridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
294	{"pci-generic-ecam-bridge", 4, 24, 0, 8}, /* places), so make sure that nested */
295	{"pci-generic-ecam-bridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
296	{"pci-generic-ecam-bridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
297	{"pci-generic-ecam-bridge", 6, 25, 0, 7}, /* everything before starting the VM. */
298	{"pci-generic-ecam-bridge", 8, 24, 0, 6},
299	{"pci-generic-ecam-bridge", 8, 25, 0, 6},
300	{"pci-generic-ecam-bridge", 10, 24, 0, 5},
301	{"pci-generic-ecam-bridge", 10, 25, 0, 5},
302
303	/* Storage controllers */
304	{"ahci", 1, 0, 0, 0},
305	{"ahci", 1, 1, 0, 0},
306	{"ahci", 1, 2, 0, 0},
307	{"ahci", 1, 3, 0, 0},
308	{"ahci", 1, 4, 0, 0},
309	{"ahci", 1, 5, 0, 0},
310	{"ahci", 1, 6, 0, 0},
311	{"lsilogic", 1, 7, 0, 0},
312	{"lsilogic", 1, 8, 0, 0},
313	{"lsilogic", 1, 9, 0, 0},
314	{"lsilogic", 1, 10, 0, 0},
315	{"lsilogic", 1, 11, 0, 0},
316	{"lsilogic", 1, 12, 0, 0},
317	{"lsilogic", 1, 13, 0, 0},
318	{"buslogic", 1, 14, 0, 0},
319	{"buslogic", 1, 15, 0, 0},
320	{"buslogic", 1, 16, 0, 0},
321	{"buslogic", 1, 17, 0, 0},
322	{"buslogic", 1, 18, 0, 0},
323	{"buslogic", 1, 19, 0, 0},
324	{"buslogic", 1, 20, 0, 0},
325	{"lsilogicsas", 1, 21, 0, 0},
326	{"lsilogicsas", 1, 26, 0, 0},
327	{"lsilogicsas", 1, 27, 0, 0},
328	{"lsilogicsas", 1, 28, 0, 0},
329	{"lsilogicsas", 1, 29, 0, 0},
330	{"lsilogicsas", 1, 30, 0, 0},
331	{"lsilogicsas", 1, 31, 0, 0},
332
333	/* NICs */
334	{"nic", 2, 0, 0, 0},
335	{"nic", 2, 1, 0, 0},
336	{"nic", 2, 2, 0, 0},
337	{"nic", 2, 3, 0, 0},
338	{"nic", 2, 4, 0, 0},
339	{"nic", 2, 5, 0, 0},
340	{"nic", 2, 6, 0, 0},
341	{"nic", 2, 7, 0, 0},
342	{"nic", 2, 8, 0, 0},
343	{"nic", 2, 9, 0, 0},
344	{"nic", 2, 10, 0, 0},
345	{"nic", 2, 11, 0, 0},
346	{"nic", 2, 12, 0, 0},
347	{"nic", 2, 13, 0, 0},
348	{"nic", 2, 14, 0, 0},
349	{"nic", 2, 15, 0, 0},
350	{"nic", 2, 16, 0, 0},
351	{"nic", 2, 17, 0, 0},
352	{"nic", 2, 18, 0, 0},
353	{"nic", 2, 19, 0, 0},
354	{"nic", 2, 20, 0, 0},
355	{"nic", 2, 21, 0, 0},
356	{"nic", 2, 26, 0, 0},
357	{"nic", 2, 27, 0, 0},
358	{"nic", 2, 28, 0, 0},
359	{"nic", 2, 29, 0, 0},
360	{"nic", 2, 30, 0, 0},
361	{"nic", 2, 31, 0, 0},
362
363	/* Storage controller #2 (NVMe, virtio-scsi) */
364	{"nvme", 3, 0, 0, 0},
365	{"nvme", 3, 1, 0, 0},
366	{"nvme", 3, 2, 0, 0},
367	{"nvme", 3, 3, 0, 0},
368	{"nvme", 3, 4, 0, 0},
369	{"nvme", 3, 5, 0, 0},
370	{"nvme", 3, 6, 0, 0},
371	{"virtio-scsi", 3, 7, 0, 0},
372	{"virtio-scsi", 3, 8, 0, 0},
373	{"virtio-scsi", 3, 9, 0, 0},
374	{"virtio-scsi", 3, 10, 0, 0},
375	{"virtio-scsi", 3, 11, 0, 0},
376	{"virtio-scsi", 3, 12, 0, 0},
377	{"virtio-scsi", 3, 13, 0, 0},
378
379	{ NULL, -1, -1, -1, 0}
380	};
381
382
383	#ifdef VBOX_WITH_IOMMU_AMD
384	/*
385	* AMD IOMMU and LSI Logic controller rules.
386	*
387	* Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
388	* conflicts with the SB I/O APIC, we assign the LSI Logic controller
389	* to device number 23 when the VM is configured for an AMD IOMMU.
390	*/
391	static const DeviceAssignmentRule g_aIch9IommuAmdRules[] =
392	{
393	/* AMD IOMMU. */
394	{"iommu-amd", 0, 0, 0, 0},
395	/* AMD IOMMU: Reserved for southbridge I/O APIC. */
396	{"sb-ioapic", 0, 20, 0, 0},
397
398	/* Storage controller */
399	{"lsilogic", 0, 23, 0, 1},
400	{ NULL, -1, -1, -1, 0}
401	};
402	#endif
403
404	#ifdef VBOX_WITH_IOMMU_INTEL
405	/*
406	* Intel IOMMU.
407	* The VT-d misc, address remapping, system management device is
408	* located at BDF 0:5:0 on real hardware but we use 0:1:0 since that
409	* slot isn't used for anything else.
410	*
411	* While we could place the I/O APIC anywhere, we keep it consistent
412	* with the AMD IOMMU and we assign the LSI Logic controller to
413	* device number 23 (and I/O APIC at device 20).
414	*/
415	static const DeviceAssignmentRule g_aIch9IommuIntelRules[] =
416	{
417	/* Intel IOMMU. */
418	{"iommu-intel", 0, 1, 0, 0},
419	/* Intel IOMMU: Reserved for I/O APIC. */
420	{"sb-ioapic", 0, 20, 0, 0},
421
422	/* Storage controller */
423	{"lsilogic", 0, 23, 0, 1},
424	{ NULL, -1, -1, -1, 0}
425	};
426	#endif
427
428	/* LSI Logic Controller. */
429	static const DeviceAssignmentRule g_aIch9LsiRules[] =
430	{
431	/* Storage controller */
432	{"lsilogic", 0, 20, 0, 1},
433	{ NULL, -1, -1, -1, 0}
434	};
435
436	/* Aliasing rules */
437	static const DeviceAliasRule g_aDeviceAliases[] =
438	{
439	{"e1000", "nic"},
440	{"pcnet", "nic"},
441	{"virtio-net", "nic"},
442	{"ahci", "storage"},
443	{"lsilogic", "storage"},
444	{"buslogic", "storage"},
445	{"lsilogicsas", "storage"},
446	{"nvme", "storage"},
447	{"virtio-scsi", "storage"}
448	};
449
450
451
452	/**
453	* Bus assignment manage state data.
454	* @internal
455	*/
456	struct BusAssignmentManager::State
457	{
458	struct PCIDeviceRecord
459	{
460	char szDevName[32];
461	PCIBusAddress HostAddress;
462
463	PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
464	{
465	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
466	this->HostAddress = aHostAddress;
467	}
468
469	PCIDeviceRecord(const char *pszName)
470	{
471	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
472	}
473
474	bool operator<(const PCIDeviceRecord &a) const
475	{
476	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
477	}
478
479	bool operator==(const PCIDeviceRecord &a) const
480	{
481	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
482	}
483	};
484
485	typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
486	typedef std::vector<PCIBusAddress> PCIAddrList;
487	typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
488	typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
489
490	volatile int32_t cRefCnt;
491	ChipsetType_T mChipsetType;
492	const char * mpszBridgeName;
493	IommuType_T mIommuType;
494	PCIMap mPCIMap;
495	ReversePCIMap mReversePCIMap;
496	PCVMMR3VTABLE mpVMM;
497
498	State()
499	: cRefCnt(1)
500	, mChipsetType(ChipsetType_Null)
501	, mpszBridgeName("unknownbridge")
502	, mIommuType(IommuType_None)
503	, mpVMM(NULL)
504	{}
505	~State()
506	{}
507
508	HRESULT init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType);
509
510	HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
511	HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
512	bool checkAvailable(PCIBusAddress& Address);
513	bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
514
515	const char findAlias(const char pszName);
516	void addMatchingRules(const char *pszName, PCIRulesList& aList);
517	void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
518	};
519
520
521	HRESULT BusAssignmentManager::State::init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
522	{
523	mpVMM = pVMM;
524
525	if (iommuType != IommuType_None)
526	{
527	#if defined(VBOX_WITH_IOMMU_AMD) && defined(VBOX_WITH_IOMMU_INTEL)
528	Assert(iommuType == IommuType_AMD \|\| iommuType == IommuType_Intel);
529	#elif defined(VBOX_WITH_IOMMU_AMD)
530	Assert(iommuType == IommuType_AMD);
531	#elif defined(VBOX_WITH_IOMMU_INTEL)
532	Assert(iommuType == IommuType_Intel);
533	#endif
534	}
535
536	mChipsetType = chipsetType;
537	mIommuType = iommuType;
538	switch (chipsetType)
539	{
540	case ChipsetType_PIIX3:
541	mpszBridgeName = "pcibridge";
542	break;
543	case ChipsetType_ICH9:
544	mpszBridgeName = "ich9pcibridge";
545	break;
546	case ChipsetType_ARMv8Virtual:
547	mpszBridgeName = "pci-generic-ecam-bridge";
548	break;
549	default:
550	mpszBridgeName = "unknownbridge";
551	AssertFailed();
552	break;
553	}
554	return S_OK;
555	}
556
557	HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
558	{
559	PCIDeviceRecord devRec(pszName, HostAddress);
560
561	/* Remember address -> device mapping */
562	mPCIMap.insert(PCIMap::value_type(Address, devRec));
563
564	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
565	if (it == mReversePCIMap.end())
566	{
567	mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
568	it = mReversePCIMap.find(devRec);
569	}
570
571	/* Remember device name -> addresses mapping */
572	it->second.push_back(Address);
573
574	return S_OK;
575	}
576
577	bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
578	{
579	PCIDeviceRecord devRec(pszDevName);
580
581	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
582	if (it == mReversePCIMap.end())
583	return false;
584
585	if (iInstance >= (int)it->second.size())
586	return false;
587
588	Address = it->second[iInstance];
589	return true;
590	}
591
592	void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
593	{
594	size_t iRuleset, iRule;
595	const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
596
597	switch (mChipsetType)
598	{
599	case ChipsetType_PIIX3:
600	aArrays[1] = g_aPiix3Rules;
601	break;
602	case ChipsetType_ICH9:
603	{
604	aArrays[1] = g_aIch9Rules;
605	#ifdef VBOX_WITH_IOMMU_AMD
606	if (mIommuType == IommuType_AMD)
607	aArrays[2] = g_aIch9IommuAmdRules;
608	else
609	#endif
610	#ifdef VBOX_WITH_IOMMU_INTEL
611	if (mIommuType == IommuType_Intel)
612	aArrays[2] = g_aIch9IommuIntelRules;
613	else
614	#endif
615	{
616	aArrays[2] = g_aIch9LsiRules;
617	}
618	break;
619	}
620	case ChipsetType_ARMv8Virtual:
621	aArrays[0] = g_aArmv8Rules;
622	break;
623	default:
624	AssertFailed();
625	break;
626	}
627
628	for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
629	{
630	if (aArrays[iRuleset] == NULL)
631	continue;
632
633	for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
634	{
635	if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
636	aList.push_back(&aArrays[iRuleset][iRule]);
637	}
638	}
639	}
640
641	const char BusAssignmentManager::State::findAlias(const char pszDev)
642	{
643	for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
644	{
645	if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
646	return g_aDeviceAliases[iAlias].pszDevAlias;
647	}
648	return NULL;
649	}
650
651	static bool RuleComparator(const DeviceAssignmentRule r1, const DeviceAssignmentRule r2)
652	{
653	return (r1->iPriority > r2->iPriority);
654	}
655
656	HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
657	{
658	PCIRulesList matchingRules;
659
660	addMatchingRules(pszName, matchingRules);
661	const char *pszAlias = findAlias(pszName);
662	if (pszAlias)
663	addMatchingRules(pszAlias, matchingRules);
664
665	AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
666
667	stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
668
669	for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
670	{
671	const DeviceAssignmentRule *rule = matchingRules[iRule];
672
673	Address.miBus = rule->iBus;
674	Address.miDevice = rule->iDevice;
675	Address.miFn = rule->iFn;
676
677	if (checkAvailable(Address))
678	return S_OK;
679	}
680	AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
681
682	return E_INVALIDARG;
683	}
684
685	bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
686	{
687	PCIMap::const_iterator it = mPCIMap.find(Address);
688
689	return (it == mPCIMap.end());
690	}
691
692	void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
693	{
694	aAttached.resize(mPCIMap.size());
695
696	size_t i = 0;
697	PCIDeviceInfo dev;
698	for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
699	{
700	dev.strDeviceName = it->second.szDevName;
701	dev.guestAddress = it->first;
702	dev.hostAddress = it->second.HostAddress;
703	aAttached[i] = dev;
704	}
705	}
706
707	BusAssignmentManager::BusAssignmentManager()
708	: pState(NULL)
709	{
710	pState = new State();
711	Assert(pState);
712	}
713
714	BusAssignmentManager::~BusAssignmentManager()
715	{
716	if (pState)
717	{
718	delete pState;
719	pState = NULL;
720	}
721	}
722
723	BusAssignmentManager *BusAssignmentManager::createInstance(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
724	{
725	BusAssignmentManager *pInstance = new BusAssignmentManager();
726	pInstance->pState->init(pVMM, chipsetType, iommuType);
727	Assert(pInstance);
728	return pInstance;
729	}
730
731	void BusAssignmentManager::AddRef()
732	{
733	ASMAtomicIncS32(&pState->cRefCnt);
734	}
735
736	void BusAssignmentManager::Release()
737	{
738	if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
739	delete this;
740	}
741
742	DECLINLINE(HRESULT) InsertConfigInteger(PCVMMR3VTABLE pVMM, PCFGMNODE pCfg, const char *pszName, uint64_t u64)
743	{
744	int vrc = pVMM->pfnCFGMR3InsertInteger(pCfg, pszName, u64);
745	if (RT_FAILURE(vrc))
746	return E_INVALIDARG;
747
748	return S_OK;
749	}
750
751	DECLINLINE(HRESULT) InsertConfigNode(PCVMMR3VTABLE pVMM, PCFGMNODE pNode, const char pcszName, PCFGMNODE ppChild)
752	{
753	int vrc = pVMM->pfnCFGMR3InsertNode(pNode, pcszName, ppChild);
754	if (RT_FAILURE(vrc))
755	return E_INVALIDARG;
756
757	return S_OK;
758	}
759
760
761	HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
762	PCFGMNODE pCfg,
763	PCIBusAddress& GuestAddress,
764	PCIBusAddress HostAddress,
765	bool fGuestAddressRequired)
766	{
767	HRESULT hrc = S_OK;
768
769	if (!GuestAddress.valid())
770	hrc = pState->autoAssign(pszDevName, GuestAddress);
771	else
772	{
773	bool fAvailable = pState->checkAvailable(GuestAddress);
774
775	if (!fAvailable)
776	{
777	if (fGuestAddressRequired)
778	hrc = E_ACCESSDENIED;
779	else
780	hrc = pState->autoAssign(pszDevName, GuestAddress);
781	}
782	}
783
784	if (FAILED(hrc))
785	return hrc;
786
787	Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
788
789	hrc = pState->record(pszDevName, GuestAddress, HostAddress);
790	if (FAILED(hrc))
791	return hrc;
792
793	PCVMMR3VTABLE const pVMM = pState->mpVMM;
794	if (pCfg)
795	{
796	hrc = InsertConfigInteger(pVMM, pCfg, "PCIBusNo", GuestAddress.miBus);
797	if (FAILED(hrc))
798	return hrc;
799	hrc = InsertConfigInteger(pVMM, pCfg, "PCIDeviceNo", GuestAddress.miDevice);
800	if (FAILED(hrc))
801	return hrc;
802	hrc = InsertConfigInteger(pVMM, pCfg, "PCIFunctionNo", GuestAddress.miFn);
803	if (FAILED(hrc))
804	return hrc;
805	}
806
807	/* Check if the bus is still unknown, i.e. the bridge to it is missing */
808	if ( GuestAddress.miBus > 0
809	&& !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
810	{
811	PCFGMNODE pDevices = pVMM->pfnCFGMR3GetParent(pVMM->pfnCFGMR3GetParent(pCfg));
812	AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
813	PCFGMNODE pBridges = pVMM->pfnCFGMR3GetChild(pDevices, pState->mpszBridgeName);
814	AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
815
816	/* Device should be on a not yet existing bus, add it automatically */
817	for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
818	{
819	if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
820	{
821	PCIBusAddress BridgeGuestAddress;
822	hrc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
823	if (FAILED(hrc))
824	return hrc;
825	if (BridgeGuestAddress.miBus > iBridge)
826	AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
827
828	PCFGMNODE pInst;
829	InsertConfigNode(pVMM, pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
830	InsertConfigInteger(pVMM, pInst, "Trusted", 1);
831	hrc = assignPCIDevice(pState->mpszBridgeName, pInst);
832	if (FAILED(hrc))
833	return hrc;
834	}
835	}
836	}
837
838	return S_OK;
839	}
840
841
842	bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
843	{
844	return pState->findPCIAddress(pszDevName, iInstance, Address);
845	}
846	void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
847	{
848	pState->listAttachedPCIDevices(aAttached);
849	}

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source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 107491

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