VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 82423

Last change on this file since 82423 was 79674, checked in by vboxsync, 5 years ago

Comment.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 17.9 KB
Line 
1/* $Id: BusAssignmentManager.cpp 79674 2019-07-10 14:10:43Z vboxsync $ */
2/** @file
3 * VirtualBox bus slots assignment manager
4 */
5
6/*
7 * Copyright (C) 2010-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#define LOG_GROUP LOG_GROUP_MAIN
19#include "LoggingNew.h"
20
21#include "BusAssignmentManager.h"
22
23#include <iprt/asm.h>
24#include <iprt/string.h>
25
26#include <VBox/vmm/cfgm.h>
27#include <VBox/com/array.h>
28
29#include <map>
30#include <vector>
31#include <algorithm>
32
33struct DeviceAssignmentRule
34{
35 const char *pszName;
36 int iBus;
37 int iDevice;
38 int iFn;
39 int iPriority;
40};
41
42struct DeviceAliasRule
43{
44 const char *pszDevName;
45 const char *pszDevAlias;
46};
47
48/* Those rules define PCI slots assignment */
49/** @note
50 * The EFI takes assumptions about PCI slot assignments which are different
51 * from the following tables in certain cases, for example the IDE device
52 * is assumed to be 00:01.1! */
53
54/* Device Bus Device Function Priority */
55
56/* Generic rules */
57static const DeviceAssignmentRule aGenericRules[] =
58{
59 /* VGA controller */
60 {"vga", 0, 2, 0, 0},
61
62 /* VMM device */
63 {"VMMDev", 0, 4, 0, 0},
64
65 /* Audio controllers */
66 {"ichac97", 0, 5, 0, 0},
67 {"hda", 0, 5, 0, 0},
68
69 /* Storage controllers */
70 {"lsilogic", 0, 20, 0, 1},
71 {"buslogic", 0, 21, 0, 1},
72 {"lsilogicsas", 0, 22, 0, 1},
73 {"nvme", 0, 14, 0, 1},
74 {"virtio-scsi", 0, 15, 0, 1},
75
76 /* USB controllers */
77 {"usb-ohci", 0, 6, 0, 0},
78 {"usb-ehci", 0, 11, 0, 0},
79 {"usb-xhci", 0, 12, 0, 0},
80
81 /* ACPI controller */
82#if 0
83 // It really should be this for 440FX chipset (part of PIIX4 actually)
84 {"acpi", 0, 1, 3, 0},
85#else
86 {"acpi", 0, 7, 0, 0},
87#endif
88
89 /* Network controllers */
90 /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
91 * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
92 * swap places, i.e. the first card goes to ID 17=0x11. */
93 {"nic", 0, 3, 0, 1},
94 {"nic", 0, 8, 0, 1},
95 {"nic", 0, 9, 0, 1},
96 {"nic", 0, 10, 0, 1},
97 {"nic", 0, 16, 0, 1},
98 {"nic", 0, 17, 0, 1},
99 {"nic", 0, 18, 0, 1},
100 {"nic", 0, 19, 0, 1},
101
102 /* ISA/LPC controller */
103 {"lpc", 0, 31, 0, 0},
104
105 { NULL, -1, -1, -1, 0}
106};
107
108/* PIIX3 chipset rules */
109static const DeviceAssignmentRule aPiix3Rules[] =
110{
111 {"piix3ide", 0, 1, 1, 0},
112 {"ahci", 0, 13, 0, 1},
113 {"pcibridge", 0, 24, 0, 0},
114 {"pcibridge", 0, 25, 0, 0},
115 { NULL, -1, -1, -1, 0}
116};
117
118
119/* ICH9 chipset rules */
120static const DeviceAssignmentRule aIch9Rules[] =
121{
122 /* Host Controller */
123 {"i82801", 0, 30, 0, 0},
124
125 /* Those are functions of LPC at 00:1e:00 */
126 /**
127 * Please note, that for devices being functions, like we do here, device 0
128 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
129 * Alternative approach is to assign separate slot to each device.
130 */
131 {"piix3ide", 0, 31, 1, 2},
132 {"ahci", 0, 31, 2, 2},
133 {"smbus", 0, 31, 3, 2},
134 {"usb-ohci", 0, 31, 4, 2},
135 {"usb-ehci", 0, 31, 5, 2},
136 {"thermal", 0, 31, 6, 2},
137
138 /* to make sure rule never used before rules assigning devices on it */
139 {"ich9pcibridge", 0, 24, 0, 10},
140 {"ich9pcibridge", 0, 25, 0, 10},
141 {"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
142 {"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
143 {"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
144 {"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
145 {"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
146 {"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
147 {"ich9pcibridge", 8, 24, 0, 6},
148 {"ich9pcibridge", 8, 25, 0, 6},
149 {"ich9pcibridge", 10, 24, 0, 5},
150 {"ich9pcibridge", 10, 25, 0, 5},
151
152 /* Storage controllers */
153 {"ahci", 1, 0, 0, 0},
154 {"ahci", 1, 1, 0, 0},
155 {"ahci", 1, 2, 0, 0},
156 {"ahci", 1, 3, 0, 0},
157 {"ahci", 1, 4, 0, 0},
158 {"ahci", 1, 5, 0, 0},
159 {"ahci", 1, 6, 0, 0},
160 {"lsilogic", 1, 7, 0, 0},
161 {"lsilogic", 1, 8, 0, 0},
162 {"lsilogic", 1, 9, 0, 0},
163 {"lsilogic", 1, 10, 0, 0},
164 {"lsilogic", 1, 11, 0, 0},
165 {"lsilogic", 1, 12, 0, 0},
166 {"lsilogic", 1, 13, 0, 0},
167 {"buslogic", 1, 14, 0, 0},
168 {"buslogic", 1, 15, 0, 0},
169 {"buslogic", 1, 16, 0, 0},
170 {"buslogic", 1, 17, 0, 0},
171 {"buslogic", 1, 18, 0, 0},
172 {"buslogic", 1, 19, 0, 0},
173 {"buslogic", 1, 20, 0, 0},
174 {"lsilogicsas", 1, 21, 0, 0},
175 {"lsilogicsas", 1, 26, 0, 0},
176 {"lsilogicsas", 1, 27, 0, 0},
177 {"lsilogicsas", 1, 28, 0, 0},
178 {"lsilogicsas", 1, 29, 0, 0},
179 {"lsilogicsas", 1, 30, 0, 0},
180 {"lsilogicsas", 1, 31, 0, 0},
181
182 /* NICs */
183 {"nic", 2, 0, 0, 0},
184 {"nic", 2, 1, 0, 0},
185 {"nic", 2, 2, 0, 0},
186 {"nic", 2, 3, 0, 0},
187 {"nic", 2, 4, 0, 0},
188 {"nic", 2, 5, 0, 0},
189 {"nic", 2, 6, 0, 0},
190 {"nic", 2, 7, 0, 0},
191 {"nic", 2, 8, 0, 0},
192 {"nic", 2, 9, 0, 0},
193 {"nic", 2, 10, 0, 0},
194 {"nic", 2, 11, 0, 0},
195 {"nic", 2, 12, 0, 0},
196 {"nic", 2, 13, 0, 0},
197 {"nic", 2, 14, 0, 0},
198 {"nic", 2, 15, 0, 0},
199 {"nic", 2, 16, 0, 0},
200 {"nic", 2, 17, 0, 0},
201 {"nic", 2, 18, 0, 0},
202 {"nic", 2, 19, 0, 0},
203 {"nic", 2, 20, 0, 0},
204 {"nic", 2, 21, 0, 0},
205 {"nic", 2, 26, 0, 0},
206 {"nic", 2, 27, 0, 0},
207 {"nic", 2, 28, 0, 0},
208 {"nic", 2, 29, 0, 0},
209 {"nic", 2, 30, 0, 0},
210 {"nic", 2, 31, 0, 0},
211
212 /* Storage controller #2 (NVMe, virtio-scsi) */
213 {"nvme", 3, 0, 0, 0},
214 {"nvme", 3, 1, 0, 0},
215 {"nvme", 3, 2, 0, 0},
216 {"nvme", 3, 3, 0, 0},
217 {"nvme", 3, 4, 0, 0},
218 {"nvme", 3, 5, 0, 0},
219 {"nvme", 3, 6, 0, 0},
220 {"virtio-scsi", 3, 7, 0, 0},
221 {"virtio-scsi", 3, 8, 0, 0},
222 {"virtio-scsi", 3, 9, 0, 0},
223 {"virtio-scsi", 3, 10, 0, 0},
224 {"virtio-scsi", 3, 11, 0, 0},
225 {"virtio-scsi", 3, 12, 0, 0},
226 {"virtio-scsi", 3, 13, 0, 0},
227
228 { NULL, -1, -1, -1, 0}
229};
230
231/* Aliasing rules */
232static const DeviceAliasRule aDeviceAliases[] =
233{
234 {"e1000", "nic"},
235 {"pcnet", "nic"},
236 {"virtio-net", "nic"},
237 {"ahci", "storage"},
238 {"lsilogic", "storage"},
239 {"buslogic", "storage"},
240 {"lsilogicsas", "storage"},
241 {"nvme", "storage"},
242 {"virtio-scsi", "storage"}
243};
244
245struct BusAssignmentManager::State
246{
247 struct PCIDeviceRecord
248 {
249 char szDevName[32];
250 PCIBusAddress HostAddress;
251
252 PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
253 {
254 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
255 this->HostAddress = aHostAddress;
256 }
257
258 PCIDeviceRecord(const char *pszName)
259 {
260 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
261 }
262
263 bool operator<(const PCIDeviceRecord &a) const
264 {
265 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
266 }
267
268 bool operator==(const PCIDeviceRecord &a) const
269 {
270 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
271 }
272 };
273
274 typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
275 typedef std::vector<PCIBusAddress> PCIAddrList;
276 typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
277 typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
278
279 volatile int32_t cRefCnt;
280 ChipsetType_T mChipsetType;
281 const char * mpszBridgeName;
282 PCIMap mPCIMap;
283 ReversePCIMap mReversePCIMap;
284
285 State()
286 : cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge")
287 {}
288 ~State()
289 {}
290
291 HRESULT init(ChipsetType_T chipsetType);
292
293 HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
294 HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
295 bool checkAvailable(PCIBusAddress& Address);
296 bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
297
298 const char *findAlias(const char *pszName);
299 void addMatchingRules(const char *pszName, PCIRulesList& aList);
300 void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
301};
302
303HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
304{
305 mChipsetType = chipsetType;
306 switch (chipsetType)
307 {
308 case ChipsetType_PIIX3:
309 mpszBridgeName = "pcibridge";
310 break;
311 case ChipsetType_ICH9:
312 mpszBridgeName = "ich9pcibridge";
313 break;
314 default:
315 mpszBridgeName = "unknownbridge";
316 AssertFailed();
317 break;
318 }
319 return S_OK;
320}
321
322HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
323{
324 PCIDeviceRecord devRec(pszName, HostAddress);
325
326 /* Remember address -> device mapping */
327 mPCIMap.insert(PCIMap::value_type(Address, devRec));
328
329 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
330 if (it == mReversePCIMap.end())
331 {
332 mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
333 it = mReversePCIMap.find(devRec);
334 }
335
336 /* Remember device name -> addresses mapping */
337 it->second.push_back(Address);
338
339 return S_OK;
340}
341
342bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
343{
344 PCIDeviceRecord devRec(pszDevName);
345
346 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
347 if (it == mReversePCIMap.end())
348 return false;
349
350 if (iInstance >= (int)it->second.size())
351 return false;
352
353 Address = it->second[iInstance];
354 return true;
355}
356
357void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
358{
359 size_t iRuleset, iRule;
360 const DeviceAssignmentRule *aArrays[2] = {aGenericRules, NULL};
361
362 switch (mChipsetType)
363 {
364 case ChipsetType_PIIX3:
365 aArrays[1] = aPiix3Rules;
366 break;
367 case ChipsetType_ICH9:
368 aArrays[1] = aIch9Rules;
369 break;
370 default:
371 AssertFailed();
372 break;
373 }
374
375 for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
376 {
377 if (aArrays[iRuleset] == NULL)
378 continue;
379
380 for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
381 {
382 if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
383 aList.push_back(&aArrays[iRuleset][iRule]);
384 }
385 }
386}
387
388const char *BusAssignmentManager::State::findAlias(const char *pszDev)
389{
390 for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
391 {
392 if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
393 return aDeviceAliases[iAlias].pszDevAlias;
394 }
395 return NULL;
396}
397
398static bool RuleComparator(const DeviceAssignmentRule *r1, const DeviceAssignmentRule *r2)
399{
400 return (r1->iPriority > r2->iPriority);
401}
402
403HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
404{
405 PCIRulesList matchingRules;
406
407 addMatchingRules(pszName, matchingRules);
408 const char *pszAlias = findAlias(pszName);
409 if (pszAlias)
410 addMatchingRules(pszAlias, matchingRules);
411
412 AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
413
414 stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
415
416 for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
417 {
418 const DeviceAssignmentRule *rule = matchingRules[iRule];
419
420 Address.miBus = rule->iBus;
421 Address.miDevice = rule->iDevice;
422 Address.miFn = rule->iFn;
423
424 if (checkAvailable(Address))
425 return S_OK;
426 }
427 AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
428
429 return E_INVALIDARG;
430}
431
432bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
433{
434 PCIMap::const_iterator it = mPCIMap.find(Address);
435
436 return (it == mPCIMap.end());
437}
438
439void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
440{
441 aAttached.resize(mPCIMap.size());
442
443 size_t i = 0;
444 PCIDeviceInfo dev;
445 for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
446 {
447 dev.strDeviceName = it->second.szDevName;
448 dev.guestAddress = it->first;
449 dev.hostAddress = it->second.HostAddress;
450 aAttached[i] = dev;
451 }
452}
453
454BusAssignmentManager::BusAssignmentManager()
455 : pState(NULL)
456{
457 pState = new State();
458 Assert(pState);
459}
460
461BusAssignmentManager::~BusAssignmentManager()
462{
463 if (pState)
464 {
465 delete pState;
466 pState = NULL;
467 }
468}
469
470BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
471{
472 BusAssignmentManager *pInstance = new BusAssignmentManager();
473 pInstance->pState->init(chipsetType);
474 Assert(pInstance);
475 return pInstance;
476}
477
478void BusAssignmentManager::AddRef()
479{
480 ASMAtomicIncS32(&pState->cRefCnt);
481}
482void BusAssignmentManager::Release()
483{
484 if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
485 delete this;
486}
487
488DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char *pszName, uint64_t u64)
489{
490 int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
491 if (RT_FAILURE(vrc))
492 return E_INVALIDARG;
493
494 return S_OK;
495}
496
497DECLINLINE(HRESULT) InsertConfigNode(PCFGMNODE pNode, const char *pcszName, PCFGMNODE *ppChild)
498{
499 int vrc = CFGMR3InsertNode(pNode, pcszName, ppChild);
500 if (RT_FAILURE(vrc))
501 return E_INVALIDARG;
502
503 return S_OK;
504}
505
506
507HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
508 PCFGMNODE pCfg,
509 PCIBusAddress& GuestAddress,
510 PCIBusAddress HostAddress,
511 bool fGuestAddressRequired)
512{
513 HRESULT rc = S_OK;
514
515 if (!GuestAddress.valid())
516 rc = pState->autoAssign(pszDevName, GuestAddress);
517 else
518 {
519 bool fAvailable = pState->checkAvailable(GuestAddress);
520
521 if (!fAvailable)
522 {
523 if (fGuestAddressRequired)
524 rc = E_ACCESSDENIED;
525 else
526 rc = pState->autoAssign(pszDevName, GuestAddress);
527 }
528 }
529
530 if (FAILED(rc))
531 return rc;
532
533 Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
534
535 rc = pState->record(pszDevName, GuestAddress, HostAddress);
536 if (FAILED(rc))
537 return rc;
538
539 rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
540 if (FAILED(rc))
541 return rc;
542 rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
543 if (FAILED(rc))
544 return rc;
545 rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
546 if (FAILED(rc))
547 return rc;
548
549 /* Check if the bus is still unknown, i.e. the bridge to it is missing */
550 if ( GuestAddress.miBus > 0
551 && !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
552 {
553 PCFGMNODE pDevices = CFGMR3GetParent(CFGMR3GetParent(pCfg));
554 AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
555 PCFGMNODE pBridges = CFGMR3GetChild(pDevices, "ich9pcibridge");
556 AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
557
558 /* Device should be on a not yet existing bus, add it automatically */
559 for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
560 {
561 if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
562 {
563 PCIBusAddress BridgeGuestAddress;
564 rc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
565 if (FAILED(rc))
566 return rc;
567 if (BridgeGuestAddress.miBus > iBridge)
568 AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
569
570 PCFGMNODE pInst;
571 InsertConfigNode(pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
572 InsertConfigInteger(pInst, "Trusted", 1);
573 rc = assignPCIDevice(pState->mpszBridgeName, pInst);
574 if (FAILED(rc))
575 return rc;
576 }
577 }
578 }
579
580 return S_OK;
581}
582
583
584bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
585{
586 return pState->findPCIAddress(pszDevName, iInstance, Address);
587}
588void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
589{
590 pState->listAttachedPCIDevices(aAttached);
591}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette