ConsoleImplConfigArmV8.cpp@ 108838

Last change on this file since 108838 was 108821, checked in by vboxsync, 7 weeks ago
Main: bugref:10877 Explicitly configure the GIC architecture revision to the VM as we need to expose it to the guest system registers via CPUM (primarily required for EFI firmware).
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1	/* $Id: ConsoleImplConfigArmV8.cpp 108821 2025-04-02 05:35:55Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/gic.h>
65	#include <VBox/param.h>
66	#include <VBox/version.h>
67	#include <VBox/platforms/vbox-armv8.h>
68
69	#include "BusAssignmentManager.h"
70	#include "ResourceAssignmentManager.h"
71	#include "SystemTableBuilder.h"
72	#ifdef VBOX_WITH_EXTPACK
73	# include "ExtPackManagerImpl.h"
74	#endif
75
76
77	/*********************************************************************************************************************************
78	* Internal Functions *
79	*********************************************************************************************************************************/
80
81	/* Darwin compile kludge */
82	#undef PVM
83
84	#ifdef VBOX_WITH_VIRT_ARMV8
85	/**
86	* Worker for configConstructor.
87	*
88	* @return VBox status code.
89	* @param pUVM The user mode VM handle.
90	* @param pVM The cross context VM handle.
91	* @param pVMM The VMM vtable.
92	* @param pAlock The automatic lock instance. This is for when we have
93	* to leave it in order to avoid deadlocks (ext packs and
94	* more).
95	*/
96	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97	{
98	RT_NOREF(pVM /* when everything is disabled */);
99	ComPtr<IMachine> pMachine = i_machine();
100
101	HRESULT hrc;
102	Utf8Str strTmp;
103	Bstr bstr;
104
105	RTFDT hFdt = NIL_RTFDT;
106	int vrc = RTFdtCreateEmpty(&hFdt);
107	AssertRCReturn(vrc, vrc);
108
109	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112	/*
113	* Get necessary objects and frequently used parameters.
114	*/
115	ComPtr<IVirtualBox> virtualBox;
116	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
117
118	ComPtr<IHost> host;
119	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
120
121	PlatformArchitecture_T platformArchHost;
122	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
123
124	ComPtr<ISystemProperties> systemProperties;
125	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
126
127	ComPtr<IFirmwareSettings> firmwareSettings;
128	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
129
130	ComPtr<INvramStore> nvramStore;
131	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
132
133	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
134	RTUUID HardwareUuid;
135	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
136	AssertRCReturn(vrc, vrc);
137
138	ULONG cRamMBs;
139	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
140	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
141
142	ComPtr<IPlatform> platform;
143	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
144
145	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
146	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
147	PlatformArchitecture_T platformArchMachine;
148	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
149	if (platformArchMachine != platformArchHost)
150	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
151	N_("VM platform architecture (%s) not supported on this host (%s)."),
152	Global::stringifyPlatformArchitecture(platformArchMachine),
153	Global::stringifyPlatformArchitecture(platformArchHost));
154	#endif
155
156	/* Get the ARM platform object. */
157	ComPtr<IPlatformARM> platformARM;
158	hrc = platform->COMGETTER(ARM)(platformARM.asOutParam()); H();
159
160	ComPtr<IPlatformProperties> pPlatformProperties;
161	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
162
163	ChipsetType_T chipsetType;
164	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
165
166	ULONG cCpus = 1;
167	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
168	Assert(cCpus);
169
170	ULONG ulCpuExecutionCap = 100;
171	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
172
173	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
174	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
175
176	if ( enmExecEngine != VMExecutionEngine_Default
177	&& enmExecEngine != VMExecutionEngine_NativeApi)
178	{
179	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
180	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
181	}
182
183	LogRel(("Guest architecture: ARM\n"));
184
185	Bstr osTypeId;
186	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
187	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
188
189	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
190	ResourceAssignmentManager pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None, 32 /cInterrupts*/,
191	_4G); /* Start looking for free MMIO regions at 4GiB downwards. */
192	SystemTableBuilder *pSysTblsBldAcpi = NULL;
193
194	/*
195	* ACPI
196	*/
197	BOOL fACPI;
198	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
199	if (fACPI)
200	pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
201
202
203	/*
204	* Get root node first.
205	* This is the only node in the tree.
206	*/
207	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
208	Assert(pRoot);
209
210	/*
211	* The VBox platform descriptor, FDT and ACPI tables will reside at the end of the 4GiB
212	* address space and we reserve 2MiB for those.
213	*/
214	RTGCPHYS cbPlatformDesc = _2M;
215	RTGCPHYS GCPhysPlatformDesc = VBOXPLATFORMARMV8_PHYS_ADDR - (cbPlatformDesc - _64K);
216
217	RTGCPHYS GCPhysRamBase = 128 * _1M;
218	RTGCPHYS cbRamBase = RT_MIN(cbRam, _4G - _512M - 128 * _1M);
219
220	RTGCPHYS GCPhysFw = 0;
221	RTGCPHYS cbFw = _64M;
222
223	// catching throws from InsertConfigString and friends.
224	try
225	{
226
227	/*
228	* Set the root (and VMM) level values.
229	*/
230	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
231	InsertConfigString(pRoot, "Name", bstr);
232	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
233	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
234	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
235	InsertConfigInteger(pRoot, "TimerMillies", 10);
236
237	/*
238	* NEM
239	*/
240	PCFGMNODE pNEM;
241	InsertConfigNode(pRoot, "NEM", &pNEM);
242
243	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
244	Assert(idPHandleIntCtrl != UINT32_MAX);
245	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
246	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
247	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
248	Assert(idPHandleAbpPClk != UINT32_MAX);
249	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
250	Assert(idPHandleGpio != UINT32_MAX);
251
252	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
253	for (uint32_t i = 0; i < cCpus; i++)
254	{
255	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
256	Assert(aidPHandleCpus[i] != UINT32_MAX);
257	}
258
259	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
260	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
261	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
262	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
263	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
264
265	/* Configure the Power State Coordination Interface. */
266	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
267	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
268	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
269	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
270	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
271	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
272	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
273	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
274	vrc = RTFdtNodeFinalize(hFdt); VRC();
275
276	/* Configure the timer and clock. */
277	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
278	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
279	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
280	0x01, 0x0d, 0x104,
281	0x01, 0x0e, 0x104,
282	0x01, 0x0b, 0x104,
283	0x01, 0x0a, 0x104); VRC();
284	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
285	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
286	vrc = RTFdtNodeFinalize(hFdt); VRC();
287
288	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
289	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
290	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
291	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", ASMReadCntFrqEl0()); VRC();
292	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
293	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
294	vrc = RTFdtNodeFinalize(hFdt); VRC();
295
296	if (pSysTblsBldAcpi)
297	{
298	vrc = pSysTblsBldAcpi->configureClock();
299	VRC();
300	}
301
302	/*
303	* MM values.
304	*/
305	PCFGMNODE pMM;
306	InsertConfigNode(pRoot, "MM", &pMM);
307
308	/*
309	* Memory setup.
310	*/
311	PCFGMNODE pMem = NULL;
312	InsertConfigNode(pMM, "MemRegions", &pMem);
313
314	/*
315	* Windows requires the TPM to be available at 0xfed40000 so reserve this region first, even
316	* if no TPM is configured.
317	*/
318	RTGCPHYS GCPhysTpm = 0xfed40000;
319	RTGCPHYS cbTpm = 0x5000 + 0x1000; /* TPM + PPI region. */
320	hrc = pResMgr->assignFixedMmioRegion("tpm", GCPhysTpm, cbTpm); H();
321
322	/*
323	* The firmware ROM will start at the beginning of the address space and span 64MiB
324	* After that comes the flash and spans another 64MiB (even if the real size is smaller).
325	*/
326	hrc = pResMgr->assignFixedRomRegion("firmware", GCPhysFw, cbFw); H();
327
328	RTGCPHYS GCPhysFlash = _64M;
329	RTGCPHYS cbFlash = _64M;
330	hrc = pResMgr->assignFixedMmioRegion("flash", GCPhysFlash, cbFlash); H();
331
332	hrc = pResMgr->assignFixedRomRegion("platform-tables", GCPhysPlatformDesc, cbPlatformDesc); H();
333
334	/*
335	* The base RAM will start at 128MiB (end of flash region) and goes up to 4GiB - 512MiB
336	* (for the MMIO hole).
337	* If more RAM is configured the high region will start at 4GiB.
338	*/
339	hrc = pResMgr->assignFixedRamRegion("RAM Base", GCPhysRamBase, cbRamBase); H();
340
341	PCFGMNODE pMemRegion = NULL;
342	InsertConfigNode(pMem, "Base", &pMemRegion);
343	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamBase);
344	InsertConfigInteger(pMemRegion, "Size", cbRamBase);
345
346	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamBase); VRC();
347	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamBase, cbRamBase); VRC();
348	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
349	vrc = RTFdtNodeFinalize(hFdt); VRC();
350
351	if (pSysTblsBldAcpi)
352	{
353	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamBase, cbRamBase);
354	VRC();
355	}
356
357	if (cbRamBase < cbRam)
358	{
359	RTGCPHYS GCPhysRamHigh = _4G;
360	RTGCPHYS cbRamHigh = cbRam - cbRamBase;
361
362	hrc = pResMgr->assignFixedRamRegion("RAM High", GCPhysRamHigh, cbRamHigh); H();
363
364	InsertConfigNode(pMem, "High", &pMemRegion);
365	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamHigh);
366	InsertConfigInteger(pMemRegion, "Size", cbRamHigh);
367
368	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamHigh); VRC();
369	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamHigh, cbRamHigh); VRC();
370	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
371	vrc = RTFdtNodeFinalize(hFdt); VRC();
372
373	if (pSysTblsBldAcpi)
374	{
375	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamHigh, cbRamHigh);
376	VRC();
377	}
378	}
379
380	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
381	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
382	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
383	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
384
385	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
386	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
387
388	for (uint32_t i = 0; i < cCpus; i++)
389	{
390	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
391	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
392	vrc = RTFdtNodeFinalize(hFdt); VRC();
393	}
394
395	vrc = RTFdtNodeFinalize(hFdt); VRC();
396	vrc = RTFdtNodeFinalize(hFdt); VRC();
397
398	for (uint32_t i = 0; i < cCpus; i++)
399	{
400	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
401	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
402	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
403	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
404	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
405	if (cCpus > 1)
406	{
407	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
408	}
409	vrc = RTFdtNodeFinalize(hFdt); VRC();
410
411	if (pSysTblsBldAcpi)
412	{
413	vrc = pSysTblsBldAcpi->addCpu(i);
414	VRC();
415	}
416	}
417
418	vrc = RTFdtNodeFinalize(hFdt); VRC();
419
420
421	/*
422	* CPUM values.
423	*/
424	PCFGMNODE pCpum;
425	InsertConfigNode(pRoot, "CPUM", &pCpum);
426
427	/* Nested Virtualization. */
428	BOOL fNestedHWVirt = FALSE;
429	hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_HWVirt, &fNestedHWVirt); H();
430	InsertConfigInteger(pCpum, "NestedHWVirt", fNestedHWVirt ? true : false);
431
432	/* GIC. */
433	uint8_t const uGicArchRev = GIC_DIST_REG_PIDR2_ARCHREV_GICV3;
434	InsertConfigInteger(pCpum, "GicArchRev", uGicArchRev);
435
436	/*
437	* PDM config.
438	* Load drivers in VBoxC.[so\|dll]
439	*/
440	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
441
442
443	/*
444	* VGA.
445	*/
446	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
447	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
448	GraphicsControllerType_T enmGraphicsController;
449	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
450
451	/*
452	* Devices
453	*/
454	PCFGMNODE pDevices = NULL; /* /Devices */
455	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
456	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
457	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
458	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
459
460	InsertConfigNode(pRoot, "Devices", &pDevices);
461
462	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
463
464	InsertConfigNode(pDevices, "platform", &pDev);
465	InsertConfigNode(pDev, "0", &pInst);
466	InsertConfigNode(pInst, "Config", &pCfg);
467	InsertConfigNode(pInst, "LUN#0", &pLunL0);
468	InsertConfigString(pLunL0, "Driver", "ResourceStore");
469
470	/* Add the resources. */
471	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
472	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
473	InsertConfigString(pCfg, "ResourceNamespace", "resources");
474	InsertConfigNode(pCfg, "Resources", &pResources);
475	InsertConfigNode(pResources, "EfiRom", &pRes);
476	InsertConfigInteger(pRes, "RegisterAsRom", 1);
477	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
478
479	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
480	/*
481	* Firmware.
482	*/
483	FirmwareType_T eFwType = FirmwareType_EFI64;
484	#ifdef VBOX_WITH_EFI_IN_DD2
485	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
486	: eFwType == FirmwareType_EFI32 ? "VBoxEFI-arm32.fd"
487	: "VBoxEFI-arm64.fd";
488	const char *pszKey = "ResourceId";
489	#else
490	Utf8Str efiRomFile;
491	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
492	AssertRCReturn(vrc, vrc);
493	const char *pszEfiRomFile = efiRomFile.c_str();
494	const char *pszKey = "Filename";
495	#endif
496	InsertConfigString(pRes, pszKey, pszEfiRomFile);
497
498	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
499	InsertConfigInteger(pRes, "RegisterAsRom", 1);
500	InsertConfigInteger(pRes, "GCPhysLoadAddress", GCPhysPlatformDesc);
501	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
502
503	/*
504	* Configure the interrupt controller.
505	*/
506	RTGCPHYS GCPhysIntcDist;
507	RTGCPHYS GCPhysIntcIts;
508	RTGCPHYS cbMmioIntcDist;
509	RTGCPHYS cbMmioIntcIts;
510	RTGCPHYS GCPhysIntcReDist;
511	RTGCPHYS cbMmioIntcReDist;
512
513	/** @todo Add API for configuring a GIC ITS for the VM and init this value from
514	* there. */
515	BOOL fGicIts = FALSE;
516
517	/* Allow for up to 256 vCPUs in the future without changing the address space layout. */
518	hrc = pResMgr->assignMmioRegion("gic", _64K + 256 * _128K, &GCPhysIntcDist, &cbMmioIntcDist); H();
519	GCPhysIntcReDist = GCPhysIntcDist + _64K;
520	cbMmioIntcReDist = 256 * _128K;
521	cbMmioIntcDist = _64K;
522
523	/* Reserve an MMIO region for the GIC ITS even if it might not be configured for the VM. */
524	hrc = pResMgr->assignMmioRegion("gic-its", 2 * _64K, &GCPhysIntcIts, &cbMmioIntcIts); H();
525
526	#ifdef RT_OS_DARWIN
527	InsertConfigNode(pDevices, "gic", &pDev);
528	#else
529	/* On Linux we default to the KVM in-kernel GIC and on Windows we are forced to the Hyper-V GIC for now. */
530	InsertConfigNode(pDevices, "gic-nem", &pDev);
531	#endif
532	InsertConfigNode(pDev, "0", &pInst);
533	InsertConfigInteger(pInst, "Trusted", 1);
534	InsertConfigNode(pInst, "Config", &pCfg);
535	InsertConfigInteger(pCfg, "ArchRev", uGicArchRev);
536	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
537	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
538	if (fGicIts == TRUE)
539	{
540	InsertConfigInteger(pCfg, "ItsMmioBase", GCPhysIntcIts);
541	InsertConfigInteger(pCfg, "Lpi", 1);
542	InsertConfigInteger(pCfg, "Mbi", 1);
543	}
544	else
545	GCPhysIntcIts = cbMmioIntcIts = 0;
546
547	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
548	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
549	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
550	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
551	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
552	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
553	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
554	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
555	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
556	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
557	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
558	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
559
560	if (pSysTblsBldAcpi)
561	{
562	vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
563	GCPhysIntcReDist, cbMmioIntcReDist, GCPhysIntcIts, cbMmioIntcIts);
564	VRC();
565	}
566
567	#if 0
568	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
569	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
570	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
571	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
572	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
573	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
574	vrc = RTFdtNodeFinalize(hFdt); VRC();
575	#endif
576
577	vrc = RTFdtNodeFinalize(hFdt); VRC();
578
579	/*
580	* Configure the performance monitoring unit.
581	*/
582	/** @todo Make this configurable and enable as default for Windows VMs because they assume a working PMU
583	* (which is not available in hardware on AppleSilicon).
584	*/
585	InsertConfigNode(pDevices, "pmu", &pDev);
586	InsertConfigNode(pDev, "0", &pInst);
587	InsertConfigInteger(pInst, "Trusted", 1);
588	InsertConfigNode(pInst, "Config", &pCfg);
589
590	RTGCPHYS GCPhysMmioStart;
591	RTGCPHYS cbMmio;
592	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
593	{
594	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
595
596	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
597	InsertConfigNode(pDev, "0", &pInst);
598	InsertConfigNode(pInst, "Config", &pCfg);
599	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
600	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
601	InsertConfigInteger(pCfg, "DmaEnabled", 1);
602	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
603	InsertConfigNode(pInst, "LUN#0", &pLunL0);
604	InsertConfigString(pLunL0, "Driver", "MainDisplay");
605
606	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
607	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
608	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
609	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
610	vrc = RTFdtNodeFinalize(hFdt); VRC();
611
612	if (pSysTblsBldAcpi)
613	{
614	vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
615	VRC();
616	}
617	}
618
619	InsertConfigNode(pDevices, "flash-cfi", &pDev);
620	InsertConfigNode(pDev, "0", &pInst);
621	InsertConfigNode(pInst, "Config", &pCfg);
622	InsertConfigInteger(pCfg, "BaseAddress", GCPhysFlash);
623	InsertConfigInteger(pCfg, "Size", 768 * _1K);
624	InsertConfigString(pCfg, "FlashFile", "nvram");
625	/* Attach the NVRAM storage driver. */
626	InsertConfigNode(pInst, "LUN#0", &pLunL0);
627	InsertConfigString(pLunL0, "Driver", "NvramStore");
628
629	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
630	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
631	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
632	GCPhysFw, cbFw, /* First region (EFI). */
633	GCPhysFlash, 3 * _256K); /* Second region (NVRAM), see NvramStoreImpl.cpp for an explanation of the size choice. */ VRC();
634	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
635	vrc = RTFdtNodeFinalize(hFdt); VRC();
636
637	InsertConfigNode(pDevices, "arm-pl011", &pDev);
638	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
639	{
640	ComPtr<ISerialPort> serialPort;
641	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
642	BOOL fEnabledSerPort = FALSE;
643	if (serialPort)
644	{
645	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
646	}
647	if (!fEnabledSerPort)
648	{
649	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
650	continue;
651	}
652
653	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
654	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
655	InsertConfigNode(pInst, "Config", &pCfg);
656
657	uint32_t iIrq = 0;
658	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
659	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
660
661	InsertConfigInteger(pCfg, "Irq", iIrq);
662	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
663
664	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
665	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
666	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
667	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
668	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
669	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
670	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
671	"arm,pl011", "arm,primecell"); VRC();
672	vrc = RTFdtNodeFinalize(hFdt); VRC();
673
674	if (pSysTblsBldAcpi)
675	{
676	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
677	VRC();
678	}
679
680	BOOL fServer;
681	hrc = serialPort->COMGETTER(Server)(&fServer); H();
682	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
683
684	PortMode_T eHostMode;
685	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
686
687	m_aeSerialPortMode[ulInstance] = eHostMode;
688	if (eHostMode != PortMode_Disconnected)
689	{
690	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
691	if (RT_FAILURE(vrc))
692	return vrc;
693	}
694	}
695
696	BOOL fRTCUseUTC;
697	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
698
699	uint32_t iIrq = 0;
700	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
701	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
702	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
703	InsertConfigNode(pDev, "0", &pInst);
704	InsertConfigNode(pInst, "Config", &pCfg);
705	InsertConfigInteger(pCfg, "Irq", iIrq);
706	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
707	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
708
709	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
710	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
711	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
712	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
713	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
714	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
715	"arm,pl031", "arm,primecell"); VRC();
716	vrc = RTFdtNodeFinalize(hFdt); VRC();
717
718	/* Configure gpio keys (The Windows GPIO PL061 driver doesn't like 64-bit MMIO addresses...). */
719	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
720	hrc = pResMgr->assignMmio32Region("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
721	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
722	InsertConfigNode(pDev, "0", &pInst);
723	InsertConfigNode(pInst, "Config", &pCfg);
724	InsertConfigInteger(pCfg, "Irq", iIrq);
725	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
726	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
727	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
728	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
729	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
730	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
731	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
732	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
733	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
734	"arm,pl061", "arm,primecell"); VRC();
735	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
736	vrc = RTFdtNodeFinalize(hFdt); VRC();
737
738	InsertConfigNode(pInst, "LUN#0", &pLunL0);
739	InsertConfigString(pLunL0, "Driver", "GpioButton");
740	InsertConfigNode(pLunL0, "Config", &pCfg);
741	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
742	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
743
744	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
745	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
746
747	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
748	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
749	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
750	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
751	vrc = RTFdtNodeFinalize(hFdt); VRC();
752
753	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
754	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
755	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
756	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
757	vrc = RTFdtNodeFinalize(hFdt); VRC();
758
759	vrc = RTFdtNodeFinalize(hFdt); VRC();
760
761	if (pSysTblsBldAcpi)
762	{
763	vrc = pSysTblsBldAcpi->configureGpioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, cbMmio, iIrq,
764	3 /u16PinShutdown/, 4 /u16PinSuspend/);
765	VRC();
766	}
767
768	#if defined(VBOX_WITH_TPM)
769	/*
770	* Configure the Trusted Platform Module.
771	*/
772	ComObjPtr<ITrustedPlatformModule> ptrTpm;
773	TpmType_T enmTpmType = TpmType_None;
774
775	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
776	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
777	if (enmTpmType != TpmType_None)
778	{
779	hrc = pResMgr->assignSingleInterrupt("tpm", &iIrq); H();
780
781	vrc = i_configTpm(ptrTpm, enmTpmType, pDevices, GCPhysTpm, iIrq /uIrq/,
782	GCPhysTpm + 0x5000, true /fCrb/); VRC();
783
784	vrc = RTFdtNodeAddF(hFdt, "tpm@%RGp", GCPhysTpm); VRC();
785	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
786	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysTpm, cbTpm); VRC();
787	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 1, "tcg,tpm-tis-mmio"); VRC();
788	vrc = RTFdtNodeFinalize(hFdt); VRC();
789
790	if (pSysTblsBldAcpi)
791	{
792	vrc = pSysTblsBldAcpi->configureTpm2(true /fCrb/, GCPhysTpm, cbTpm, iIrq);
793	VRC();
794	}
795	}
796	#endif
797
798	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
799	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
800	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
801	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
802
803	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio, false /fOnly32Bit/); H();
804	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
805	hrc = pResMgr->assignMmio64Region( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
806	hrc = pResMgr->assignMmio32Region( "pci-mmio32", _256M, &GCPhysPciMmio32, &cbPciMmio32); H();
807
808	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
809	InsertConfigNode(pDev, "0", &pInst);
810	InsertConfigNode(pInst, "Config", &pCfg);
811	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
812	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
813	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
814	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
815	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
816	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
817	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
818	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
819	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
820	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
821
822	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
823	uint32_t *pau32IrqCell = &aIrqCells[0];
824	uint32_t iIrqPinSwizzle = 0;
825
826	for (uint32_t i = 0; i < 32; i++)
827	{
828	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
829	{
830	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
831	pau32IrqCell[1] = 0;
832	pau32IrqCell[2] = 0;
833	pau32IrqCell[3] = iIrqPin + 1;
834	pau32IrqCell[4] = idPHandleIntCtrl;
835	pau32IrqCell[5] = 0;
836	pau32IrqCell[6] = 0;
837	pau32IrqCell[7] = 0;
838	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
839	pau32IrqCell[9] = 0x04;
840	pau32IrqCell += 10;
841	}
842
843	iIrqPinSwizzle++;
844	}
845
846	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]); VRC();
847	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
848	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
849	0x1000000, 0, 0,
850	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
851	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
852	cbPciMmio32 >> 32, cbPciMmio32,
853	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
854	cbPciMmio >> 32, cbPciMmio); VRC();
855	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
856	/** @todo msi-map */
857	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
858	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
859	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
860	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
861	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
862	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
863	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
864	vrc = RTFdtNodeFinalize(hFdt); VRC();
865
866	if (pSysTblsBldAcpi)
867	{
868	vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
869	cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
870	VRC();
871	}
872
873	/*
874	* VMSVGA compliant graphics controller.
875	*/
876	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
877	&& enmGraphicsController != GraphicsControllerType_Null)
878	{
879	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
880	pGraphicsAdapter, firmwareSettings,
881	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
882	}
883
884	/*
885	* The USB Controllers and input devices.
886	*/
887	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
888	KeyboardHIDType_T aKbdHID;
889	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
890	#endif
891
892	PointingHIDType_T aPointingHID;
893	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
894
895	PCFGMNODE pUsbDevices = NULL;
896	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
897
898	/*
899	* Storage controllers.
900	*/
901	bool fFdcEnabled = false;
902	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
903	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
904
905	/*
906	* Network adapters
907	*/
908	std::list<BootNic> llBootNics;
909	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
910	pVMM, pUVM, pDevices, pUsbDevices, llBootNics); VRC();
911
912	/*
913	* The VMM device.
914	*/
915	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
916
917	/*
918	* Audio configuration.
919	*/
920	bool fAudioEnabled = false;
921	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
922	false /fOsXGuest/, &fAudioEnabled); VRC();
923
924	/*
925	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
926	*/
927	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
928	}
929	catch (ConfigError &x)
930	{
931	RTFdtDestroy(hFdt);
932
933	// InsertConfig threw something:
934	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
935	return x.m_vrc;
936	}
937	catch (HRESULT hrcXcpt)
938	{
939	RTFdtDestroy(hFdt);
940	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
941	}
942
943	#ifdef VBOX_WITH_EXTPACK
944	/*
945	* Call the extension pack hooks if everything went well thus far.
946	*/
947	if (RT_SUCCESS(vrc))
948	{
949	pAlock->release();
950	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
951	pAlock->acquire();
952	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
953	}
954	#endif
955
956	#if 0
957	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
958	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
959	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
960	vrc = RTFdtNodeFinalize(hFdt);
961	#endif
962
963	/* Finalize the FDT and add it to the resource store. */
964	vrc = RTFdtFinalize(hFdt);
965	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
966
967	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
968	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
969	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
970	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
971	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
972
973	/* Initialize the VBox platform descriptor. */
974	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
975
976	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
977	uint64_t cbFdt = 0;
978	if (RT_SUCCESS(vrc))
979	vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
980	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
981
982	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
983	AssertRCReturn(vrc, vrc);
984
985	cbFdt = RT_ALIGN_64(cbFdt, _64K);
986
987	RTGCPHYS GCPhysMmioStart;
988	RTGCPHYS cbMmio;
989	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
990	Assert(SUCCEEDED(hrc));
991
992	RTGCPHYS GCPhysMmio32Start;
993	RTGCPHYS cbMmio32;
994	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
995	Assert(SUCCEEDED(hrc));
996
997	RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
998	size_t cbAcpiXsdp = 0;
999	size_t cbAcpi = 0;
1000	if (pSysTblsBldAcpi)
1001	{
1002	vrc = pSysTblsBldAcpi->finishTables(GCPhysPlatformDesc + cbFdt,
1003	hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
1004	AssertRCReturn(vrc, vrc);
1005	Assert( GCPhysXsdp > GCPhysPlatformDesc
1006	&& GCPhysXsdp < VBOXPLATFORMARMV8_PHYS_ADDR);
1007
1008	/* Dump the ACPI table for debugging purposes if requested. */
1009	Bstr SysTblsDumpVal;
1010	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
1011	SysTblsDumpVal.asOutParam());
1012	if ( hrc == S_OK
1013	&& SysTblsDumpVal.isNotEmpty())
1014	{
1015	vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
1016	AssertRCReturn(vrc, vrc);
1017	}
1018
1019	delete pSysTblsBldAcpi;
1020
1021	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
1022	AssertRCReturn(vrc, vrc);
1023
1024	cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
1025	}
1026
1027	/* Fill the room until the end where the platform descriptor lives. */
1028	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, cbPlatformDesc - sizeof(ArmV8Platform) - cbFdt - cbAcpi);
1029	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1030
1031	RTGCPHYS GCPhysMmio = 0;
1032	RTGCPHYS cbMmioAbove4G = 0;
1033	pResMgr->queryMmioRegion(&GCPhysMmio, &cbMmioAbove4G);
1034
1035	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
1036	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
1037	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
1038	ArmV8Platform.fFlags = 0;
1039	ArmV8Platform.u64PhysAddrRamBase = GCPhysRamBase;
1040	ArmV8Platform.cbRamBase = cbRamBase;
1041	ArmV8Platform.i64OffFdt = (int64_t)GCPhysPlatformDesc - VBOXPLATFORMARMV8_PHYS_ADDR;
1042	ArmV8Platform.cbFdt = cbFdt;
1043	if (cbAcpi)
1044	{
1045	ArmV8Platform.i64OffAcpi = (int64_t)(GCPhysPlatformDesc + cbFdt) - VBOXPLATFORMARMV8_PHYS_ADDR;
1046	ArmV8Platform.cbAcpi = cbAcpi;
1047	ArmV8Platform.i64OffAcpiXsdp = (int64_t)GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
1048	ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
1049	}
1050	ArmV8Platform.i64OffUefiRom = (int64_t)GCPhysFw - VBOXPLATFORMARMV8_PHYS_ADDR;
1051	ArmV8Platform.cbUefiRom = _64M;
1052	ArmV8Platform.i64OffMmio = GCPhysMmio ? (int64_t)GCPhysMmio - VBOXPLATFORMARMV8_PHYS_ADDR : 0;
1053	ArmV8Platform.cbMmio = cbMmioAbove4G;
1054	ArmV8Platform.i64OffMmio32 = (int64_t)(_4G - _512M) - VBOXPLATFORMARMV8_PHYS_ADDR;
1055	ArmV8Platform.cbMmio32 = _512M - _2M; /* Just assign the whole MMIO hole (except for the platform descriptor region). */
1056
1057	/* Add the VBox platform descriptor to the resource store. */
1058	vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
1059	RTVfsIoStrmRelease(hVfsIosDesc);
1060	AssertRCReturnStmt(vrc, RTVfsFileRelease(hVfsFileDesc), vrc);
1061
1062	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
1063	RTVfsFileRelease(hVfsFileDesc);
1064	AssertRCReturn(vrc, vrc);
1065
1066	/* Dump the DTB for debugging purposes if requested. */
1067	Bstr DtbDumpVal;
1068	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
1069	DtbDumpVal.asOutParam());
1070	if ( hrc == S_OK
1071	&& DtbDumpVal.isNotEmpty())
1072	{
1073	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
1074	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1075	}
1076
1077	pResMgr->dumpMemoryRegionsToReleaseLog();
1078
1079	delete pResMgr; /* Delete the address/interrupt assignment manager. */
1080
1081	/*
1082	* Apply the CFGM overlay.
1083	*/
1084	if (RT_SUCCESS(vrc))
1085	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
1086
1087	/*
1088	* Dump all extradata API settings tweaks, both global and per VM.
1089	*/
1090	if (RT_SUCCESS(vrc))
1091	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
1092
1093	#undef H
1094
1095	pAlock->release(); /* Avoid triggering the lock order inversion check. */
1096
1097	/*
1098	* Register VM state change handler.
1099	*/
1100	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
1101	AssertRC(vrc2);
1102	if (RT_SUCCESS(vrc))
1103	vrc = vrc2;
1104
1105	/*
1106	* Register VM runtime error handler.
1107	*/
1108	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
1109	AssertRC(vrc2);
1110	if (RT_SUCCESS(vrc))
1111	vrc = vrc2;
1112
1113	pAlock->acquire();
1114
1115	LogFlowFunc(("vrc = %Rrc\n", vrc));
1116	LogFlowFuncLeave();
1117
1118	return vrc;
1119	}
1120	#endif /* !VBOX_WITH_VIRT_ARMV8 */
1121

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 108838

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