VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 101515

Last change on this file since 101515 was 101515, checked in by vboxsync, 18 months ago

Main: Don't apply the PCI slot swap hack for the ARMv8 virtual platform, bugref:10528
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1/* $Id: ConsoleImplConfigArmV8.cpp 101515 2023-10-20 10:47:48Z vboxsync $ */
2/** @file
3 * VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33#include "LoggingNew.h"
34
35#include "ConsoleImpl.h"
36#include "ResourceStoreImpl.h"
37#include "Global.h"
38#include "VMMDev.h"
39
40// generated header
41#include "SchemaDefs.h"
42
43#include "AutoCaller.h"
44
45#include <iprt/buildconfig.h>
46#include <iprt/ctype.h>
47#include <iprt/dir.h>
48#include <iprt/fdt.h>
49#include <iprt/file.h>
50#include <iprt/param.h>
51#include <iprt/path.h>
52#include <iprt/string.h>
53#include <iprt/system.h>
54#if 0 /* enable to play with lots of memory. */
55# include <iprt/env.h>
56#endif
57#include <iprt/stream.h>
58
59#include <iprt/formats/arm-psci.h>
60
61#include <VBox/vmm/vmmr3vtable.h>
62#include <VBox/vmm/vmapi.h>
63#include <VBox/err.h>
64#include <VBox/param.h>
65#include <VBox/version.h>
66#include <VBox/platforms/vbox-armv8.h>
67
68#include "BusAssignmentManager.h"
69#ifdef VBOX_WITH_EXTPACK
70# include "ExtPackManagerImpl.h"
71#endif
72
73
74/*********************************************************************************************************************************
75* Internal Functions *
76*********************************************************************************************************************************/
77
78/* Darwin compile kludge */
79#undef PVM
80
81#ifdef VBOX_WITH_VIRT_ARMV8
82/**
83 * Worker for configConstructor.
84 *
85 * @return VBox status code.
86 * @param pUVM The user mode VM handle.
87 * @param pVM The cross context VM handle.
88 * @param pVMM The VMM vtable.
89 * @param pAlock The automatic lock instance. This is for when we have
90 * to leave it in order to avoid deadlocks (ext packs and
91 * more).
92 *
93 * @todo This is a big hack at the moment and provides a static VM config to work with, will be adjusted later
94 * on to adhere to the VM config when sorting out the API bits.
95 */
96int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97{
98 RT_NOREF(pVM /* when everything is disabled */);
99 ComPtr<IMachine> pMachine = i_machine();
100
101 HRESULT hrc;
102 Utf8Str strTmp;
103 Bstr bstr;
104
105 RTFDT hFdt = NIL_RTFDT;
106 int vrc = RTFdtCreateEmpty(&hFdt);
107 AssertRCReturn(vrc, vrc);
108
109#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112 /** @todo Find a way to figure it out before CPUM is set up, can't use CPUMGetGuestAddrWidths() and on macOS we need
113 * access to Hypervisor.framework to query the ID registers (Linux can in theory parse /proc/cpuinfo, no idea for Windows). */
114 RTGCPHYS GCPhysTopOfAddrSpace = RT_BIT_64(36);
115
116 /*
117 * Get necessary objects and frequently used parameters.
118 */
119 ComPtr<IVirtualBox> virtualBox;
120 hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
121
122 ComPtr<IHost> host;
123 hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
124
125 PlatformArchitecture_T platformArchHost;
126 hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
127
128 ComPtr<ISystemProperties> systemProperties;
129 hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
130
131 ComPtr<IFirmwareSettings> firmwareSettings;
132 hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
133
134 ComPtr<INvramStore> nvramStore;
135 hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
136
137 hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
138 RTUUID HardwareUuid;
139 vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
140 AssertRCReturn(vrc, vrc);
141
142 ULONG cRamMBs;
143 hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
144 uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
145
146 ComPtr<IPlatform> platform;
147 hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
148
149 /* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
150#if 1 /* For now we only support running ARM VMs on ARM hosts. */
151 PlatformArchitecture_T platformArchMachine;
152 hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
153 if (platformArchMachine != platformArchHost)
154 return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
155 N_("VM platform architecture (%s) not supported on this host (%s)."),
156 Global::stringifyPlatformArchitecture(platformArchMachine),
157 Global::stringifyPlatformArchitecture(platformArchHost));
158#endif
159
160 ComPtr<IPlatformProperties> pPlatformProperties;
161 hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
162
163 ChipsetType_T chipsetType;
164 hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
165
166 ULONG cCpus = 1;
167 hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
168 Assert(cCpus);
169
170 ULONG ulCpuExecutionCap = 100;
171 hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
172
173 LogRel(("Guest architecture: ARM\n"));
174
175 Bstr osTypeId;
176 hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
177 LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
178
179 BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
180
181 /*
182 * Get root node first.
183 * This is the only node in the tree.
184 */
185 PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
186 Assert(pRoot);
187
188 // catching throws from InsertConfigString and friends.
189 try
190 {
191
192 /*
193 * Set the root (and VMM) level values.
194 */
195 hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
196 InsertConfigString(pRoot, "Name", bstr);
197 InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
198 InsertConfigInteger(pRoot, "NumCPUs", cCpus);
199 InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
200 InsertConfigInteger(pRoot, "TimerMillies", 10);
201
202 /*
203 * NEM
204 */
205 PCFGMNODE pNEM;
206 InsertConfigNode(pRoot, "NEM", &pNEM);
207
208 uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
209 Assert(idPHandleIntCtrl != UINT32_MAX);
210 uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
211 Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
212 uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
213 Assert(idPHandleAbpPClk != UINT32_MAX);
214 uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
215 Assert(idPHandleGpio != UINT32_MAX);
216
217 uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
218 for (uint32_t i = 0; i < cCpus; i++)
219 {
220 aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
221 Assert(aidPHandleCpus[i] != UINT32_MAX);
222 }
223
224 vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
225 vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
226 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
227 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
228 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
229
230 /* Configure the Power State Coordination Interface. */
231 vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
232 vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
233 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
234 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
235 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
236 vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
237 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
238 "arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
239 vrc = RTFdtNodeFinalize(hFdt); VRC();
240
241 /* Configure the timer and clock. */
242 InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
243 vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
244 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
245 0x01, 0x0d, 0x104,
246 0x01, 0x0e, 0x104,
247 0x01, 0x0b, 0x104,
248 0x01, 0x0a, 0x104); VRC();
249 vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
250 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv7-timer"); VRC();
251 vrc = RTFdtNodeFinalize(hFdt);
252
253 vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
254 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
255 vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
256 vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
257 vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
258 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
259 vrc = RTFdtNodeFinalize(hFdt);
260
261 /* Configure gpio keys (non functional at the moment). */
262 vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
263 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
264
265 vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
266 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
267 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
268 vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
269 vrc = RTFdtNodeFinalize(hFdt); VRC();
270
271 vrc = RTFdtNodeFinalize(hFdt); VRC();
272
273 /*
274 * MM values.
275 */
276 PCFGMNODE pMM;
277 InsertConfigNode(pRoot, "MM", &pMM);
278
279 /*
280 * Memory setup.
281 */
282 PCFGMNODE pMem = NULL;
283 InsertConfigNode(pMM, "MemRegions", &pMem);
284
285 PCFGMNODE pMemRegion = NULL;
286 InsertConfigNode(pMem, "Conventional", &pMemRegion);
287 InsertConfigInteger(pMemRegion, "GCPhysStart", 0x40000000);
288 InsertConfigInteger(pMemRegion, "Size", cbRam);
289
290 vrc = RTFdtNodeAddF(hFdt, "memory@%RX32", 0x40000000); VRC();
291 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4,
292 0, 0x40000000,
293 (uint32_t)(cbRam >> 32), cbRam & UINT32_MAX); VRC();
294 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
295 vrc = RTFdtNodeFinalize(hFdt); VRC();
296
297 /* Configure the CPUs in the system, only one socket and cluster at the moment. */
298 vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
299 vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
300 vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
301
302 vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
303 vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
304
305 for (uint32_t i = 0; i < cCpus; i++)
306 {
307 vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
308 vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
309 vrc = RTFdtNodeFinalize(hFdt); VRC();
310 }
311
312 vrc = RTFdtNodeFinalize(hFdt); VRC();
313 vrc = RTFdtNodeFinalize(hFdt); VRC();
314
315 for (uint32_t i = 0; i < cCpus; i++)
316 {
317 vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
318 vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
319 vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
320 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
321 vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
322 if (cCpus > 1)
323 {
324 vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
325 }
326 vrc = RTFdtNodeFinalize(hFdt); VRC();
327 }
328
329 vrc = RTFdtNodeFinalize(hFdt); VRC();
330
331
332 /*
333 * PDM config.
334 * Load drivers in VBoxC.[so|dll]
335 */
336 vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
337
338
339 /*
340 * VGA.
341 */
342 ComPtr<IGraphicsAdapter> pGraphicsAdapter;
343 hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
344 GraphicsControllerType_T enmGraphicsController;
345 hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
346
347 /*
348 * Devices
349 */
350 PCFGMNODE pDevices = NULL; /* /Devices */
351 PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
352 PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
353 PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
354 PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
355
356 InsertConfigNode(pRoot, "Devices", &pDevices);
357
358 InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
359
360 InsertConfigNode(pDevices, "platform", &pDev);
361 InsertConfigNode(pDev, "0", &pInst);
362 InsertConfigNode(pInst, "Config", &pCfg);
363 InsertConfigNode(pInst, "LUN#0", &pLunL0);
364 InsertConfigString(pLunL0, "Driver", "ResourceStore");
365
366 /* Add the resources. */
367 PCFGMNODE pResources = NULL; /* /Devices/efi-armv8/Config/Resources */
368 PCFGMNODE pRes = NULL; /* /Devices/efi-armv8/Config/Resources/<Resource> */
369 InsertConfigString(pCfg, "ResourceNamespace", "resources");
370 InsertConfigNode(pCfg, "Resources", &pResources);
371 InsertConfigNode(pResources, "EfiRom", &pRes);
372 InsertConfigInteger(pRes, "RegisterAsRom", 1);
373 InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
374
375 /** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
376 /*
377 * Firmware.
378 */
379 FirmwareType_T eFwType = FirmwareType_EFI64;
380#ifdef VBOX_WITH_EFI_IN_DD2
381 const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
382 : eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
383 : "VBoxEFIAArch64.fd";
384 const char *pszKey = "ResourceId";
385#else
386 Utf8Str efiRomFile;
387 vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
388 AssertRCReturn(vrc, vrc);
389 const char *pszEfiRomFile = efiRomFile.c_str();
390 const char *pszKey = "Filename";
391#endif
392 InsertConfigString(pRes, pszKey, pszEfiRomFile);
393
394 InsertConfigNode(pResources, "ArmV8Desc", &pRes);
395 InsertConfigInteger(pRes, "RegisterAsRom", 1);
396 InsertConfigInteger(pRes, "GCPhysLoadAddress", UINT64_MAX); /* End of physical address space. */
397 InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
398
399 vrc = RTFdtNodeAddF(hFdt, "platform-bus@%RX32", 0x0c000000); VRC();
400 vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
401 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 4, 0, 0, 0x0c000000, 0x02000000); VRC();
402 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 1); VRC();
403 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 1); VRC();
404 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
405 "qemu,platform", "simple-bus"); VRC();
406 vrc = RTFdtNodeFinalize(hFdt); VRC();
407
408 InsertConfigNode(pDevices, "gic", &pDev);
409 InsertConfigNode(pDev, "0", &pInst);
410 InsertConfigInteger(pInst, "Trusted", 1);
411 InsertConfigNode(pInst, "Config", &pCfg);
412 InsertConfigInteger(pCfg, "DistributorMmioBase", 0x08000000);
413 InsertConfigInteger(pCfg, "RedistributorMmioBase", 0x080a0000);
414
415 vrc = RTFdtNodeAddF(hFdt, "intc@%RX32", 0x08000000); VRC();
416 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
417 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 8,
418 0, 0x08000000, 0, 0x10000,
419 0, 0x080a0000, 0, 0xf60000); VRC();
420 vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
421 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
422 vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
423 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
424 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
425 vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
426 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
427
428#if 0
429 vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
430 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
431 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
432 vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
433 vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
434 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
435 vrc = RTFdtNodeFinalize(hFdt); VRC();
436#endif
437
438 vrc = RTFdtNodeFinalize(hFdt); VRC();
439
440
441 InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
442 InsertConfigNode(pDev, "0", &pInst);
443 InsertConfigNode(pInst, "Config", &pCfg);
444 InsertConfigInteger(pCfg, "MmioSize", 4096);
445 InsertConfigInteger(pCfg, "MmioBase", 0x09020000);
446 InsertConfigInteger(pCfg, "DmaEnabled", 1);
447 InsertConfigInteger(pCfg, "QemuRamfbSupport", enmGraphicsController == GraphicsControllerType_QemuRamFB ? 1 : 0);
448 if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
449 {
450 InsertConfigNode(pInst, "LUN#0", &pLunL0);
451 InsertConfigString(pLunL0, "Driver", "MainDisplay");
452 }
453
454 vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RX32", 0x09020000); VRC();
455 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
456 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09020000, 0, 0x18); VRC();
457 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
458 vrc = RTFdtNodeFinalize(hFdt); VRC();
459
460
461 InsertConfigNode(pDevices, "flash-cfi", &pDev);
462 InsertConfigNode(pDev, "0", &pInst);
463 InsertConfigNode(pInst, "Config", &pCfg);
464 InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
465 InsertConfigInteger(pCfg, "Size", 768 * _1K);
466 InsertConfigString(pCfg, "FlashFile", "nvram");
467 /* Attach the NVRAM storage driver. */
468 InsertConfigNode(pInst, "LUN#0", &pLunL0);
469 InsertConfigString(pLunL0, "Driver", "NvramStore");
470
471 vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
472 vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
473 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 8,
474 0, 0, 0, 0x04000000,
475 0, 0x04000000, 0, 0x04000000); VRC();
476 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
477 vrc = RTFdtNodeFinalize(hFdt); VRC();
478
479 InsertConfigNode(pDevices, "arm-pl011", &pDev);
480 for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
481 {
482 ComPtr<ISerialPort> serialPort;
483 hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
484 BOOL fEnabledSerPort = FALSE;
485 if (serialPort)
486 {
487 hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
488 }
489 if (!fEnabledSerPort)
490 {
491 m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
492 continue;
493 }
494
495 InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
496 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
497 InsertConfigNode(pInst, "Config", &pCfg);
498
499 InsertConfigInteger(pCfg, "Irq", 1);
500 InsertConfigInteger(pCfg, "MmioBase", 0x09000000);
501
502 vrc = RTFdtNodeAddF(hFdt, "pl011@%RX32", 0x09000000); VRC();
503 vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
504 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
505 idPHandleAbpPClk, idPHandleAbpPClk); VRC();
506 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x01, 0x04); VRC();
507 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09000000, 0, 0x1000); VRC();
508 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
509 "arm,pl011", "arm,primecell"); VRC();
510 vrc = RTFdtNodeFinalize(hFdt); VRC();
511
512 BOOL fServer;
513 hrc = serialPort->COMGETTER(Server)(&fServer); H();
514 hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
515
516 PortMode_T eHostMode;
517 hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
518
519 m_aeSerialPortMode[ulInstance] = eHostMode;
520 if (eHostMode != PortMode_Disconnected)
521 {
522 vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
523 if (RT_FAILURE(vrc))
524 return vrc;
525 }
526 }
527
528 BOOL fRTCUseUTC;
529 hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
530
531 InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
532 InsertConfigNode(pDev, "0", &pInst);
533 InsertConfigNode(pInst, "Config", &pCfg);
534 InsertConfigInteger(pCfg, "Irq", 2);
535 InsertConfigInteger(pCfg, "MmioBase", 0x09010000);
536 InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
537
538 vrc = RTFdtNodeAddF(hFdt, "pl032@%RX32", 0x09010000); VRC();
539 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
540 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
541 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x02, 0x04); VRC();
542 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09010000, 0, 0x1000); VRC();
543 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
544 "arm,pl031", "arm,primecell"); VRC();
545 vrc = RTFdtNodeFinalize(hFdt); VRC();
546
547 InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
548 InsertConfigNode(pDev, "0", &pInst);
549 InsertConfigNode(pInst, "Config", &pCfg);
550 InsertConfigInteger(pCfg, "Irq", 7);
551 InsertConfigInteger(pCfg, "MmioBase", 0x09030000);
552 vrc = RTFdtNodeAddF(hFdt, "pl061@%RX32", 0x09030000); VRC();
553 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
554 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
555 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
556 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x07, 0x04); VRC();
557 vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
558 vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
559 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
560 "arm,pl061", "arm,primecell"); VRC();
561 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09030000, 0, 0x1000); VRC();
562 vrc = RTFdtNodeFinalize(hFdt); VRC();
563
564 uint32_t aPinIrqs[] = { 3, 4, 5, 6 };
565 InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
566 InsertConfigNode(pDev, "0", &pInst);
567 InsertConfigNode(pInst, "Config", &pCfg);
568 InsertConfigInteger(pCfg, "MmioEcamBase", 0x3f000000);
569 InsertConfigInteger(pCfg, "MmioEcamLength", 0x01000000);
570 InsertConfigInteger(pCfg, "MmioPioBase", 0x3eff0000);
571 InsertConfigInteger(pCfg, "MmioPioSize", 0x0000ffff);
572 InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
573 InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
574 InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
575 InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
576 vrc = RTFdtNodeAddF(hFdt, "pcie@%RX32", 0x10000000); VRC();
577 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
578
579 uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
580 uint32_t *pau32IrqCell = &aIrqCells[0];
581 uint32_t iIrqPinSwizzle = 0;
582
583 for (uint32_t i = 0; i < 32; i++)
584 {
585 for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
586 {
587 pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
588 pau32IrqCell[1] = 0;
589 pau32IrqCell[2] = 0;
590 pau32IrqCell[3] = iIrqPin + 1;
591 pau32IrqCell[4] = idPHandleIntCtrl;
592 pau32IrqCell[5] = 0;
593 pau32IrqCell[6] = 0;
594 pau32IrqCell[7] = 0;
595 pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
596 pau32IrqCell[9] = 0x04;
597 pau32IrqCell += 10;
598 }
599
600 iIrqPinSwizzle++;
601 }
602
603 vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
604 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
605 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 14,
606 0x1000000, 0, 0, 0, 0x3eff0000, 0, 0x10000,
607 0x2000000, 0, 0x10000000, 0, 0x10000000, 0,
608 0x2eff0000); VRC();
609 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x3f000000, 0, 0x1000000); VRC();
610 /** @todo msi-map */
611 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
612 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
613 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
614 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
615 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
616 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
617 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
618 vrc = RTFdtNodeFinalize(hFdt); VRC();
619
620 /*
621 * VMSVGA compliant graphics controller.
622 */
623 if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
624 && enmGraphicsController != GraphicsControllerType_Null)
625 {
626 vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
627 pGraphicsAdapter, firmwareSettings,
628 true /*fForceVmSvga3*/, false /*fExposeLegacyVga*/); VRC();
629 }
630
631 /*
632 * The USB Controllers and input devices.
633 */
634#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
635 KeyboardHIDType_T aKbdHID;
636 hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
637#endif
638
639 PointingHIDType_T aPointingHID;
640 hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
641
642 PCFGMNODE pUsbDevices = NULL;
643 vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
644
645 /*
646 * Storage controllers.
647 */
648 bool fFdcEnabled = false;
649 vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
650 pDevices, pUsbDevices, NULL /*pBiosCfg*/, &fFdcEnabled); VRC();
651
652 /*
653 * Network adapters
654 */
655 std::list<BootNic> llBootNics;
656 vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
657 pVMM, pUVM, pDevices, llBootNics); VRC();
658
659 /*
660 * The VMM device.
661 */
662 vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /*fMmioReq*/); VRC();
663
664 /*
665 * Audio configuration.
666 */
667 bool fAudioEnabled = false;
668 vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
669 false /*fOsXGuest*/, &fAudioEnabled); VRC();
670 }
671 catch (ConfigError &x)
672 {
673 RTFdtDestroy(hFdt);
674
675 // InsertConfig threw something:
676 pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
677 return x.m_vrc;
678 }
679 catch (HRESULT hrcXcpt)
680 {
681 RTFdtDestroy(hFdt);
682 AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
683 }
684
685#ifdef VBOX_WITH_EXTPACK
686 /*
687 * Call the extension pack hooks if everything went well thus far.
688 */
689 if (RT_SUCCESS(vrc))
690 {
691 pAlock->release();
692 vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
693 pAlock->acquire();
694 }
695#endif
696
697#if 0
698 vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
699 vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
700 vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
701 vrc = RTFdtNodeFinalize(hFdt);
702#endif
703
704 /* Finalize the FDT and add it to the resource store. */
705 vrc = RTFdtFinalize(hFdt);
706 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
707
708 RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
709 vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /*cbEstimate*/, &hVfsFileDesc);
710 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
711 RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
712 AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
713
714 /* Initialize the VBox platform descriptor. */
715 VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
716
717 vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, hVfsIosDesc, NULL /*pErrInfo*/);
718 if (RT_SUCCESS(vrc))
719 vrc = RTVfsFileQuerySize(hVfsFileDesc, &ArmV8Platform.cbFdt);
720 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
721
722 vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(ArmV8Platform.cbFdt, _64K) - ArmV8Platform.cbFdt));
723 AssertRCReturn(vrc, vrc);
724
725 ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
726 ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
727 ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
728 ArmV8Platform.fFlags = 0;
729 ArmV8Platform.u64PhysAddrRamBase = UINT64_C(0x40000000);
730 ArmV8Platform.cbRamBase = cbRam;
731 ArmV8Platform.u64OffBackFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
732 ArmV8Platform.cbFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
733 ArmV8Platform.u64OffBackAcpiXsdp = 0;
734 ArmV8Platform.cbAcpiXsdp = 0;
735 ArmV8Platform.u64OffBackUefiRom = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform);
736 ArmV8Platform.cbUefiRom = _64M; /** @todo Fixed reservation but the ROM region is usually much smaller. */
737 ArmV8Platform.u64OffBackMmio = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform) - 0x08000000; /** @todo Start of generic MMIO area containing the GIC,UART,RTC, etc. Will be changed soon */
738 ArmV8Platform.cbMmio = _128M;
739
740 /* Add the VBox platform descriptor to the resource store. */
741 vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /*fBlocking*/, NULL /*pcbWritten*/);
742 RTVfsIoStrmRelease(hVfsIosDesc);
743 vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
744 RTVfsFileRelease(hVfsFileDesc);
745 AssertRCReturn(vrc, vrc);
746
747 /* Dump the DTB for debugging purposes if requested. */
748 Bstr DtbDumpVal;
749 hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
750 DtbDumpVal.asOutParam());
751 if ( hrc == S_OK
752 && DtbDumpVal.isNotEmpty())
753 {
754 vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, Utf8Str(DtbDumpVal).c_str(), NULL /*pErrInfo*/);
755 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
756 }
757
758
759 /*
760 * Apply the CFGM overlay.
761 */
762 if (RT_SUCCESS(vrc))
763 vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
764
765 /*
766 * Dump all extradata API settings tweaks, both global and per VM.
767 */
768 if (RT_SUCCESS(vrc))
769 vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
770
771#undef H
772
773 pAlock->release(); /* Avoid triggering the lock order inversion check. */
774
775 /*
776 * Register VM state change handler.
777 */
778 int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
779 AssertRC(vrc2);
780 if (RT_SUCCESS(vrc))
781 vrc = vrc2;
782
783 /*
784 * Register VM runtime error handler.
785 */
786 vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
787 AssertRC(vrc2);
788 if (RT_SUCCESS(vrc))
789 vrc = vrc2;
790
791 pAlock->acquire();
792
793 LogFlowFunc(("vrc = %Rrc\n", vrc));
794 LogFlowFuncLeave();
795
796 return vrc;
797}
798#endif /* !VBOX_WITH_VIRT_ARMV8 */
799
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