ConsoleImplConfigX86.cpp@ 102654

Last change on this file since 102654 was 101482, checked in by vboxsync, 14 months ago
Main/src-client/ConsoleImplConfigX86.cpp: Remove some now unused headers, bugref:10528
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 83.0 KB

Line
1	/* $Id: ConsoleImplConfigX86.cpp 101482 2023-10-17 15:05:54Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits.
4	*
5	* @remark We've split out the code that the 64-bit VC++ v8 compiler finds
6	* problematic to optimize so we can disable optimizations and later,
7	* perhaps, find a real solution for it (like rewriting the code and
8	* to stop resemble a tonne of spaghetti).
9	*/
10
11	/*
12	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
13	*
14	* This file is part of VirtualBox base platform packages, as
15	* available from https://www.virtualbox.org.
16	*
17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License
19	* as published by the Free Software Foundation, in version 3 of the
20	* License.
21	*
22	* This program is distributed in the hope that it will be useful, but
23	* WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25	* General Public License for more details.
26	*
27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, see <https://www.gnu.org/licenses>.
29	*
30	* SPDX-License-Identifier: GPL-3.0-only
31	*/
32
33
34	/*********************************************************************************************************************************
35	* Header Files *
36	*********************************************************************************************************************************/
37	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
38	#include "LoggingNew.h"
39
40	#include "ConsoleImpl.h"
41	#include "DisplayImpl.h"
42	#include "NvramStoreImpl.h"
43	#include "PlatformImpl.h"
44	#include "VMMDev.h"
45	#include "Global.h"
46	#ifdef VBOX_WITH_PCI_PASSTHROUGH
47	# include "PCIRawDevImpl.h"
48	#endif
49
50	// generated header
51	#include "SchemaDefs.h"
52
53	#include "AutoCaller.h"
54
55	#include <iprt/base64.h>
56	#include <iprt/buildconfig.h>
57	#include <iprt/ctype.h>
58	#include <iprt/dir.h>
59	#include <iprt/file.h>
60	#include <iprt/param.h>
61	#include <iprt/path.h>
62	#include <iprt/string.h>
63	#include <iprt/system.h>
64	#if 0 /* enable to play with lots of memory. */
65	# include <iprt/env.h>
66	#endif
67	#include <iprt/stream.h>
68
69	#include <iprt/http.h>
70	#include <iprt/socket.h>
71	#include <iprt/uri.h>
72
73	#include <VBox/vmm/vmmr3vtable.h>
74	#include <VBox/vmm/vmapi.h>
75	#include <VBox/err.h>
76	#include <VBox/param.h>
77	#include <VBox/settings.h> /* For MachineConfigFile::getHostDefaultAudioDriver(). */
78	#include <VBox/vmm/pdmapi.h> /* For PDMR3DriverAttach/PDMR3DriverDetach. */
79	#include <VBox/vmm/pdmusb.h> /* For PDMR3UsbCreateEmulatedDevice. */
80	#include <VBox/vmm/pdmdev.h> /* For PDMAPICMODE enum. */
81	#include <VBox/vmm/pdmstorageifs.h>
82	#include <VBox/vmm/gcm.h>
83	#include <VBox/version.h>
84
85	#include <VBox/com/com.h>
86	#include <VBox/com/string.h>
87	#include <VBox/com/array.h>
88
89	#include "NetworkServiceRunner.h"
90	#include "BusAssignmentManager.h"
91	#ifdef VBOX_WITH_EXTPACK
92	# include "ExtPackManagerImpl.h"
93	#endif
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99
100	/* Darwin compile kludge */
101	#undef PVM
102
103	/**
104	* @throws HRESULT on extra data retrival error.
105	*/
106	static int getSmcDeviceKey(IVirtualBox pVirtualBox, IMachine pMachine, Utf8Str pStrKey, bool pfGetKeyFromRealSMC)
107	{
108	*pfGetKeyFromRealSMC = false;
109
110	/*
111	* The extra data takes precedence (if non-zero).
112	*/
113	GetExtraDataBoth(pVirtualBox, pMachine, "VBoxInternal2/SmcDeviceKey", pStrKey);
114	if (pStrKey->isNotEmpty())
115	return VINF_SUCCESS;
116
117	#ifdef RT_OS_DARWIN
118
119	/*
120	* Work done in EFI/DevSmc
121	*/
122	*pfGetKeyFromRealSMC = true;
123	int vrc = VINF_SUCCESS;
124
125	#else
126	/*
127	* Is it apple hardware in bootcamp?
128	*/
129	/** @todo implement + test RTSYSDMISTR_MANUFACTURER on all hosts.
130	* Currently falling back on the product name. */
131	char szManufacturer[256];
132	szManufacturer[0] = '\0';
133	RTSystemQueryDmiString(RTSYSDMISTR_MANUFACTURER, szManufacturer, sizeof(szManufacturer));
134	if (szManufacturer[0] != '\0')
135	{
136	if ( !strcmp(szManufacturer, "Apple Computer, Inc.")
137	\|\| !strcmp(szManufacturer, "Apple Inc.")
138	)
139	*pfGetKeyFromRealSMC = true;
140	}
141	else
142	{
143	char szProdName[256];
144	szProdName[0] = '\0';
145	RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME, szProdName, sizeof(szProdName));
146	if ( ( !strncmp(szProdName, RT_STR_TUPLE("Mac"))
147	\|\| !strncmp(szProdName, RT_STR_TUPLE("iMac"))
148	\|\| !strncmp(szProdName, RT_STR_TUPLE("Xserve"))
149	)
150	&& !strchr(szProdName, ' ') /* no spaces */
151	&& RT_C_IS_DIGIT(szProdName[strlen(szProdName) - 1]) /* version number */
152	)
153	*pfGetKeyFromRealSMC = true;
154	}
155
156	int vrc = VINF_SUCCESS;
157	#endif
158
159	return vrc;
160	}
161
162
163	/*
164	* VC++ 8 / amd64 has some serious trouble with the next functions.
165	* As a temporary measure, we'll drop global optimizations.
166	*/
167	#if defined(_MSC_VER) && defined(RT_ARCH_AMD64)
168	# if _MSC_VER >= RT_MSC_VER_VC80 && _MSC_VER < RT_MSC_VER_VC100
169	# pragma optimize("g", off)
170	# endif
171	#endif
172
173	/** Helper that finds out the next HBA port used
174	*/
175	static LONG GetNextUsedPort(LONG aPortUsed[30], LONG lBaseVal, uint32_t u32Size)
176	{
177	LONG lNextPortUsed = 30;
178	for (size_t j = 0; j < u32Size; ++j)
179	{
180	if ( aPortUsed[j] > lBaseVal
181	&& aPortUsed[j] <= lNextPortUsed)
182	lNextPortUsed = aPortUsed[j];
183	}
184	return lNextPortUsed;
185	}
186
187	#define MAX_BIOS_LUN_COUNT 4
188
189	int Console::SetBiosDiskInfo(ComPtr<IMachine> pMachine, PCFGMNODE pCfg, PCFGMNODE pBiosCfg,
190	Bstr controllerName, const char * const s_apszBiosConfig[4])
191	{
192	RT_NOREF(pCfg);
193	HRESULT hrc;
194	#define MAX_DEVICES 30
195	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
196	#define VRC() AssertLogRelMsgReturn(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), vrc)
197
198	LONG lPortLUN[MAX_BIOS_LUN_COUNT];
199	LONG lPortUsed[MAX_DEVICES];
200	uint32_t u32HDCount = 0;
201
202	/* init to max value */
203	lPortLUN[0] = MAX_DEVICES;
204
205	com::SafeIfaceArray<IMediumAttachment> atts;
206	hrc = pMachine->GetMediumAttachmentsOfController(controllerName.raw(),
207	ComSafeArrayAsOutParam(atts)); H();
208	size_t uNumAttachments = atts.size();
209	if (uNumAttachments > MAX_DEVICES)
210	{
211	LogRel(("Number of Attachments > Max=%d.\n", uNumAttachments));
212	uNumAttachments = MAX_DEVICES;
213	}
214
215	/* Find the relevant ports/IDs, i.e the ones to which a HD is attached. */
216	for (size_t j = 0; j < uNumAttachments; ++j)
217	{
218	IMediumAttachment *pMediumAtt = atts[j];
219	LONG lPortNum = 0;
220	hrc = pMediumAtt->COMGETTER(Port)(&lPortNum); H();
221	if (SUCCEEDED(hrc))
222	{
223	DeviceType_T lType;
224	hrc = pMediumAtt->COMGETTER(Type)(&lType); H();
225	if (SUCCEEDED(hrc) && lType == DeviceType_HardDisk)
226	{
227	/* find min port number used for HD */
228	if (lPortNum < lPortLUN[0])
229	lPortLUN[0] = lPortNum;
230	lPortUsed[u32HDCount++] = lPortNum;
231	LogFlowFunc(("HD port Count=%d\n", u32HDCount));
232	}
233	}
234	}
235
236
237	/* Pick only the top 4 used HD Ports as CMOS doesn't have space
238	* to save details for all 30 ports
239	*/
240	uint32_t u32MaxPortCount = MAX_BIOS_LUN_COUNT;
241	if (u32HDCount < MAX_BIOS_LUN_COUNT)
242	u32MaxPortCount = u32HDCount;
243	for (size_t j = 1; j < u32MaxPortCount; j++)
244	lPortLUN[j] = GetNextUsedPort(lPortUsed, lPortLUN[j-1], u32HDCount);
245	if (pBiosCfg)
246	{
247	for (size_t j = 0; j < u32MaxPortCount; j++)
248	{
249	InsertConfigInteger(pBiosCfg, s_apszBiosConfig[j], lPortLUN[j]);
250	LogFlowFunc(("Top %d HBA ports = %s, %d\n", j, s_apszBiosConfig[j], lPortLUN[j]));
251	}
252	}
253	return VINF_SUCCESS;
254	}
255
256	#ifdef VBOX_WITH_PCI_PASSTHROUGH
257	HRESULT Console::i_attachRawPCIDevices(PUVM pUVM, BusAssignmentManager *pBusMgr, PCFGMNODE pDevices)
258	{
259	# ifndef VBOX_WITH_EXTPACK
260	RT_NOREF(pUVM);
261	# endif
262	HRESULT hrc = S_OK;
263	PCFGMNODE pInst, pCfg, pLunL0, pLunL1;
264
265	SafeIfaceArray<IPCIDeviceAttachment> assignments;
266	ComPtr<IMachine> aMachine = i_machine();
267
268	hrc = aMachine->COMGETTER(PCIDeviceAssignments)(ComSafeArrayAsOutParam(assignments));
269	if ( hrc != S_OK
270	\|\| assignments.size() < 1)
271	return hrc;
272
273	/*
274	* PCI passthrough is only available if the proper ExtPack is installed.
275	*
276	* Note. Configuring PCI passthrough here and providing messages about
277	* the missing extpack isn't exactly clean, but it is a necessary evil
278	* to patch over legacy compatability issues introduced by the new
279	* distribution model.
280	*/
281	# ifdef VBOX_WITH_EXTPACK
282	static const char *s_pszPCIRawExtPackName = "Oracle VM VirtualBox Extension Pack";
283	if (!mptrExtPackManager->i_isExtPackUsable(s_pszPCIRawExtPackName))
284	/* Always fatal! */
285	return pVMM->pfnVMR3SetError(pUVM, VERR_NOT_FOUND, RT_SRC_POS,
286	N_("Implementation of the PCI passthrough framework not found!\n"
287	"The VM cannot be started. To fix this problem, either "
288	"install the '%s' or disable PCI passthrough via VBoxManage"),
289	s_pszPCIRawExtPackName);
290	# endif
291
292	/* Now actually add devices */
293	PCFGMNODE pPCIDevs = NULL;
294
295	if (assignments.size() > 0)
296	{
297	InsertConfigNode(pDevices, "pciraw", &pPCIDevs);
298
299	PCFGMNODE pRoot = CFGMR3GetParent(pDevices); Assert(pRoot);
300
301	/* Tell PGM to tell GPCIRaw about guest mappings. */
302	CFGMR3InsertNode(pRoot, "PGM", NULL);
303	InsertConfigInteger(CFGMR3GetChild(pRoot, "PGM"), "PciPassThrough", 1);
304
305	/*
306	* Currently, using IOMMU needed for PCI passthrough
307	* requires RAM preallocation.
308	*/
309	/** @todo check if we can lift this requirement */
310	CFGMR3RemoveValue(pRoot, "RamPreAlloc");
311	InsertConfigInteger(pRoot, "RamPreAlloc", 1);
312	}
313
314	for (size_t iDev = 0; iDev < assignments.size(); iDev++)
315	{
316	ComPtr<IPCIDeviceAttachment> const assignment = assignments[iDev];
317
318	LONG host;
319	hrc = assignment->COMGETTER(HostAddress)(&host); H();
320	LONG guest;
321	hrc = assignment->COMGETTER(GuestAddress)(&guest); H();
322	Bstr bstrDevName;
323	hrc = assignment->COMGETTER(Name)(bstrDevName.asOutParam()); H();
324
325	InsertConfigNodeF(pPCIDevs, &pInst, "%d", iDev);
326	InsertConfigInteger(pInst, "Trusted", 1);
327
328	PCIBusAddress HostPCIAddress(host);
329	Assert(HostPCIAddress.valid());
330	InsertConfigNode(pInst, "Config", &pCfg);
331	InsertConfigString(pCfg, "DeviceName", bstrDevName);
332
333	InsertConfigInteger(pCfg, "DetachHostDriver", 1);
334	InsertConfigInteger(pCfg, "HostPCIBusNo", HostPCIAddress.miBus);
335	InsertConfigInteger(pCfg, "HostPCIDeviceNo", HostPCIAddress.miDevice);
336	InsertConfigInteger(pCfg, "HostPCIFunctionNo", HostPCIAddress.miFn);
337
338	PCIBusAddress GuestPCIAddress(guest);
339	Assert(GuestPCIAddress.valid());
340	hrc = pBusMgr->assignHostPCIDevice("pciraw", pInst, HostPCIAddress, GuestPCIAddress, true);
341	if (hrc != S_OK)
342	return hrc;
343
344	InsertConfigInteger(pCfg, "GuestPCIBusNo", GuestPCIAddress.miBus);
345	InsertConfigInteger(pCfg, "GuestPCIDeviceNo", GuestPCIAddress.miDevice);
346	InsertConfigInteger(pCfg, "GuestPCIFunctionNo", GuestPCIAddress.miFn);
347
348	/* the driver */
349	InsertConfigNode(pInst, "LUN#0", &pLunL0);
350	InsertConfigString(pLunL0, "Driver", "pciraw");
351	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
352
353	/* the Main driver */
354	InsertConfigString(pLunL1, "Driver", "MainPciRaw");
355	InsertConfigNode(pLunL1, "Config", &pCfg);
356	PCIRawDev *pMainDev = new PCIRawDev(this);
357	# error This is not allowed any more
358	InsertConfigInteger(pCfg, "Object", (uintptr_t)pMainDev);
359	}
360
361	return hrc;
362	}
363	#endif
364
365
366	/**
367	* Worker for configConstructor.
368	*
369	* @return VBox status code.
370	* @param pUVM The user mode VM handle.
371	* @param pVM The cross context VM handle.
372	* @param pVMM The VMM vtable.
373	* @param pAlock The automatic lock instance. This is for when we have
374	* to leave it in order to avoid deadlocks (ext packs and
375	* more).
376	*/
377	int Console::i_configConstructorX86(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
378	{
379	RT_NOREF(pVM /* when everything is disabled */);
380	ComPtr<IMachine> pMachine = i_machine();
381
382	int vrc;
383	HRESULT hrc;
384	Utf8Str strTmp;
385	Bstr bstr;
386
387	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
388
389	/*
390	* Get necessary objects and frequently used parameters.
391	*/
392	ComPtr<IVirtualBox> virtualBox;
393	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
394
395	ComPtr<IHost> host;
396	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
397
398	ComPtr<ISystemProperties> systemProperties;
399	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
400
401	ComPtr<IFirmwareSettings> firmwareSettings;
402	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
403
404	ComPtr<INvramStore> nvramStore;
405	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
406
407	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
408	RTUUID HardwareUuid;
409	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
410	AssertRCReturn(vrc, vrc);
411
412	ULONG cRamMBs;
413	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
414	#if 0 /* enable to play with lots of memory. */
415	if (RTEnvExist("VBOX_RAM_SIZE"))
416	cRamMBs = RTStrToUInt64(RTEnvGet("VBOX_RAM_SIZE"));
417	#endif
418	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
419	uint32_t cbRamHole = MM_RAM_HOLE_SIZE_DEFAULT;
420	uint64_t uMcfgBase = 0;
421	uint32_t cbMcfgLength = 0;
422
423	ParavirtProvider_T enmParavirtProvider;
424	hrc = pMachine->GetEffectiveParavirtProvider(&enmParavirtProvider); H();
425
426	Bstr strParavirtDebug;
427	hrc = pMachine->COMGETTER(ParavirtDebug)(strParavirtDebug.asOutParam()); H();
428
429	BOOL fIOAPIC;
430	uint32_t uIoApicPciAddress = NIL_PCIBDF;
431	hrc = firmwareSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC); H();
432
433	ComPtr<IPlatform> platform;
434	pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
435
436	ChipsetType_T chipsetType;
437	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
438	if (chipsetType == ChipsetType_ICH9)
439	{
440	/* We'd better have 0x10000000 region, to cover 256 buses but this put
441	* too much load on hypervisor heap. Linux 4.8 currently complains with
442	* ``acpi PNP0A03:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f]
443	* only partially covers this bridge'' */
444	cbMcfgLength = 0x4000000; //0x10000000;
445	cbRamHole += cbMcfgLength;
446	uMcfgBase = _4G - cbRamHole;
447	}
448
449	/* Get the CPU profile name. */
450	Bstr bstrCpuProfile;
451	hrc = pMachine->COMGETTER(CPUProfile)(bstrCpuProfile.asOutParam()); H();
452
453	/* Get the X86 platform object. */
454	ComPtr<IPlatformX86> platformX86;
455	hrc = platform->COMGETTER(X86)(platformX86.asOutParam()); H();
456
457	/* Check if long mode is enabled. */
458	BOOL fIsGuest64Bit;
459	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_LongMode, &fIsGuest64Bit); H();
460
461	/*
462	* Figure out the IOMMU config.
463	*/
464	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
465	IommuType_T enmIommuType;
466	hrc = platform->COMGETTER(IommuType)(&enmIommuType); H();
467
468	/* Resolve 'automatic' type to an Intel or AMD IOMMU based on the host CPU. */
469	if (enmIommuType == IommuType_Automatic)
470	{
471	if ( bstrCpuProfile.startsWith("AMD")
472	\|\| bstrCpuProfile.startsWith("Quad-Core AMD")
473	\|\| bstrCpuProfile.startsWith("Hygon"))
474	enmIommuType = IommuType_AMD;
475	else if (bstrCpuProfile.startsWith("Intel"))
476	{
477	if ( bstrCpuProfile.equals("Intel 8086")
478	\|\| bstrCpuProfile.equals("Intel 80186")
479	\|\| bstrCpuProfile.equals("Intel 80286")
480	\|\| bstrCpuProfile.equals("Intel 80386")
481	\|\| bstrCpuProfile.equals("Intel 80486"))
482	enmIommuType = IommuType_None;
483	else
484	enmIommuType = IommuType_Intel;
485	}
486	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
487	else if (ASMIsAmdCpu())
488	enmIommuType = IommuType_AMD;
489	else if (ASMIsIntelCpu())
490	enmIommuType = IommuType_Intel;
491	# endif
492	else
493	{
494	/** @todo Should we handle other CPUs like Shanghai, VIA etc. here? */
495	LogRel(("WARNING! Unrecognized CPU type, IOMMU disabled.\n"));
496	enmIommuType = IommuType_None;
497	}
498	}
499
500	if (enmIommuType == IommuType_AMD)
501	{
502	# ifdef VBOX_WITH_IOMMU_AMD
503	/*
504	* Reserve the specific PCI address of the "SB I/O APIC" when using
505	* an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
506	*/
507	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
508	# else
509	LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
510	enmIommuType = IommuType_None;
511	# endif
512	}
513
514	if (enmIommuType == IommuType_Intel)
515	{
516	# ifdef VBOX_WITH_IOMMU_INTEL
517	/*
518	* Reserve a unique PCI address for the I/O APIC when using
519	* an Intel IOMMU. For convenience we use the same address as
520	* we do on AMD, see @bugref{9967#c13}.
521	*/
522	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
523	# else
524	LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
525	enmIommuType = IommuType_None;
526	# endif
527	}
528
529	if ( enmIommuType == IommuType_AMD
530	\|\| enmIommuType == IommuType_Intel)
531	{
532	if (chipsetType != ChipsetType_ICH9)
533	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
534	N_("IOMMU uses MSIs which requires the ICH9 chipset implementation."));
535	if (!fIOAPIC)
536	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
537	N_("IOMMU requires an I/O APIC for remapping interrupts."));
538	}
539	#else
540	IommuType_T const enmIommuType = IommuType_None;
541	#endif
542
543	/* Instantiate the bus assignment manager. */
544	Assert(enmIommuType != IommuType_Automatic);
545	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, enmIommuType);
546
547	ULONG cCpus = 1;
548	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
549
550	ULONG ulCpuExecutionCap = 100;
551	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
552
553	LogRel(("Guest architecture: x86\n"));
554
555	Bstr osTypeId;
556	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
557	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
558
559	APICMode_T apicMode;
560	hrc = firmwareSettings->COMGETTER(APICMode)(&apicMode); H();
561	uint32_t uFwAPIC;
562	switch (apicMode)
563	{
564	case APICMode_Disabled:
565	uFwAPIC = 0;
566	break;
567	case APICMode_APIC:
568	uFwAPIC = 1;
569	break;
570	case APICMode_X2APIC:
571	uFwAPIC = 2;
572	break;
573	default:
574	AssertMsgFailed(("Invalid APICMode=%d\n", apicMode));
575	uFwAPIC = 1;
576	break;
577	}
578
579	ComPtr<IGuestOSType> pGuestOSType;
580	virtualBox->GetGuestOSType(osTypeId.raw(), pGuestOSType.asOutParam());
581
582	BOOL fOsXGuest = FALSE;
583	BOOL fWinGuest = FALSE;
584	BOOL fOs2Guest = FALSE;
585	BOOL fW9xGuest = FALSE;
586	BOOL fDosGuest = FALSE;
587	if (pGuestOSType.isNotNull())
588	{
589	Bstr guestTypeFamilyId;
590	hrc = pGuestOSType->COMGETTER(FamilyId)(guestTypeFamilyId.asOutParam()); H();
591	fOsXGuest = guestTypeFamilyId == Bstr("MacOS");
592	fWinGuest = guestTypeFamilyId == Bstr("Windows");
593	fOs2Guest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("OS2"));
594	fW9xGuest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("Windows9")); /* Does not include Windows Me. */
595	fDosGuest = osTypeId.equals(GUEST_OS_ID_STR_X86("DOS")) \|\| osTypeId.equals(GUEST_OS_ID_STR_X86("Windows31"));
596	}
597
598	ComPtr<IPlatformProperties> platformProperties;
599	virtualBox->GetPlatformProperties(PlatformArchitecture_x86, platformProperties.asOutParam());
600
601	/*
602	* Get root node first.
603	* This is the only node in the tree.
604	*/
605	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
606	Assert(pRoot);
607
608	// catching throws from InsertConfigString and friends.
609	try
610	{
611
612	/*
613	* Set the root (and VMM) level values.
614	*/
615	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
616	InsertConfigString(pRoot, "Name", bstr);
617	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
618	InsertConfigInteger(pRoot, "RamSize", cbRam);
619	InsertConfigInteger(pRoot, "RamHoleSize", cbRamHole);
620	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
621	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
622	InsertConfigInteger(pRoot, "TimerMillies", 10);
623
624	BOOL fPageFusion = FALSE;
625	hrc = pMachine->COMGETTER(PageFusionEnabled)(&fPageFusion); H();
626	InsertConfigInteger(pRoot, "PageFusionAllowed", fPageFusion); /* boolean */
627
628	/* Not necessary, but makes sure this setting ends up in the release log. */
629	ULONG ulBalloonSize = 0;
630	hrc = pMachine->COMGETTER(MemoryBalloonSize)(&ulBalloonSize); H();
631	InsertConfigInteger(pRoot, "MemBalloonSize", ulBalloonSize);
632
633	/*
634	* EM values (before CPUM as it may need to set IemExecutesAll).
635	*/
636	PCFGMNODE pEM;
637	InsertConfigNode(pRoot, "EM", &pEM);
638
639	/* Triple fault behavior. */
640	BOOL fTripleFaultReset = false;
641	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_TripleFaultReset, &fTripleFaultReset); H();
642	InsertConfigInteger(pEM, "TripleFaultReset", fTripleFaultReset);
643
644	/*
645	* CPUM values.
646	*/
647	PCFGMNODE pCPUM;
648	InsertConfigNode(pRoot, "CPUM", &pCPUM);
649	PCFGMNODE pIsaExts;
650	InsertConfigNode(pCPUM, "IsaExts", &pIsaExts);
651
652	/* Host CPUID leaf overrides. */
653	for (uint32_t iOrdinal = 0; iOrdinal < _4K; iOrdinal++)
654	{
655	ULONG uLeaf, uSubLeaf, uEax, uEbx, uEcx, uEdx;
656	hrc = platformX86->GetCPUIDLeafByOrdinal(iOrdinal, &uLeaf, &uSubLeaf, &uEax, &uEbx, &uEcx, &uEdx);
657	if (hrc == E_INVALIDARG)
658	break;
659	H();
660	PCFGMNODE pLeaf;
661	InsertConfigNode(pCPUM, Utf8StrFmt("HostCPUID/%RX32", uLeaf).c_str(), &pLeaf);
662	/** @todo Figure out how to tell the VMM about uSubLeaf */
663	InsertConfigInteger(pLeaf, "eax", uEax);
664	InsertConfigInteger(pLeaf, "ebx", uEbx);
665	InsertConfigInteger(pLeaf, "ecx", uEcx);
666	InsertConfigInteger(pLeaf, "edx", uEdx);
667	}
668
669	/* We must limit CPUID count for Windows NT 4, as otherwise it stops
670	with error 0x3e (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED). */
671	if (osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4"))
672	{
673	LogRel(("Limiting CPUID leaf count for NT4 guests\n"));
674	InsertConfigInteger(pCPUM, "NT4LeafLimit", true);
675	}
676
677	if (fOsXGuest)
678	{
679	/* Expose extended MWAIT features to Mac OS X guests. */
680	LogRel(("Using MWAIT extensions\n"));
681	InsertConfigInteger(pIsaExts, "MWaitExtensions", true);
682
683	/* Fake the CPU family/model so the guest works. This is partly
684	because older mac releases really doesn't work on newer cpus,
685	and partly because mac os x expects more from systems with newer
686	cpus (MSRs, power features, whatever). */
687	uint32_t uMaxIntelFamilyModelStep = UINT32_MAX;
688	if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS")
689	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS"))
690	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482. */
691	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS106")
692	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS106"))
693	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */
694	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS107")
695	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS107"))
696	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
697	what is required here. */
698	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS108")
699	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS108"))
700	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
701	what is required here. */
702	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS109")
703	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS109"))
704	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure
705	out what is required here. */
706	if (uMaxIntelFamilyModelStep != UINT32_MAX)
707	InsertConfigInteger(pCPUM, "MaxIntelFamilyModelStep", uMaxIntelFamilyModelStep);
708	}
709
710	/* CPU Portability level, */
711	ULONG uCpuIdPortabilityLevel = 0;
712	hrc = pMachine->COMGETTER(CPUIDPortabilityLevel)(&uCpuIdPortabilityLevel); H();
713	InsertConfigInteger(pCPUM, "PortableCpuIdLevel", uCpuIdPortabilityLevel);
714
715	/* Physical Address Extension (PAE) */
716	BOOL fEnablePAE = false;
717	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_PAE, &fEnablePAE); H();
718	fEnablePAE \|= fIsGuest64Bit;
719	InsertConfigInteger(pRoot, "EnablePAE", fEnablePAE);
720
721	/* 64-bit guests (long mode) */
722	InsertConfigInteger(pCPUM, "Enable64bit", fIsGuest64Bit);
723
724	/* APIC/X2APIC configuration */
725	BOOL fEnableAPIC = true;
726	BOOL fEnableX2APIC = true;
727	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_APIC, &fEnableAPIC); H();
728	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_X2APIC, &fEnableX2APIC); H();
729	if (fEnableX2APIC)
730	Assert(fEnableAPIC);
731
732	/* CPUM profile name. */
733	InsertConfigString(pCPUM, "GuestCpuName", bstrCpuProfile);
734
735	/*
736	* Temporary(?) hack to make sure we emulate the ancient 16-bit CPUs
737	* correctly. There are way too many #UDs we'll miss using VT-x,
738	* raw-mode or qemu for the 186 and 286, while we'll get undefined opcodes
739	* dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
740	*/
741	if ( bstrCpuProfile.equals("Intel 80386") /* just for now */
742	\|\| bstrCpuProfile.equals("Intel 80286")
743	\|\| bstrCpuProfile.equals("Intel 80186")
744	\|\| bstrCpuProfile.equals("Nec V20")
745	\|\| bstrCpuProfile.equals("Intel 8086") )
746	{
747	InsertConfigInteger(pEM, "IemExecutesAll", true);
748	if (!bstrCpuProfile.equals("Intel 80386"))
749	{
750	fEnableAPIC = false;
751	fIOAPIC = false;
752	}
753	fEnableX2APIC = false;
754	}
755
756	/* Adjust firmware APIC handling to stay within the VCPU limits. */
757	if (uFwAPIC == 2 && !fEnableX2APIC)
758	{
759	if (fEnableAPIC)
760	uFwAPIC = 1;
761	else
762	uFwAPIC = 0;
763	LogRel(("Limiting the firmware APIC level from x2APIC to %s\n", fEnableAPIC ? "APIC" : "Disabled"));
764	}
765	else if (uFwAPIC == 1 && !fEnableAPIC)
766	{
767	uFwAPIC = 0;
768	LogRel(("Limiting the firmware APIC level from APIC to Disabled\n"));
769	}
770
771	/* Speculation Control. */
772	BOOL fSpecCtrl = FALSE;
773	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrl, &fSpecCtrl); H();
774	InsertConfigInteger(pCPUM, "SpecCtrl", fSpecCtrl);
775
776	/* Nested VT-x / AMD-V. */
777	BOOL fNestedHWVirt = FALSE;
778	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_HWVirt, &fNestedHWVirt); H();
779	InsertConfigInteger(pCPUM, "NestedHWVirt", fNestedHWVirt ? true : false);
780
781	/*
782	* Hardware virtualization extensions.
783	*/
784	/* Sanitize valid/useful APIC combinations, see @bugref{8868}. */
785	if (!fEnableAPIC)
786	{
787	if (fIsGuest64Bit)
788	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
789	N_("Cannot disable the APIC for a 64-bit guest."));
790	if (cCpus > 1)
791	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
792	N_("Cannot disable the APIC for an SMP guest."));
793	if (fIOAPIC)
794	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
795	N_("Cannot disable the APIC when the I/O APIC is present."));
796	}
797
798	BOOL fHMEnabled;
799	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Enabled, &fHMEnabled); H();
800	if (cCpus > 1 && !fHMEnabled)
801	{
802	LogRel(("Forced fHMEnabled to TRUE by SMP guest.\n"));
803	fHMEnabled = TRUE;
804	}
805
806	BOOL fHMForced;
807	fHMEnabled = fHMForced = TRUE;
808	LogRel(("fHMForced=true - No raw-mode support in this build!\n"));
809	if (!fHMForced) /* No need to query if already forced above. */
810	{
811	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Force, &fHMForced); H();
812	if (fHMForced)
813	LogRel(("fHMForced=true - HWVirtExPropertyType_Force\n"));
814	}
815	InsertConfigInteger(pRoot, "HMEnabled", fHMEnabled);
816
817	/* /HM/xyz */
818	PCFGMNODE pHM;
819	InsertConfigNode(pRoot, "HM", &pHM);
820	InsertConfigInteger(pHM, "HMForced", fHMForced);
821	if (fHMEnabled)
822	{
823	/* Indicate whether 64-bit guests are supported or not. */
824	InsertConfigInteger(pHM, "64bitEnabled", fIsGuest64Bit);
825
826	/** @todo Not exactly pretty to check strings; VBOXOSTYPE would be better,
827	but that requires quite a bit of API change in Main. */
828	if ( fIOAPIC
829	&& ( osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4")
830	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2000")
831	\|\| osTypeId == GUEST_OS_ID_STR_X86("WindowsXP")
832	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2003")))
833	{
834	/* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
835	* We may want to consider adding more guest OSes (Solaris) later on.
836	*/
837	InsertConfigInteger(pHM, "TPRPatchingEnabled", 1);
838	}
839	}
840
841	/* HWVirtEx exclusive mode */
842	BOOL fHMExclusive = true;
843	hrc = platformProperties->COMGETTER(ExclusiveHwVirt)(&fHMExclusive); H();
844	InsertConfigInteger(pHM, "Exclusive", fHMExclusive);
845
846	/* Nested paging (VT-x/AMD-V) */
847	BOOL fEnableNestedPaging = false;
848	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_NestedPaging, &fEnableNestedPaging); H();
849	InsertConfigInteger(pHM, "EnableNestedPaging", fEnableNestedPaging);
850
851	/* Large pages; requires nested paging */
852	BOOL fEnableLargePages = false;
853	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_LargePages, &fEnableLargePages); H();
854	InsertConfigInteger(pHM, "EnableLargePages", fEnableLargePages);
855
856	/* VPID (VT-x) */
857	BOOL fEnableVPID = false;
858	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_VPID, &fEnableVPID); H();
859	InsertConfigInteger(pHM, "EnableVPID", fEnableVPID);
860
861	/* Unrestricted execution aka UX (VT-x) */
862	BOOL fEnableUX = false;
863	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UnrestrictedExecution, &fEnableUX); H();
864	InsertConfigInteger(pHM, "EnableUX", fEnableUX);
865
866	/* Virtualized VMSAVE/VMLOAD (AMD-V) */
867	BOOL fVirtVmsaveVmload = true;
868	hrc = host->GetProcessorFeature(ProcessorFeature_VirtVmsaveVmload, &fVirtVmsaveVmload); H();
869	InsertConfigInteger(pHM, "SvmVirtVmsaveVmload", fVirtVmsaveVmload);
870
871	/* Indirect branch prediction boundraries. */
872	BOOL fIBPBOnVMExit = false;
873	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMExit, &fIBPBOnVMExit); H();
874	InsertConfigInteger(pHM, "IBPBOnVMExit", fIBPBOnVMExit);
875
876	BOOL fIBPBOnVMEntry = false;
877	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMEntry, &fIBPBOnVMEntry); H();
878	InsertConfigInteger(pHM, "IBPBOnVMEntry", fIBPBOnVMEntry);
879
880	BOOL fSpecCtrlByHost = false;
881	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrlByHost, &fSpecCtrlByHost); H();
882	InsertConfigInteger(pHM, "SpecCtrlByHost", fSpecCtrlByHost);
883
884	BOOL fL1DFlushOnSched = true;
885	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnEMTScheduling, &fL1DFlushOnSched); H();
886	InsertConfigInteger(pHM, "L1DFlushOnSched", fL1DFlushOnSched);
887
888	BOOL fL1DFlushOnVMEntry = false;
889	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
890	InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
891
892	BOOL fMDSClearOnSched = true;
893	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
894	InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
895
896	BOOL fMDSClearOnVMEntry = false;
897	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
898	InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
899
900	/* Reset overwrite. */
901	mfTurnResetIntoPowerOff = GetExtraDataBoth(virtualBox, pMachine,
902	"VBoxInternal2/TurnResetIntoPowerOff", &strTmp)->equals("1");
903	if (mfTurnResetIntoPowerOff)
904	InsertConfigInteger(pRoot, "PowerOffInsteadOfReset", 1);
905
906	/* Use NEM rather than HM. */
907	BOOL fUseNativeApi = false;
908	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UseNativeApi, &fUseNativeApi); H();
909	InsertConfigInteger(pHM, "UseNEMInstead", fUseNativeApi);
910
911	/* Enable workaround for missing TLB flush for OS/2 guests, see ticketref:20625. */
912	if (fOs2Guest)
913	InsertConfigInteger(pHM, "MissingOS2TlbFlushWorkaround", 1);
914
915	/*
916	* NEM
917	*/
918	PCFGMNODE pNEM;
919	InsertConfigNode(pRoot, "NEM", &pNEM);
920	InsertConfigInteger(pNEM, "Allow64BitGuests", fIsGuest64Bit);
921
922	/*
923	* Paravirt. provider.
924	*/
925	PCFGMNODE pParavirtNode;
926	InsertConfigNode(pRoot, "GIM", &pParavirtNode);
927	const char *pcszParavirtProvider;
928	bool fGimDeviceNeeded = true;
929	switch (enmParavirtProvider)
930	{
931	case ParavirtProvider_None:
932	pcszParavirtProvider = "None";
933	fGimDeviceNeeded = false;
934	break;
935
936	case ParavirtProvider_Minimal:
937	pcszParavirtProvider = "Minimal";
938	break;
939
940	case ParavirtProvider_HyperV:
941	pcszParavirtProvider = "HyperV";
942	break;
943
944	case ParavirtProvider_KVM:
945	pcszParavirtProvider = "KVM";
946	break;
947
948	default:
949	AssertMsgFailed(("Invalid enmParavirtProvider=%d\n", enmParavirtProvider));
950	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, N_("Invalid paravirt. provider '%d'"),
951	enmParavirtProvider);
952	}
953	InsertConfigString(pParavirtNode, "Provider", pcszParavirtProvider);
954
955	/*
956	* Parse paravirt. debug options.
957	*/
958	bool fGimDebug = false;
959	com::Utf8Str strGimDebugAddress = "127.0.0.1";
960	uint32_t uGimDebugPort = 50000;
961	if (strParavirtDebug.isNotEmpty())
962	{
963	/* Hyper-V debug options. */
964	if (enmParavirtProvider == ParavirtProvider_HyperV)
965	{
966	bool fGimHvDebug = false;
967	com::Utf8Str strGimHvVendor;
968	bool fGimHvVsIf = false;
969	bool fGimHvHypercallIf = false;
970
971	size_t uPos = 0;
972	com::Utf8Str strDebugOptions = strParavirtDebug;
973	com::Utf8Str strKey;
974	com::Utf8Str strVal;
975	while ((uPos = strDebugOptions.parseKeyValue(strKey, strVal, uPos)) != com::Utf8Str::npos)
976	{
977	if (strKey == "enabled")
978	{
979	if (strVal.toUInt32() == 1)
980	{
981	/* Apply defaults.
982	The defaults are documented in the user manual,
983	changes need to be reflected accordingly. */
984	fGimHvDebug = true;
985	strGimHvVendor = "Microsoft Hv";
986	fGimHvVsIf = true;
987	fGimHvHypercallIf = false;
988	}
989	/* else: ignore, i.e. don't assert below with 'enabled=0'. */
990	}
991	else if (strKey == "address")
992	strGimDebugAddress = strVal;
993	else if (strKey == "port")
994	uGimDebugPort = strVal.toUInt32();
995	else if (strKey == "vendor")
996	strGimHvVendor = strVal;
997	else if (strKey == "vsinterface")
998	fGimHvVsIf = RT_BOOL(strVal.toUInt32());
999	else if (strKey == "hypercallinterface")
1000	fGimHvHypercallIf = RT_BOOL(strVal.toUInt32());
1001	else
1002	{
1003	AssertMsgFailed(("Unrecognized Hyper-V debug option '%s'\n", strKey.c_str()));
1004	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1005	N_("Unrecognized Hyper-V debug option '%s' in '%s'"), strKey.c_str(),
1006	strDebugOptions.c_str());
1007	}
1008	}
1009
1010	/* Update HyperV CFGM node with active debug options. */
1011	if (fGimHvDebug)
1012	{
1013	PCFGMNODE pHvNode;
1014	InsertConfigNode(pParavirtNode, "HyperV", &pHvNode);
1015	InsertConfigString(pHvNode, "VendorID", strGimHvVendor);
1016	InsertConfigInteger(pHvNode, "VSInterface", fGimHvVsIf ? 1 : 0);
1017	InsertConfigInteger(pHvNode, "HypercallDebugInterface", fGimHvHypercallIf ? 1 : 0);
1018	fGimDebug = true;
1019	}
1020	}
1021	}
1022
1023	/*
1024	* Guest Compatibility Manager.
1025	*/
1026	PCFGMNODE pGcmNode;
1027	uint32_t u32FixerSet = 0;
1028	InsertConfigNode(pRoot, "GCM", &pGcmNode);
1029	/* OS/2 and Win9x guests can run DOS apps so they get
1030	* the DOS specific fixes as well.
1031	*/
1032	if (fOs2Guest)
1033	u32FixerSet = GCMFIXER_DBZ_DOS \| GCMFIXER_DBZ_OS2;
1034	else if (fW9xGuest)
1035	u32FixerSet = GCMFIXER_DBZ_DOS \| GCMFIXER_DBZ_WIN9X;
1036	else if (fDosGuest)
1037	u32FixerSet = GCMFIXER_DBZ_DOS;
1038	InsertConfigInteger(pGcmNode, "FixerSet", u32FixerSet);
1039
1040
1041	/*
1042	* MM values.
1043	*/
1044	PCFGMNODE pMM;
1045	InsertConfigNode(pRoot, "MM", &pMM);
1046	InsertConfigInteger(pMM, "CanUseLargerHeap", chipsetType == ChipsetType_ICH9);
1047
1048	/*
1049	* PDM config.
1050	* Load drivers in VBoxC.[so\|dll]
1051	*/
1052	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
1053
1054	/*
1055	* Devices
1056	*/
1057	PCFGMNODE pDevices = NULL; /* /Devices */
1058	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
1059	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
1060	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
1061	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
1062	PCFGMNODE pLunL1 = NULL; /* /Devices/Dev/0/LUN#0/AttachedDriver/ */
1063	PCFGMNODE pBiosCfg = NULL; /* /Devices/pcbios/0/Config/ */
1064	PCFGMNODE pNetBootCfg = NULL; /* /Devices/pcbios/0/Config/NetBoot/ */
1065
1066	InsertConfigNode(pRoot, "Devices", &pDevices);
1067
1068	/*
1069	* GIM Device
1070	*/
1071	if (fGimDeviceNeeded)
1072	{
1073	InsertConfigNode(pDevices, "GIMDev", &pDev);
1074	InsertConfigNode(pDev, "0", &pInst);
1075	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1076	//InsertConfigNode(pInst, "Config", &pCfg);
1077
1078	if (fGimDebug)
1079	{
1080	InsertConfigNode(pInst, "LUN#998", &pLunL0);
1081	InsertConfigString(pLunL0, "Driver", "UDP");
1082	InsertConfigNode(pLunL0, "Config", &pLunL1);
1083	InsertConfigString(pLunL1, "ServerAddress", strGimDebugAddress);
1084	InsertConfigInteger(pLunL1, "ServerPort", uGimDebugPort);
1085	}
1086	}
1087
1088	/*
1089	* PC Arch.
1090	*/
1091	InsertConfigNode(pDevices, "pcarch", &pDev);
1092	InsertConfigNode(pDev, "0", &pInst);
1093	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1094	InsertConfigNode(pInst, "Config", &pCfg);
1095
1096	/*
1097	* The time offset
1098	*/
1099	LONG64 timeOffset;
1100	hrc = firmwareSettings->COMGETTER(TimeOffset)(&timeOffset); H();
1101	PCFGMNODE pTMNode;
1102	InsertConfigNode(pRoot, "TM", &pTMNode);
1103	InsertConfigInteger(pTMNode, "UTCOffset", timeOffset * 1000000);
1104
1105	/*
1106	* DMA
1107	*/
1108	InsertConfigNode(pDevices, "8237A", &pDev);
1109	InsertConfigNode(pDev, "0", &pInst);
1110	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1111
1112	/*
1113	* PCI buses.
1114	*/
1115	uint32_t uIocPCIAddress, uHbcPCIAddress;
1116	switch (chipsetType)
1117	{
1118	default:
1119	AssertFailed();
1120	RT_FALL_THRU();
1121	case ChipsetType_PIIX3:
1122	/* Create the base for adding bridges on demand */
1123	InsertConfigNode(pDevices, "pcibridge", NULL);
1124
1125	InsertConfigNode(pDevices, "pci", &pDev);
1126	uHbcPCIAddress = (0x0 << 16) \| 0;
1127	uIocPCIAddress = (0x1 << 16) \| 0; // ISA controller
1128	break;
1129	case ChipsetType_ICH9:
1130	/* Create the base for adding bridges on demand */
1131	InsertConfigNode(pDevices, "ich9pcibridge", NULL);
1132
1133	InsertConfigNode(pDevices, "ich9pci", &pDev);
1134	uHbcPCIAddress = (0x1e << 16) \| 0;
1135	uIocPCIAddress = (0x1f << 16) \| 0; // LPC controller
1136	break;
1137	}
1138	InsertConfigNode(pDev, "0", &pInst);
1139	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1140	InsertConfigNode(pInst, "Config", &pCfg);
1141	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1142	if (chipsetType == ChipsetType_ICH9)
1143	{
1144	/* Provide MCFG info */
1145	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1146	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1147
1148	#ifdef VBOX_WITH_PCI_PASSTHROUGH
1149	/* Add PCI passthrough devices */
1150	hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices); H();
1151	#endif
1152
1153	if (enmIommuType == IommuType_AMD)
1154	{
1155	/* AMD IOMMU. */
1156	InsertConfigNode(pDevices, "iommu-amd", &pDev);
1157	InsertConfigNode(pDev, "0", &pInst);
1158	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1159	InsertConfigNode(pInst, "Config", &pCfg);
1160	hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst); H();
1161
1162	/* The AMD IOMMU device needs to know which PCI slot it's in, see @bugref{9654#c104}. */
1163	{
1164	PCIBusAddress Address;
1165	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1166	{
1167	uint32_t const u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1168	InsertConfigInteger(pCfg, "PCIAddress", u32IommuAddress);
1169	}
1170	else
1171	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1172	N_("Failed to find PCI address of the assigned IOMMU device!"));
1173	}
1174
1175	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1176	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1177	}
1178	else if (enmIommuType == IommuType_Intel)
1179	{
1180	/* Intel IOMMU. */
1181	InsertConfigNode(pDevices, "iommu-intel", &pDev);
1182	InsertConfigNode(pDev, "0", &pInst);
1183	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1184	InsertConfigNode(pInst, "Config", &pCfg);
1185	hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst); H();
1186
1187	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1188	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1189	}
1190	}
1191
1192	/*
1193	* Enable the following devices: HPET, SMC and LPC on MacOS X guests or on ICH9 chipset
1194	*/
1195
1196	/*
1197	* High Precision Event Timer (HPET)
1198	*/
1199	BOOL fHPETEnabled;
1200	/* Other guests may wish to use HPET too, but MacOS X not functional without it */
1201	hrc = platformX86->COMGETTER(HPETEnabled)(&fHPETEnabled); H();
1202	/* so always enable HPET in extended profile */
1203	fHPETEnabled \|= fOsXGuest;
1204	/* HPET is always present on ICH9 */
1205	fHPETEnabled \|= (chipsetType == ChipsetType_ICH9);
1206	if (fHPETEnabled)
1207	{
1208	InsertConfigNode(pDevices, "hpet", &pDev);
1209	InsertConfigNode(pDev, "0", &pInst);
1210	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1211	InsertConfigNode(pInst, "Config", &pCfg);
1212	InsertConfigInteger(pCfg, "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0); /* boolean */
1213	}
1214
1215	/*
1216	* System Management Controller (SMC)
1217	*/
1218	BOOL fSmcEnabled;
1219	fSmcEnabled = fOsXGuest;
1220	if (fSmcEnabled)
1221	{
1222	InsertConfigNode(pDevices, "smc", &pDev);
1223	InsertConfigNode(pDev, "0", &pInst);
1224	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1225	InsertConfigNode(pInst, "Config", &pCfg);
1226
1227	bool fGetKeyFromRealSMC;
1228	Utf8Str strKey;
1229	vrc = getSmcDeviceKey(virtualBox, pMachine, &strKey, &fGetKeyFromRealSMC);
1230	AssertRCReturn(vrc, vrc);
1231
1232	if (!fGetKeyFromRealSMC)
1233	InsertConfigString(pCfg, "DeviceKey", strKey);
1234	InsertConfigInteger(pCfg, "GetKeyFromRealSMC", fGetKeyFromRealSMC);
1235	}
1236
1237	/*
1238	* Low Pin Count (LPC) bus
1239	*/
1240	BOOL fLpcEnabled;
1241	/** @todo implement appropriate getter */
1242	fLpcEnabled = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1243	if (fLpcEnabled)
1244	{
1245	InsertConfigNode(pDevices, "lpc", &pDev);
1246	InsertConfigNode(pDev, "0", &pInst);
1247	hrc = pBusMgr->assignPCIDevice("lpc", pInst); H();
1248	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1249	}
1250
1251	BOOL fShowRtc;
1252	fShowRtc = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1253
1254	/*
1255	* PS/2 keyboard & mouse.
1256	*/
1257	InsertConfigNode(pDevices, "pckbd", &pDev);
1258	InsertConfigNode(pDev, "0", &pInst);
1259	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1260	InsertConfigNode(pInst, "Config", &pCfg);
1261
1262	KeyboardHIDType_T aKbdHID;
1263	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
1264	if (aKbdHID != KeyboardHIDType_None)
1265	{
1266	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1267	InsertConfigString(pLunL0, "Driver", "KeyboardQueue");
1268	InsertConfigNode(pLunL0, "Config", &pCfg);
1269	InsertConfigInteger(pCfg, "QueueSize", 64);
1270
1271	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1272	InsertConfigString(pLunL1, "Driver", "MainKeyboard");
1273	}
1274
1275	PointingHIDType_T aPointingHID;
1276	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
1277	if (aPointingHID != PointingHIDType_None)
1278	{
1279	InsertConfigNode(pInst, "LUN#1", &pLunL0);
1280	InsertConfigString(pLunL0, "Driver", "MouseQueue");
1281	InsertConfigNode(pLunL0, "Config", &pCfg);
1282	InsertConfigInteger(pCfg, "QueueSize", 128);
1283
1284	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1285	InsertConfigString(pLunL1, "Driver", "MainMouse");
1286	}
1287
1288	/*
1289	* i8254 Programmable Interval Timer And Dummy Speaker
1290	*/
1291	InsertConfigNode(pDevices, "i8254", &pDev);
1292	InsertConfigNode(pDev, "0", &pInst);
1293	InsertConfigNode(pInst, "Config", &pCfg);
1294	#ifdef DEBUG
1295	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1296	#endif
1297
1298	/*
1299	* i8259 Programmable Interrupt Controller.
1300	*/
1301	InsertConfigNode(pDevices, "i8259", &pDev);
1302	InsertConfigNode(pDev, "0", &pInst);
1303	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1304	InsertConfigNode(pInst, "Config", &pCfg);
1305
1306	/*
1307	* Advanced Programmable Interrupt Controller.
1308	* SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
1309	* thus only single insert
1310	*/
1311	if (fEnableAPIC)
1312	{
1313	InsertConfigNode(pDevices, "apic", &pDev);
1314	InsertConfigNode(pDev, "0", &pInst);
1315	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1316	InsertConfigNode(pInst, "Config", &pCfg);
1317	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1318	PDMAPICMODE enmAPICMode = PDMAPICMODE_APIC;
1319	if (fEnableX2APIC)
1320	enmAPICMode = PDMAPICMODE_X2APIC;
1321	else if (!fEnableAPIC)
1322	enmAPICMode = PDMAPICMODE_NONE;
1323	InsertConfigInteger(pCfg, "Mode", enmAPICMode);
1324	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1325
1326	if (fIOAPIC)
1327	{
1328	/*
1329	* I/O Advanced Programmable Interrupt Controller.
1330	*/
1331	InsertConfigNode(pDevices, "ioapic", &pDev);
1332	InsertConfigNode(pDev, "0", &pInst);
1333	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1334	InsertConfigNode(pInst, "Config", &pCfg);
1335	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1336	if (enmIommuType == IommuType_AMD)
1337	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1338	else if (enmIommuType == IommuType_Intel)
1339	{
1340	InsertConfigString(pCfg, "ChipType", "DMAR");
1341	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1342	}
1343	}
1344	}
1345
1346	/*
1347	* RTC MC146818.
1348	*/
1349	InsertConfigNode(pDevices, "mc146818", &pDev);
1350	InsertConfigNode(pDev, "0", &pInst);
1351	InsertConfigNode(pInst, "Config", &pCfg);
1352	BOOL fRTCUseUTC;
1353	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
1354	InsertConfigInteger(pCfg, "UseUTC", fRTCUseUTC ? 1 : 0);
1355
1356	/*
1357	* VGA.
1358	*/
1359	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
1360	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
1361	GraphicsControllerType_T enmGraphicsController;
1362	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
1363	switch (enmGraphicsController)
1364	{
1365	case GraphicsControllerType_Null:
1366	break;
1367	#ifdef VBOX_WITH_VMSVGA
1368	case GraphicsControllerType_VMSVGA:
1369	InsertConfigInteger(pHM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1370	InsertConfigInteger(pNEM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1371	RT_FALL_THROUGH();
1372	case GraphicsControllerType_VBoxSVGA:
1373	#endif
1374	case GraphicsControllerType_VBoxVGA:
1375	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine, pGraphicsAdapter, firmwareSettings);
1376	if (FAILED(vrc))
1377	return vrc;
1378	break;
1379	default:
1380	AssertMsgFailed(("Invalid graphicsController=%d\n", enmGraphicsController));
1381	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1382	N_("Invalid graphics controller type '%d'"), enmGraphicsController);
1383	}
1384
1385	/*
1386	* Firmware.
1387	*/
1388	FirmwareType_T eFwType = FirmwareType_BIOS;
1389	hrc = firmwareSettings->COMGETTER(FirmwareType)(&eFwType); H();
1390
1391	#ifdef VBOX_WITH_EFI
1392	BOOL fEfiEnabled = (eFwType >= FirmwareType_EFI) && (eFwType <= FirmwareType_EFIDUAL);
1393	#else
1394	BOOL fEfiEnabled = false;
1395	#endif
1396	if (!fEfiEnabled)
1397	{
1398	/*
1399	* PC Bios.
1400	*/
1401	InsertConfigNode(pDevices, "pcbios", &pDev);
1402	InsertConfigNode(pDev, "0", &pInst);
1403	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1404	InsertConfigNode(pInst, "Config", &pBiosCfg);
1405	InsertConfigInteger(pBiosCfg, "NumCPUs", cCpus);
1406	InsertConfigString(pBiosCfg, "HardDiskDevice", "piix3ide");
1407	InsertConfigString(pBiosCfg, "FloppyDevice", "i82078");
1408	InsertConfigInteger(pBiosCfg, "IOAPIC", fIOAPIC);
1409	InsertConfigInteger(pBiosCfg, "APIC", uFwAPIC);
1410	BOOL fPXEDebug;
1411	hrc = firmwareSettings->COMGETTER(PXEDebugEnabled)(&fPXEDebug); H();
1412	InsertConfigInteger(pBiosCfg, "PXEDebug", fPXEDebug);
1413	InsertConfigBytes(pBiosCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1414	BOOL fUuidLe;
1415	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1416	InsertConfigInteger(pBiosCfg, "UuidLe", fUuidLe);
1417	BOOL fAutoSerialNumGen;
1418	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1419	if (fAutoSerialNumGen)
1420	InsertConfigString(pBiosCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1421	InsertConfigNode(pBiosCfg, "NetBoot", &pNetBootCfg);
1422	InsertConfigInteger(pBiosCfg, "McfgBase", uMcfgBase);
1423	InsertConfigInteger(pBiosCfg, "McfgLength", cbMcfgLength);
1424
1425	AssertMsgReturn(SchemaDefs::MaxBootPosition <= 9, ("Too many boot devices %d\n", SchemaDefs::MaxBootPosition),
1426	VERR_INVALID_PARAMETER);
1427
1428	for (ULONG pos = 1; pos <= SchemaDefs::MaxBootPosition; ++pos)
1429	{
1430	DeviceType_T enmBootDevice;
1431	hrc = pMachine->GetBootOrder(pos, &enmBootDevice); H();
1432
1433	char szParamName[] = "BootDeviceX";
1434	szParamName[sizeof(szParamName) - 2] = (char)(pos - 1 + '0');
1435
1436	const char *pszBootDevice;
1437	switch (enmBootDevice)
1438	{
1439	case DeviceType_Null:
1440	pszBootDevice = "NONE";
1441	break;
1442	case DeviceType_HardDisk:
1443	pszBootDevice = "IDE";
1444	break;
1445	case DeviceType_DVD:
1446	pszBootDevice = "DVD";
1447	break;
1448	case DeviceType_Floppy:
1449	pszBootDevice = "FLOPPY";
1450	break;
1451	case DeviceType_Network:
1452	pszBootDevice = "LAN";
1453	break;
1454	default:
1455	AssertMsgFailed(("Invalid enmBootDevice=%d\n", enmBootDevice));
1456	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1457	N_("Invalid boot device '%d'"), enmBootDevice);
1458	}
1459	InsertConfigString(pBiosCfg, szParamName, pszBootDevice);
1460	}
1461
1462	/** @todo @bugref{7145}: We might want to enable this by default for new VMs. For now,
1463	* this is required for Windows 2012 guests. */
1464	if (osTypeId == GUEST_OS_ID_STR_X64("Windows2012"))
1465	InsertConfigInteger(pBiosCfg, "DmiExposeMemoryTable", 1); /* boolean */
1466	}
1467	else
1468	{
1469	/* Autodetect firmware type, basing on guest type */
1470	if (eFwType == FirmwareType_EFI)
1471	eFwType = fIsGuest64Bit ? FirmwareType_EFI64 : FirmwareType_EFI32;
1472	bool const f64BitEntry = eFwType == FirmwareType_EFI64;
1473
1474	Assert(eFwType == FirmwareType_EFI64 \|\| eFwType == FirmwareType_EFI32 \|\| eFwType == FirmwareType_EFIDUAL);
1475	#ifdef VBOX_WITH_EFI_IN_DD2
1476	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "VBoxEFIDual.fd"
1477	: eFwType == FirmwareType_EFI32 ? "VBoxEFI32.fd"
1478	: "VBoxEFI64.fd";
1479	#else
1480	Utf8Str efiRomFile;
1481	vrc = findEfiRom(virtualBox, PlatformArchitecture_x86, eFwType, &efiRomFile);
1482	AssertRCReturn(vrc, vrc);
1483	const char *pszEfiRomFile = efiRomFile.c_str();
1484	#endif
1485
1486	/* Get boot args */
1487	Utf8Str bootArgs;
1488	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiBootArgs", &bootArgs);
1489
1490	/* Get device props */
1491	Utf8Str deviceProps;
1492	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiDeviceProps", &deviceProps);
1493
1494	/* Get NVRAM file name */
1495	Utf8Str strNvram = mptrNvramStore->i_getNonVolatileStorageFile();
1496
1497	BOOL fUuidLe;
1498	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1499
1500	BOOL fAutoSerialNumGen;
1501	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1502
1503	/* Get graphics mode settings */
1504	uint32_t u32GraphicsMode = UINT32_MAX;
1505	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsMode", &strTmp);
1506	if (strTmp.isEmpty())
1507	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGopMode", &strTmp);
1508	if (!strTmp.isEmpty())
1509	u32GraphicsMode = strTmp.toUInt32();
1510
1511	/* Get graphics resolution settings, with some sanity checking */
1512	Utf8Str strResolution;
1513	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsResolution", &strResolution);
1514	if (!strResolution.isEmpty())
1515	{
1516	size_t pos = strResolution.find("x");
1517	if (pos != strResolution.npos)
1518	{
1519	Utf8Str strH, strV;
1520	strH.assignEx(strResolution, 0, pos);
1521	strV.assignEx(strResolution, pos+1, strResolution.length()-pos-1);
1522	uint32_t u32H = strH.toUInt32();
1523	uint32_t u32V = strV.toUInt32();
1524	if (u32H == 0 \|\| u32V == 0)
1525	strResolution.setNull();
1526	}
1527	else
1528	strResolution.setNull();
1529	}
1530	else
1531	{
1532	uint32_t u32H = 0;
1533	uint32_t u32V = 0;
1534	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiHorizontalResolution", &strTmp);
1535	if (strTmp.isEmpty())
1536	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaHorizontalResolution", &strTmp);
1537	if (!strTmp.isEmpty())
1538	u32H = strTmp.toUInt32();
1539
1540	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiVerticalResolution", &strTmp);
1541	if (strTmp.isEmpty())
1542	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaVerticalResolution", &strTmp);
1543	if (!strTmp.isEmpty())
1544	u32V = strTmp.toUInt32();
1545	if (u32H != 0 && u32V != 0)
1546	strResolution = Utf8StrFmt("%ux%u", u32H, u32V);
1547	}
1548
1549	/*
1550	* EFI subtree.
1551	*/
1552	InsertConfigNode(pDevices, "efi", &pDev);
1553	InsertConfigNode(pDev, "0", &pInst);
1554	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1555	InsertConfigNode(pInst, "Config", &pCfg);
1556	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1557	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1558	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1559	InsertConfigString(pCfg, "EfiRom", pszEfiRomFile);
1560	InsertConfigString(pCfg, "BootArgs", bootArgs);
1561	InsertConfigString(pCfg, "DeviceProps", deviceProps);
1562	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1563	InsertConfigInteger(pCfg, "APIC", uFwAPIC);
1564	InsertConfigBytes(pCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1565	InsertConfigInteger(pCfg, "UuidLe", fUuidLe);
1566	if (fAutoSerialNumGen)
1567	InsertConfigString(pCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1568	InsertConfigInteger(pCfg, "64BitEntry", f64BitEntry); /* boolean */
1569	InsertConfigString(pCfg, "NvramFile", strNvram);
1570	if (u32GraphicsMode != UINT32_MAX)
1571	InsertConfigInteger(pCfg, "GraphicsMode", u32GraphicsMode);
1572	if (!strResolution.isEmpty())
1573	InsertConfigString(pCfg, "GraphicsResolution", strResolution);
1574
1575	/* For OS X guests we'll force passing host's DMI info to the guest */
1576	if (fOsXGuest)
1577	{
1578	InsertConfigInteger(pCfg, "DmiUseHostInfo", 1);
1579	InsertConfigInteger(pCfg, "DmiExposeMemoryTable", 1);
1580	}
1581
1582	/* Attach the NVRAM storage driver. */
1583	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1584	InsertConfigString(pLunL0, "Driver", "NvramStore");
1585	}
1586
1587	/*
1588	* The USB Controllers.
1589	*/
1590	PCFGMNODE pUsbDevices = NULL;
1591	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, aKbdHID, aPointingHID, &pUsbDevices);
1592
1593	/*
1594	* Storage controllers.
1595	*/
1596	bool fFdcEnabled = false;
1597	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
1598	pDevices, pUsbDevices, pBiosCfg, &fFdcEnabled); VRC();
1599
1600	/*
1601	* Network adapters
1602	*/
1603	std::list<BootNic> llBootNics;
1604	vrc = i_configNetworkCtrls(pMachine, platformProperties, chipsetType, pBusMgr,
1605	pVMM, pUVM, pDevices, llBootNics); VRC();
1606
1607	/*
1608	* Build network boot information and transfer it to the BIOS.
1609	*/
1610	if (pNetBootCfg && !llBootNics.empty()) /* NetBoot node doesn't exist for EFI! */
1611	{
1612	llBootNics.sort(); /* Sort the list by boot priority. */
1613
1614	char achBootIdx[] = "0";
1615	unsigned uBootIdx = 0;
1616
1617	for (std::list<BootNic>::iterator it = llBootNics.begin(); it != llBootNics.end(); ++it)
1618	{
1619	/* A NIC with priority 0 is only used if it's first in the list. */
1620	if (it->mBootPrio == 0 && uBootIdx != 0)
1621	break;
1622
1623	PCFGMNODE pNetBtDevCfg;
1624	achBootIdx[0] = (char)('0' + uBootIdx++); /* Boot device order. */
1625	InsertConfigNode(pNetBootCfg, achBootIdx, &pNetBtDevCfg);
1626	InsertConfigInteger(pNetBtDevCfg, "NIC", it->mInstance);
1627	InsertConfigInteger(pNetBtDevCfg, "PCIBusNo", it->mPCIAddress.miBus);
1628	InsertConfigInteger(pNetBtDevCfg, "PCIDeviceNo", it->mPCIAddress.miDevice);
1629	InsertConfigInteger(pNetBtDevCfg, "PCIFunctionNo", it->mPCIAddress.miFn);
1630	}
1631	}
1632
1633	/*
1634	* Serial (UART) Ports
1635	*/
1636	/* serial enabled mask to be passed to dev ACPI */
1637	uint16_t auSerialIoPortBase[SchemaDefs::SerialPortCount] = {0};
1638	uint8_t auSerialIrq[SchemaDefs::SerialPortCount] = {0};
1639	InsertConfigNode(pDevices, "serial", &pDev);
1640	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::SerialPortCount; ++ulInstance)
1641	{
1642	ComPtr<ISerialPort> serialPort;
1643	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
1644	BOOL fEnabledSerPort = FALSE;
1645	if (serialPort)
1646	{
1647	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
1648	}
1649	if (!fEnabledSerPort)
1650	{
1651	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
1652	continue;
1653	}
1654
1655	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1656	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1657	InsertConfigNode(pInst, "Config", &pCfg);
1658
1659	ULONG ulIRQ;
1660	hrc = serialPort->COMGETTER(IRQ)(&ulIRQ); H();
1661	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1662	auSerialIrq[ulInstance] = (uint8_t)ulIRQ;
1663
1664	ULONG ulIOBase;
1665	hrc = serialPort->COMGETTER(IOAddress)(&ulIOBase); H();
1666	InsertConfigInteger(pCfg, "IOAddress", ulIOBase);
1667	auSerialIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1668
1669	BOOL fServer;
1670	hrc = serialPort->COMGETTER(Server)(&fServer); H();
1671	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
1672	UartType_T eUartType;
1673	const char *pszUartType;
1674	hrc = serialPort->COMGETTER(UartType)(&eUartType); H();
1675	switch (eUartType)
1676	{
1677	case UartType_U16450: pszUartType = "16450"; break;
1678	case UartType_U16750: pszUartType = "16750"; break;
1679	default: AssertFailed(); RT_FALL_THRU();
1680	case UartType_U16550A: pszUartType = "16550A"; break;
1681	}
1682	InsertConfigString(pCfg, "UartType", pszUartType);
1683
1684	PortMode_T eHostMode;
1685	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
1686
1687	m_aeSerialPortMode[ulInstance] = eHostMode;
1688	if (eHostMode != PortMode_Disconnected)
1689	{
1690	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
1691	if (RT_FAILURE(vrc))
1692	return vrc;
1693	}
1694	}
1695
1696	/*
1697	* Parallel (LPT) Ports
1698	*/
1699	/* parallel enabled mask to be passed to dev ACPI */
1700	uint16_t auParallelIoPortBase[SchemaDefs::ParallelPortCount] = {0};
1701	uint8_t auParallelIrq[SchemaDefs::ParallelPortCount] = {0};
1702	InsertConfigNode(pDevices, "parallel", &pDev);
1703	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::ParallelPortCount; ++ulInstance)
1704	{
1705	ComPtr<IParallelPort> parallelPort;
1706	hrc = pMachine->GetParallelPort(ulInstance, parallelPort.asOutParam()); H();
1707	BOOL fEnabledParPort = FALSE;
1708	if (parallelPort)
1709	{
1710	hrc = parallelPort->COMGETTER(Enabled)(&fEnabledParPort); H();
1711	}
1712	if (!fEnabledParPort)
1713	continue;
1714
1715	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1716	InsertConfigNode(pInst, "Config", &pCfg);
1717
1718	ULONG ulIRQ;
1719	hrc = parallelPort->COMGETTER(IRQ)(&ulIRQ); H();
1720	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1721	auParallelIrq[ulInstance] = (uint8_t)ulIRQ;
1722	ULONG ulIOBase;
1723	hrc = parallelPort->COMGETTER(IOBase)(&ulIOBase); H();
1724	InsertConfigInteger(pCfg, "IOBase", ulIOBase);
1725	auParallelIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1726
1727	hrc = parallelPort->COMGETTER(Path)(bstr.asOutParam()); H();
1728	if (!bstr.isEmpty())
1729	{
1730	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1731	InsertConfigString(pLunL0, "Driver", "HostParallel");
1732	InsertConfigNode(pLunL0, "Config", &pLunL1);
1733	InsertConfigString(pLunL1, "DevicePath", bstr);
1734	}
1735	}
1736
1737	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices); VRC();
1738
1739	/*
1740	* Audio configuration.
1741	*/
1742	bool fAudioEnabled = false;
1743	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
1744	fOsXGuest, &fAudioEnabled); VRC();
1745
1746	#if defined(VBOX_WITH_TPM)
1747	/*
1748	* Configure the Trusted Platform Module.
1749	*/
1750	ComObjPtr<ITrustedPlatformModule> ptrTpm;
1751	TpmType_T enmTpmType = TpmType_None;
1752
1753	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
1754	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
1755	if (enmTpmType != TpmType_None)
1756	{
1757	InsertConfigNode(pDevices, "tpm", &pDev);
1758	InsertConfigNode(pDev, "0", &pInst);
1759	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1760	InsertConfigNode(pInst, "Config", &pCfg);
1761	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1762
1763	switch (enmTpmType)
1764	{
1765	case TpmType_v1_2:
1766	case TpmType_v2_0:
1767	InsertConfigString(pLunL0, "Driver", "TpmEmuTpms");
1768	InsertConfigNode(pLunL0, "Config", &pCfg);
1769	InsertConfigInteger(pCfg, "TpmVersion", enmTpmType == TpmType_v1_2 ? 1 : 2);
1770	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1771	InsertConfigString(pLunL1, "Driver", "NvramStore");
1772	break;
1773	case TpmType_Host:
1774	#if defined(RT_OS_LINUX) \|\| defined(RT_OS_WINDOWS)
1775	InsertConfigString(pLunL0, "Driver", "TpmHost");
1776	InsertConfigNode(pLunL0, "Config", &pCfg);
1777	#endif
1778	break;
1779	case TpmType_Swtpm:
1780	hrc = ptrTpm->COMGETTER(Location)(bstr.asOutParam()); H();
1781	InsertConfigString(pLunL0, "Driver", "TpmEmu");
1782	InsertConfigNode(pLunL0, "Config", &pCfg);
1783	InsertConfigString(pCfg, "Location", bstr);
1784	break;
1785	default:
1786	AssertFailedBreak();
1787	}
1788	}
1789	#endif
1790
1791	/*
1792	* ACPI
1793	*/
1794	BOOL fACPI;
1795	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
1796	if (fACPI)
1797	{
1798	/* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1799	* The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1800	* intelppm driver refuses to register an idle state handler.
1801	* Always show CPU leafs for OS X guests. */
1802	BOOL fShowCpu = fOsXGuest;
1803	if (cCpus > 1 \|\| fIOAPIC)
1804	fShowCpu = true;
1805
1806	BOOL fCpuHotPlug;
1807	hrc = pMachine->COMGETTER(CPUHotPlugEnabled)(&fCpuHotPlug); H();
1808
1809	InsertConfigNode(pDevices, "acpi", &pDev);
1810	InsertConfigNode(pDev, "0", &pInst);
1811	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1812	InsertConfigNode(pInst, "Config", &pCfg);
1813	hrc = pBusMgr->assignPCIDevice("acpi", pInst); H();
1814
1815	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1816
1817	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1818	InsertConfigInteger(pCfg, "FdcEnabled", fFdcEnabled);
1819	InsertConfigInteger(pCfg, "HpetEnabled", fHPETEnabled);
1820	InsertConfigInteger(pCfg, "SmcEnabled", fSmcEnabled);
1821	InsertConfigInteger(pCfg, "ShowRtc", fShowRtc);
1822	if (fOsXGuest && !llBootNics.empty())
1823	{
1824	BootNic aNic = llBootNics.front();
1825	uint32_t u32NicPCIAddr = (aNic.mPCIAddress.miDevice << 16) \| aNic.mPCIAddress.miFn;
1826	InsertConfigInteger(pCfg, "NicPciAddress", u32NicPCIAddr);
1827	}
1828	if (fOsXGuest && fAudioEnabled)
1829	{
1830	PCIBusAddress Address;
1831	if (pBusMgr->findPCIAddress("hda", 0, Address))
1832	{
1833	uint32_t u32AudioPCIAddr = (Address.miDevice << 16) \| Address.miFn;
1834	InsertConfigInteger(pCfg, "AudioPciAddress", u32AudioPCIAddr);
1835	}
1836	}
1837	if (fOsXGuest)
1838	{
1839	PCIBusAddress Address;
1840	if (pBusMgr->findPCIAddress("nvme", 0, Address))
1841	{
1842	uint32_t u32NvmePCIAddr = (Address.miDevice << 16) \| Address.miFn;
1843	InsertConfigInteger(pCfg, "NvmePciAddress", u32NvmePCIAddr);
1844	}
1845	}
1846	if (enmIommuType == IommuType_AMD)
1847	{
1848	PCIBusAddress Address;
1849	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1850	{
1851	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1852	InsertConfigInteger(pCfg, "IommuAmdEnabled", true);
1853	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1854	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1855	{
1856	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1857	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1858	}
1859	else
1860	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1861	N_("AMD IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1862	}
1863	}
1864	else if (enmIommuType == IommuType_Intel)
1865	{
1866	PCIBusAddress Address;
1867	if (pBusMgr->findPCIAddress("iommu-intel", 0, Address))
1868	{
1869	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1870	InsertConfigInteger(pCfg, "IommuIntelEnabled", true);
1871	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1872	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1873	{
1874	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1875	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1876	}
1877	else
1878	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1879	N_("Intel IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1880	}
1881	}
1882
1883	InsertConfigInteger(pCfg, "IocPciAddress", uIocPCIAddress);
1884	if (chipsetType == ChipsetType_ICH9)
1885	{
1886	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1887	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1888	/* 64-bit prefetch window root resource: Only for ICH9 and if PAE or Long Mode is enabled (@bugref{5454}). */
1889	if (fIsGuest64Bit \|\| fEnablePAE)
1890	InsertConfigInteger(pCfg, "PciPref64Enabled", 1);
1891	}
1892	InsertConfigInteger(pCfg, "HostBusPciAddress", uHbcPCIAddress);
1893	InsertConfigInteger(pCfg, "ShowCpu", fShowCpu);
1894	InsertConfigInteger(pCfg, "CpuHotPlug", fCpuHotPlug);
1895
1896	InsertConfigInteger(pCfg, "Serial0IoPortBase", auSerialIoPortBase[0]);
1897	InsertConfigInteger(pCfg, "Serial0Irq", auSerialIrq[0]);
1898
1899	InsertConfigInteger(pCfg, "Serial1IoPortBase", auSerialIoPortBase[1]);
1900	InsertConfigInteger(pCfg, "Serial1Irq", auSerialIrq[1]);
1901
1902	if (auSerialIoPortBase[2])
1903	{
1904	InsertConfigInteger(pCfg, "Serial2IoPortBase", auSerialIoPortBase[2]);
1905	InsertConfigInteger(pCfg, "Serial2Irq", auSerialIrq[2]);
1906	}
1907
1908	if (auSerialIoPortBase[3])
1909	{
1910	InsertConfigInteger(pCfg, "Serial3IoPortBase", auSerialIoPortBase[3]);
1911	InsertConfigInteger(pCfg, "Serial3Irq", auSerialIrq[3]);
1912	}
1913
1914	InsertConfigInteger(pCfg, "Parallel0IoPortBase", auParallelIoPortBase[0]);
1915	InsertConfigInteger(pCfg, "Parallel0Irq", auParallelIrq[0]);
1916
1917	InsertConfigInteger(pCfg, "Parallel1IoPortBase", auParallelIoPortBase[1]);
1918	InsertConfigInteger(pCfg, "Parallel1Irq", auParallelIrq[1]);
1919
1920	#if defined(VBOX_WITH_TPM)
1921	switch (enmTpmType)
1922	{
1923	case TpmType_v1_2:
1924	InsertConfigString(pCfg, "TpmMode", "tis1.2");
1925	break;
1926	case TpmType_v2_0:
1927	InsertConfigString(pCfg, "TpmMode", "fifo2.0");
1928	break;
1929	/** @todo Host and swtpm. */
1930	default:
1931	break;
1932	}
1933	#endif
1934
1935	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1936	InsertConfigString(pLunL0, "Driver", "ACPIHost");
1937	InsertConfigNode(pLunL0, "Config", &pCfg);
1938
1939	/* Attach the dummy CPU drivers */
1940	for (ULONG iCpuCurr = 1; iCpuCurr < cCpus; iCpuCurr++)
1941	{
1942	BOOL fCpuAttached = true;
1943
1944	if (fCpuHotPlug)
1945	{
1946	hrc = pMachine->GetCPUStatus(iCpuCurr, &fCpuAttached); H();
1947	}
1948
1949	if (fCpuAttached)
1950	{
1951	InsertConfigNode(pInst, Utf8StrFmt("LUN#%u", iCpuCurr).c_str(), &pLunL0);
1952	InsertConfigString(pLunL0, "Driver", "ACPICpu");
1953	InsertConfigNode(pLunL0, "Config", &pCfg);
1954	}
1955	}
1956	}
1957
1958	/*
1959	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
1960	*/
1961	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
1962	}
1963	catch (ConfigError &x)
1964	{
1965	// InsertConfig threw something:
1966	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
1967	return x.m_vrc;
1968	}
1969	catch (HRESULT hrcXcpt)
1970	{
1971	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
1972	}
1973
1974	#ifdef VBOX_WITH_EXTPACK
1975	/*
1976	* Call the extension pack hooks if everything went well thus far.
1977	*/
1978	if (RT_SUCCESS(vrc))
1979	{
1980	pAlock->release();
1981	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
1982	pAlock->acquire();
1983	}
1984	#endif
1985
1986	/*
1987	* Apply the CFGM overlay.
1988	*/
1989	if (RT_SUCCESS(vrc))
1990	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
1991
1992	/*
1993	* Dump all extradata API settings tweaks, both global and per VM.
1994	*/
1995	if (RT_SUCCESS(vrc))
1996	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
1997
1998	#undef H
1999
2000	pAlock->release(); /* Avoid triggering the lock order inversion check. */
2001
2002	/*
2003	* Register VM state change handler.
2004	*/
2005	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
2006	AssertRC(vrc2);
2007	if (RT_SUCCESS(vrc))
2008	vrc = vrc2;
2009
2010	/*
2011	* Register VM runtime error handler.
2012	*/
2013	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
2014	AssertRC(vrc2);
2015	if (RT_SUCCESS(vrc))
2016	vrc = vrc2;
2017
2018	pAlock->acquire();
2019
2020	LogFlowFunc(("vrc = %Rrc\n", vrc));
2021	LogFlowFuncLeave();
2022
2023	return vrc;
2024	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp@ 102654

Download in other formats: