tstInlineAsm.cpp@ 8774

Last change on this file since 8774 was 8245, checked in by vboxsync, 17 years ago
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1	/* $Id: tstInlineAsm.cpp 8245 2008-04-21 17:24:28Z vboxsync $ */
2	/** @file
3	* IPRT Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*
26	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
27	* Clara, CA 95054 USA or visit http://www.sun.com if you need
28	* additional information or have any questions.
29	*/
30
31	/*******************************************************************************
32	* Header Files *
33	*******************************************************************************/
34	#include <iprt/asm.h>
35	#include <iprt/stream.h>
36	#include <iprt/string.h>
37	#include <iprt/runtime.h>
38	#include <iprt/param.h>
39
40
41	/*******************************************************************************
42	* Global Variables *
43	*******************************************************************************/
44	/** Global error count. */
45	static unsigned g_cErrors;
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	#define CHECKVAL(val, expect, fmt) \
52	do \
53	{ \
54	if ((val) != (expect)) \
55	{ \
56	g_cErrors++; \
57	RTPrintf("%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
58	} \
59	} while (0)
60
61	#define CHECKOP(op, expect, fmt, type) \
62	do \
63	{ \
64	type val = op; \
65	if (val != (type)(expect)) \
66	{ \
67	g_cErrors++; \
68	RTPrintf("%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
69	} \
70	} while (0)
71
72
73	#if !defined(PIC) \|\| !defined(RT_ARCH_X86)
74	const char *getCacheAss(unsigned u)
75	{
76	if (u == 0)
77	return "res0 ";
78	if (u == 1)
79	return "direct";
80	if (u >= 256)
81	return "???";
82
83	char *pszRet;
84	RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
85	return pszRet;
86	}
87
88
89	const char *getL2CacheAss(unsigned u)
90	{
91	switch (u)
92	{
93	case 0: return "off ";
94	case 1: return "direct";
95	case 2: return "2 way ";
96	case 3: return "res3 ";
97	case 4: return "4 way ";
98	case 5: return "res5 ";
99	case 6: return "8 way ";
100	case 7: return "res7 ";
101	case 8: return "16 way";
102	case 9: return "res9 ";
103	case 10: return "res10 ";
104	case 11: return "res11 ";
105	case 12: return "res12 ";
106	case 13: return "res13 ";
107	case 14: return "res14 ";
108	case 15: return "fully ";
109	default:
110	return "????";
111	}
112	}
113
114
115	/**
116	* Test and dump all possible info from the CPUID instruction.
117	*
118	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
119	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
120	*/
121	void tstASMCpuId(void)
122	{
123	unsigned iBit;
124	struct
125	{
126	uint32_t uEBX, uEAX, uEDX, uECX;
127	} s;
128	if (!ASMHasCpuId())
129	{
130	RTPrintf("tstInlineAsm: warning! CPU doesn't support CPUID\n");
131	return;
132	}
133
134	/*
135	* Try the 0 function and use that for checking the ASMCpuId_* variants.
136	*/
137	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
138
139	uint32_t u32 = ASMCpuId_ECX(0);
140	CHECKVAL(u32, s.uECX, "%x");
141
142	u32 = ASMCpuId_EDX(0);
143	CHECKVAL(u32, s.uEDX, "%x");
144
145	uint32_t uECX2 = s.uECX - 1;
146	uint32_t uEDX2 = s.uEDX - 1;
147	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
148
149	CHECKVAL(uECX2, s.uECX, "%x");
150	CHECKVAL(uEDX2, s.uEDX, "%x");
151
152	/*
153	* Done testing, dump the information.
154	*/
155	RTPrintf("tstInlineAsm: CPUID Dump\n");
156	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
157	const uint32_t cFunctions = s.uEAX;
158
159	/* raw dump */
160	RTPrintf("\n"
161	" RAW Standard CPUIDs\n"
162	"Function eax ebx ecx edx\n");
163	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
164	{
165	ASMCpuId(iStd, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
166	RTPrintf("%08x %08x %08x %08x %08x%s\n",
167	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
168	}
169
170	/*
171	* Understandable output
172	*/
173	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
174	RTPrintf("Name: %.04s%.04s%.04s\n"
175	"Support: 0-%u\n",
176	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
177
178	/*
179	* Get Features.
180	*/
181	if (cFunctions >= 1)
182	{
183	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
184	RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
185	"Model: %d \tExtended: %d \tEffectiv: %d\n"
186	"Stepping: %d\n"
187	"APIC ID: %#04x\n"
188	"Logical CPUs: %d\n"
189	"CLFLUSH Size: %d\n"
190	"Brand ID: %#04x\n",
191	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
192	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) \| (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
193	(s.uEAX >> 0) & 0xf,
194	(s.uEBX >> 24) & 0xff,
195	(s.uEBX >> 16) & 0xff,
196	(s.uEBX >> 8) & 0xff,
197	(s.uEBX >> 0) & 0xff);
198
199	RTPrintf("Features EDX: ");
200	if (s.uEDX & RT_BIT(0)) RTPrintf(" FPU");
201	if (s.uEDX & RT_BIT(1)) RTPrintf(" VME");
202	if (s.uEDX & RT_BIT(2)) RTPrintf(" DE");
203	if (s.uEDX & RT_BIT(3)) RTPrintf(" PSE");
204	if (s.uEDX & RT_BIT(4)) RTPrintf(" TSC");
205	if (s.uEDX & RT_BIT(5)) RTPrintf(" MSR");
206	if (s.uEDX & RT_BIT(6)) RTPrintf(" PAE");
207	if (s.uEDX & RT_BIT(7)) RTPrintf(" MCE");
208	if (s.uEDX & RT_BIT(8)) RTPrintf(" CX8");
209	if (s.uEDX & RT_BIT(9)) RTPrintf(" APIC");
210	if (s.uEDX & RT_BIT(10)) RTPrintf(" 10");
211	if (s.uEDX & RT_BIT(11)) RTPrintf(" SEP");
212	if (s.uEDX & RT_BIT(12)) RTPrintf(" MTRR");
213	if (s.uEDX & RT_BIT(13)) RTPrintf(" PGE");
214	if (s.uEDX & RT_BIT(14)) RTPrintf(" MCA");
215	if (s.uEDX & RT_BIT(15)) RTPrintf(" CMOV");
216	if (s.uEDX & RT_BIT(16)) RTPrintf(" PAT");
217	if (s.uEDX & RT_BIT(17)) RTPrintf(" PSE36");
218	if (s.uEDX & RT_BIT(18)) RTPrintf(" PSN");
219	if (s.uEDX & RT_BIT(19)) RTPrintf(" CLFSH");
220	if (s.uEDX & RT_BIT(20)) RTPrintf(" 20");
221	if (s.uEDX & RT_BIT(21)) RTPrintf(" DS");
222	if (s.uEDX & RT_BIT(22)) RTPrintf(" ACPI");
223	if (s.uEDX & RT_BIT(23)) RTPrintf(" MMX");
224	if (s.uEDX & RT_BIT(24)) RTPrintf(" FXSR");
225	if (s.uEDX & RT_BIT(25)) RTPrintf(" SSE");
226	if (s.uEDX & RT_BIT(26)) RTPrintf(" SSE2");
227	if (s.uEDX & RT_BIT(27)) RTPrintf(" SS");
228	if (s.uEDX & RT_BIT(28)) RTPrintf(" HTT");
229	if (s.uEDX & RT_BIT(29)) RTPrintf(" 29");
230	if (s.uEDX & RT_BIT(30)) RTPrintf(" 30");
231	if (s.uEDX & RT_BIT(31)) RTPrintf(" 31");
232	RTPrintf("\n");
233
234	/** @todo check intel docs. */
235	RTPrintf("Features ECX: ");
236	if (s.uECX & RT_BIT(0)) RTPrintf(" SSE3");
237	for (iBit = 1; iBit < 13; iBit++)
238	if (s.uECX & RT_BIT(iBit))
239	RTPrintf(" %d", iBit);
240	if (s.uECX & RT_BIT(13)) RTPrintf(" CX16");
241	for (iBit = 14; iBit < 32; iBit++)
242	if (s.uECX & RT_BIT(iBit))
243	RTPrintf(" %d", iBit);
244	RTPrintf("\n");
245	}
246
247	/*
248	* Extended.
249	* Implemented after AMD specs.
250	*/
251	/** @todo check out the intel specs. */
252	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
253	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
254	{
255	RTPrintf("No extended CPUID info? Check the manual on how to detect this...\n");
256	return;
257	}
258	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
259
260	/* raw dump */
261	RTPrintf("\n"
262	" RAW Extended CPUIDs\n"
263	"Function eax ebx ecx edx\n");
264	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
265	{
266	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
267	RTPrintf("%08x %08x %08x %08x %08x%s\n",
268	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
269	}
270
271	/*
272	* Understandable output
273	*/
274	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
275	RTPrintf("Ext Name: %.4s%.4s%.4s\n"
276	"Ext Supports: 0x80000000-%#010x\n",
277	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
278
279	if (cExtFunctions >= 0x80000001)
280	{
281	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
282	RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
283	"Model: %d \tExtended: %d \tEffectiv: %d\n"
284	"Stepping: %d\n"
285	"Brand ID: %#05x\n",
286	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
287	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) \| (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
288	(s.uEAX >> 0) & 0xf,
289	s.uEBX & 0xfff);
290
291	RTPrintf("Features EDX: ");
292	if (s.uEDX & RT_BIT(0)) RTPrintf(" FPU");
293	if (s.uEDX & RT_BIT(1)) RTPrintf(" VME");
294	if (s.uEDX & RT_BIT(2)) RTPrintf(" DE");
295	if (s.uEDX & RT_BIT(3)) RTPrintf(" PSE");
296	if (s.uEDX & RT_BIT(4)) RTPrintf(" TSC");
297	if (s.uEDX & RT_BIT(5)) RTPrintf(" MSR");
298	if (s.uEDX & RT_BIT(6)) RTPrintf(" PAE");
299	if (s.uEDX & RT_BIT(7)) RTPrintf(" MCE");
300	if (s.uEDX & RT_BIT(8)) RTPrintf(" CMPXCHG8B");
301	if (s.uEDX & RT_BIT(9)) RTPrintf(" APIC");
302	if (s.uEDX & RT_BIT(10)) RTPrintf(" 10");
303	if (s.uEDX & RT_BIT(11)) RTPrintf(" SysCallSysRet");
304	if (s.uEDX & RT_BIT(12)) RTPrintf(" MTRR");
305	if (s.uEDX & RT_BIT(13)) RTPrintf(" PGE");
306	if (s.uEDX & RT_BIT(14)) RTPrintf(" MCA");
307	if (s.uEDX & RT_BIT(15)) RTPrintf(" CMOV");
308	if (s.uEDX & RT_BIT(16)) RTPrintf(" PAT");
309	if (s.uEDX & RT_BIT(17)) RTPrintf(" PSE36");
310	if (s.uEDX & RT_BIT(18)) RTPrintf(" 18");
311	if (s.uEDX & RT_BIT(19)) RTPrintf(" 19");
312	if (s.uEDX & RT_BIT(20)) RTPrintf(" NX");
313	if (s.uEDX & RT_BIT(21)) RTPrintf(" 21");
314	if (s.uEDX & RT_BIT(22)) RTPrintf(" MmxExt");
315	if (s.uEDX & RT_BIT(23)) RTPrintf(" MMX");
316	if (s.uEDX & RT_BIT(24)) RTPrintf(" FXSR");
317	if (s.uEDX & RT_BIT(25)) RTPrintf(" FastFXSR");
318	if (s.uEDX & RT_BIT(26)) RTPrintf(" 26");
319	if (s.uEDX & RT_BIT(27)) RTPrintf(" RDTSCP");
320	if (s.uEDX & RT_BIT(28)) RTPrintf(" 28");
321	if (s.uEDX & RT_BIT(29)) RTPrintf(" LongMode");
322	if (s.uEDX & RT_BIT(30)) RTPrintf(" 3DNowExt");
323	if (s.uEDX & RT_BIT(31)) RTPrintf(" 3DNow");
324	RTPrintf("\n");
325
326	RTPrintf("Features ECX: ");
327	if (s.uECX & RT_BIT(0)) RTPrintf(" LahfSahf");
328	if (s.uECX & RT_BIT(1)) RTPrintf(" CmpLegacy");
329	if (s.uECX & RT_BIT(2)) RTPrintf(" SVM");
330	if (s.uECX & RT_BIT(3)) RTPrintf(" 3");
331	if (s.uECX & RT_BIT(4)) RTPrintf(" AltMovCr8");
332	for (iBit = 5; iBit < 32; iBit++)
333	if (s.uECX & RT_BIT(iBit))
334	RTPrintf(" %d", iBit);
335	RTPrintf("\n");
336	}
337
338	char szString[443+1] = {0};
339	if (cExtFunctions >= 0x80000002)
340	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
341	if (cExtFunctions >= 0x80000003)
342	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
343	if (cExtFunctions >= 0x80000004)
344	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
345	if (cExtFunctions >= 0x80000002)
346	RTPrintf("Full Name: %s\n", szString);
347
348	if (cExtFunctions >= 0x80000005)
349	{
350	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
351	RTPrintf("TLB 2/4M Instr/Uni: %s %3d entries\n"
352	"TLB 2/4M Data: %s %3d entries\n",
353	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
354	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
355	RTPrintf("TLB 4K Instr/Uni: %s %3d entries\n"
356	"TLB 4K Data: %s %3d entries\n",
357	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
358	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
359	RTPrintf("L1 Instr Cache Line Size: %d bytes\n"
360	"L1 Instr Cache Lines Per Tag: %d\n"
361	"L1 Instr Cache Associativity: %s\n"
362	"L1 Instr Cache Size: %d KB\n",
363	(s.uEDX >> 0) & 0xff,
364	(s.uEDX >> 8) & 0xff,
365	getCacheAss((s.uEDX >> 16) & 0xff),
366	(s.uEDX >> 24) & 0xff);
367	RTPrintf("L1 Data Cache Line Size: %d bytes\n"
368	"L1 Data Cache Lines Per Tag: %d\n"
369	"L1 Data Cache Associativity: %s\n"
370	"L1 Data Cache Size: %d KB\n",
371	(s.uECX >> 0) & 0xff,
372	(s.uECX >> 8) & 0xff,
373	getCacheAss((s.uECX >> 16) & 0xff),
374	(s.uECX >> 24) & 0xff);
375	}
376
377	if (cExtFunctions >= 0x80000006)
378	{
379	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
380	RTPrintf("L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
381	"L2 TLB 2/4M Data: %s %4d entries\n",
382	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
383	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
384	RTPrintf("L2 TLB 4K Instr/Uni: %s %4d entries\n"
385	"L2 TLB 4K Data: %s %4d entries\n",
386	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
387	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
388	RTPrintf("L2 Cache Line Size: %d bytes\n"
389	"L2 Cache Lines Per Tag: %d\n"
390	"L2 Cache Associativity: %s\n"
391	"L2 Cache Size: %d KB\n",
392	(s.uEDX >> 0) & 0xff,
393	(s.uEDX >> 8) & 0xf,
394	getL2CacheAss((s.uEDX >> 12) & 0xf),
395	(s.uEDX >> 16) & 0xffff);
396	}
397
398	if (cExtFunctions >= 0x80000007)
399	{
400	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
401	RTPrintf("APM Features: ");
402	if (s.uEDX & RT_BIT(0)) RTPrintf(" TS");
403	if (s.uEDX & RT_BIT(1)) RTPrintf(" FID");
404	if (s.uEDX & RT_BIT(2)) RTPrintf(" VID");
405	if (s.uEDX & RT_BIT(3)) RTPrintf(" TTP");
406	if (s.uEDX & RT_BIT(4)) RTPrintf(" TM");
407	if (s.uEDX & RT_BIT(5)) RTPrintf(" STC");
408	if (s.uEDX & RT_BIT(6)) RTPrintf(" 6");
409	if (s.uEDX & RT_BIT(7)) RTPrintf(" 7");
410	if (s.uEDX & RT_BIT(8)) RTPrintf(" TscInvariant");
411	for (iBit = 9; iBit < 32; iBit++)
412	if (s.uEDX & RT_BIT(iBit))
413	RTPrintf(" %d", iBit);
414	RTPrintf("\n");
415	}
416
417	if (cExtFunctions >= 0x80000008)
418	{
419	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
420	RTPrintf("Physical Address Width: %d bits\n"
421	"Virtual Address Width: %d bits\n",
422	(s.uEAX >> 0) & 0xff,
423	(s.uEAX >> 8) & 0xff);
424	RTPrintf("Physical Core Count: %d\n",
425	((s.uECX >> 0) & 0xff) + 1);
426	if ((s.uECX >> 12) & 0xf)
427	RTPrintf("ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
428	}
429
430	if (cExtFunctions >= 0x8000000a)
431	{
432	ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
433	RTPrintf("SVM Revision: %d (%#x)\n"
434	"Number of Address Space IDs: %d (%#x)\n",
435	s.uEAX & 0xff, s.uEAX & 0xff,
436	s.uEBX, s.uEBX);
437	}
438	}
439	#endif /* !PIC \|\| !X86 */
440
441
442	static void tstASMAtomicXchgU8(void)
443	{
444	struct
445	{
446	uint8_t u8Dummy0;
447	uint8_t u8;
448	uint8_t u8Dummy1;
449	} s;
450
451	s.u8 = 0;
452	s.u8Dummy0 = s.u8Dummy1 = 0x42;
453	CHECKOP(ASMAtomicXchgU8(&s.u8, 1), 0, "%#x", uint8_t);
454	CHECKVAL(s.u8, 1, "%#x");
455
456	CHECKOP(ASMAtomicXchgU8(&s.u8, 0), 1, "%#x", uint8_t);
457	CHECKVAL(s.u8, 0, "%#x");
458
459	CHECKOP(ASMAtomicXchgU8(&s.u8, 0xff), 0, "%#x", uint8_t);
460	CHECKVAL(s.u8, 0xff, "%#x");
461
462	CHECKOP(ASMAtomicXchgU8(&s.u8, 0x87), 0xffff, "%#x", uint8_t);
463	CHECKVAL(s.u8, 0x87, "%#x");
464	CHECKVAL(s.u8Dummy0, 0x42, "%#x");
465	CHECKVAL(s.u8Dummy1, 0x42, "%#x");
466	}
467
468
469	static void tstASMAtomicXchgU16(void)
470	{
471	struct
472	{
473	uint16_t u16Dummy0;
474	uint16_t u16;
475	uint16_t u16Dummy1;
476	} s;
477
478	s.u16 = 0;
479	s.u16Dummy0 = s.u16Dummy1 = 0x1234;
480	CHECKOP(ASMAtomicXchgU16(&s.u16, 1), 0, "%#x", uint16_t);
481	CHECKVAL(s.u16, 1, "%#x");
482
483	CHECKOP(ASMAtomicXchgU16(&s.u16, 0), 1, "%#x", uint16_t);
484	CHECKVAL(s.u16, 0, "%#x");
485
486	CHECKOP(ASMAtomicXchgU16(&s.u16, 0xffff), 0, "%#x", uint16_t);
487	CHECKVAL(s.u16, 0xffff, "%#x");
488
489	CHECKOP(ASMAtomicXchgU16(&s.u16, 0x8765), 0xffff, "%#x", uint16_t);
490	CHECKVAL(s.u16, 0x8765, "%#x");
491	CHECKVAL(s.u16Dummy0, 0x1234, "%#x");
492	CHECKVAL(s.u16Dummy1, 0x1234, "%#x");
493	}
494
495
496	static void tstASMAtomicXchgU32(void)
497	{
498	struct
499	{
500	uint32_t u32Dummy0;
501	uint32_t u32;
502	uint32_t u32Dummy1;
503	} s;
504
505	s.u32 = 0;
506	s.u32Dummy0 = s.u32Dummy1 = 0x11223344;
507
508	CHECKOP(ASMAtomicXchgU32(&s.u32, 1), 0, "%#x", uint32_t);
509	CHECKVAL(s.u32, 1, "%#x");
510
511	CHECKOP(ASMAtomicXchgU32(&s.u32, 0), 1, "%#x", uint32_t);
512	CHECKVAL(s.u32, 0, "%#x");
513
514	CHECKOP(ASMAtomicXchgU32(&s.u32, ~0U), 0, "%#x", uint32_t);
515	CHECKVAL(s.u32, ~0U, "%#x");
516
517	CHECKOP(ASMAtomicXchgU32(&s.u32, 0x87654321), ~0U, "%#x", uint32_t);
518	CHECKVAL(s.u32, 0x87654321, "%#x");
519
520	CHECKVAL(s.u32Dummy0, 0x11223344, "%#x");
521	CHECKVAL(s.u32Dummy1, 0x11223344, "%#x");
522	}
523
524
525	static void tstASMAtomicXchgU64(void)
526	{
527	struct
528	{
529	uint64_t u64Dummy0;
530	uint64_t u64;
531	uint64_t u64Dummy1;
532	} s;
533
534	s.u64 = 0;
535	s.u64Dummy0 = s.u64Dummy1 = 0x1122334455667788ULL;
536
537	CHECKOP(ASMAtomicXchgU64(&s.u64, 1), 0ULL, "%#llx", uint64_t);
538	CHECKVAL(s.u64, 1ULL, "%#llx");
539
540	CHECKOP(ASMAtomicXchgU64(&s.u64, 0), 1ULL, "%#llx", uint64_t);
541	CHECKVAL(s.u64, 0ULL, "%#llx");
542
543	CHECKOP(ASMAtomicXchgU64(&s.u64, ~0ULL), 0ULL, "%#llx", uint64_t);
544	CHECKVAL(s.u64, ~0ULL, "%#llx");
545
546	CHECKOP(ASMAtomicXchgU64(&s.u64, 0xfedcba0987654321ULL), ~0ULL, "%#llx", uint64_t);
547	CHECKVAL(s.u64, 0xfedcba0987654321ULL, "%#llx");
548
549	CHECKVAL(s.u64Dummy0, 0x1122334455667788ULL, "%#x");
550	CHECKVAL(s.u64Dummy1, 0x1122334455667788ULL, "%#x");
551	}
552
553
554	#ifdef RT_ARCH_AMD64
555	static void tstASMAtomicXchgU128(void)
556	{
557	struct
558	{
559	RTUINT128U u128Dummy0;
560	RTUINT128U u128;
561	RTUINT128U u128Dummy1;
562	} s;
563	RTUINT128U u128Ret;
564	RTUINT128U u128Arg;
565
566
567	s.u128Dummy0.s.Lo = s.u128Dummy0.s.Hi = 0x1122334455667788;
568	s.u128.s.Lo = 0;
569	s.u128.s.Hi = 0;
570	s.u128Dummy1 = s.u128Dummy0;
571
572	u128Arg.s.Lo = 1;
573	u128Arg.s.Hi = 0;
574	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
575	CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
576	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
577	CHECKVAL(s.u128.s.Lo, 1ULL, "%#llx");
578	CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
579
580	u128Arg.s.Lo = 0;
581	u128Arg.s.Hi = 0;
582	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
583	CHECKVAL(u128Ret.s.Lo, 1ULL, "%#llx");
584	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
585	CHECKVAL(s.u128.s.Lo, 0ULL, "%#llx");
586	CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
587
588	u128Arg.s.Lo = ~0ULL;
589	u128Arg.s.Hi = ~0ULL;
590	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
591	CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
592	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
593	CHECKVAL(s.u128.s.Lo, ~0ULL, "%#llx");
594	CHECKVAL(s.u128.s.Hi, ~0ULL, "%#llx");
595
596
597	u128Arg.s.Lo = 0xfedcba0987654321ULL;
598	u128Arg.s.Hi = 0x8897a6b5c4d3e2f1ULL;
599	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
600	CHECKVAL(u128Ret.s.Lo, ~0ULL, "%#llx");
601	CHECKVAL(u128Ret.s.Hi, ~0ULL, "%#llx");
602	CHECKVAL(s.u128.s.Lo, 0xfedcba0987654321ULL, "%#llx");
603	CHECKVAL(s.u128.s.Hi, 0x8897a6b5c4d3e2f1ULL, "%#llx");
604
605	CHECKVAL(s.u128Dummy0.s.Lo, 0x1122334455667788, "%#llx");
606	CHECKVAL(s.u128Dummy0.s.Hi, 0x1122334455667788, "%#llx");
607	CHECKVAL(s.u128Dummy1.s.Lo, 0x1122334455667788, "%#llx");
608	CHECKVAL(s.u128Dummy1.s.Hi, 0x1122334455667788, "%#llx");
609	}
610	#endif
611
612
613	static void tstASMAtomicXchgPtr(void)
614	{
615	void *pv = NULL;
616
617	CHECKOP(ASMAtomicXchgPtr(&pv, (void )(~(uintptr_t)0)), NULL, "%p", void );
618	CHECKVAL(pv, (void *)(~(uintptr_t)0), "%p");
619
620	CHECKOP(ASMAtomicXchgPtr(&pv, (void )0x87654321), (void )(~(uintptr_t)0), "%p", void *);
621	CHECKVAL(pv, (void *)0x87654321, "%p");
622
623	CHECKOP(ASMAtomicXchgPtr(&pv, NULL), (void )0x87654321, "%p", void );
624	CHECKVAL(pv, NULL, "%p");
625	}
626
627
628	static void tstASMAtomicCmpXchgU32(void)
629	{
630	uint32_t u32 = 0xffffffff;
631
632	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0), false, "%d", bool);
633	CHECKVAL(u32, 0xffffffff, "%x");
634
635	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0xffffffff), true, "%d", bool);
636	CHECKVAL(u32, 0, "%x");
637
638	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0xffffffff), false, "%d", bool);
639	CHECKVAL(u32, 0, "%x");
640
641	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0), true, "%d", bool);
642	CHECKVAL(u32, 0x8008efd, "%x");
643	}
644
645
646	static void tstASMAtomicCmpXchgU64(void)
647	{
648	uint64_t u64 = 0xffffffffffffffULL;
649
650	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0), false, "%d", bool);
651	CHECKVAL(u64, 0xffffffffffffffULL, "%x");
652
653	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0xffffffffffffffULL), true, "%d", bool);
654	CHECKVAL(u64, 0, "%x");
655
656	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff), false, "%d", bool);
657	CHECKVAL(u64, 0, "%x");
658
659	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff00000000ULL), false, "%d", bool);
660	CHECKVAL(u64, 0, "%x");
661
662	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0), true, "%d", bool);
663	CHECKVAL(u64, 0x80040008008efdULL, "%x");
664	}
665
666
667	static void tstASMAtomicCmpXchgExU32(void)
668	{
669	uint32_t u32 = 0xffffffff;
670	uint32_t u32Old = 0x80005111;
671
672	CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0, &u32Old), false, "%d", bool);
673	CHECKVAL(u32, 0xffffffff, "%x");
674	CHECKVAL(u32Old, 0xffffffff, "%x");
675
676	CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0xffffffff, &u32Old), true, "%d", bool);
677	CHECKVAL(u32, 0, "%x");
678	CHECKVAL(u32Old, 0xffffffff, "%x");
679
680	CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0x8008efd, 0xffffffff, &u32Old), false, "%d", bool);
681	CHECKVAL(u32, 0, "%x");
682	CHECKVAL(u32Old, 0, "%x");
683
684	CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0x8008efd, 0, &u32Old), true, "%d", bool);
685	CHECKVAL(u32, 0x8008efd, "%x");
686	CHECKVAL(u32Old, 0, "%x");
687
688	CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0x8008efd, &u32Old), true, "%d", bool);
689	CHECKVAL(u32, 0, "%x");
690	CHECKVAL(u32Old, 0x8008efd, "%x");
691	}
692
693
694	static void tstASMAtomicCmpXchgExU64(void)
695	{
696	uint64_t u64 = 0xffffffffffffffffULL;
697	uint64_t u64Old = 0x8000000051111111ULL;
698
699	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0, &u64Old), false, "%d", bool);
700	CHECKVAL(u64, 0xffffffffffffffffULL, "%llx");
701	CHECKVAL(u64Old, 0xffffffffffffffffULL, "%llx");
702
703	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0xffffffffffffffffULL, &u64Old), true, "%d", bool);
704	CHECKVAL(u64, 0ULL, "%llx");
705	CHECKVAL(u64Old, 0xffffffffffffffffULL, "%llx");
706
707	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0xffffffff, &u64Old), false, "%d", bool);
708	CHECKVAL(u64, 0ULL, "%llx");
709	CHECKVAL(u64Old, 0ULL, "%llx");
710
711	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0xffffffff00000000ULL, &u64Old), false, "%d", bool);
712	CHECKVAL(u64, 0ULL, "%llx");
713	CHECKVAL(u64Old, 0ULL, "%llx");
714
715	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0, &u64Old), true, "%d", bool);
716	CHECKVAL(u64, 0x80040008008efdULL, "%llx");
717	CHECKVAL(u64Old, 0ULL, "%llx");
718
719	CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0x80040008008efdULL, &u64Old), true, "%d", bool);
720	CHECKVAL(u64, 0ULL, "%llx");
721	CHECKVAL(u64Old, 0x80040008008efdULL, "%llx");
722	}
723
724
725	static void tstASMAtomicReadU64(void)
726	{
727	uint64_t u64 = 0;
728
729	CHECKOP(ASMAtomicReadU64(&u64), 0ULL, "%#llx", uint64_t);
730	CHECKVAL(u64, 0ULL, "%#llx");
731
732	u64 = ~0ULL;
733	CHECKOP(ASMAtomicReadU64(&u64), ~0ULL, "%#llx", uint64_t);
734	CHECKVAL(u64, ~0ULL, "%#llx");
735
736	u64 = 0xfedcba0987654321ULL;
737	CHECKOP(ASMAtomicReadU64(&u64), 0xfedcba0987654321ULL, "%#llx", uint64_t);
738	CHECKVAL(u64, 0xfedcba0987654321ULL, "%#llx");
739	}
740
741
742	static void tstASMAtomicAddS32(void)
743	{
744	int32_t i32Rc;
745	int32_t i32 = 10;
746	#define MYCHECK(op, rc, val) \
747	do { \
748	i32Rc = op; \
749	if (i32Rc != (rc)) \
750	{ \
751	RTPrintf("%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
752	g_cErrors++; \
753	} \
754	if (i32 != (val)) \
755	{ \
756	RTPrintf("%s, %d: FAILURE: %s => i32=%d expected %d\n", __FUNCTION__, __LINE__, #op, i32, val); \
757	g_cErrors++; \
758	} \
759	} while (0)
760	MYCHECK(ASMAtomicAddS32(&i32, 1), 10, 11);
761	MYCHECK(ASMAtomicAddS32(&i32, -2), 11, 9);
762	MYCHECK(ASMAtomicAddS32(&i32, -9), 9, 0);
763	MYCHECK(ASMAtomicAddS32(&i32, -0x7fffffff), 0, -0x7fffffff);
764	MYCHECK(ASMAtomicAddS32(&i32, 0), -0x7fffffff, -0x7fffffff);
765	MYCHECK(ASMAtomicAddS32(&i32, 0x7fffffff), -0x7fffffff, 0);
766	MYCHECK(ASMAtomicAddS32(&i32, 0), 0, 0);
767	#undef MYCHECK
768	}
769
770
771	static void tstASMAtomicDecIncS32(void)
772	{
773	int32_t i32Rc;
774	int32_t i32 = 10;
775	#define MYCHECK(op, rc) \
776	do { \
777	i32Rc = op; \
778	if (i32Rc != (rc)) \
779	{ \
780	RTPrintf("%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
781	g_cErrors++; \
782	} \
783	if (i32 != (rc)) \
784	{ \
785	RTPrintf("%s, %d: FAILURE: %s => i32=%d expected %d\n", __FUNCTION__, __LINE__, #op, i32, rc); \
786	g_cErrors++; \
787	} \
788	} while (0)
789	MYCHECK(ASMAtomicDecS32(&i32), 9);
790	MYCHECK(ASMAtomicDecS32(&i32), 8);
791	MYCHECK(ASMAtomicDecS32(&i32), 7);
792	MYCHECK(ASMAtomicDecS32(&i32), 6);
793	MYCHECK(ASMAtomicDecS32(&i32), 5);
794	MYCHECK(ASMAtomicDecS32(&i32), 4);
795	MYCHECK(ASMAtomicDecS32(&i32), 3);
796	MYCHECK(ASMAtomicDecS32(&i32), 2);
797	MYCHECK(ASMAtomicDecS32(&i32), 1);
798	MYCHECK(ASMAtomicDecS32(&i32), 0);
799	MYCHECK(ASMAtomicDecS32(&i32), -1);
800	MYCHECK(ASMAtomicDecS32(&i32), -2);
801	MYCHECK(ASMAtomicIncS32(&i32), -1);
802	MYCHECK(ASMAtomicIncS32(&i32), 0);
803	MYCHECK(ASMAtomicIncS32(&i32), 1);
804	MYCHECK(ASMAtomicIncS32(&i32), 2);
805	MYCHECK(ASMAtomicIncS32(&i32), 3);
806	MYCHECK(ASMAtomicDecS32(&i32), 2);
807	MYCHECK(ASMAtomicIncS32(&i32), 3);
808	MYCHECK(ASMAtomicDecS32(&i32), 2);
809	MYCHECK(ASMAtomicIncS32(&i32), 3);
810	#undef MYCHECK
811	}
812
813
814	static void tstASMAtomicAndOrU32(void)
815	{
816	uint32_t u32 = 0xffffffff;
817
818	ASMAtomicOrU32(&u32, 0xffffffff);
819	CHECKVAL(u32, 0xffffffff, "%x");
820
821	ASMAtomicAndU32(&u32, 0xffffffff);
822	CHECKVAL(u32, 0xffffffff, "%x");
823
824	ASMAtomicAndU32(&u32, 0x8f8f8f8f);
825	CHECKVAL(u32, 0x8f8f8f8f, "%x");
826
827	ASMAtomicOrU32(&u32, 0x70707070);
828	CHECKVAL(u32, 0xffffffff, "%x");
829
830	ASMAtomicAndU32(&u32, 1);
831	CHECKVAL(u32, 1, "%x");
832
833	ASMAtomicOrU32(&u32, 0x80000000);
834	CHECKVAL(u32, 0x80000001, "%x");
835
836	ASMAtomicAndU32(&u32, 0x80000000);
837	CHECKVAL(u32, 0x80000000, "%x");
838
839	ASMAtomicAndU32(&u32, 0);
840	CHECKVAL(u32, 0, "%x");
841
842	ASMAtomicOrU32(&u32, 0x42424242);
843	CHECKVAL(u32, 0x42424242, "%x");
844	}
845
846
847	void tstASMMemZeroPage(void)
848	{
849	struct
850	{
851	uint64_t u64Magic1;
852	uint8_t abPage[PAGE_SIZE];
853	uint64_t u64Magic2;
854	} Buf1, Buf2, Buf3;
855
856	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
857	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
858	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
859	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
860	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
861	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
862	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
863	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
864	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
865	ASMMemZeroPage(Buf1.abPage);
866	ASMMemZeroPage(Buf2.abPage);
867	ASMMemZeroPage(Buf3.abPage);
868	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
869	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
870	\|\| Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
871	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
872	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
873	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff))
874	{
875	RTPrintf("tstInlineAsm: ASMMemZeroPage violated one/both magic(s)!\n");
876	g_cErrors++;
877	}
878	for (unsigned i = 0; i < sizeof(Buf1.abPage); i++)
879	if (Buf1.abPage[i])
880	{
881	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
882	g_cErrors++;
883	}
884	for (unsigned i = 0; i < sizeof(Buf1.abPage); i++)
885	if (Buf1.abPage[i])
886	{
887	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
888	g_cErrors++;
889	}
890	for (unsigned i = 0; i < sizeof(Buf2.abPage); i++)
891	if (Buf2.abPage[i])
892	{
893	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
894	g_cErrors++;
895	}
896	}
897
898
899	void tstASMMath(void)
900	{
901	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
902	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
903
904	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
905	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
906
907	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
908	CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
909	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
910	CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
911	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
912	CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
913	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
914	CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
915	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
916	CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
917	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
918	CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
919	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
920	CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
921
922	#if 0 /* bird: question is whether this should trap or not:
923	*
924	* frank: Of course it must trap:
925	*
926	* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
927	*
928	* During the following division, the quotient must fit into a 32-bit register.
929	* Therefore the smallest valid divisor is
930	*
931	* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
932	*
933	* which is definitely greater than 0x3b9aca00.
934	*
935	* bird: No, the C version does not crash. So, the question is whether there any
936	* code depending on it not crashing.
937	*
938	* Of course the assembly versions of the code crash right now for the reasons you've
939	* given, but the the 32-bit MSC version does not crash.
940	*
941	* frank: The C version does not crash but delivers incorrect results for this case.
942	* The reason is
943	*
944	* u.s.Hi = (unsigned long)(u64Hi / u32C);
945	*
946	* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
947	* to 32 bit. If using this (optimized and fast) function we should just be sure that
948	* the operands are in a valid range.
949	*/
950	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
951	CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
952	#endif
953	}
954
955	/*
956	* Make this static. We don't want to have this located on the stack.
957	*/
958	void tstASMBench(void)
959	{
960	static uint8_t volatile s_u8;
961	static int8_t volatile s_i8;
962	static uint16_t volatile s_u16;
963	static int16_t volatile s_i16;
964	static uint32_t volatile s_u32;
965	static int32_t volatile s_i32;
966	static uint64_t volatile s_u64;
967	static int64_t volatile s_i64;
968	register unsigned i;
969	const unsigned cRounds = 1000000;
970	register uint64_t u64Elapsed;
971
972	RTPrintf("tstInlineASM: Benchmarking:\n");
973
974	#define BENCH(op, str) \
975	RTThreadYield(); \
976	u64Elapsed = ASMReadTSC(); \
977	for (i = cRounds; i > 0; i--) \
978	op; \
979	u64Elapsed = ASMReadTSC() - u64Elapsed; \
980	RTPrintf(" %-30s %3llu cycles\n", str, u64Elapsed / cRounds);
981
982	BENCH(s_u32 = 0, "s_u32 = 0:");
983	BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8:");
984	BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8:");
985	BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16:");
986	BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16:");
987	BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32:");
988	BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32:");
989	BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64:");
990	BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64:");
991	BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8:");
992	BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8:");
993	BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16:");
994	BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16:");
995	BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32:");
996	BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32:");
997	BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64:");
998	BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64:");
999	BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8:");
1000	BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8:");
1001	BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16:");
1002	BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16:");
1003	BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32:");
1004	BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32:");
1005	BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64:");
1006	BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64:");
1007	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32:");
1008	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32:");
1009	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64:");
1010	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64:");
1011	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg:");
1012	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg:");
1013	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg:");
1014	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg:");
1015	BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32:");
1016	BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32:");
1017	BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32:");
1018	BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32:");
1019	BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32:");
1020	BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32:");
1021
1022	RTPrintf("Done.\n");
1023
1024	#undef BENCH
1025	}
1026
1027
1028	int main(int argc, char *argv[])
1029	{
1030	RTR3Init();
1031	RTPrintf("tstInlineAsm: TESTING\n");
1032
1033	/*
1034	* Execute the tests.
1035	*/
1036	#if !defined(PIC) \|\| !defined(RT_ARCH_X86)
1037	tstASMCpuId();
1038	#endif
1039	tstASMAtomicXchgU8();
1040	tstASMAtomicXchgU16();
1041	tstASMAtomicXchgU32();
1042	tstASMAtomicXchgU64();
1043	#ifdef RT_ARCH_AMD64
1044	tstASMAtomicXchgU128();
1045	#endif
1046	tstASMAtomicXchgPtr();
1047	tstASMAtomicCmpXchgU32();
1048	tstASMAtomicCmpXchgU64();
1049	tstASMAtomicCmpXchgExU32();
1050	tstASMAtomicCmpXchgExU64();
1051	tstASMAtomicReadU64();
1052	tstASMAtomicAddS32();
1053	tstASMAtomicDecIncS32();
1054	tstASMAtomicAndOrU32();
1055	tstASMMemZeroPage();
1056	tstASMMath();
1057
1058	tstASMBench();
1059
1060	/*
1061	* Show the result.
1062	*/
1063	if (!g_cErrors)
1064	RTPrintf("tstInlineAsm: SUCCESS\n", g_cErrors);
1065	else
1066	RTPrintf("tstInlineAsm: FAILURE - %d errors\n", g_cErrors);
1067	return !!g_cErrors;
1068	}
1069

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source: vbox/trunk/src/VBox/Runtime/testcase/tstInlineAsm.cpp@ 8774

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