tstInlineAsm.cpp@ 918

Last change on this file since 918 was 639, checked in by vboxsync, 18 years ago
Be careful with 32-bit types and registers. (it seems like it was working fine here with 4.1.1 but obviously not for everyone.)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 27.8 KB

Line
1	/* $Id: tstInlineAsm.cpp 639 2007-02-05 14:25:02Z vboxsync $ */
2	/** @file
3	* InnoTek Portable Runtime Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#include <iprt/asm.h>
26	#include <iprt/stream.h>
27	#include <iprt/string.h>
28	#include <iprt/runtime.h>
29	#include <iprt/param.h>
30
31
32	/*******************************************************************************
33	* Global Variables *
34	*******************************************************************************/
35	/** Global error count. */
36	static unsigned g_cErrors;
37
38
39	/*******************************************************************************
40	* Defined Constants And Macros *
41	*******************************************************************************/
42	#define CHECKVAL(val, expect, fmt) \
43	do \
44	{ \
45	if ((val) != (expect)) \
46	{ \
47	g_cErrors++; \
48	RTPrintf("%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
49	} \
50	} while (0)
51
52	#define CHECKOP(op, expect, fmt, type) \
53	do \
54	{ \
55	type val = op; \
56	if (val != (type)(expect)) \
57	{ \
58	g_cErrors++; \
59	RTPrintf("%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
60	} \
61	} while (0)
62
63
64	#if !defined(PIC) \|\| !defined(__X86__)
65	const char *getCacheAss(unsigned u)
66	{
67	if (u == 0)
68	return "res0 ";
69	if (u == 1)
70	return "direct";
71	if (u >= 256)
72	return "???";
73
74	char *pszRet;
75	RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
76	return pszRet;
77	}
78
79
80	const char *getL2CacheAss(unsigned u)
81	{
82	switch (u)
83	{
84	case 0: return "off ";
85	case 1: return "direct";
86	case 2: return "2 way ";
87	case 3: return "res3 ";
88	case 4: return "4 way ";
89	case 5: return "res5 ";
90	case 6: return "8 way ";
91	case 7: return "res7 ";
92	case 8: return "16 way";
93	case 9: return "res9 ";
94	case 10: return "res10 ";
95	case 11: return "res11 ";
96	case 12: return "res12 ";
97	case 13: return "res13 ";
98	case 14: return "res14 ";
99	case 15: return "fully ";
100	default:
101	return "????";
102	}
103	}
104
105
106	/**
107	* Test and dump all possible info from the CPUID instruction.
108	*
109	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
110	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
111	*/
112	void tstASMCpuId(void)
113	{
114	unsigned iBit;
115	struct
116	{
117	uint32_t uEBX, uEAX, uEDX, uECX;
118	} s;
119	if (!ASMHasCpuId())
120	{
121	RTPrintf("tstInlineAsm: warning! CPU doesn't support CPUID\n");
122	return;
123	}
124
125	/*
126	* Try the 0 function and use that for checking the ASMCpuId_* variants.
127	*/
128	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
129
130	uint32_t u32 = ASMCpuId_ECX(0);
131	CHECKVAL(u32, s.uECX, "%x");
132
133	u32 = ASMCpuId_EDX(0);
134	CHECKVAL(u32, s.uEDX, "%x");
135
136	uint32_t uECX2 = s.uECX - 1;
137	uint32_t uEDX2 = s.uEDX - 1;
138	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
139
140	CHECKVAL(uECX2, s.uECX, "%x");
141	CHECKVAL(uEDX2, s.uEDX, "%x");
142
143	/*
144	* Done testing, dump the information.
145	*/
146	RTPrintf("tstInlineAsm: CPUID Dump\n");
147	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
148	const uint32_t cFunctions = s.uEAX;
149
150	/* raw dump */
151	RTPrintf("\n"
152	" RAW Standard CPUIDs\n"
153	"Function eax ebx ecx edx\n");
154	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
155	{
156	ASMCpuId(iStd, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
157	RTPrintf("%08x %08x %08x %08x %08x%s\n",
158	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
159	}
160
161	/*
162	* Understandable output
163	*/
164	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
165	RTPrintf("Name: %.04s%.04s%.04s\n"
166	"Support: 0-%u\n",
167	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
168
169	/*
170	* Get Features.
171	*/
172	if (cFunctions >= 1)
173	{
174	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
175	RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
176	"Model: %d \tExtended: %d \tEffectiv: %d\n"
177	"Stepping: %d\n"
178	"APIC ID: %#04x\n"
179	"Logical CPUs: %d\n"
180	"CLFLUSH Size: %d\n"
181	"Brand ID: %#04x\n",
182	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
183	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) \| (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
184	(s.uEAX >> 0) & 0xf,
185	(s.uEBX >> 24) & 0xff,
186	(s.uEBX >> 16) & 0xff,
187	(s.uEBX >> 8) & 0xff,
188	(s.uEBX >> 0) & 0xff);
189
190	RTPrintf("Features EDX: ");
191	if (s.uEDX & BIT(0)) RTPrintf(" FPU");
192	if (s.uEDX & BIT(1)) RTPrintf(" VME");
193	if (s.uEDX & BIT(2)) RTPrintf(" DE");
194	if (s.uEDX & BIT(3)) RTPrintf(" PSE");
195	if (s.uEDX & BIT(4)) RTPrintf(" TSC");
196	if (s.uEDX & BIT(5)) RTPrintf(" MSR");
197	if (s.uEDX & BIT(6)) RTPrintf(" PAE");
198	if (s.uEDX & BIT(7)) RTPrintf(" MCE");
199	if (s.uEDX & BIT(8)) RTPrintf(" CX8");
200	if (s.uEDX & BIT(9)) RTPrintf(" APIC");
201	if (s.uEDX & BIT(10)) RTPrintf(" 10");
202	if (s.uEDX & BIT(11)) RTPrintf(" SEP");
203	if (s.uEDX & BIT(12)) RTPrintf(" MTRR");
204	if (s.uEDX & BIT(13)) RTPrintf(" PGE");
205	if (s.uEDX & BIT(14)) RTPrintf(" MCA");
206	if (s.uEDX & BIT(15)) RTPrintf(" CMOV");
207	if (s.uEDX & BIT(16)) RTPrintf(" PAT");
208	if (s.uEDX & BIT(17)) RTPrintf(" PSE36");
209	if (s.uEDX & BIT(18)) RTPrintf(" PSN");
210	if (s.uEDX & BIT(19)) RTPrintf(" CLFSH");
211	if (s.uEDX & BIT(20)) RTPrintf(" 20");
212	if (s.uEDX & BIT(21)) RTPrintf(" DS");
213	if (s.uEDX & BIT(22)) RTPrintf(" ACPI");
214	if (s.uEDX & BIT(23)) RTPrintf(" MMX");
215	if (s.uEDX & BIT(24)) RTPrintf(" FXSR");
216	if (s.uEDX & BIT(25)) RTPrintf(" SSE");
217	if (s.uEDX & BIT(26)) RTPrintf(" SSE2");
218	if (s.uEDX & BIT(27)) RTPrintf(" SS");
219	if (s.uEDX & BIT(28)) RTPrintf(" HTT");
220	if (s.uEDX & BIT(29)) RTPrintf(" 29");
221	if (s.uEDX & BIT(30)) RTPrintf(" 30");
222	if (s.uEDX & BIT(31)) RTPrintf(" 31");
223	RTPrintf("\n");
224
225	/** @todo check intel docs. */
226	RTPrintf("Features ECX: ");
227	if (s.uECX & BIT(0)) RTPrintf(" SSE3");
228	for (iBit = 1; iBit < 13; iBit++)
229	if (s.uECX & BIT(iBit))
230	RTPrintf(" %d", iBit);
231	if (s.uECX & BIT(13)) RTPrintf(" CX16");
232	for (iBit = 14; iBit < 32; iBit++)
233	if (s.uECX & BIT(iBit))
234	RTPrintf(" %d", iBit);
235	RTPrintf("\n");
236	}
237
238	/*
239	* Extended.
240	* Implemented after AMD specs.
241	*/
242	/** @todo check out the intel specs. */
243	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
244	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
245	{
246	RTPrintf("No extended CPUID info? Check the manual on how to detect this...\n");
247	return;
248	}
249	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
250
251	/* raw dump */
252	RTPrintf("\n"
253	" RAW Extended CPUIDs\n"
254	"Function eax ebx ecx edx\n");
255	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
256	{
257	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
258	RTPrintf("%08x %08x %08x %08x %08x%s\n",
259	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
260	}
261
262	/*
263	* Understandable output
264	*/
265	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
266	RTPrintf("Ext Name: %.4s%.4s%.4s\n"
267	"Ext Supports: 0x80000000-%#010x\n",
268	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
269
270	if (cExtFunctions >= 0x80000001)
271	{
272	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
273	RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
274	"Model: %d \tExtended: %d \tEffectiv: %d\n"
275	"Stepping: %d\n"
276	"Brand ID: %#05x\n",
277	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
278	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) \| (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
279	(s.uEAX >> 0) & 0xf,
280	s.uEBX & 0xfff);
281
282	RTPrintf("Features EDX: ");
283	if (s.uEDX & BIT(0)) RTPrintf(" FPU");
284	if (s.uEDX & BIT(1)) RTPrintf(" VME");
285	if (s.uEDX & BIT(2)) RTPrintf(" DE");
286	if (s.uEDX & BIT(3)) RTPrintf(" PSE");
287	if (s.uEDX & BIT(4)) RTPrintf(" TSC");
288	if (s.uEDX & BIT(5)) RTPrintf(" MSR");
289	if (s.uEDX & BIT(6)) RTPrintf(" PAE");
290	if (s.uEDX & BIT(7)) RTPrintf(" MCE");
291	if (s.uEDX & BIT(8)) RTPrintf(" CX8");
292	if (s.uEDX & BIT(9)) RTPrintf(" APIC");
293	if (s.uEDX & BIT(10)) RTPrintf(" 10");
294	if (s.uEDX & BIT(11)) RTPrintf(" SCR");
295	if (s.uEDX & BIT(12)) RTPrintf(" MTRR");
296	if (s.uEDX & BIT(13)) RTPrintf(" PGE");
297	if (s.uEDX & BIT(14)) RTPrintf(" MCA");
298	if (s.uEDX & BIT(15)) RTPrintf(" CMOV");
299	if (s.uEDX & BIT(16)) RTPrintf(" PAT");
300	if (s.uEDX & BIT(17)) RTPrintf(" PSE36");
301	if (s.uEDX & BIT(18)) RTPrintf(" 18");
302	if (s.uEDX & BIT(19)) RTPrintf(" 19");
303	if (s.uEDX & BIT(20)) RTPrintf(" NX");
304	if (s.uEDX & BIT(21)) RTPrintf(" 21");
305	if (s.uEDX & BIT(22)) RTPrintf(" ExtMMX");
306	if (s.uEDX & BIT(23)) RTPrintf(" MMX");
307	if (s.uEDX & BIT(24)) RTPrintf(" FXSR");
308	if (s.uEDX & BIT(25)) RTPrintf(" FastFXSR");
309	if (s.uEDX & BIT(26)) RTPrintf(" 26");
310	if (s.uEDX & BIT(27)) RTPrintf(" RDTSCP");
311	if (s.uEDX & BIT(28)) RTPrintf(" 29");
312	if (s.uEDX & BIT(29)) RTPrintf(" LongMode");
313	if (s.uEDX & BIT(30)) RTPrintf(" Ext3DNow");
314	if (s.uEDX & BIT(31)) RTPrintf(" 3DNow");
315	RTPrintf("\n");
316
317	/** @todo Check intel docs. */
318	RTPrintf("Features ECX: ");
319	if (s.uECX & BIT(0)) RTPrintf(" LAHF/SAHF");
320	if (s.uECX & BIT(1)) RTPrintf(" CMPL");
321	if (s.uECX & BIT(2)) RTPrintf(" 2");
322	if (s.uECX & BIT(3)) RTPrintf(" 3");
323	if (s.uECX & BIT(4)) RTPrintf(" CR8L");
324	for (iBit = 5; iBit < 32; iBit++)
325	if (s.uECX & BIT(iBit))
326	RTPrintf(" %d", iBit);
327	RTPrintf("\n");
328	}
329
330	char szString[443+1] = {0};
331	if (cExtFunctions >= 0x80000002)
332	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
333	if (cExtFunctions >= 0x80000003)
334	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
335	if (cExtFunctions >= 0x80000004)
336	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
337	if (cExtFunctions >= 0x80000002)
338	RTPrintf("Full Name: %s\n", szString);
339
340	if (cExtFunctions >= 0x80000005)
341	{
342	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
343	RTPrintf("TLB 2/4M Instr/Uni: %s %3d entries\n"
344	"TLB 2/4M Data: %s %3d entries\n",
345	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
346	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
347	RTPrintf("TLB 4K Instr/Uni: %s %3d entries\n"
348	"TLB 4K Data: %s %3d entries\n",
349	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
350	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
351	RTPrintf("L1 Instr Cache Line Size: %d bytes\n"
352	"L1 Instr Cache Lines Per Tag: %d\n"
353	"L1 Instr Cache Associativity: %s\n"
354	"L1 Instr Cache Size: %d KB\n",
355	(s.uEDX >> 0) & 0xff,
356	(s.uEDX >> 8) & 0xff,
357	getCacheAss((s.uEDX >> 16) & 0xff),
358	(s.uEDX >> 24) & 0xff);
359	RTPrintf("L1 Data Cache Line Size: %d bytes\n"
360	"L1 Data Cache Lines Per Tag: %d\n"
361	"L1 Data Cache Associativity: %s\n"
362	"L1 Data Cache Size: %d KB\n",
363	(s.uECX >> 0) & 0xff,
364	(s.uECX >> 8) & 0xff,
365	getCacheAss((s.uECX >> 16) & 0xff),
366	(s.uECX >> 24) & 0xff);
367	}
368
369	if (cExtFunctions >= 0x80000006)
370	{
371	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
372	RTPrintf("L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
373	"L2 TLB 2/4M Data: %s %4d entries\n",
374	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
375	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
376	RTPrintf("L2 TLB 4K Instr/Uni: %s %4d entries\n"
377	"L2 TLB 4K Data: %s %4d entries\n",
378	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
379	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
380	RTPrintf("L2 Cache Line Size: %d bytes\n"
381	"L2 Cache Lines Per Tag: %d\n"
382	"L2 Cache Associativity: %s\n"
383	"L2 Cache Size: %d KB\n",
384	(s.uEDX >> 0) & 0xff,
385	(s.uEDX >> 8) & 0xf,
386	getL2CacheAss((s.uEDX >> 12) & 0xf),
387	(s.uEDX >> 16) & 0xffff);
388	}
389
390	if (cExtFunctions >= 0x80000007)
391	{
392	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
393	RTPrintf("APM Features: ");
394	if (s.uEDX & BIT(0)) RTPrintf(" TS");
395	if (s.uEDX & BIT(1)) RTPrintf(" FID");
396	if (s.uEDX & BIT(2)) RTPrintf(" VID");
397	if (s.uEDX & BIT(3)) RTPrintf(" TTP");
398	if (s.uEDX & BIT(4)) RTPrintf(" TM");
399	if (s.uEDX & BIT(5)) RTPrintf(" STC");
400	for (iBit = 6; iBit < 32; iBit++)
401	if (s.uEDX & BIT(iBit))
402	RTPrintf(" %d", iBit);
403	RTPrintf("\n");
404	}
405
406	if (cExtFunctions >= 0x80000008)
407	{
408	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
409	RTPrintf("Physical Address Width: %d bits\n"
410	"Virtual Address Width: %d bits\n",
411	(s.uEAX >> 0) & 0xff,
412	(s.uEAX >> 8) & 0xff);
413	RTPrintf("Physical Core Count: %d\n",
414	(s.uECX >> 0) & 0xff);
415	}
416	}
417	#endif /* !PIC \|\| !X86 */
418
419
420	static void tstASMAtomicXchgU8(void)
421	{
422	struct
423	{
424	uint8_t u8Dummy0;
425	uint8_t u8;
426	uint8_t u8Dummy1;
427	} s;
428
429	s.u8 = 0;
430	s.u8Dummy0 = s.u8Dummy1 = 0x42;
431	CHECKOP(ASMAtomicXchgU8(&s.u8, 1), 0, "%#x", uint8_t);
432	CHECKVAL(s.u8, 1, "%#x");
433
434	CHECKOP(ASMAtomicXchgU8(&s.u8, 0), 1, "%#x", uint8_t);
435	CHECKVAL(s.u8, 0, "%#x");
436
437	CHECKOP(ASMAtomicXchgU8(&s.u8, 0xff), 0, "%#x", uint8_t);
438	CHECKVAL(s.u8, 0xff, "%#x");
439
440	CHECKOP(ASMAtomicXchgU8(&s.u8, 0x87), 0xffff, "%#x", uint8_t);
441	CHECKVAL(s.u8, 0x87, "%#x");
442	CHECKVAL(s.u8Dummy0, 0x42, "%#x");
443	CHECKVAL(s.u8Dummy1, 0x42, "%#x");
444	}
445
446
447	static void tstASMAtomicXchgU16(void)
448	{
449	struct
450	{
451	uint16_t u16Dummy0;
452	uint16_t u16;
453	uint16_t u16Dummy1;
454	} s;
455
456	s.u16 = 0;
457	s.u16Dummy0 = s.u16Dummy1 = 0x1234;
458	CHECKOP(ASMAtomicXchgU16(&s.u16, 1), 0, "%#x", uint16_t);
459	CHECKVAL(s.u16, 1, "%#x");
460
461	CHECKOP(ASMAtomicXchgU16(&s.u16, 0), 1, "%#x", uint16_t);
462	CHECKVAL(s.u16, 0, "%#x");
463
464	CHECKOP(ASMAtomicXchgU16(&s.u16, 0xffff), 0, "%#x", uint16_t);
465	CHECKVAL(s.u16, 0xffff, "%#x");
466
467	CHECKOP(ASMAtomicXchgU16(&s.u16, 0x8765), 0xffff, "%#x", uint16_t);
468	CHECKVAL(s.u16, 0x8765, "%#x");
469	CHECKVAL(s.u16Dummy0, 0x1234, "%#x");
470	CHECKVAL(s.u16Dummy1, 0x1234, "%#x");
471	}
472
473
474	static void tstASMAtomicXchgU32(void)
475	{
476	struct
477	{
478	uint32_t u32Dummy0;
479	uint32_t u32;
480	uint32_t u32Dummy1;
481	} s;
482
483	s.u32 = 0;
484	s.u32Dummy0 = s.u32Dummy1 = 0x11223344;
485
486	CHECKOP(ASMAtomicXchgU32(&s.u32, 1), 0, "%#x", uint32_t);
487	CHECKVAL(s.u32, 1, "%#x");
488
489	CHECKOP(ASMAtomicXchgU32(&s.u32, 0), 1, "%#x", uint32_t);
490	CHECKVAL(s.u32, 0, "%#x");
491
492	CHECKOP(ASMAtomicXchgU32(&s.u32, ~0U), 0, "%#x", uint32_t);
493	CHECKVAL(s.u32, ~0U, "%#x");
494
495	CHECKOP(ASMAtomicXchgU32(&s.u32, 0x87654321), ~0U, "%#x", uint32_t);
496	CHECKVAL(s.u32, 0x87654321, "%#x");
497
498	CHECKVAL(s.u32Dummy0, 0x11223344, "%#x");
499	CHECKVAL(s.u32Dummy1, 0x11223344, "%#x");
500	}
501
502
503	static void tstASMAtomicXchgU64(void)
504	{
505	struct
506	{
507	uint64_t u64Dummy0;
508	uint64_t u64;
509	uint64_t u64Dummy1;
510	} s;
511
512	s.u64 = 0;
513	s.u64Dummy0 = s.u64Dummy1 = 0x1122334455667788ULL;
514
515	CHECKOP(ASMAtomicXchgU64(&s.u64, 1), 0ULL, "%#llx", uint64_t);
516	CHECKVAL(s.u64, 1ULL, "%#llx");
517
518	CHECKOP(ASMAtomicXchgU64(&s.u64, 0), 1ULL, "%#llx", uint64_t);
519	CHECKVAL(s.u64, 0ULL, "%#llx");
520
521	CHECKOP(ASMAtomicXchgU64(&s.u64, ~0ULL), 0ULL, "%#llx", uint64_t);
522	CHECKVAL(s.u64, ~0ULL, "%#llx");
523
524	CHECKOP(ASMAtomicXchgU64(&s.u64, 0xfedcba0987654321ULL), ~0ULL, "%#llx", uint64_t);
525	CHECKVAL(s.u64, 0xfedcba0987654321ULL, "%#llx");
526
527	CHECKVAL(s.u64Dummy0, 0x1122334455667788ULL, "%#x");
528	CHECKVAL(s.u64Dummy1, 0x1122334455667788ULL, "%#x");
529	}
530
531
532	#ifdef __AMD64__
533	static void tstASMAtomicXchgU128(void)
534	{
535	struct
536	{
537	RTUINT128U u128Dummy0;
538	RTUINT128U u128;
539	RTUINT128U u128Dummy1;
540	} s;
541	RTUINT128U u128Ret;
542	RTUINT128U u128Arg;
543
544
545	s.u128Dummy0.s.Lo = s.u128Dummy0.s.Hi = 0x1122334455667788;
546	s.u128.s.Lo = 0;
547	s.u128.s.Hi = 0;
548	s.u128Dummy1 = s.u128Dummy0;
549
550	u128Arg.s.Lo = 1;
551	u128Arg.s.Hi = 0;
552	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
553	CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
554	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
555	CHECKVAL(s.u128.s.Lo, 1ULL, "%#llx");
556	CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
557
558	u128Arg.s.Lo = 0;
559	u128Arg.s.Hi = 0;
560	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
561	CHECKVAL(u128Ret.s.Lo, 1ULL, "%#llx");
562	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
563	CHECKVAL(s.u128.s.Lo, 0ULL, "%#llx");
564	CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
565
566	u128Arg.s.Lo = ~0ULL;
567	u128Arg.s.Hi = ~0ULL;
568	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
569	CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
570	CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
571	CHECKVAL(s.u128.s.Lo, ~0ULL, "%#llx");
572	CHECKVAL(s.u128.s.Hi, ~0ULL, "%#llx");
573
574
575	u128Arg.s.Lo = 0xfedcba0987654321ULL;
576	u128Arg.s.Hi = 0x8897a6b5c4d3e2f1ULL;
577	u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
578	CHECKVAL(u128Ret.s.Lo, ~0ULL, "%#llx");
579	CHECKVAL(u128Ret.s.Hi, ~0ULL, "%#llx");
580	CHECKVAL(s.u128.s.Lo, 0xfedcba0987654321ULL, "%#llx");
581	CHECKVAL(s.u128.s.Hi, 0x8897a6b5c4d3e2f1ULL, "%#llx");
582
583	CHECKVAL(s.u128Dummy0.s.Lo, 0x1122334455667788, "%#llx");
584	CHECKVAL(s.u128Dummy0.s.Hi, 0x1122334455667788, "%#llx");
585	CHECKVAL(s.u128Dummy1.s.Lo, 0x1122334455667788, "%#llx");
586	CHECKVAL(s.u128Dummy1.s.Hi, 0x1122334455667788, "%#llx");
587	}
588	#endif
589
590
591	static void tstASMAtomicXchgPtr(void)
592	{
593	void *pv = NULL;
594
595	CHECKOP(ASMAtomicXchgPtr(&pv, (void )(~(uintptr_t)0)), NULL, "%p", void );
596	CHECKVAL(pv, (void *)(~(uintptr_t)0), "%p");
597
598	CHECKOP(ASMAtomicXchgPtr(&pv, (void )0x87654321), (void )(~(uintptr_t)0), "%p", void *);
599	CHECKVAL(pv, (void *)0x87654321, "%p");
600
601	CHECKOP(ASMAtomicXchgPtr(&pv, NULL), (void )0x87654321, "%p", void );
602	CHECKVAL(pv, NULL, "%p");
603	}
604
605
606	static void tstASMAtomicCmpXchgU32(void)
607	{
608	uint32_t u32 = 0xffffffff;
609
610	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0), false, "%d", bool);
611	CHECKVAL(u32, 0xffffffff, "%x");
612
613	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0xffffffff), true, "%d", bool);
614	CHECKVAL(u32, 0, "%x");
615
616	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0xffffffff), false, "%d", bool);
617	CHECKVAL(u32, 0, "%x");
618
619	CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0), true, "%d", bool);
620	CHECKVAL(u32, 0x8008efd, "%x");
621	}
622
623
624	static void tstASMAtomicCmpXchgU64(void)
625	{
626	uint64_t u64 = 0xffffffffffffffULL;
627
628	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0), false, "%d", bool);
629	CHECKVAL(u64, 0xffffffffffffffULL, "%x");
630
631	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0xffffffffffffffULL), true, "%d", bool);
632	CHECKVAL(u64, 0, "%x");
633
634	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff), false, "%d", bool);
635	CHECKVAL(u64, 0, "%x");
636
637	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff00000000ULL), false, "%d", bool);
638	CHECKVAL(u64, 0, "%x");
639
640	CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0), true, "%d", bool);
641	CHECKVAL(u64, 0x80040008008efdULL, "%x");
642	}
643
644
645	static void tstASMAtomicReadU64(void)
646	{
647	uint64_t u64 = 0;
648
649	CHECKOP(ASMAtomicReadU64(&u64), 0ULL, "%#llx", uint64_t);
650	CHECKVAL(u64, 0ULL, "%#llx");
651
652	u64 = ~0ULL;
653	CHECKOP(ASMAtomicReadU64(&u64), ~0ULL, "%#llx", uint64_t);
654	CHECKVAL(u64, ~0ULL, "%#llx");
655
656	u64 = 0xfedcba0987654321ULL;
657	CHECKOP(ASMAtomicReadU64(&u64), 0xfedcba0987654321ULL, "%#llx", uint64_t);
658	CHECKVAL(u64, 0xfedcba0987654321ULL, "%#llx");
659	}
660
661
662	static void tstASMAtomicDecIncS32(void)
663	{
664	int32_t i32Rc;
665	int32_t i32 = 10;
666	#define MYCHECK(op, rc) \
667	do { \
668	i32Rc = op; \
669	if (i32Rc != (rc)) \
670	{ \
671	RTPrintf("%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
672	g_cErrors++; \
673	} \
674	if (i32 != (rc)) \
675	{ \
676	RTPrintf("%s, %d: FAILURE: %s => i32=%d expected %d\n", __FUNCTION__, __LINE__, #op, i32, rc); \
677	g_cErrors++; \
678	} \
679	} while (0)
680	MYCHECK(ASMAtomicDecS32(&i32), 9);
681	MYCHECK(ASMAtomicDecS32(&i32), 8);
682	MYCHECK(ASMAtomicDecS32(&i32), 7);
683	MYCHECK(ASMAtomicDecS32(&i32), 6);
684	MYCHECK(ASMAtomicDecS32(&i32), 5);
685	MYCHECK(ASMAtomicDecS32(&i32), 4);
686	MYCHECK(ASMAtomicDecS32(&i32), 3);
687	MYCHECK(ASMAtomicDecS32(&i32), 2);
688	MYCHECK(ASMAtomicDecS32(&i32), 1);
689	MYCHECK(ASMAtomicDecS32(&i32), 0);
690	MYCHECK(ASMAtomicDecS32(&i32), -1);
691	MYCHECK(ASMAtomicDecS32(&i32), -2);
692	MYCHECK(ASMAtomicIncS32(&i32), -1);
693	MYCHECK(ASMAtomicIncS32(&i32), 0);
694	MYCHECK(ASMAtomicIncS32(&i32), 1);
695	MYCHECK(ASMAtomicIncS32(&i32), 2);
696	MYCHECK(ASMAtomicIncS32(&i32), 3);
697	MYCHECK(ASMAtomicDecS32(&i32), 2);
698	MYCHECK(ASMAtomicIncS32(&i32), 3);
699	MYCHECK(ASMAtomicDecS32(&i32), 2);
700	MYCHECK(ASMAtomicIncS32(&i32), 3);
701	#undef MYCHECK
702
703	}
704
705
706	static void tstASMAtomicAndOrU32(void)
707	{
708	uint32_t u32 = 0xffffffff;
709
710	ASMAtomicOrU32(&u32, 0xffffffff);
711	CHECKVAL(u32, 0xffffffff, "%x");
712
713	ASMAtomicAndU32(&u32, 0xffffffff);
714	CHECKVAL(u32, 0xffffffff, "%x");
715
716	ASMAtomicAndU32(&u32, 0x8f8f8f8f);
717	CHECKVAL(u32, 0x8f8f8f8f, "%x");
718
719	ASMAtomicOrU32(&u32, 0x70707070);
720	CHECKVAL(u32, 0xffffffff, "%x");
721
722	ASMAtomicAndU32(&u32, 1);
723	CHECKVAL(u32, 1, "%x");
724
725	ASMAtomicOrU32(&u32, 0x80000000);
726	CHECKVAL(u32, 0x80000001, "%x");
727
728	ASMAtomicAndU32(&u32, 0x80000000);
729	CHECKVAL(u32, 0x80000000, "%x");
730
731	ASMAtomicAndU32(&u32, 0);
732	CHECKVAL(u32, 0, "%x");
733
734	ASMAtomicOrU32(&u32, 0x42424242);
735	CHECKVAL(u32, 0x42424242, "%x");
736	}
737
738
739	void tstASMMemZeroPage(void)
740	{
741	struct
742	{
743	uint64_t u64Magic1;
744	uint8_t abPage[PAGE_SIZE];
745	uint64_t u64Magic2;
746	} Buf1, Buf2, Buf3;
747
748	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
749	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
750	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
751	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
752	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
753	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
754	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
755	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
756	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
757	ASMMemZeroPage(Buf1.abPage);
758	ASMMemZeroPage(Buf2.abPage);
759	ASMMemZeroPage(Buf3.abPage);
760	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
761	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
762	\|\| Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
763	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
764	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
765	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff))
766	{
767	RTPrintf("tstInlineAsm: ASMMemZeroPage violated one/both magic(s)!\n");
768	g_cErrors++;
769	}
770	for (unsigned i = 0; i < sizeof(Buf1.abPage); i++)
771	if (Buf1.abPage[i])
772	{
773	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
774	g_cErrors++;
775	}
776	for (unsigned i = 0; i < sizeof(Buf1.abPage); i++)
777	if (Buf1.abPage[i])
778	{
779	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
780	g_cErrors++;
781	}
782	for (unsigned i = 0; i < sizeof(Buf2.abPage); i++)
783	if (Buf2.abPage[i])
784	{
785	RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
786	g_cErrors++;
787	}
788	}
789
790
791	void tstASMMath(void)
792	{
793	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
794	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
795
796	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
797	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
798	}
799
800
801	int main(int argc, char *argv[])
802	{
803	RTR3Init();
804	RTPrintf("tstInlineAsm: TESTING\n");
805
806	/*
807	* Execute the tests.
808	*/
809	#if !defined(PIC) \|\| !defined(__X86__)
810	tstASMCpuId();
811	#endif
812	tstASMAtomicXchgU8();
813	tstASMAtomicXchgU16();
814	tstASMAtomicXchgU32();
815	tstASMAtomicXchgU64();
816	#ifdef __AMD64__
817	tstASMAtomicXchgU128();
818	#endif
819	tstASMAtomicXchgPtr();
820	tstASMAtomicCmpXchgU32();
821	tstASMAtomicCmpXchgU64();
822	tstASMAtomicReadU64();
823	tstASMAtomicDecIncS32();
824	tstASMAtomicAndOrU32();
825	tstASMMemZeroPage();
826	tstASMMath();
827
828	/*
829	* Show the result.
830	*/
831	if (!g_cErrors)
832	RTPrintf("tstInlineAsm: SUCCESS\n", g_cErrors);
833	else
834	RTPrintf("tstInlineAsm: FAILURE - %d errors\n", g_cErrors);
835	return !!g_cErrors;
836	}
837

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source: vbox/trunk/src/VBox/Runtime/testcase/tstInlineAsm.cpp@ 918

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