| 1 | /* $Id: tstInlineAsm.cpp 9909 2008-06-25 11:47:50Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IPRT Testcase - inline assembly.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * The contents of this file may alternatively be used under the terms
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| 18 | * of the Common Development and Distribution License Version 1.0
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| 19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | * VirtualBox OSE distribution, in which case the provisions of the
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| 21 | * CDDL are applicable instead of those of the GPL.
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| 22 | *
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| 23 | * You may elect to license modified versions of this file under the
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| 24 | * terms and conditions of either the GPL or the CDDL or both.
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| 25 | *
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| 26 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 27 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 28 | * additional information or have any questions.
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| 29 | */
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| 30 |
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| 31 | /*******************************************************************************
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| 32 | * Header Files *
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| 33 | *******************************************************************************/
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| 34 | #include <iprt/asm.h>
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| 35 | #include <iprt/stream.h>
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| 36 | #include <iprt/string.h>
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| 37 | #include <iprt/runtime.h>
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| 38 | #include <iprt/param.h>
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| 39 |
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| 40 |
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| 41 | /*******************************************************************************
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| 42 | * Global Variables *
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| 43 | *******************************************************************************/
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| 44 | /** Global error count. */
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| 45 | static unsigned g_cErrors;
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| 46 |
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| 47 |
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| 48 | /*******************************************************************************
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| 49 | * Defined Constants And Macros *
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| 50 | *******************************************************************************/
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| 51 | #define CHECKVAL(val, expect, fmt) \
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| 52 | do \
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| 53 | { \
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| 54 | if ((val) != (expect)) \
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| 55 | { \
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| 56 | g_cErrors++; \
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| 57 | RTPrintf("%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
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| 58 | } \
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| 59 | } while (0)
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| 60 |
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| 61 | #define CHECKOP(op, expect, fmt, type) \
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| 62 | do \
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| 63 | { \
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| 64 | type val = op; \
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| 65 | if (val != (type)(expect)) \
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| 66 | { \
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| 67 | g_cErrors++; \
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| 68 | RTPrintf("%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
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| 69 | } \
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| 70 | } while (0)
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| 71 |
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| 72 |
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| 73 | #if !defined(PIC) || !defined(RT_ARCH_X86)
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| 74 | const char *getCacheAss(unsigned u)
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| 75 | {
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| 76 | if (u == 0)
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| 77 | return "res0 ";
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| 78 | if (u == 1)
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| 79 | return "direct";
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| 80 | if (u >= 256)
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| 81 | return "???";
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| 82 |
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| 83 | char *pszRet;
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| 84 | RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
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| 85 | return pszRet;
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| 86 | }
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| 87 |
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| 88 |
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| 89 | const char *getL2CacheAss(unsigned u)
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| 90 | {
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| 91 | switch (u)
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| 92 | {
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| 93 | case 0: return "off ";
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| 94 | case 1: return "direct";
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| 95 | case 2: return "2 way ";
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| 96 | case 3: return "res3 ";
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| 97 | case 4: return "4 way ";
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| 98 | case 5: return "res5 ";
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| 99 | case 6: return "8 way ";
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| 100 | case 7: return "res7 ";
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| 101 | case 8: return "16 way";
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| 102 | case 9: return "res9 ";
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| 103 | case 10: return "res10 ";
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| 104 | case 11: return "res11 ";
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| 105 | case 12: return "res12 ";
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| 106 | case 13: return "res13 ";
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| 107 | case 14: return "res14 ";
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| 108 | case 15: return "fully ";
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| 109 | default:
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| 110 | return "????";
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| 111 | }
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| 112 | }
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| 113 |
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| 114 |
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| 115 | /**
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| 116 | * Test and dump all possible info from the CPUID instruction.
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| 117 | *
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| 118 | * @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
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| 119 | * @todo transform the dumping into a generic runtime function. We'll need it for logging!
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| 120 | */
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| 121 | void tstASMCpuId(void)
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| 122 | {
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| 123 | unsigned iBit;
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| 124 | struct
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| 125 | {
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| 126 | uint32_t uEBX, uEAX, uEDX, uECX;
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| 127 | } s;
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| 128 | if (!ASMHasCpuId())
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| 129 | {
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| 130 | RTPrintf("tstInlineAsm: warning! CPU doesn't support CPUID\n");
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| 131 | return;
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| 132 | }
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| 133 |
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| 134 | /*
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| 135 | * Try the 0 function and use that for checking the ASMCpuId_* variants.
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| 136 | */
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| 137 | ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 138 |
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| 139 | uint32_t u32 = ASMCpuId_ECX(0);
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| 140 | CHECKVAL(u32, s.uECX, "%x");
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| 141 |
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| 142 | u32 = ASMCpuId_EDX(0);
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| 143 | CHECKVAL(u32, s.uEDX, "%x");
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| 144 |
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| 145 | uint32_t uECX2 = s.uECX - 1;
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| 146 | uint32_t uEDX2 = s.uEDX - 1;
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| 147 | ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
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| 148 |
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| 149 | CHECKVAL(uECX2, s.uECX, "%x");
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| 150 | CHECKVAL(uEDX2, s.uEDX, "%x");
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| 151 |
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| 152 | /*
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| 153 | * Done testing, dump the information.
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| 154 | */
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| 155 | RTPrintf("tstInlineAsm: CPUID Dump\n");
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| 156 | ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 157 | const uint32_t cFunctions = s.uEAX;
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| 158 |
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| 159 | /* raw dump */
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| 160 | RTPrintf("\n"
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| 161 | " RAW Standard CPUIDs\n"
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| 162 | "Function eax ebx ecx edx\n");
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| 163 | for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
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| 164 | {
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| 165 | ASMCpuId(iStd, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 166 | RTPrintf("%08x %08x %08x %08x %08x%s\n",
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| 167 | iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
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| 168 | }
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| 169 |
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| 170 | /*
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| 171 | * Understandable output
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| 172 | */
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| 173 | ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 174 | RTPrintf("Name: %.04s%.04s%.04s\n"
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| 175 | "Support: 0-%u\n",
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| 176 | &s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
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| 177 | bool const fIntel = ASMIsIntelCpuEx(s.uEBX, s.uECX, s.uEDX);
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| 178 |
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| 179 | /*
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| 180 | * Get Features.
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| 181 | */
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| 182 | if (cFunctions >= 1)
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| 183 | {
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| 184 | ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 185 | RTPrintf("Family: %#x \tExtended: %#x \tEffective: %#x\n"
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| 186 | "Model: %#x \tExtended: %#x \tEffective: %#x\n"
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| 187 | "Stepping: %d\n"
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| 188 | "APIC ID: %#04x\n"
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| 189 | "Logical CPUs: %d\n"
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| 190 | "CLFLUSH Size: %d\n"
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| 191 | "Brand ID: %#04x\n",
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| 192 | (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
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| 193 | (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
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| 194 | ASMGetCpuStepping(s.uEAX),
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| 195 | (s.uEBX >> 24) & 0xff,
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| 196 | (s.uEBX >> 16) & 0xff,
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| 197 | (s.uEBX >> 8) & 0xff,
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| 198 | (s.uEBX >> 0) & 0xff);
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| 199 |
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| 200 | RTPrintf("Features EDX: ");
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| 201 | if (s.uEDX & RT_BIT(0)) RTPrintf(" FPU");
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| 202 | if (s.uEDX & RT_BIT(1)) RTPrintf(" VME");
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| 203 | if (s.uEDX & RT_BIT(2)) RTPrintf(" DE");
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| 204 | if (s.uEDX & RT_BIT(3)) RTPrintf(" PSE");
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| 205 | if (s.uEDX & RT_BIT(4)) RTPrintf(" TSC");
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| 206 | if (s.uEDX & RT_BIT(5)) RTPrintf(" MSR");
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| 207 | if (s.uEDX & RT_BIT(6)) RTPrintf(" PAE");
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| 208 | if (s.uEDX & RT_BIT(7)) RTPrintf(" MCE");
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| 209 | if (s.uEDX & RT_BIT(8)) RTPrintf(" CX8");
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| 210 | if (s.uEDX & RT_BIT(9)) RTPrintf(" APIC");
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| 211 | if (s.uEDX & RT_BIT(10)) RTPrintf(" 10");
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| 212 | if (s.uEDX & RT_BIT(11)) RTPrintf(" SEP");
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| 213 | if (s.uEDX & RT_BIT(12)) RTPrintf(" MTRR");
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| 214 | if (s.uEDX & RT_BIT(13)) RTPrintf(" PGE");
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| 215 | if (s.uEDX & RT_BIT(14)) RTPrintf(" MCA");
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| 216 | if (s.uEDX & RT_BIT(15)) RTPrintf(" CMOV");
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| 217 | if (s.uEDX & RT_BIT(16)) RTPrintf(" PAT");
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| 218 | if (s.uEDX & RT_BIT(17)) RTPrintf(" PSE36");
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| 219 | if (s.uEDX & RT_BIT(18)) RTPrintf(" PSN");
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| 220 | if (s.uEDX & RT_BIT(19)) RTPrintf(" CLFSH");
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| 221 | if (s.uEDX & RT_BIT(20)) RTPrintf(" 20");
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| 222 | if (s.uEDX & RT_BIT(21)) RTPrintf(" DS");
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| 223 | if (s.uEDX & RT_BIT(22)) RTPrintf(" ACPI");
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| 224 | if (s.uEDX & RT_BIT(23)) RTPrintf(" MMX");
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| 225 | if (s.uEDX & RT_BIT(24)) RTPrintf(" FXSR");
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| 226 | if (s.uEDX & RT_BIT(25)) RTPrintf(" SSE");
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| 227 | if (s.uEDX & RT_BIT(26)) RTPrintf(" SSE2");
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| 228 | if (s.uEDX & RT_BIT(27)) RTPrintf(" SS");
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| 229 | if (s.uEDX & RT_BIT(28)) RTPrintf(" HTT");
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| 230 | if (s.uEDX & RT_BIT(29)) RTPrintf(" 29");
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| 231 | if (s.uEDX & RT_BIT(30)) RTPrintf(" 30");
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| 232 | if (s.uEDX & RT_BIT(31)) RTPrintf(" 31");
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| 233 | RTPrintf("\n");
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| 234 |
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| 235 | /** @todo check intel docs. */
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| 236 | RTPrintf("Features ECX: ");
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| 237 | if (s.uECX & RT_BIT(0)) RTPrintf(" SSE3");
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| 238 | for (iBit = 1; iBit < 13; iBit++)
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| 239 | if (s.uECX & RT_BIT(iBit))
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| 240 | RTPrintf(" %d", iBit);
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| 241 | if (s.uECX & RT_BIT(13)) RTPrintf(" CX16");
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| 242 | for (iBit = 14; iBit < 32; iBit++)
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| 243 | if (s.uECX & RT_BIT(iBit))
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| 244 | RTPrintf(" %d", iBit);
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| 245 | RTPrintf("\n");
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| 246 | }
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| 247 |
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| 248 | /*
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| 249 | * Extended.
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| 250 | * Implemented after AMD specs.
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| 251 | */
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| 252 | /** @todo check out the intel specs. */
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| 253 | ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 254 | if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
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| 255 | {
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| 256 | RTPrintf("No extended CPUID info? Check the manual on how to detect this...\n");
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| 257 | return;
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| 258 | }
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| 259 | const uint32_t cExtFunctions = s.uEAX | 0x80000000;
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| 260 |
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| 261 | /* raw dump */
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| 262 | RTPrintf("\n"
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| 263 | " RAW Extended CPUIDs\n"
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| 264 | "Function eax ebx ecx edx\n");
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| 265 | for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
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| 266 | {
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| 267 | ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 268 | RTPrintf("%08x %08x %08x %08x %08x%s\n",
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| 269 | iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
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| 270 | }
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| 271 |
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| 272 | /*
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| 273 | * Understandable output
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| 274 | */
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| 275 | ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 276 | RTPrintf("Ext Name: %.4s%.4s%.4s\n"
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| 277 | "Ext Supports: 0x80000000-%#010x\n",
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| 278 | &s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
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| 279 |
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| 280 | if (cExtFunctions >= 0x80000001)
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| 281 | {
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| 282 | ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
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| 283 | RTPrintf("Family: %#x \tExtended: %#x \tEffective: %#x\n"
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| 284 | "Model: %#x \tExtended: %#x \tEffective: %#x\n"
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| 285 | "Stepping: %d\n"
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| 286 | "Brand ID: %#05x\n",
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| 287 | (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
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| 288 | (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
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| 289 | ASMGetCpuStepping(s.uEAX),
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| 290 | s.uEBX & 0xfff);
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| 291 |
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| 292 | RTPrintf("Features EDX: ");
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| 293 | if (s.uEDX & RT_BIT(0)) RTPrintf(" FPU");
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| 294 | if (s.uEDX & RT_BIT(1)) RTPrintf(" VME");
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| 295 | if (s.uEDX & RT_BIT(2)) RTPrintf(" DE");
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| 296 | if (s.uEDX & RT_BIT(3)) RTPrintf(" PSE");
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| 297 | if (s.uEDX & RT_BIT(4)) RTPrintf(" TSC");
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| 298 | if (s.uEDX & RT_BIT(5)) RTPrintf(" MSR");
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| 299 | if (s.uEDX & RT_BIT(6)) RTPrintf(" PAE");
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| 300 | if (s.uEDX & RT_BIT(7)) RTPrintf(" MCE");
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| 301 | if (s.uEDX & RT_BIT(8)) RTPrintf(" CMPXCHG8B");
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| 302 | if (s.uEDX & RT_BIT(9)) RTPrintf(" APIC");
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| 303 | if (s.uEDX & RT_BIT(10)) RTPrintf(" 10");
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| 304 | if (s.uEDX & RT_BIT(11)) RTPrintf(" SysCallSysRet");
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| 305 | if (s.uEDX & RT_BIT(12)) RTPrintf(" MTRR");
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| 306 | if (s.uEDX & RT_BIT(13)) RTPrintf(" PGE");
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| 307 | if (s.uEDX & RT_BIT(14)) RTPrintf(" MCA");
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| 308 | if (s.uEDX & RT_BIT(15)) RTPrintf(" CMOV");
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| 309 | if (s.uEDX & RT_BIT(16)) RTPrintf(" PAT");
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| 310 | if (s.uEDX & RT_BIT(17)) RTPrintf(" PSE36");
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| 311 | if (s.uEDX & RT_BIT(18)) RTPrintf(" 18");
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| 312 | if (s.uEDX & RT_BIT(19)) RTPrintf(" 19");
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| 313 | if (s.uEDX & RT_BIT(20)) RTPrintf(" NX");
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| 314 | if (s.uEDX & RT_BIT(21)) RTPrintf(" 21");
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| 315 | if (s.uEDX & RT_BIT(22)) RTPrintf(" MmxExt");
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| 316 | if (s.uEDX & RT_BIT(23)) RTPrintf(" MMX");
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| 317 | if (s.uEDX & RT_BIT(24)) RTPrintf(" FXSR");
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| 318 | if (s.uEDX & RT_BIT(25)) RTPrintf(" FastFXSR");
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| 319 | if (s.uEDX & RT_BIT(26)) RTPrintf(" 26");
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| 320 | if (s.uEDX & RT_BIT(27)) RTPrintf(" RDTSCP");
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| 321 | if (s.uEDX & RT_BIT(28)) RTPrintf(" 28");
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| 322 | if (s.uEDX & RT_BIT(29)) RTPrintf(" LongMode");
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| 323 | if (s.uEDX & RT_BIT(30)) RTPrintf(" 3DNowExt");
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| 324 | if (s.uEDX & RT_BIT(31)) RTPrintf(" 3DNow");
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| 325 | RTPrintf("\n");
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| 326 |
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| 327 | RTPrintf("Features ECX: ");
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| 328 | if (s.uECX & RT_BIT(0)) RTPrintf(" LahfSahf");
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| 329 | if (s.uECX & RT_BIT(1)) RTPrintf(" CmpLegacy");
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| 330 | if (s.uECX & RT_BIT(2)) RTPrintf(" SVM");
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| 331 | if (s.uECX & RT_BIT(3)) RTPrintf(" 3");
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| 332 | if (s.uECX & RT_BIT(4)) RTPrintf(" AltMovCr8");
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| 333 | for (iBit = 5; iBit < 32; iBit++)
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| 334 | if (s.uECX & RT_BIT(iBit))
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| 335 | RTPrintf(" %d", iBit);
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| 336 | RTPrintf("\n");
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| 337 | }
|
|---|
| 338 |
|
|---|
| 339 | char szString[4*4*3+1] = {0};
|
|---|
| 340 | if (cExtFunctions >= 0x80000002)
|
|---|
| 341 | ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
|
|---|
| 342 | if (cExtFunctions >= 0x80000003)
|
|---|
| 343 | ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
|
|---|
| 344 | if (cExtFunctions >= 0x80000004)
|
|---|
| 345 | ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
|
|---|
| 346 | if (cExtFunctions >= 0x80000002)
|
|---|
| 347 | RTPrintf("Full Name: %s\n", szString);
|
|---|
| 348 |
|
|---|
| 349 | if (cExtFunctions >= 0x80000005)
|
|---|
| 350 | {
|
|---|
| 351 | ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
|
|---|
| 352 | RTPrintf("TLB 2/4M Instr/Uni: %s %3d entries\n"
|
|---|
| 353 | "TLB 2/4M Data: %s %3d entries\n",
|
|---|
| 354 | getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
|
|---|
| 355 | getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
|
|---|
| 356 | RTPrintf("TLB 4K Instr/Uni: %s %3d entries\n"
|
|---|
| 357 | "TLB 4K Data: %s %3d entries\n",
|
|---|
| 358 | getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
|
|---|
| 359 | getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
|
|---|
| 360 | RTPrintf("L1 Instr Cache Line Size: %d bytes\n"
|
|---|
| 361 | "L1 Instr Cache Lines Per Tag: %d\n"
|
|---|
| 362 | "L1 Instr Cache Associativity: %s\n"
|
|---|
| 363 | "L1 Instr Cache Size: %d KB\n",
|
|---|
| 364 | (s.uEDX >> 0) & 0xff,
|
|---|
| 365 | (s.uEDX >> 8) & 0xff,
|
|---|
| 366 | getCacheAss((s.uEDX >> 16) & 0xff),
|
|---|
| 367 | (s.uEDX >> 24) & 0xff);
|
|---|
| 368 | RTPrintf("L1 Data Cache Line Size: %d bytes\n"
|
|---|
| 369 | "L1 Data Cache Lines Per Tag: %d\n"
|
|---|
| 370 | "L1 Data Cache Associativity: %s\n"
|
|---|
| 371 | "L1 Data Cache Size: %d KB\n",
|
|---|
| 372 | (s.uECX >> 0) & 0xff,
|
|---|
| 373 | (s.uECX >> 8) & 0xff,
|
|---|
| 374 | getCacheAss((s.uECX >> 16) & 0xff),
|
|---|
| 375 | (s.uECX >> 24) & 0xff);
|
|---|
| 376 | }
|
|---|
| 377 |
|
|---|
| 378 | if (cExtFunctions >= 0x80000006)
|
|---|
| 379 | {
|
|---|
| 380 | ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
|
|---|
| 381 | RTPrintf("L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
|
|---|
| 382 | "L2 TLB 2/4M Data: %s %4d entries\n",
|
|---|
| 383 | getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
|
|---|
| 384 | getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
|
|---|
| 385 | RTPrintf("L2 TLB 4K Instr/Uni: %s %4d entries\n"
|
|---|
| 386 | "L2 TLB 4K Data: %s %4d entries\n",
|
|---|
| 387 | getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
|
|---|
| 388 | getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
|
|---|
| 389 | RTPrintf("L2 Cache Line Size: %d bytes\n"
|
|---|
| 390 | "L2 Cache Lines Per Tag: %d\n"
|
|---|
| 391 | "L2 Cache Associativity: %s\n"
|
|---|
| 392 | "L2 Cache Size: %d KB\n",
|
|---|
| 393 | (s.uEDX >> 0) & 0xff,
|
|---|
| 394 | (s.uEDX >> 8) & 0xf,
|
|---|
| 395 | getL2CacheAss((s.uEDX >> 12) & 0xf),
|
|---|
| 396 | (s.uEDX >> 16) & 0xffff);
|
|---|
| 397 | }
|
|---|
| 398 |
|
|---|
| 399 | if (cExtFunctions >= 0x80000007)
|
|---|
| 400 | {
|
|---|
| 401 | ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
|
|---|
| 402 | RTPrintf("APM Features: ");
|
|---|
| 403 | if (s.uEDX & RT_BIT(0)) RTPrintf(" TS");
|
|---|
| 404 | if (s.uEDX & RT_BIT(1)) RTPrintf(" FID");
|
|---|
| 405 | if (s.uEDX & RT_BIT(2)) RTPrintf(" VID");
|
|---|
| 406 | if (s.uEDX & RT_BIT(3)) RTPrintf(" TTP");
|
|---|
| 407 | if (s.uEDX & RT_BIT(4)) RTPrintf(" TM");
|
|---|
| 408 | if (s.uEDX & RT_BIT(5)) RTPrintf(" STC");
|
|---|
| 409 | if (s.uEDX & RT_BIT(6)) RTPrintf(" 6");
|
|---|
| 410 | if (s.uEDX & RT_BIT(7)) RTPrintf(" 7");
|
|---|
| 411 | if (s.uEDX & RT_BIT(8)) RTPrintf(" TscInvariant");
|
|---|
| 412 | for (iBit = 9; iBit < 32; iBit++)
|
|---|
| 413 | if (s.uEDX & RT_BIT(iBit))
|
|---|
| 414 | RTPrintf(" %d", iBit);
|
|---|
| 415 | RTPrintf("\n");
|
|---|
| 416 | }
|
|---|
| 417 |
|
|---|
| 418 | if (cExtFunctions >= 0x80000008)
|
|---|
| 419 | {
|
|---|
| 420 | ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
|
|---|
| 421 | RTPrintf("Physical Address Width: %d bits\n"
|
|---|
| 422 | "Virtual Address Width: %d bits\n",
|
|---|
| 423 | (s.uEAX >> 0) & 0xff,
|
|---|
| 424 | (s.uEAX >> 8) & 0xff);
|
|---|
| 425 | RTPrintf("Physical Core Count: %d\n",
|
|---|
| 426 | ((s.uECX >> 0) & 0xff) + 1);
|
|---|
| 427 | if ((s.uECX >> 12) & 0xf)
|
|---|
| 428 | RTPrintf("ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
|
|---|
| 429 | }
|
|---|
| 430 |
|
|---|
| 431 | if (cExtFunctions >= 0x8000000a)
|
|---|
| 432 | {
|
|---|
| 433 | ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
|
|---|
| 434 | RTPrintf("SVM Revision: %d (%#x)\n"
|
|---|
| 435 | "Number of Address Space IDs: %d (%#x)\n",
|
|---|
| 436 | s.uEAX & 0xff, s.uEAX & 0xff,
|
|---|
| 437 | s.uEBX, s.uEBX);
|
|---|
| 438 | }
|
|---|
| 439 | }
|
|---|
| 440 | #endif /* !PIC || !X86 */
|
|---|
| 441 |
|
|---|
| 442 |
|
|---|
| 443 | static void tstASMAtomicXchgU8(void)
|
|---|
| 444 | {
|
|---|
| 445 | struct
|
|---|
| 446 | {
|
|---|
| 447 | uint8_t u8Dummy0;
|
|---|
| 448 | uint8_t u8;
|
|---|
| 449 | uint8_t u8Dummy1;
|
|---|
| 450 | } s;
|
|---|
| 451 |
|
|---|
| 452 | s.u8 = 0;
|
|---|
| 453 | s.u8Dummy0 = s.u8Dummy1 = 0x42;
|
|---|
| 454 | CHECKOP(ASMAtomicXchgU8(&s.u8, 1), 0, "%#x", uint8_t);
|
|---|
| 455 | CHECKVAL(s.u8, 1, "%#x");
|
|---|
| 456 |
|
|---|
| 457 | CHECKOP(ASMAtomicXchgU8(&s.u8, 0), 1, "%#x", uint8_t);
|
|---|
| 458 | CHECKVAL(s.u8, 0, "%#x");
|
|---|
| 459 |
|
|---|
| 460 | CHECKOP(ASMAtomicXchgU8(&s.u8, 0xff), 0, "%#x", uint8_t);
|
|---|
| 461 | CHECKVAL(s.u8, 0xff, "%#x");
|
|---|
| 462 |
|
|---|
| 463 | CHECKOP(ASMAtomicXchgU8(&s.u8, 0x87), 0xffff, "%#x", uint8_t);
|
|---|
| 464 | CHECKVAL(s.u8, 0x87, "%#x");
|
|---|
| 465 | CHECKVAL(s.u8Dummy0, 0x42, "%#x");
|
|---|
| 466 | CHECKVAL(s.u8Dummy1, 0x42, "%#x");
|
|---|
| 467 | }
|
|---|
| 468 |
|
|---|
| 469 |
|
|---|
| 470 | static void tstASMAtomicXchgU16(void)
|
|---|
| 471 | {
|
|---|
| 472 | struct
|
|---|
| 473 | {
|
|---|
| 474 | uint16_t u16Dummy0;
|
|---|
| 475 | uint16_t u16;
|
|---|
| 476 | uint16_t u16Dummy1;
|
|---|
| 477 | } s;
|
|---|
| 478 |
|
|---|
| 479 | s.u16 = 0;
|
|---|
| 480 | s.u16Dummy0 = s.u16Dummy1 = 0x1234;
|
|---|
| 481 | CHECKOP(ASMAtomicXchgU16(&s.u16, 1), 0, "%#x", uint16_t);
|
|---|
| 482 | CHECKVAL(s.u16, 1, "%#x");
|
|---|
| 483 |
|
|---|
| 484 | CHECKOP(ASMAtomicXchgU16(&s.u16, 0), 1, "%#x", uint16_t);
|
|---|
| 485 | CHECKVAL(s.u16, 0, "%#x");
|
|---|
| 486 |
|
|---|
| 487 | CHECKOP(ASMAtomicXchgU16(&s.u16, 0xffff), 0, "%#x", uint16_t);
|
|---|
| 488 | CHECKVAL(s.u16, 0xffff, "%#x");
|
|---|
| 489 |
|
|---|
| 490 | CHECKOP(ASMAtomicXchgU16(&s.u16, 0x8765), 0xffff, "%#x", uint16_t);
|
|---|
| 491 | CHECKVAL(s.u16, 0x8765, "%#x");
|
|---|
| 492 | CHECKVAL(s.u16Dummy0, 0x1234, "%#x");
|
|---|
| 493 | CHECKVAL(s.u16Dummy1, 0x1234, "%#x");
|
|---|
| 494 | }
|
|---|
| 495 |
|
|---|
| 496 |
|
|---|
| 497 | static void tstASMAtomicXchgU32(void)
|
|---|
| 498 | {
|
|---|
| 499 | struct
|
|---|
| 500 | {
|
|---|
| 501 | uint32_t u32Dummy0;
|
|---|
| 502 | uint32_t u32;
|
|---|
| 503 | uint32_t u32Dummy1;
|
|---|
| 504 | } s;
|
|---|
| 505 |
|
|---|
| 506 | s.u32 = 0;
|
|---|
| 507 | s.u32Dummy0 = s.u32Dummy1 = 0x11223344;
|
|---|
| 508 |
|
|---|
| 509 | CHECKOP(ASMAtomicXchgU32(&s.u32, 1), 0, "%#x", uint32_t);
|
|---|
| 510 | CHECKVAL(s.u32, 1, "%#x");
|
|---|
| 511 |
|
|---|
| 512 | CHECKOP(ASMAtomicXchgU32(&s.u32, 0), 1, "%#x", uint32_t);
|
|---|
| 513 | CHECKVAL(s.u32, 0, "%#x");
|
|---|
| 514 |
|
|---|
| 515 | CHECKOP(ASMAtomicXchgU32(&s.u32, ~0U), 0, "%#x", uint32_t);
|
|---|
| 516 | CHECKVAL(s.u32, ~0U, "%#x");
|
|---|
| 517 |
|
|---|
| 518 | CHECKOP(ASMAtomicXchgU32(&s.u32, 0x87654321), ~0U, "%#x", uint32_t);
|
|---|
| 519 | CHECKVAL(s.u32, 0x87654321, "%#x");
|
|---|
| 520 |
|
|---|
| 521 | CHECKVAL(s.u32Dummy0, 0x11223344, "%#x");
|
|---|
| 522 | CHECKVAL(s.u32Dummy1, 0x11223344, "%#x");
|
|---|
| 523 | }
|
|---|
| 524 |
|
|---|
| 525 |
|
|---|
| 526 | static void tstASMAtomicXchgU64(void)
|
|---|
| 527 | {
|
|---|
| 528 | struct
|
|---|
| 529 | {
|
|---|
| 530 | uint64_t u64Dummy0;
|
|---|
| 531 | uint64_t u64;
|
|---|
| 532 | uint64_t u64Dummy1;
|
|---|
| 533 | } s;
|
|---|
| 534 |
|
|---|
| 535 | s.u64 = 0;
|
|---|
| 536 | s.u64Dummy0 = s.u64Dummy1 = 0x1122334455667788ULL;
|
|---|
| 537 |
|
|---|
| 538 | CHECKOP(ASMAtomicXchgU64(&s.u64, 1), 0ULL, "%#llx", uint64_t);
|
|---|
| 539 | CHECKVAL(s.u64, 1ULL, "%#llx");
|
|---|
| 540 |
|
|---|
| 541 | CHECKOP(ASMAtomicXchgU64(&s.u64, 0), 1ULL, "%#llx", uint64_t);
|
|---|
| 542 | CHECKVAL(s.u64, 0ULL, "%#llx");
|
|---|
| 543 |
|
|---|
| 544 | CHECKOP(ASMAtomicXchgU64(&s.u64, ~0ULL), 0ULL, "%#llx", uint64_t);
|
|---|
| 545 | CHECKVAL(s.u64, ~0ULL, "%#llx");
|
|---|
| 546 |
|
|---|
| 547 | CHECKOP(ASMAtomicXchgU64(&s.u64, 0xfedcba0987654321ULL), ~0ULL, "%#llx", uint64_t);
|
|---|
| 548 | CHECKVAL(s.u64, 0xfedcba0987654321ULL, "%#llx");
|
|---|
| 549 |
|
|---|
| 550 | CHECKVAL(s.u64Dummy0, 0x1122334455667788ULL, "%#x");
|
|---|
| 551 | CHECKVAL(s.u64Dummy1, 0x1122334455667788ULL, "%#x");
|
|---|
| 552 | }
|
|---|
| 553 |
|
|---|
| 554 |
|
|---|
| 555 | #ifdef RT_ARCH_AMD64
|
|---|
| 556 | static void tstASMAtomicXchgU128(void)
|
|---|
| 557 | {
|
|---|
| 558 | struct
|
|---|
| 559 | {
|
|---|
| 560 | RTUINT128U u128Dummy0;
|
|---|
| 561 | RTUINT128U u128;
|
|---|
| 562 | RTUINT128U u128Dummy1;
|
|---|
| 563 | } s;
|
|---|
| 564 | RTUINT128U u128Ret;
|
|---|
| 565 | RTUINT128U u128Arg;
|
|---|
| 566 |
|
|---|
| 567 |
|
|---|
| 568 | s.u128Dummy0.s.Lo = s.u128Dummy0.s.Hi = 0x1122334455667788;
|
|---|
| 569 | s.u128.s.Lo = 0;
|
|---|
| 570 | s.u128.s.Hi = 0;
|
|---|
| 571 | s.u128Dummy1 = s.u128Dummy0;
|
|---|
| 572 |
|
|---|
| 573 | u128Arg.s.Lo = 1;
|
|---|
| 574 | u128Arg.s.Hi = 0;
|
|---|
| 575 | u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
|
|---|
| 576 | CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
|
|---|
| 577 | CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
|
|---|
| 578 | CHECKVAL(s.u128.s.Lo, 1ULL, "%#llx");
|
|---|
| 579 | CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
|
|---|
| 580 |
|
|---|
| 581 | u128Arg.s.Lo = 0;
|
|---|
| 582 | u128Arg.s.Hi = 0;
|
|---|
| 583 | u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
|
|---|
| 584 | CHECKVAL(u128Ret.s.Lo, 1ULL, "%#llx");
|
|---|
| 585 | CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
|
|---|
| 586 | CHECKVAL(s.u128.s.Lo, 0ULL, "%#llx");
|
|---|
| 587 | CHECKVAL(s.u128.s.Hi, 0ULL, "%#llx");
|
|---|
| 588 |
|
|---|
| 589 | u128Arg.s.Lo = ~0ULL;
|
|---|
| 590 | u128Arg.s.Hi = ~0ULL;
|
|---|
| 591 | u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
|
|---|
| 592 | CHECKVAL(u128Ret.s.Lo, 0ULL, "%#llx");
|
|---|
| 593 | CHECKVAL(u128Ret.s.Hi, 0ULL, "%#llx");
|
|---|
| 594 | CHECKVAL(s.u128.s.Lo, ~0ULL, "%#llx");
|
|---|
| 595 | CHECKVAL(s.u128.s.Hi, ~0ULL, "%#llx");
|
|---|
| 596 |
|
|---|
| 597 |
|
|---|
| 598 | u128Arg.s.Lo = 0xfedcba0987654321ULL;
|
|---|
| 599 | u128Arg.s.Hi = 0x8897a6b5c4d3e2f1ULL;
|
|---|
| 600 | u128Ret.u = ASMAtomicXchgU128(&s.u128.u, u128Arg.u);
|
|---|
| 601 | CHECKVAL(u128Ret.s.Lo, ~0ULL, "%#llx");
|
|---|
| 602 | CHECKVAL(u128Ret.s.Hi, ~0ULL, "%#llx");
|
|---|
| 603 | CHECKVAL(s.u128.s.Lo, 0xfedcba0987654321ULL, "%#llx");
|
|---|
| 604 | CHECKVAL(s.u128.s.Hi, 0x8897a6b5c4d3e2f1ULL, "%#llx");
|
|---|
| 605 |
|
|---|
| 606 | CHECKVAL(s.u128Dummy0.s.Lo, 0x1122334455667788, "%#llx");
|
|---|
| 607 | CHECKVAL(s.u128Dummy0.s.Hi, 0x1122334455667788, "%#llx");
|
|---|
| 608 | CHECKVAL(s.u128Dummy1.s.Lo, 0x1122334455667788, "%#llx");
|
|---|
| 609 | CHECKVAL(s.u128Dummy1.s.Hi, 0x1122334455667788, "%#llx");
|
|---|
| 610 | }
|
|---|
| 611 | #endif
|
|---|
| 612 |
|
|---|
| 613 |
|
|---|
| 614 | static void tstASMAtomicXchgPtr(void)
|
|---|
| 615 | {
|
|---|
| 616 | void *pv = NULL;
|
|---|
| 617 |
|
|---|
| 618 | CHECKOP(ASMAtomicXchgPtr(&pv, (void *)(~(uintptr_t)0)), NULL, "%p", void *);
|
|---|
| 619 | CHECKVAL(pv, (void *)(~(uintptr_t)0), "%p");
|
|---|
| 620 |
|
|---|
| 621 | CHECKOP(ASMAtomicXchgPtr(&pv, (void *)0x87654321), (void *)(~(uintptr_t)0), "%p", void *);
|
|---|
| 622 | CHECKVAL(pv, (void *)0x87654321, "%p");
|
|---|
| 623 |
|
|---|
| 624 | CHECKOP(ASMAtomicXchgPtr(&pv, NULL), (void *)0x87654321, "%p", void *);
|
|---|
| 625 | CHECKVAL(pv, NULL, "%p");
|
|---|
| 626 | }
|
|---|
| 627 |
|
|---|
| 628 |
|
|---|
| 629 | static void tstASMAtomicCmpXchgU32(void)
|
|---|
| 630 | {
|
|---|
| 631 | uint32_t u32 = 0xffffffff;
|
|---|
| 632 |
|
|---|
| 633 | CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0), false, "%d", bool);
|
|---|
| 634 | CHECKVAL(u32, 0xffffffff, "%x");
|
|---|
| 635 |
|
|---|
| 636 | CHECKOP(ASMAtomicCmpXchgU32(&u32, 0, 0xffffffff), true, "%d", bool);
|
|---|
| 637 | CHECKVAL(u32, 0, "%x");
|
|---|
| 638 |
|
|---|
| 639 | CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0xffffffff), false, "%d", bool);
|
|---|
| 640 | CHECKVAL(u32, 0, "%x");
|
|---|
| 641 |
|
|---|
| 642 | CHECKOP(ASMAtomicCmpXchgU32(&u32, 0x8008efd, 0), true, "%d", bool);
|
|---|
| 643 | CHECKVAL(u32, 0x8008efd, "%x");
|
|---|
| 644 | }
|
|---|
| 645 |
|
|---|
| 646 |
|
|---|
| 647 | static void tstASMAtomicCmpXchgU64(void)
|
|---|
| 648 | {
|
|---|
| 649 | uint64_t u64 = 0xffffffffffffffULL;
|
|---|
| 650 |
|
|---|
| 651 | CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0), false, "%d", bool);
|
|---|
| 652 | CHECKVAL(u64, 0xffffffffffffffULL, "%x");
|
|---|
| 653 |
|
|---|
| 654 | CHECKOP(ASMAtomicCmpXchgU64(&u64, 0, 0xffffffffffffffULL), true, "%d", bool);
|
|---|
| 655 | CHECKVAL(u64, 0, "%x");
|
|---|
| 656 |
|
|---|
| 657 | CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff), false, "%d", bool);
|
|---|
| 658 | CHECKVAL(u64, 0, "%x");
|
|---|
| 659 |
|
|---|
| 660 | CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0xffffffff00000000ULL), false, "%d", bool);
|
|---|
| 661 | CHECKVAL(u64, 0, "%x");
|
|---|
| 662 |
|
|---|
| 663 | CHECKOP(ASMAtomicCmpXchgU64(&u64, 0x80040008008efdULL, 0), true, "%d", bool);
|
|---|
| 664 | CHECKVAL(u64, 0x80040008008efdULL, "%x");
|
|---|
| 665 | }
|
|---|
| 666 |
|
|---|
| 667 |
|
|---|
| 668 | static void tstASMAtomicCmpXchgExU32(void)
|
|---|
| 669 | {
|
|---|
| 670 | uint32_t u32 = 0xffffffff;
|
|---|
| 671 | uint32_t u32Old = 0x80005111;
|
|---|
| 672 |
|
|---|
| 673 | CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0, &u32Old), false, "%d", bool);
|
|---|
| 674 | CHECKVAL(u32, 0xffffffff, "%x");
|
|---|
| 675 | CHECKVAL(u32Old, 0xffffffff, "%x");
|
|---|
| 676 |
|
|---|
| 677 | CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0xffffffff, &u32Old), true, "%d", bool);
|
|---|
| 678 | CHECKVAL(u32, 0, "%x");
|
|---|
| 679 | CHECKVAL(u32Old, 0xffffffff, "%x");
|
|---|
| 680 |
|
|---|
| 681 | CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0x8008efd, 0xffffffff, &u32Old), false, "%d", bool);
|
|---|
| 682 | CHECKVAL(u32, 0, "%x");
|
|---|
| 683 | CHECKVAL(u32Old, 0, "%x");
|
|---|
| 684 |
|
|---|
| 685 | CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0x8008efd, 0, &u32Old), true, "%d", bool);
|
|---|
| 686 | CHECKVAL(u32, 0x8008efd, "%x");
|
|---|
| 687 | CHECKVAL(u32Old, 0, "%x");
|
|---|
| 688 |
|
|---|
| 689 | CHECKOP(ASMAtomicCmpXchgExU32(&u32, 0, 0x8008efd, &u32Old), true, "%d", bool);
|
|---|
| 690 | CHECKVAL(u32, 0, "%x");
|
|---|
| 691 | CHECKVAL(u32Old, 0x8008efd, "%x");
|
|---|
| 692 | }
|
|---|
| 693 |
|
|---|
| 694 |
|
|---|
| 695 | static void tstASMAtomicCmpXchgExU64(void)
|
|---|
| 696 | {
|
|---|
| 697 | uint64_t u64 = 0xffffffffffffffffULL;
|
|---|
| 698 | uint64_t u64Old = 0x8000000051111111ULL;
|
|---|
| 699 |
|
|---|
| 700 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0, &u64Old), false, "%d", bool);
|
|---|
| 701 | CHECKVAL(u64, 0xffffffffffffffffULL, "%llx");
|
|---|
| 702 | CHECKVAL(u64Old, 0xffffffffffffffffULL, "%llx");
|
|---|
| 703 |
|
|---|
| 704 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0xffffffffffffffffULL, &u64Old), true, "%d", bool);
|
|---|
| 705 | CHECKVAL(u64, 0ULL, "%llx");
|
|---|
| 706 | CHECKVAL(u64Old, 0xffffffffffffffffULL, "%llx");
|
|---|
| 707 |
|
|---|
| 708 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0xffffffff, &u64Old), false, "%d", bool);
|
|---|
| 709 | CHECKVAL(u64, 0ULL, "%llx");
|
|---|
| 710 | CHECKVAL(u64Old, 0ULL, "%llx");
|
|---|
| 711 |
|
|---|
| 712 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0xffffffff00000000ULL, &u64Old), false, "%d", bool);
|
|---|
| 713 | CHECKVAL(u64, 0ULL, "%llx");
|
|---|
| 714 | CHECKVAL(u64Old, 0ULL, "%llx");
|
|---|
| 715 |
|
|---|
| 716 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0x80040008008efdULL, 0, &u64Old), true, "%d", bool);
|
|---|
| 717 | CHECKVAL(u64, 0x80040008008efdULL, "%llx");
|
|---|
| 718 | CHECKVAL(u64Old, 0ULL, "%llx");
|
|---|
| 719 |
|
|---|
| 720 | CHECKOP(ASMAtomicCmpXchgExU64(&u64, 0, 0x80040008008efdULL, &u64Old), true, "%d", bool);
|
|---|
| 721 | CHECKVAL(u64, 0ULL, "%llx");
|
|---|
| 722 | CHECKVAL(u64Old, 0x80040008008efdULL, "%llx");
|
|---|
| 723 | }
|
|---|
| 724 |
|
|---|
| 725 |
|
|---|
| 726 | static void tstASMAtomicReadU64(void)
|
|---|
| 727 | {
|
|---|
| 728 | uint64_t u64 = 0;
|
|---|
| 729 |
|
|---|
| 730 | CHECKOP(ASMAtomicReadU64(&u64), 0ULL, "%#llx", uint64_t);
|
|---|
| 731 | CHECKVAL(u64, 0ULL, "%#llx");
|
|---|
| 732 |
|
|---|
| 733 | u64 = ~0ULL;
|
|---|
| 734 | CHECKOP(ASMAtomicReadU64(&u64), ~0ULL, "%#llx", uint64_t);
|
|---|
| 735 | CHECKVAL(u64, ~0ULL, "%#llx");
|
|---|
| 736 |
|
|---|
| 737 | u64 = 0xfedcba0987654321ULL;
|
|---|
| 738 | CHECKOP(ASMAtomicReadU64(&u64), 0xfedcba0987654321ULL, "%#llx", uint64_t);
|
|---|
| 739 | CHECKVAL(u64, 0xfedcba0987654321ULL, "%#llx");
|
|---|
| 740 | }
|
|---|
| 741 |
|
|---|
| 742 |
|
|---|
| 743 | static void tstASMAtomicAddS32(void)
|
|---|
| 744 | {
|
|---|
| 745 | int32_t i32Rc;
|
|---|
| 746 | int32_t i32 = 10;
|
|---|
| 747 | #define MYCHECK(op, rc, val) \
|
|---|
| 748 | do { \
|
|---|
| 749 | i32Rc = op; \
|
|---|
| 750 | if (i32Rc != (rc)) \
|
|---|
| 751 | { \
|
|---|
| 752 | RTPrintf("%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
|
|---|
| 753 | g_cErrors++; \
|
|---|
| 754 | } \
|
|---|
| 755 | if (i32 != (val)) \
|
|---|
| 756 | { \
|
|---|
| 757 | RTPrintf("%s, %d: FAILURE: %s => i32=%d expected %d\n", __FUNCTION__, __LINE__, #op, i32, val); \
|
|---|
| 758 | g_cErrors++; \
|
|---|
| 759 | } \
|
|---|
| 760 | } while (0)
|
|---|
| 761 | MYCHECK(ASMAtomicAddS32(&i32, 1), 10, 11);
|
|---|
| 762 | MYCHECK(ASMAtomicAddS32(&i32, -2), 11, 9);
|
|---|
| 763 | MYCHECK(ASMAtomicAddS32(&i32, -9), 9, 0);
|
|---|
| 764 | MYCHECK(ASMAtomicAddS32(&i32, -0x7fffffff), 0, -0x7fffffff);
|
|---|
| 765 | MYCHECK(ASMAtomicAddS32(&i32, 0), -0x7fffffff, -0x7fffffff);
|
|---|
| 766 | MYCHECK(ASMAtomicAddS32(&i32, 0x7fffffff), -0x7fffffff, 0);
|
|---|
| 767 | MYCHECK(ASMAtomicAddS32(&i32, 0), 0, 0);
|
|---|
| 768 | #undef MYCHECK
|
|---|
| 769 | }
|
|---|
| 770 |
|
|---|
| 771 |
|
|---|
| 772 | static void tstASMAtomicDecIncS32(void)
|
|---|
| 773 | {
|
|---|
| 774 | int32_t i32Rc;
|
|---|
| 775 | int32_t i32 = 10;
|
|---|
| 776 | #define MYCHECK(op, rc) \
|
|---|
| 777 | do { \
|
|---|
| 778 | i32Rc = op; \
|
|---|
| 779 | if (i32Rc != (rc)) \
|
|---|
| 780 | { \
|
|---|
| 781 | RTPrintf("%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
|
|---|
| 782 | g_cErrors++; \
|
|---|
| 783 | } \
|
|---|
| 784 | if (i32 != (rc)) \
|
|---|
| 785 | { \
|
|---|
| 786 | RTPrintf("%s, %d: FAILURE: %s => i32=%d expected %d\n", __FUNCTION__, __LINE__, #op, i32, rc); \
|
|---|
| 787 | g_cErrors++; \
|
|---|
| 788 | } \
|
|---|
| 789 | } while (0)
|
|---|
| 790 | MYCHECK(ASMAtomicDecS32(&i32), 9);
|
|---|
| 791 | MYCHECK(ASMAtomicDecS32(&i32), 8);
|
|---|
| 792 | MYCHECK(ASMAtomicDecS32(&i32), 7);
|
|---|
| 793 | MYCHECK(ASMAtomicDecS32(&i32), 6);
|
|---|
| 794 | MYCHECK(ASMAtomicDecS32(&i32), 5);
|
|---|
| 795 | MYCHECK(ASMAtomicDecS32(&i32), 4);
|
|---|
| 796 | MYCHECK(ASMAtomicDecS32(&i32), 3);
|
|---|
| 797 | MYCHECK(ASMAtomicDecS32(&i32), 2);
|
|---|
| 798 | MYCHECK(ASMAtomicDecS32(&i32), 1);
|
|---|
| 799 | MYCHECK(ASMAtomicDecS32(&i32), 0);
|
|---|
| 800 | MYCHECK(ASMAtomicDecS32(&i32), -1);
|
|---|
| 801 | MYCHECK(ASMAtomicDecS32(&i32), -2);
|
|---|
| 802 | MYCHECK(ASMAtomicIncS32(&i32), -1);
|
|---|
| 803 | MYCHECK(ASMAtomicIncS32(&i32), 0);
|
|---|
| 804 | MYCHECK(ASMAtomicIncS32(&i32), 1);
|
|---|
| 805 | MYCHECK(ASMAtomicIncS32(&i32), 2);
|
|---|
| 806 | MYCHECK(ASMAtomicIncS32(&i32), 3);
|
|---|
| 807 | MYCHECK(ASMAtomicDecS32(&i32), 2);
|
|---|
| 808 | MYCHECK(ASMAtomicIncS32(&i32), 3);
|
|---|
| 809 | MYCHECK(ASMAtomicDecS32(&i32), 2);
|
|---|
| 810 | MYCHECK(ASMAtomicIncS32(&i32), 3);
|
|---|
| 811 | #undef MYCHECK
|
|---|
| 812 | }
|
|---|
| 813 |
|
|---|
| 814 |
|
|---|
| 815 | static void tstASMAtomicAndOrU32(void)
|
|---|
| 816 | {
|
|---|
| 817 | uint32_t u32 = 0xffffffff;
|
|---|
| 818 |
|
|---|
| 819 | ASMAtomicOrU32(&u32, 0xffffffff);
|
|---|
| 820 | CHECKVAL(u32, 0xffffffff, "%x");
|
|---|
| 821 |
|
|---|
| 822 | ASMAtomicAndU32(&u32, 0xffffffff);
|
|---|
| 823 | CHECKVAL(u32, 0xffffffff, "%x");
|
|---|
| 824 |
|
|---|
| 825 | ASMAtomicAndU32(&u32, 0x8f8f8f8f);
|
|---|
| 826 | CHECKVAL(u32, 0x8f8f8f8f, "%x");
|
|---|
| 827 |
|
|---|
| 828 | ASMAtomicOrU32(&u32, 0x70707070);
|
|---|
| 829 | CHECKVAL(u32, 0xffffffff, "%x");
|
|---|
| 830 |
|
|---|
| 831 | ASMAtomicAndU32(&u32, 1);
|
|---|
| 832 | CHECKVAL(u32, 1, "%x");
|
|---|
| 833 |
|
|---|
| 834 | ASMAtomicOrU32(&u32, 0x80000000);
|
|---|
| 835 | CHECKVAL(u32, 0x80000001, "%x");
|
|---|
| 836 |
|
|---|
| 837 | ASMAtomicAndU32(&u32, 0x80000000);
|
|---|
| 838 | CHECKVAL(u32, 0x80000000, "%x");
|
|---|
| 839 |
|
|---|
| 840 | ASMAtomicAndU32(&u32, 0);
|
|---|
| 841 | CHECKVAL(u32, 0, "%x");
|
|---|
| 842 |
|
|---|
| 843 | ASMAtomicOrU32(&u32, 0x42424242);
|
|---|
| 844 | CHECKVAL(u32, 0x42424242, "%x");
|
|---|
| 845 | }
|
|---|
| 846 |
|
|---|
| 847 |
|
|---|
| 848 | void tstASMMemZeroPage(void)
|
|---|
| 849 | {
|
|---|
| 850 | struct
|
|---|
| 851 | {
|
|---|
| 852 | uint64_t u64Magic1;
|
|---|
| 853 | uint8_t abPage[PAGE_SIZE];
|
|---|
| 854 | uint64_t u64Magic2;
|
|---|
| 855 | } Buf1, Buf2, Buf3;
|
|---|
| 856 |
|
|---|
| 857 | Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 858 | memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
|
|---|
| 859 | Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 860 | Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 861 | memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
|
|---|
| 862 | Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 863 | Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 864 | memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
|
|---|
| 865 | Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 866 | ASMMemZeroPage(Buf1.abPage);
|
|---|
| 867 | ASMMemZeroPage(Buf2.abPage);
|
|---|
| 868 | ASMMemZeroPage(Buf3.abPage);
|
|---|
| 869 | if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 870 | || Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 871 | || Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 872 | || Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 873 | || Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 874 | || Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
|
|---|
| 875 | {
|
|---|
| 876 | RTPrintf("tstInlineAsm: ASMMemZeroPage violated one/both magic(s)!\n");
|
|---|
| 877 | g_cErrors++;
|
|---|
| 878 | }
|
|---|
| 879 | for (unsigned i = 0; i < sizeof(Buf1.abPage); i++)
|
|---|
| 880 | if (Buf1.abPage[i])
|
|---|
| 881 | {
|
|---|
| 882 | RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
|
|---|
| 883 | g_cErrors++;
|
|---|
| 884 | }
|
|---|
| 885 | for (unsigned i = 0; i < sizeof(Buf2.abPage); i++)
|
|---|
| 886 | if (Buf2.abPage[i])
|
|---|
| 887 | {
|
|---|
| 888 | RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
|
|---|
| 889 | g_cErrors++;
|
|---|
| 890 | }
|
|---|
| 891 | for (unsigned i = 0; i < sizeof(Buf3.abPage); i++)
|
|---|
| 892 | if (Buf3.abPage[i])
|
|---|
| 893 | {
|
|---|
| 894 | RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
|
|---|
| 895 | g_cErrors++;
|
|---|
| 896 | }
|
|---|
| 897 | }
|
|---|
| 898 |
|
|---|
| 899 |
|
|---|
| 900 | void tstASMMemZero32(void)
|
|---|
| 901 | {
|
|---|
| 902 | struct
|
|---|
| 903 | {
|
|---|
| 904 | uint64_t u64Magic1;
|
|---|
| 905 | uint8_t abPage[PAGE_SIZE - 32];
|
|---|
| 906 | uint64_t u64Magic2;
|
|---|
| 907 | } Buf1, Buf2, Buf3;
|
|---|
| 908 |
|
|---|
| 909 | Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 910 | memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
|
|---|
| 911 | Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 912 | Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 913 | memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
|
|---|
| 914 | Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 915 | Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 916 | memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
|
|---|
| 917 | Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 918 | ASMMemZero32(Buf1.abPage, sizeof(Buf1.abPage));
|
|---|
| 919 | ASMMemZero32(Buf2.abPage, sizeof(Buf2.abPage));
|
|---|
| 920 | ASMMemZero32(Buf3.abPage, sizeof(Buf3.abPage));
|
|---|
| 921 | if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 922 | || Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 923 | || Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 924 | || Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 925 | || Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 926 | || Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
|
|---|
| 927 | {
|
|---|
| 928 | RTPrintf("tstInlineAsm: ASMMemZero32 violated one/both magic(s)!\n");
|
|---|
| 929 | g_cErrors++;
|
|---|
| 930 | }
|
|---|
| 931 | for (unsigned i = 0; i < RT_ELEMENTS(Buf1.abPage); i++)
|
|---|
| 932 | if (Buf1.abPage[i])
|
|---|
| 933 | {
|
|---|
| 934 | RTPrintf("tstInlineAsm: ASMMemZero32 didn't clear byte at offset %#x!\n", i);
|
|---|
| 935 | g_cErrors++;
|
|---|
| 936 | }
|
|---|
| 937 | for (unsigned i = 0; i < RT_ELEMENTS(Buf2.abPage); i++)
|
|---|
| 938 | if (Buf2.abPage[i])
|
|---|
| 939 | {
|
|---|
| 940 | RTPrintf("tstInlineAsm: ASMMemZero32 didn't clear byte at offset %#x!\n", i);
|
|---|
| 941 | g_cErrors++;
|
|---|
| 942 | }
|
|---|
| 943 | for (unsigned i = 0; i < RT_ELEMENTS(Buf3.abPage); i++)
|
|---|
| 944 | if (Buf3.abPage[i])
|
|---|
| 945 | {
|
|---|
| 946 | RTPrintf("tstInlineAsm: ASMMemZero32 didn't clear byte at offset %#x!\n", i);
|
|---|
| 947 | g_cErrors++;
|
|---|
| 948 | }
|
|---|
| 949 | }
|
|---|
| 950 |
|
|---|
| 951 |
|
|---|
| 952 | void tstASMMemFill32(void)
|
|---|
| 953 | {
|
|---|
| 954 | struct
|
|---|
| 955 | {
|
|---|
| 956 | uint64_t u64Magic1;
|
|---|
| 957 | uint32_t au32Page[PAGE_SIZE / 4];
|
|---|
| 958 | uint64_t u64Magic2;
|
|---|
| 959 | } Buf1;
|
|---|
| 960 | struct
|
|---|
| 961 | {
|
|---|
| 962 | uint64_t u64Magic1;
|
|---|
| 963 | uint32_t au32Page[(PAGE_SIZE / 4) - 3];
|
|---|
| 964 | uint64_t u64Magic2;
|
|---|
| 965 | } Buf2;
|
|---|
| 966 | struct
|
|---|
| 967 | {
|
|---|
| 968 | uint64_t u64Magic1;
|
|---|
| 969 | uint32_t au32Page[(PAGE_SIZE / 4) - 1];
|
|---|
| 970 | uint64_t u64Magic2;
|
|---|
| 971 | } Buf3;
|
|---|
| 972 |
|
|---|
| 973 | Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 974 | memset(Buf1.au32Page, 0x55, sizeof(Buf1.au32Page));
|
|---|
| 975 | Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 976 | Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 977 | memset(Buf2.au32Page, 0x77, sizeof(Buf2.au32Page));
|
|---|
| 978 | Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 979 | Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
|
|---|
| 980 | memset(Buf3.au32Page, 0x99, sizeof(Buf3.au32Page));
|
|---|
| 981 | Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
|
|---|
| 982 | ASMMemFill32(Buf1.au32Page, sizeof(Buf1.au32Page), 0xdeadbeef);
|
|---|
| 983 | ASMMemFill32(Buf2.au32Page, sizeof(Buf2.au32Page), 0xcafeff01);
|
|---|
| 984 | ASMMemFill32(Buf3.au32Page, sizeof(Buf3.au32Page), 0xf00dd00f);
|
|---|
| 985 | if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 986 | || Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 987 | || Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 988 | || Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
|
|---|
| 989 | || Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
|
|---|
| 990 | || Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
|
|---|
| 991 | {
|
|---|
| 992 | RTPrintf("tstInlineAsm: ASMMemFill32 violated one/both magic(s)!\n");
|
|---|
| 993 | g_cErrors++;
|
|---|
| 994 | }
|
|---|
| 995 | for (unsigned i = 0; i < RT_ELEMENTS(Buf1.au32Page); i++)
|
|---|
| 996 | if (Buf1.au32Page[i] != 0xdeadbeef)
|
|---|
| 997 | {
|
|---|
| 998 | RTPrintf("tstInlineAsm: ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf1.au32Page[i], 0xdeadbeef);
|
|---|
| 999 | g_cErrors++;
|
|---|
| 1000 | }
|
|---|
| 1001 | for (unsigned i = 0; i < RT_ELEMENTS(Buf2.au32Page); i++)
|
|---|
| 1002 | if (Buf2.au32Page[i] != 0xcafeff01)
|
|---|
| 1003 | {
|
|---|
| 1004 | RTPrintf("tstInlineAsm: ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf2.au32Page[i], 0xcafeff01);
|
|---|
| 1005 | g_cErrors++;
|
|---|
| 1006 | }
|
|---|
| 1007 | for (unsigned i = 0; i < RT_ELEMENTS(Buf3.au32Page); i++)
|
|---|
| 1008 | if (Buf3.au32Page[i] != 0xf00dd00f)
|
|---|
| 1009 | {
|
|---|
| 1010 | RTPrintf("tstInlineAsm: ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf3.au32Page[i], 0xf00dd00f);
|
|---|
| 1011 | g_cErrors++;
|
|---|
| 1012 | }
|
|---|
| 1013 | }
|
|---|
| 1014 |
|
|---|
| 1015 |
|
|---|
| 1016 |
|
|---|
| 1017 | void tstASMMath(void)
|
|---|
| 1018 | {
|
|---|
| 1019 | uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
|
|---|
| 1020 | CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
|
|---|
| 1021 |
|
|---|
| 1022 | uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
|
|---|
| 1023 | CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
|
|---|
| 1024 |
|
|---|
| 1025 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
|
|---|
| 1026 | CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
|
|---|
| 1027 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
|
|---|
| 1028 | CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
|
|---|
| 1029 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
|
|---|
| 1030 | CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
|
|---|
| 1031 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
|
|---|
| 1032 | CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
|
|---|
| 1033 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
|
|---|
| 1034 | CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
|
|---|
| 1035 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
|
|---|
| 1036 | CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
|
|---|
| 1037 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
|
|---|
| 1038 | CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
|
|---|
| 1039 |
|
|---|
| 1040 | #if 0 /* bird: question is whether this should trap or not:
|
|---|
| 1041 | *
|
|---|
| 1042 | * frank: Of course it must trap:
|
|---|
| 1043 | *
|
|---|
| 1044 | * 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
|
|---|
| 1045 | *
|
|---|
| 1046 | * During the following division, the quotient must fit into a 32-bit register.
|
|---|
| 1047 | * Therefore the smallest valid divisor is
|
|---|
| 1048 | *
|
|---|
| 1049 | * (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
|
|---|
| 1050 | *
|
|---|
| 1051 | * which is definitely greater than 0x3b9aca00.
|
|---|
| 1052 | *
|
|---|
| 1053 | * bird: No, the C version does *not* crash. So, the question is whether there any
|
|---|
| 1054 | * code depending on it not crashing.
|
|---|
| 1055 | *
|
|---|
| 1056 | * Of course the assembly versions of the code crash right now for the reasons you've
|
|---|
| 1057 | * given, but the the 32-bit MSC version does not crash.
|
|---|
| 1058 | *
|
|---|
| 1059 | * frank: The C version does not crash but delivers incorrect results for this case.
|
|---|
| 1060 | * The reason is
|
|---|
| 1061 | *
|
|---|
| 1062 | * u.s.Hi = (unsigned long)(u64Hi / u32C);
|
|---|
| 1063 | *
|
|---|
| 1064 | * Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
|
|---|
| 1065 | * to 32 bit. If using this (optimized and fast) function we should just be sure that
|
|---|
| 1066 | * the operands are in a valid range.
|
|---|
| 1067 | */
|
|---|
| 1068 | u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
|
|---|
| 1069 | CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
|
|---|
| 1070 | #endif
|
|---|
| 1071 | }
|
|---|
| 1072 |
|
|---|
| 1073 | /*
|
|---|
| 1074 | * Make this static. We don't want to have this located on the stack.
|
|---|
| 1075 | */
|
|---|
| 1076 | void tstASMBench(void)
|
|---|
| 1077 | {
|
|---|
| 1078 | static uint8_t volatile s_u8;
|
|---|
| 1079 | static int8_t volatile s_i8;
|
|---|
| 1080 | static uint16_t volatile s_u16;
|
|---|
| 1081 | static int16_t volatile s_i16;
|
|---|
| 1082 | static uint32_t volatile s_u32;
|
|---|
| 1083 | static int32_t volatile s_i32;
|
|---|
| 1084 | static uint64_t volatile s_u64;
|
|---|
| 1085 | static int64_t volatile s_i64;
|
|---|
| 1086 | register unsigned i;
|
|---|
| 1087 | const unsigned cRounds = 1000000;
|
|---|
| 1088 | register uint64_t u64Elapsed;
|
|---|
| 1089 |
|
|---|
| 1090 | RTPrintf("tstInlineASM: Benchmarking:\n");
|
|---|
| 1091 |
|
|---|
| 1092 | #define BENCH(op, str) \
|
|---|
| 1093 | RTThreadYield(); \
|
|---|
| 1094 | u64Elapsed = ASMReadTSC(); \
|
|---|
| 1095 | for (i = cRounds; i > 0; i--) \
|
|---|
| 1096 | op; \
|
|---|
| 1097 | u64Elapsed = ASMReadTSC() - u64Elapsed; \
|
|---|
| 1098 | RTPrintf(" %-30s %3llu cycles\n", str, u64Elapsed / cRounds);
|
|---|
| 1099 |
|
|---|
| 1100 | BENCH(s_u32 = 0, "s_u32 = 0:");
|
|---|
| 1101 | BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8:");
|
|---|
| 1102 | BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8:");
|
|---|
| 1103 | BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16:");
|
|---|
| 1104 | BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16:");
|
|---|
| 1105 | BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32:");
|
|---|
| 1106 | BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32:");
|
|---|
| 1107 | BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64:");
|
|---|
| 1108 | BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64:");
|
|---|
| 1109 | BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8:");
|
|---|
| 1110 | BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8:");
|
|---|
| 1111 | BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16:");
|
|---|
| 1112 | BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16:");
|
|---|
| 1113 | BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32:");
|
|---|
| 1114 | BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32:");
|
|---|
| 1115 | BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64:");
|
|---|
| 1116 | BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64:");
|
|---|
| 1117 | BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8:");
|
|---|
| 1118 | BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8:");
|
|---|
| 1119 | BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16:");
|
|---|
| 1120 | BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16:");
|
|---|
| 1121 | BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32:");
|
|---|
| 1122 | BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32:");
|
|---|
| 1123 | BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64:");
|
|---|
| 1124 | BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64:");
|
|---|
| 1125 | BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32:");
|
|---|
| 1126 | BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32:");
|
|---|
| 1127 | BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64:");
|
|---|
| 1128 | BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64:");
|
|---|
| 1129 | BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg:");
|
|---|
| 1130 | BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg:");
|
|---|
| 1131 | BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg:");
|
|---|
| 1132 | BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg:");
|
|---|
| 1133 | BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32:");
|
|---|
| 1134 | BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32:");
|
|---|
| 1135 | BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32:");
|
|---|
| 1136 | BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32:");
|
|---|
| 1137 | BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32:");
|
|---|
| 1138 | BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32:");
|
|---|
| 1139 |
|
|---|
| 1140 | RTPrintf("Done.\n");
|
|---|
| 1141 |
|
|---|
| 1142 | #undef BENCH
|
|---|
| 1143 | }
|
|---|
| 1144 |
|
|---|
| 1145 |
|
|---|
| 1146 | int main(int argc, char *argv[])
|
|---|
| 1147 | {
|
|---|
| 1148 | RTR3Init();
|
|---|
| 1149 | RTPrintf("tstInlineAsm: TESTING\n");
|
|---|
| 1150 |
|
|---|
| 1151 | /*
|
|---|
| 1152 | * Execute the tests.
|
|---|
| 1153 | */
|
|---|
| 1154 | #if !defined(PIC) || !defined(RT_ARCH_X86)
|
|---|
| 1155 | tstASMCpuId();
|
|---|
| 1156 | #endif
|
|---|
| 1157 | tstASMAtomicXchgU8();
|
|---|
| 1158 | tstASMAtomicXchgU16();
|
|---|
| 1159 | tstASMAtomicXchgU32();
|
|---|
| 1160 | tstASMAtomicXchgU64();
|
|---|
| 1161 | #ifdef RT_ARCH_AMD64
|
|---|
| 1162 | tstASMAtomicXchgU128();
|
|---|
| 1163 | #endif
|
|---|
| 1164 | tstASMAtomicXchgPtr();
|
|---|
| 1165 | tstASMAtomicCmpXchgU32();
|
|---|
| 1166 | tstASMAtomicCmpXchgU64();
|
|---|
| 1167 | tstASMAtomicCmpXchgExU32();
|
|---|
| 1168 | tstASMAtomicCmpXchgExU64();
|
|---|
| 1169 | tstASMAtomicReadU64();
|
|---|
| 1170 | tstASMAtomicAddS32();
|
|---|
| 1171 | tstASMAtomicDecIncS32();
|
|---|
| 1172 | tstASMAtomicAndOrU32();
|
|---|
| 1173 | tstASMMemZeroPage();
|
|---|
| 1174 | tstASMMemZero32();
|
|---|
| 1175 | tstASMMemFill32();
|
|---|
| 1176 | tstASMMath();
|
|---|
| 1177 |
|
|---|
| 1178 | tstASMBench();
|
|---|
| 1179 |
|
|---|
| 1180 | /*
|
|---|
| 1181 | * Show the result.
|
|---|
| 1182 | */
|
|---|
| 1183 | if (!g_cErrors)
|
|---|
| 1184 | RTPrintf("tstInlineAsm: SUCCESS\n", g_cErrors);
|
|---|
| 1185 | else
|
|---|
| 1186 | RTPrintf("tstInlineAsm: FAILURE - %d errors\n", g_cErrors);
|
|---|
| 1187 | return !!g_cErrors;
|
|---|
| 1188 | }
|
|---|
| 1189 |
|
|---|
