tstRTInlineAsm.cpp@ 46072

Last change on this file since 46072 was 45860, checked in by vboxsync, 12 years ago
tstRTInlineAsm.cpp: Try fix the ASMCpuId test. (Don't expect local apic id to remain the same between two calls as we might be rescheduled.)
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1	/* $Id: tstRTInlineAsm.cpp 45860 2013-05-01 10:35:54Z vboxsync $ */
2	/** @file
3	* IPRT Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	/*******************************************************************************
28	* Header Files *
29	*******************************************************************************/
30	#include <iprt/asm.h>
31	#include <iprt/asm-math.h>
32
33	/* See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44018. Only gcc version 4.4
34	* is affected. No harm for the VBox code: If the cpuid code compiles, it works
35	* fine. */
36	#if defined(__GNUC__) && defined(RT_ARCH_X86) && defined(__PIC__)
37	# if __GNUC__ == 4 && __GNUC_MINOR__ == 4
38	# define GCC44_32BIT_PIC
39	# endif
40	#endif
41
42	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
43	# include <iprt/asm-amd64-x86.h>
44	#else
45	# include <iprt/time.h>
46	#endif
47	#include <iprt/stream.h>
48	#include <iprt/string.h>
49	#include <iprt/param.h>
50	#include <iprt/thread.h>
51	#include <iprt/test.h>
52	#include <iprt/time.h>
53
54
55
56	/*******************************************************************************
57	* Defined Constants And Macros *
58	*******************************************************************************/
59	#define CHECKVAL(val, expect, fmt) \
60	do \
61	{ \
62	if ((val) != (expect)) \
63	{ \
64	RTTestFailed(g_hTest, "%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
65	} \
66	} while (0)
67
68	#define CHECKOP(op, expect, fmt, type) \
69	do \
70	{ \
71	type val = op; \
72	if (val != (type)(expect)) \
73	{ \
74	RTTestFailed(g_hTest, "%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
75	} \
76	} while (0)
77
78	/**
79	* Calls a worker function with different worker variable storage types.
80	*/
81	#define DO_SIMPLE_TEST(name, type) \
82	do \
83	{ \
84	RTTestISub(#name); \
85	type StackVar; \
86	tst ## name ## Worker(&StackVar); \
87	\
88	type pVar = (type )RTTestGuardedAllocHead(g_hTest, sizeof(type)); \
89	RTTEST_CHECK_BREAK(g_hTest, pVar); \
90	tst ## name ## Worker(pVar); \
91	RTTestGuardedFree(g_hTest, pVar); \
92	\
93	pVar = (type *)RTTestGuardedAllocTail(g_hTest, sizeof(type)); \
94	RTTEST_CHECK_BREAK(g_hTest, pVar); \
95	tst ## name ## Worker(pVar); \
96	RTTestGuardedFree(g_hTest, pVar); \
97	} while (0)
98
99
100	/*******************************************************************************
101	* Global Variables *
102	*******************************************************************************/
103	/** The test instance. */
104	static RTTEST g_hTest;
105
106
107
108	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
109
110	const char *getCacheAss(unsigned u)
111	{
112	if (u == 0)
113	return "res0 ";
114	if (u == 1)
115	return "direct";
116	if (u >= 256)
117	return "???";
118
119	char *pszRet;
120	RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
121	return pszRet;
122	}
123
124
125	const char *getL2CacheAss(unsigned u)
126	{
127	switch (u)
128	{
129	case 0: return "off ";
130	case 1: return "direct";
131	case 2: return "2 way ";
132	case 3: return "res3 ";
133	case 4: return "4 way ";
134	case 5: return "res5 ";
135	case 6: return "8 way ";
136	case 7: return "res7 ";
137	case 8: return "16 way";
138	case 9: return "res9 ";
139	case 10: return "res10 ";
140	case 11: return "res11 ";
141	case 12: return "res12 ";
142	case 13: return "res13 ";
143	case 14: return "res14 ";
144	case 15: return "fully ";
145	default:
146	return "????";
147	}
148	}
149
150
151	/**
152	* Test and dump all possible info from the CPUID instruction.
153	*
154	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
155	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
156	*/
157	void tstASMCpuId(void)
158	{
159	RTTestISub("ASMCpuId");
160
161	unsigned iBit;
162	struct
163	{
164	uint32_t uEBX, uEAX, uEDX, uECX;
165	} s;
166	if (!ASMHasCpuId())
167	{
168	RTTestIPrintf(RTTESTLVL_ALWAYS, "warning! CPU doesn't support CPUID\n");
169	return;
170	}
171
172	/*
173	* Try the 0 function and use that for checking the ASMCpuId_* variants.
174	*/
175	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
176
177	uint32_t u32;
178
179	u32 = ASMCpuId_EAX(0);
180	CHECKVAL(u32, s.uEAX, "%x");
181	u32 = ASMCpuId_EBX(0);
182	CHECKVAL(u32, s.uEBX, "%x");
183	u32 = ASMCpuId_ECX(0);
184	CHECKVAL(u32, s.uECX, "%x");
185	u32 = ASMCpuId_EDX(0);
186	CHECKVAL(u32, s.uEDX, "%x");
187
188	uint32_t uECX2 = s.uECX - 1;
189	uint32_t uEDX2 = s.uEDX - 1;
190	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
191	CHECKVAL(uECX2, s.uECX, "%x");
192	CHECKVAL(uEDX2, s.uEDX, "%x");
193
194	/*
195	* Done testing, dump the information.
196	*/
197	RTTestIPrintf(RTTESTLVL_ALWAYS, "CPUID Dump\n");
198	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
199	const uint32_t cFunctions = s.uEAX;
200
201	/* raw dump */
202	RTTestIPrintf(RTTESTLVL_ALWAYS,
203	"\n"
204	" RAW Standard CPUIDs\n"
205	"Function eax ebx ecx edx\n");
206	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
207	{
208	ASMCpuId_Idx_ECX(iStd, 0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
209	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
210	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
211
212	/* Leaf 04 and leaf 0d output depend on the initial value of ECX
213	* The same seems to apply to invalid standard functions */
214	if (iStd > cFunctions)
215	continue;
216	if (iStd != 0x04 && iStd != 0x0b && iStd != 0x0d)
217	{
218	u32 = ASMCpuId_EAX(iStd);
219	CHECKVAL(u32, s.uEAX, "%x");
220
221	uint32_t u32EbxMask = UINT32_MAX;
222	if (iStd == 1)
223	u32EbxMask = UINT32_C(0x00ffffff); /* Omit the local apic ID in case we're rescheduled. */
224	u32 = ASMCpuId_EBX(iStd);
225	CHECKVAL(u32 & u32EbxMask, s.uEBX & u32EbxMask, "%x");
226
227	u32 = ASMCpuId_ECX(iStd);
228	CHECKVAL(u32, s.uECX, "%x");
229	u32 = ASMCpuId_EDX(iStd);
230	CHECKVAL(u32, s.uEDX, "%x");
231
232	uECX2 = s.uECX - 1;
233	uEDX2 = s.uEDX - 1;
234	ASMCpuId_ECX_EDX(iStd, &uECX2, &uEDX2);
235	CHECKVAL(uECX2, s.uECX, "%x");
236	CHECKVAL(uEDX2, s.uEDX, "%x");
237	}
238
239	if (iStd == 0x04)
240	for (uint32_t uECX = 1; s.uEAX & 0x1f; uECX++)
241	{
242	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
243	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
244	RTTESTI_CHECK_BREAK(uECX < 128);
245	}
246	else if (iStd == 0x0b)
247	for (uint32_t uECX = 1; (s.uEAX & 0x1f) && (s.uEBX & 0xffff); uECX++)
248	{
249	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
250	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
251	RTTESTI_CHECK_BREAK(uECX < 128);
252	}
253	else if (iStd == 0x0d)
254	for (uint32_t uECX = 1; s.uEAX != 0 \|\| s.uEBX != 0 \|\| s.uECX != 0 \|\| s.uEDX != 0; uECX++)
255	{
256	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
257	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
258	RTTESTI_CHECK_BREAK(uECX < 128);
259	}
260	}
261
262	/*
263	* Understandable output
264	*/
265	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
266	RTTestIPrintf(RTTESTLVL_ALWAYS,
267	"Name: %.04s%.04s%.04s\n"
268	"Support: 0-%u\n",
269	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
270	bool const fIntel = ASMIsIntelCpuEx(s.uEBX, s.uECX, s.uEDX);
271
272	/*
273	* Get Features.
274	*/
275	if (cFunctions >= 1)
276	{
277	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
278	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
279	RTTestIPrintf(RTTESTLVL_ALWAYS,
280	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
281	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
282	"Stepping: %d\n"
283	"Type: %d (%s)\n"
284	"APIC ID: %#04x\n"
285	"Logical CPUs: %d\n"
286	"CLFLUSH Size: %d\n"
287	"Brand ID: %#04x\n",
288	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
289	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
290	ASMGetCpuStepping(s.uEAX),
291	(s.uEAX >> 12) & 0x3, s_apszTypes[(s.uEAX >> 12) & 0x3],
292	(s.uEBX >> 24) & 0xff,
293	(s.uEBX >> 16) & 0xff,
294	(s.uEBX >> 8) & 0xff,
295	(s.uEBX >> 0) & 0xff);
296
297	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
298	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
299	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
300	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
301	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
302	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
303	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
304	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
305	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
306	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX8");
307	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
308	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
309	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SEP");
310	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
311	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
312	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
313	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
314	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
315	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
316	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSN");
317	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CLFSH");
318	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 20");
319	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DS");
320	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " ACPI");
321	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
322	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
323	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE");
324	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE2");
325	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SS");
326	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " HTT");
327	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 29");
328	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 30");
329	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 31");
330	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
331
332	/** @todo check intel docs. */
333	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
334	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE3");
335	for (iBit = 1; iBit < 13; iBit++)
336	if (s.uECX & RT_BIT(iBit))
337	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
338	if (s.uECX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX16");
339	for (iBit = 14; iBit < 32; iBit++)
340	if (s.uECX & RT_BIT(iBit))
341	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
342	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
343	}
344
345	/*
346	* Extended.
347	* Implemented after AMD specs.
348	*/
349	/** @todo check out the intel specs. */
350	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
351	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
352	{
353	RTTestIPrintf(RTTESTLVL_ALWAYS, "No extended CPUID info? Check the manual on how to detect this...\n");
354	return;
355	}
356	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
357
358	/* raw dump */
359	RTTestIPrintf(RTTESTLVL_ALWAYS,
360	"\n"
361	" RAW Extended CPUIDs\n"
362	"Function eax ebx ecx edx\n");
363	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
364	{
365	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
366	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
367	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
368
369	if (iExt > cExtFunctions)
370	continue; /* Invalid extended functions seems change the value if ECX changes */
371
372	u32 = ASMCpuId_EAX(iExt);
373	CHECKVAL(u32, s.uEAX, "%x");
374	u32 = ASMCpuId_EBX(iExt);
375	CHECKVAL(u32, s.uEBX, "%x");
376	u32 = ASMCpuId_ECX(iExt);
377	CHECKVAL(u32, s.uECX, "%x");
378	u32 = ASMCpuId_EDX(iExt);
379	CHECKVAL(u32, s.uEDX, "%x");
380
381	uECX2 = s.uECX - 1;
382	uEDX2 = s.uEDX - 1;
383	ASMCpuId_ECX_EDX(iExt, &uECX2, &uEDX2);
384	CHECKVAL(uECX2, s.uECX, "%x");
385	CHECKVAL(uEDX2, s.uEDX, "%x");
386	}
387
388	/*
389	* Understandable output
390	*/
391	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
392	RTTestIPrintf(RTTESTLVL_ALWAYS,
393	"Ext Name: %.4s%.4s%.4s\n"
394	"Ext Supports: 0x80000000-%#010x\n",
395	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
396
397	if (cExtFunctions >= 0x80000001)
398	{
399	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
400	RTTestIPrintf(RTTESTLVL_ALWAYS,
401	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
402	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
403	"Stepping: %d\n"
404	"Brand ID: %#05x\n",
405	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
406	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
407	ASMGetCpuStepping(s.uEAX),
408	s.uEBX & 0xfff);
409
410	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
411	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
412	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
413	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
414	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
415	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
416	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
417	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
418	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
419	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMPXCHG8B");
420	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
421	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
422	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SysCallSysRet");
423	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
424	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
425	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
426	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
427	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
428	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
429	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 18");
430	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 19");
431	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " NX");
432	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 21");
433	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MmxExt");
434	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
435	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
436	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FastFXSR");
437	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 26");
438	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " RDTSCP");
439	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 28");
440	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LongMode");
441	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNowExt");
442	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNow");
443	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
444
445	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
446	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LahfSahf");
447	if (s.uECX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CmpLegacy");
448	if (s.uECX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SVM");
449	if (s.uECX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3");
450	if (s.uECX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " AltMovCr8");
451	for (iBit = 5; iBit < 32; iBit++)
452	if (s.uECX & RT_BIT(iBit))
453	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
454	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
455	}
456
457	char szString[443+1] = {0};
458	if (cExtFunctions >= 0x80000002)
459	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
460	if (cExtFunctions >= 0x80000003)
461	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
462	if (cExtFunctions >= 0x80000004)
463	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
464	if (cExtFunctions >= 0x80000002)
465	RTTestIPrintf(RTTESTLVL_ALWAYS, "Full Name: %s\n", szString);
466
467	if (cExtFunctions >= 0x80000005)
468	{
469	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
470	RTTestIPrintf(RTTESTLVL_ALWAYS,
471	"TLB 2/4M Instr/Uni: %s %3d entries\n"
472	"TLB 2/4M Data: %s %3d entries\n",
473	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
474	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
475	RTTestIPrintf(RTTESTLVL_ALWAYS,
476	"TLB 4K Instr/Uni: %s %3d entries\n"
477	"TLB 4K Data: %s %3d entries\n",
478	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
479	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
480	RTTestIPrintf(RTTESTLVL_ALWAYS,
481	"L1 Instr Cache Line Size: %d bytes\n"
482	"L1 Instr Cache Lines Per Tag: %d\n"
483	"L1 Instr Cache Associativity: %s\n"
484	"L1 Instr Cache Size: %d KB\n",
485	(s.uEDX >> 0) & 0xff,
486	(s.uEDX >> 8) & 0xff,
487	getCacheAss((s.uEDX >> 16) & 0xff),
488	(s.uEDX >> 24) & 0xff);
489	RTTestIPrintf(RTTESTLVL_ALWAYS,
490	"L1 Data Cache Line Size: %d bytes\n"
491	"L1 Data Cache Lines Per Tag: %d\n"
492	"L1 Data Cache Associativity: %s\n"
493	"L1 Data Cache Size: %d KB\n",
494	(s.uECX >> 0) & 0xff,
495	(s.uECX >> 8) & 0xff,
496	getCacheAss((s.uECX >> 16) & 0xff),
497	(s.uECX >> 24) & 0xff);
498	}
499
500	if (cExtFunctions >= 0x80000006)
501	{
502	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
503	RTTestIPrintf(RTTESTLVL_ALWAYS,
504	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
505	"L2 TLB 2/4M Data: %s %4d entries\n",
506	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
507	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
508	RTTestIPrintf(RTTESTLVL_ALWAYS,
509	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
510	"L2 TLB 4K Data: %s %4d entries\n",
511	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
512	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
513	RTTestIPrintf(RTTESTLVL_ALWAYS,
514	"L2 Cache Line Size: %d bytes\n"
515	"L2 Cache Lines Per Tag: %d\n"
516	"L2 Cache Associativity: %s\n"
517	"L2 Cache Size: %d KB\n",
518	(s.uEDX >> 0) & 0xff,
519	(s.uEDX >> 8) & 0xf,
520	getL2CacheAss((s.uEDX >> 12) & 0xf),
521	(s.uEDX >> 16) & 0xffff);
522	}
523
524	if (cExtFunctions >= 0x80000007)
525	{
526	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
527	RTTestIPrintf(RTTESTLVL_ALWAYS, "APM Features: ");
528	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TS");
529	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FID");
530	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VID");
531	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TTP");
532	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TM");
533	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " STC");
534	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 6");
535	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 7");
536	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TscInvariant");
537	for (iBit = 9; iBit < 32; iBit++)
538	if (s.uEDX & RT_BIT(iBit))
539	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
540	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
541	}
542
543	if (cExtFunctions >= 0x80000008)
544	{
545	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
546	RTTestIPrintf(RTTESTLVL_ALWAYS,
547	"Physical Address Width: %d bits\n"
548	"Virtual Address Width: %d bits\n"
549	"Guest Physical Address Width: %d bits\n",
550	(s.uEAX >> 0) & 0xff,
551	(s.uEAX >> 8) & 0xff,
552	(s.uEAX >> 16) & 0xff);
553	RTTestIPrintf(RTTESTLVL_ALWAYS,
554	"Physical Core Count: %d\n",
555	((s.uECX >> 0) & 0xff) + 1);
556	if ((s.uECX >> 12) & 0xf)
557	RTTestIPrintf(RTTESTLVL_ALWAYS, "ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
558	}
559
560	if (cExtFunctions >= 0x8000000a)
561	{
562	ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
563	RTTestIPrintf(RTTESTLVL_ALWAYS,
564	"SVM Revision: %d (%#x)\n"
565	"Number of Address Space IDs: %d (%#x)\n",
566	s.uEAX & 0xff, s.uEAX & 0xff,
567	s.uEBX, s.uEBX);
568	}
569	}
570
571	#endif /* AMD64 \|\| X86 */
572
573	DECLINLINE(void) tstASMAtomicXchgU8Worker(uint8_t volatile *pu8)
574	{
575	*pu8 = 0;
576	CHECKOP(ASMAtomicXchgU8(pu8, 1), 0, "%#x", uint8_t);
577	CHECKVAL(*pu8, 1, "%#x");
578
579	CHECKOP(ASMAtomicXchgU8(pu8, 0), 1, "%#x", uint8_t);
580	CHECKVAL(*pu8, 0, "%#x");
581
582	CHECKOP(ASMAtomicXchgU8(pu8, 0xff), 0, "%#x", uint8_t);
583	CHECKVAL(*pu8, 0xff, "%#x");
584
585	CHECKOP(ASMAtomicXchgU8(pu8, 0x87), 0xffff, "%#x", uint8_t);
586	CHECKVAL(*pu8, 0x87, "%#x");
587	}
588
589
590	static void tstASMAtomicXchgU8(void)
591	{
592	DO_SIMPLE_TEST(ASMAtomicXchgU8, uint8_t);
593	}
594
595
596	DECLINLINE(void) tstASMAtomicXchgU16Worker(uint16_t volatile *pu16)
597	{
598	*pu16 = 0;
599
600	CHECKOP(ASMAtomicXchgU16(pu16, 1), 0, "%#x", uint16_t);
601	CHECKVAL(*pu16, 1, "%#x");
602
603	CHECKOP(ASMAtomicXchgU16(pu16, 0), 1, "%#x", uint16_t);
604	CHECKVAL(*pu16, 0, "%#x");
605
606	CHECKOP(ASMAtomicXchgU16(pu16, 0xffff), 0, "%#x", uint16_t);
607	CHECKVAL(*pu16, 0xffff, "%#x");
608
609	CHECKOP(ASMAtomicXchgU16(pu16, 0x8765), 0xffff, "%#x", uint16_t);
610	CHECKVAL(*pu16, 0x8765, "%#x");
611	}
612
613
614	static void tstASMAtomicXchgU16(void)
615	{
616	DO_SIMPLE_TEST(ASMAtomicXchgU16, uint16_t);
617	}
618
619
620	DECLINLINE(void) tstASMAtomicXchgU32Worker(uint32_t volatile *pu32)
621	{
622	*pu32 = 0;
623
624	CHECKOP(ASMAtomicXchgU32(pu32, 1), 0, "%#x", uint32_t);
625	CHECKVAL(*pu32, 1, "%#x");
626
627	CHECKOP(ASMAtomicXchgU32(pu32, 0), 1, "%#x", uint32_t);
628	CHECKVAL(*pu32, 0, "%#x");
629
630	CHECKOP(ASMAtomicXchgU32(pu32, ~UINT32_C(0)), 0, "%#x", uint32_t);
631	CHECKVAL(*pu32, ~UINT32_C(0), "%#x");
632
633	CHECKOP(ASMAtomicXchgU32(pu32, 0x87654321), ~UINT32_C(0), "%#x", uint32_t);
634	CHECKVAL(*pu32, 0x87654321, "%#x");
635	}
636
637
638	static void tstASMAtomicXchgU32(void)
639	{
640	DO_SIMPLE_TEST(ASMAtomicXchgU32, uint32_t);
641	}
642
643
644	DECLINLINE(void) tstASMAtomicXchgU64Worker(uint64_t volatile *pu64)
645	{
646	*pu64 = 0;
647
648	CHECKOP(ASMAtomicXchgU64(pu64, 1), UINT64_C(0), "%#llx", uint64_t);
649	CHECKVAL(*pu64, UINT64_C(1), "%#llx");
650
651	CHECKOP(ASMAtomicXchgU64(pu64, 0), UINT64_C(1), "%#llx", uint64_t);
652	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
653
654	CHECKOP(ASMAtomicXchgU64(pu64, ~UINT64_C(0)), UINT64_C(0), "%#llx", uint64_t);
655	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
656
657	CHECKOP(ASMAtomicXchgU64(pu64, UINT64_C(0xfedcba0987654321)), ~UINT64_C(0), "%#llx", uint64_t);
658	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
659	}
660
661
662	static void tstASMAtomicXchgU64(void)
663	{
664	DO_SIMPLE_TEST(ASMAtomicXchgU64, uint64_t);
665	}
666
667
668	DECLINLINE(void) tstASMAtomicXchgPtrWorker(void * volatile *ppv)
669	{
670	*ppv = NULL;
671
672	CHECKOP(ASMAtomicXchgPtr(ppv, (void )(~(uintptr_t)0)), NULL, "%p", void );
673	CHECKVAL(ppv, (void )(~(uintptr_t)0), "%p");
674
675	CHECKOP(ASMAtomicXchgPtr(ppv, (void )0x87654321), (void )(~(uintptr_t)0), "%p", void *);
676	CHECKVAL(ppv, (void )0x87654321, "%p");
677
678	CHECKOP(ASMAtomicXchgPtr(ppv, NULL), (void )0x87654321, "%p", void );
679	CHECKVAL(*ppv, NULL, "%p");
680	}
681
682
683	static void tstASMAtomicXchgPtr(void)
684	{
685	DO_SIMPLE_TEST(ASMAtomicXchgPtr, void *);
686	}
687
688
689	DECLINLINE(void) tstASMAtomicCmpXchgU8Worker(uint8_t volatile *pu8)
690	{
691	*pu8 = 0xff;
692
693	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0), false, "%d", bool);
694	CHECKVAL(*pu8, 0xff, "%x");
695
696	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0xff), true, "%d", bool);
697	CHECKVAL(*pu8, 0, "%x");
698
699	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x79, 0xff), false, "%d", bool);
700	CHECKVAL(*pu8, 0, "%x");
701
702	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x97, 0), true, "%d", bool);
703	CHECKVAL(*pu8, 0x97, "%x");
704	}
705
706
707	static void tstASMAtomicCmpXchgU8(void)
708	{
709	DO_SIMPLE_TEST(ASMAtomicCmpXchgU8, uint8_t);
710	}
711
712
713	DECLINLINE(void) tstASMAtomicCmpXchgU32Worker(uint32_t volatile *pu32)
714	{
715	*pu32 = UINT32_C(0xffffffff);
716
717	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, 0), false, "%d", bool);
718	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
719
720	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, UINT32_C(0xffffffff)), true, "%d", bool);
721	CHECKVAL(*pu32, 0, "%x");
722
723	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff)), false, "%d", bool);
724	CHECKVAL(*pu32, 0, "%x");
725
726	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), 0), true, "%d", bool);
727	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
728	}
729
730
731	static void tstASMAtomicCmpXchgU32(void)
732	{
733	DO_SIMPLE_TEST(ASMAtomicCmpXchgU32, uint32_t);
734	}
735
736
737
738	DECLINLINE(void) tstASMAtomicCmpXchgU64Worker(uint64_t volatile *pu64)
739	{
740	*pu64 = UINT64_C(0xffffffffffffff);
741
742	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, 0), false, "%d", bool);
743	CHECKVAL(*pu64, UINT64_C(0xffffffffffffff), "%#llx");
744
745	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, UINT64_C(0xffffffffffffff)), true, "%d", bool);
746	CHECKVAL(*pu64, 0, "%x");
747
748	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff)), false, "%d", bool);
749	CHECKVAL(*pu64, 0, "%x");
750
751	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000)), false, "%d", bool);
752	CHECKVAL(*pu64, 0, "%x");
753
754	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 0), true, "%d", bool);
755	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%#llx");
756	}
757
758
759	static void tstASMAtomicCmpXchgU64(void)
760	{
761	DO_SIMPLE_TEST(ASMAtomicCmpXchgU64, uint64_t);
762	}
763
764
765	DECLINLINE(void) tstASMAtomicCmpXchgExU32Worker(uint32_t volatile *pu32)
766	{
767	*pu32 = UINT32_C(0xffffffff);
768	uint32_t u32Old = UINT32_C(0x80005111);
769
770	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, 0, &u32Old), false, "%d", bool);
771	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
772	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
773
774	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0xffffffff), &u32Old), true, "%d", bool);
775	CHECKVAL(*pu32, 0, "%x");
776	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
777
778	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff), &u32Old), false, "%d", bool);
779	CHECKVAL(*pu32, 0, "%x");
780	CHECKVAL(u32Old, 0, "%x");
781
782	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), 0, &u32Old), true, "%d", bool);
783	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
784	CHECKVAL(u32Old, 0, "%x");
785
786	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0x8008efd), &u32Old), true, "%d", bool);
787	CHECKVAL(*pu32, 0, "%x");
788	CHECKVAL(u32Old, UINT32_C(0x8008efd), "%x");
789	}
790
791
792	static void tstASMAtomicCmpXchgExU32(void)
793	{
794	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU32, uint32_t);
795	}
796
797
798	DECLINLINE(void) tstASMAtomicCmpXchgExU64Worker(uint64_t volatile *pu64)
799	{
800	*pu64 = UINT64_C(0xffffffffffffffff);
801	uint64_t u64Old = UINT64_C(0x8000000051111111);
802
803	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, 0, &u64Old), false, "%d", bool);
804	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%llx");
805	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
806
807	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0xffffffffffffffff), &u64Old), true, "%d", bool);
808	CHECKVAL(*pu64, UINT64_C(0), "%llx");
809	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
810
811	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0xffffffff, &u64Old), false, "%d", bool);
812	CHECKVAL(*pu64, UINT64_C(0), "%llx");
813	CHECKVAL(u64Old, UINT64_C(0), "%llx");
814
815	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000), &u64Old), false, "%d", bool);
816	CHECKVAL(*pu64, UINT64_C(0), "%llx");
817	CHECKVAL(u64Old, UINT64_C(0), "%llx");
818
819	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0, &u64Old), true, "%d", bool);
820	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%llx");
821	CHECKVAL(u64Old, UINT64_C(0), "%llx");
822
823	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0x80040008008efd), &u64Old), true, "%d", bool);
824	CHECKVAL(*pu64, UINT64_C(0), "%llx");
825	CHECKVAL(u64Old, UINT64_C(0x80040008008efd), "%llx");
826	}
827
828
829	static void tstASMAtomicCmpXchgExU64(void)
830	{
831	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU64, uint64_t);
832	}
833
834
835	DECLINLINE(void) tstASMAtomicReadU64Worker(uint64_t volatile *pu64)
836	{
837	*pu64 = 0;
838
839	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
840	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
841
842	*pu64 = ~UINT64_C(0);
843	CHECKOP(ASMAtomicReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
844	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
845
846	*pu64 = UINT64_C(0xfedcba0987654321);
847	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
848	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
849	}
850
851
852	static void tstASMAtomicReadU64(void)
853	{
854	DO_SIMPLE_TEST(ASMAtomicReadU64, uint64_t);
855	}
856
857
858	DECLINLINE(void) tstASMAtomicUoReadU64Worker(uint64_t volatile *pu64)
859	{
860	*pu64 = 0;
861
862	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
863	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
864
865	*pu64 = ~UINT64_C(0);
866	CHECKOP(ASMAtomicUoReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
867	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
868
869	*pu64 = UINT64_C(0xfedcba0987654321);
870	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
871	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
872	}
873
874
875	static void tstASMAtomicUoReadU64(void)
876	{
877	DO_SIMPLE_TEST(ASMAtomicUoReadU64, uint64_t);
878	}
879
880
881	DECLINLINE(void) tstASMAtomicAddS32Worker(int32_t *pi32)
882	{
883	int32_t i32Rc;
884	*pi32 = 10;
885	#define MYCHECK(op, rc, val) \
886	do { \
887	i32Rc = op; \
888	if (i32Rc != (rc)) \
889	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
890	if (*pi32 != (val)) \
891	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, val); \
892	} while (0)
893	MYCHECK(ASMAtomicAddS32(pi32, 1), 10, 11);
894	MYCHECK(ASMAtomicAddS32(pi32, -2), 11, 9);
895	MYCHECK(ASMAtomicAddS32(pi32, -9), 9, 0);
896	MYCHECK(ASMAtomicAddS32(pi32, -0x7fffffff), 0, -0x7fffffff);
897	MYCHECK(ASMAtomicAddS32(pi32, 0), -0x7fffffff, -0x7fffffff);
898	MYCHECK(ASMAtomicAddS32(pi32, 0x7fffffff), -0x7fffffff, 0);
899	MYCHECK(ASMAtomicAddS32(pi32, 0), 0, 0);
900	#undef MYCHECK
901	}
902
903	static void tstASMAtomicAddS32(void)
904	{
905	DO_SIMPLE_TEST(ASMAtomicAddS32, int32_t);
906	}
907
908
909	DECLINLINE(void) tstASMAtomicAddS64Worker(int64_t volatile *pi64)
910	{
911	int64_t i64Rc;
912	*pi64 = 10;
913	#define MYCHECK(op, rc, val) \
914	do { \
915	i64Rc = op; \
916	if (i64Rc != (rc)) \
917	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %llx expected %llx\n", __FUNCTION__, __LINE__, #op, i64Rc, (int64_t)rc); \
918	if (*pi64 != (val)) \
919	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%llx expected %llx\n", __FUNCTION__, __LINE__, #op, pi64, (int64_t)(val)); \
920	} while (0)
921	MYCHECK(ASMAtomicAddS64(pi64, 1), 10, 11);
922	MYCHECK(ASMAtomicAddS64(pi64, -2), 11, 9);
923	MYCHECK(ASMAtomicAddS64(pi64, -9), 9, 0);
924	MYCHECK(ASMAtomicAddS64(pi64, -INT64_MAX), 0, -INT64_MAX);
925	MYCHECK(ASMAtomicAddS64(pi64, 0), -INT64_MAX, -INT64_MAX);
926	MYCHECK(ASMAtomicAddS64(pi64, -1), -INT64_MAX, INT64_MIN);
927	MYCHECK(ASMAtomicAddS64(pi64, INT64_MAX), INT64_MIN, -1);
928	MYCHECK(ASMAtomicAddS64(pi64, 1), -1, 0);
929	MYCHECK(ASMAtomicAddS64(pi64, 0), 0, 0);
930	#undef MYCHECK
931	}
932
933
934	static void tstASMAtomicAddS64(void)
935	{
936	DO_SIMPLE_TEST(ASMAtomicAddS64, int64_t);
937	}
938
939
940	DECLINLINE(void) tstASMAtomicDecIncS32Worker(int32_t volatile *pi32)
941	{
942	int32_t i32Rc;
943	*pi32 = 10;
944	#define MYCHECK(op, rc) \
945	do { \
946	i32Rc = op; \
947	if (i32Rc != (rc)) \
948	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
949	if (*pi32 != (rc)) \
950	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, rc); \
951	} while (0)
952	MYCHECK(ASMAtomicDecS32(pi32), 9);
953	MYCHECK(ASMAtomicDecS32(pi32), 8);
954	MYCHECK(ASMAtomicDecS32(pi32), 7);
955	MYCHECK(ASMAtomicDecS32(pi32), 6);
956	MYCHECK(ASMAtomicDecS32(pi32), 5);
957	MYCHECK(ASMAtomicDecS32(pi32), 4);
958	MYCHECK(ASMAtomicDecS32(pi32), 3);
959	MYCHECK(ASMAtomicDecS32(pi32), 2);
960	MYCHECK(ASMAtomicDecS32(pi32), 1);
961	MYCHECK(ASMAtomicDecS32(pi32), 0);
962	MYCHECK(ASMAtomicDecS32(pi32), -1);
963	MYCHECK(ASMAtomicDecS32(pi32), -2);
964	MYCHECK(ASMAtomicIncS32(pi32), -1);
965	MYCHECK(ASMAtomicIncS32(pi32), 0);
966	MYCHECK(ASMAtomicIncS32(pi32), 1);
967	MYCHECK(ASMAtomicIncS32(pi32), 2);
968	MYCHECK(ASMAtomicIncS32(pi32), 3);
969	MYCHECK(ASMAtomicDecS32(pi32), 2);
970	MYCHECK(ASMAtomicIncS32(pi32), 3);
971	MYCHECK(ASMAtomicDecS32(pi32), 2);
972	MYCHECK(ASMAtomicIncS32(pi32), 3);
973	#undef MYCHECK
974	}
975
976
977	static void tstASMAtomicDecIncS32(void)
978	{
979	DO_SIMPLE_TEST(ASMAtomicDecIncS32, int32_t);
980	}
981
982
983	DECLINLINE(void) tstASMAtomicDecIncS64Worker(int64_t volatile *pi64)
984	{
985	int64_t i64Rc;
986	*pi64 = 10;
987	#define MYCHECK(op, rc) \
988	do { \
989	i64Rc = op; \
990	if (i64Rc != (rc)) \
991	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %lld expected %lld\n", __FUNCTION__, __LINE__, #op, i64Rc, rc); \
992	if (*pi64 != (rc)) \
993	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%lld expected %lld\n", __FUNCTION__, __LINE__, #op, pi64, rc); \
994	} while (0)
995	MYCHECK(ASMAtomicDecS64(pi64), 9);
996	MYCHECK(ASMAtomicDecS64(pi64), 8);
997	MYCHECK(ASMAtomicDecS64(pi64), 7);
998	MYCHECK(ASMAtomicDecS64(pi64), 6);
999	MYCHECK(ASMAtomicDecS64(pi64), 5);
1000	MYCHECK(ASMAtomicDecS64(pi64), 4);
1001	MYCHECK(ASMAtomicDecS64(pi64), 3);
1002	MYCHECK(ASMAtomicDecS64(pi64), 2);
1003	MYCHECK(ASMAtomicDecS64(pi64), 1);
1004	MYCHECK(ASMAtomicDecS64(pi64), 0);
1005	MYCHECK(ASMAtomicDecS64(pi64), -1);
1006	MYCHECK(ASMAtomicDecS64(pi64), -2);
1007	MYCHECK(ASMAtomicIncS64(pi64), -1);
1008	MYCHECK(ASMAtomicIncS64(pi64), 0);
1009	MYCHECK(ASMAtomicIncS64(pi64), 1);
1010	MYCHECK(ASMAtomicIncS64(pi64), 2);
1011	MYCHECK(ASMAtomicIncS64(pi64), 3);
1012	MYCHECK(ASMAtomicDecS64(pi64), 2);
1013	MYCHECK(ASMAtomicIncS64(pi64), 3);
1014	MYCHECK(ASMAtomicDecS64(pi64), 2);
1015	MYCHECK(ASMAtomicIncS64(pi64), 3);
1016	#undef MYCHECK
1017	}
1018
1019
1020	static void tstASMAtomicDecIncS64(void)
1021	{
1022	DO_SIMPLE_TEST(ASMAtomicDecIncS64, int64_t);
1023	}
1024
1025
1026	DECLINLINE(void) tstASMAtomicAndOrU32Worker(uint32_t volatile *pu32)
1027	{
1028	*pu32 = UINT32_C(0xffffffff);
1029
1030	ASMAtomicOrU32(pu32, UINT32_C(0xffffffff));
1031	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1032
1033	ASMAtomicAndU32(pu32, UINT32_C(0xffffffff));
1034	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1035
1036	ASMAtomicAndU32(pu32, UINT32_C(0x8f8f8f8f));
1037	CHECKVAL(*pu32, UINT32_C(0x8f8f8f8f), "%x");
1038
1039	ASMAtomicOrU32(pu32, UINT32_C(0x70707070));
1040	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1041
1042	ASMAtomicAndU32(pu32, UINT32_C(1));
1043	CHECKVAL(*pu32, UINT32_C(1), "%x");
1044
1045	ASMAtomicOrU32(pu32, UINT32_C(0x80000000));
1046	CHECKVAL(*pu32, UINT32_C(0x80000001), "%x");
1047
1048	ASMAtomicAndU32(pu32, UINT32_C(0x80000000));
1049	CHECKVAL(*pu32, UINT32_C(0x80000000), "%x");
1050
1051	ASMAtomicAndU32(pu32, UINT32_C(0));
1052	CHECKVAL(*pu32, UINT32_C(0), "%x");
1053
1054	ASMAtomicOrU32(pu32, UINT32_C(0x42424242));
1055	CHECKVAL(*pu32, UINT32_C(0x42424242), "%x");
1056	}
1057
1058
1059	static void tstASMAtomicAndOrU32(void)
1060	{
1061	DO_SIMPLE_TEST(ASMAtomicAndOrU32, uint32_t);
1062	}
1063
1064
1065	DECLINLINE(void) tstASMAtomicAndOrU64Worker(uint64_t volatile *pu64)
1066	{
1067	*pu64 = UINT64_C(0xffffffff);
1068
1069	ASMAtomicOrU64(pu64, UINT64_C(0xffffffff));
1070	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1071
1072	ASMAtomicAndU64(pu64, UINT64_C(0xffffffff));
1073	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1074
1075	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f));
1076	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f), "%x");
1077
1078	ASMAtomicOrU64(pu64, UINT64_C(0x70707070));
1079	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1080
1081	ASMAtomicAndU64(pu64, UINT64_C(1));
1082	CHECKVAL(*pu64, UINT64_C(1), "%x");
1083
1084	ASMAtomicOrU64(pu64, UINT64_C(0x80000000));
1085	CHECKVAL(*pu64, UINT64_C(0x80000001), "%x");
1086
1087	ASMAtomicAndU64(pu64, UINT64_C(0x80000000));
1088	CHECKVAL(*pu64, UINT64_C(0x80000000), "%x");
1089
1090	ASMAtomicAndU64(pu64, UINT64_C(0));
1091	CHECKVAL(*pu64, UINT64_C(0), "%x");
1092
1093	ASMAtomicOrU64(pu64, UINT64_C(0x42424242));
1094	CHECKVAL(*pu64, UINT64_C(0x42424242), "%x");
1095
1096	// Same as above, but now 64-bit wide.
1097	ASMAtomicAndU64(pu64, UINT64_C(0));
1098	CHECKVAL(*pu64, UINT64_C(0), "%x");
1099
1100	ASMAtomicOrU64(pu64, UINT64_C(0xffffffffffffffff));
1101	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1102
1103	ASMAtomicAndU64(pu64, UINT64_C(0xffffffffffffffff));
1104	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1105
1106	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f8f8f8f8f));
1107	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f8f8f8f8f), "%x");
1108
1109	ASMAtomicOrU64(pu64, UINT64_C(0x7070707070707070));
1110	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1111
1112	ASMAtomicAndU64(pu64, UINT64_C(1));
1113	CHECKVAL(*pu64, UINT64_C(1), "%x");
1114
1115	ASMAtomicOrU64(pu64, UINT64_C(0x8000000000000000));
1116	CHECKVAL(*pu64, UINT64_C(0x8000000000000001), "%x");
1117
1118	ASMAtomicAndU64(pu64, UINT64_C(0x8000000000000000));
1119	CHECKVAL(*pu64, UINT64_C(0x8000000000000000), "%x");
1120
1121	ASMAtomicAndU64(pu64, UINT64_C(0));
1122	CHECKVAL(*pu64, UINT64_C(0), "%x");
1123
1124	ASMAtomicOrU64(pu64, UINT64_C(0x4242424242424242));
1125	CHECKVAL(*pu64, UINT64_C(0x4242424242424242), "%x");
1126	}
1127
1128
1129	static void tstASMAtomicAndOrU64(void)
1130	{
1131	DO_SIMPLE_TEST(ASMAtomicAndOrU64, uint64_t);
1132	}
1133
1134
1135	typedef struct
1136	{
1137	uint8_t ab[PAGE_SIZE];
1138	} TSTPAGE;
1139
1140
1141	DECLINLINE(void) tstASMMemZeroPageWorker(TSTPAGE *pPage)
1142	{
1143	for (unsigned j = 0; j < 16; j++)
1144	{
1145	memset(pPage, 0x11 * j, sizeof(*pPage));
1146	ASMMemZeroPage(pPage);
1147	for (unsigned i = 0; i < sizeof(pPage->ab); i++)
1148	if (pPage->ab[i])
1149	RTTestFailed(g_hTest, "ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
1150	}
1151	}
1152
1153
1154	static void tstASMMemZeroPage(void)
1155	{
1156	DO_SIMPLE_TEST(ASMMemZeroPage, TSTPAGE);
1157	}
1158
1159
1160	void tstASMMemIsZeroPage(RTTEST hTest)
1161	{
1162	RTTestSub(hTest, "ASMMemIsZeroPage");
1163
1164	void *pvPage1 = RTTestGuardedAllocHead(hTest, PAGE_SIZE);
1165	void *pvPage2 = RTTestGuardedAllocTail(hTest, PAGE_SIZE);
1166	RTTESTI_CHECK_RETV(pvPage1 && pvPage2);
1167
1168	memset(pvPage1, 0, PAGE_SIZE);
1169	memset(pvPage2, 0, PAGE_SIZE);
1170	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage1));
1171	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage2));
1172
1173	memset(pvPage1, 0xff, PAGE_SIZE);
1174	memset(pvPage2, 0xff, PAGE_SIZE);
1175	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1176	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1177
1178	memset(pvPage1, 0, PAGE_SIZE);
1179	memset(pvPage2, 0, PAGE_SIZE);
1180	for (unsigned off = 0; off < PAGE_SIZE; off++)
1181	{
1182	((uint8_t *)pvPage1)[off] = 1;
1183	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1184	((uint8_t *)pvPage1)[off] = 0;
1185
1186	((uint8_t *)pvPage2)[off] = 0x80;
1187	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1188	((uint8_t *)pvPage2)[off] = 0;
1189	}
1190
1191	RTTestSubDone(hTest);
1192	}
1193
1194
1195	void tstASMMemZero32(void)
1196	{
1197	RTTestSub(g_hTest, "ASMMemFill32");
1198
1199	struct
1200	{
1201	uint64_t u64Magic1;
1202	uint8_t abPage[PAGE_SIZE - 32];
1203	uint64_t u64Magic2;
1204	} Buf1, Buf2, Buf3;
1205
1206	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1207	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
1208	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1209	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1210	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
1211	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1212	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1213	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
1214	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1215	ASMMemZero32(Buf1.abPage, sizeof(Buf1.abPage));
1216	ASMMemZero32(Buf2.abPage, sizeof(Buf2.abPage));
1217	ASMMemZero32(Buf3.abPage, sizeof(Buf3.abPage));
1218	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1219	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1220	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1221	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1222	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1223	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1224	{
1225	RTTestFailed(g_hTest, "ASMMemZero32 violated one/both magic(s)!\n");
1226	}
1227	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.abPage); i++)
1228	if (Buf1.abPage[i])
1229	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1230	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.abPage); i++)
1231	if (Buf2.abPage[i])
1232	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1233	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.abPage); i++)
1234	if (Buf3.abPage[i])
1235	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1236	}
1237
1238
1239	void tstASMMemFill32(void)
1240	{
1241	RTTestSub(g_hTest, "ASMMemFill32");
1242
1243	struct
1244	{
1245	uint64_t u64Magic1;
1246	uint32_t au32Page[PAGE_SIZE / 4];
1247	uint64_t u64Magic2;
1248	} Buf1;
1249	struct
1250	{
1251	uint64_t u64Magic1;
1252	uint32_t au32Page[(PAGE_SIZE / 4) - 3];
1253	uint64_t u64Magic2;
1254	} Buf2;
1255	struct
1256	{
1257	uint64_t u64Magic1;
1258	uint32_t au32Page[(PAGE_SIZE / 4) - 1];
1259	uint64_t u64Magic2;
1260	} Buf3;
1261
1262	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1263	memset(Buf1.au32Page, 0x55, sizeof(Buf1.au32Page));
1264	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1265	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1266	memset(Buf2.au32Page, 0x77, sizeof(Buf2.au32Page));
1267	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1268	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1269	memset(Buf3.au32Page, 0x99, sizeof(Buf3.au32Page));
1270	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1271	ASMMemFill32(Buf1.au32Page, sizeof(Buf1.au32Page), 0xdeadbeef);
1272	ASMMemFill32(Buf2.au32Page, sizeof(Buf2.au32Page), 0xcafeff01);
1273	ASMMemFill32(Buf3.au32Page, sizeof(Buf3.au32Page), 0xf00dd00f);
1274	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1275	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1276	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1277	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1278	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1279	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1280	RTTestFailed(g_hTest, "ASMMemFill32 violated one/both magic(s)!\n");
1281	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.au32Page); i++)
1282	if (Buf1.au32Page[i] != 0xdeadbeef)
1283	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf1.au32Page[i], 0xdeadbeef);
1284	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.au32Page); i++)
1285	if (Buf2.au32Page[i] != 0xcafeff01)
1286	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf2.au32Page[i], 0xcafeff01);
1287	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.au32Page); i++)
1288	if (Buf3.au32Page[i] != 0xf00dd00f)
1289	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf3.au32Page[i], 0xf00dd00f);
1290	}
1291
1292
1293
1294	void tstASMMath(void)
1295	{
1296	RTTestSub(g_hTest, "Math");
1297
1298	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
1299	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
1300
1301	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
1302	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
1303
1304	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1305	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
1306	CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
1307	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
1308	CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
1309	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1310	CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
1311	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1312	CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
1313	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
1314	CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
1315	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
1316	CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
1317	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
1318	CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
1319
1320	# if 0 /* bird: question is whether this should trap or not:
1321	*
1322	* frank: Of course it must trap:
1323	*
1324	* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
1325	*
1326	* During the following division, the quotient must fit into a 32-bit register.
1327	* Therefore the smallest valid divisor is
1328	*
1329	* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
1330	*
1331	* which is definitely greater than 0x3b9aca00.
1332	*
1333	* bird: No, the C version does not crash. So, the question is whether there's any
1334	* code depending on it not crashing.
1335	*
1336	* Of course the assembly versions of the code crash right now for the reasons you've
1337	* given, but the 32-bit MSC version does not crash.
1338	*
1339	* frank: The C version does not crash but delivers incorrect results for this case.
1340	* The reason is
1341	*
1342	* u.s.Hi = (unsigned long)(u64Hi / u32C);
1343	*
1344	* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
1345	* to 32 bit. If using this (optimized and fast) function we should just be sure that
1346	* the operands are in a valid range.
1347	*/
1348	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
1349	CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
1350	# endif
1351	#endif /* AMD64 \|\| X86 */
1352
1353	u32 = ASMModU64ByU32RetU32(UINT64_C(0x0ffffff8c65d6731), UINT32_C(0x77d7daf8));
1354	CHECKVAL(u32, UINT32_C(0x3B642451), "%#010RX32");
1355
1356	int32_t i32;
1357	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(-2));
1358	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1359	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(2));
1360	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1361	i32 = ASMModS64ByS32RetS32(INT64_C(11), INT32_C(-2));
1362	CHECKVAL(i32, INT32_C(1), "%010RI32");
1363
1364	i32 = ASMModS64ByS32RetS32(INT64_C(92233720368547758), INT32_C(2147483647));
1365	CHECKVAL(i32, INT32_C(2104533974), "%010RI32");
1366	i32 = ASMModS64ByS32RetS32(INT64_C(-92233720368547758), INT32_C(2147483647));
1367	CHECKVAL(i32, INT32_C(-2104533974), "%010RI32");
1368	}
1369
1370
1371	void tstASMByteSwap(void)
1372	{
1373	RTTestSub(g_hTest, "ASMByteSwap*");
1374
1375	uint64_t u64In = UINT64_C(0x0011223344556677);
1376	uint64_t u64Out = ASMByteSwapU64(u64In);
1377	CHECKVAL(u64In, UINT64_C(0x0011223344556677), "%#018RX64");
1378	CHECKVAL(u64Out, UINT64_C(0x7766554433221100), "%#018RX64");
1379	u64Out = ASMByteSwapU64(u64Out);
1380	CHECKVAL(u64Out, u64In, "%#018RX64");
1381	u64In = UINT64_C(0x0123456789abcdef);
1382	u64Out = ASMByteSwapU64(u64In);
1383	CHECKVAL(u64In, UINT64_C(0x0123456789abcdef), "%#018RX64");
1384	CHECKVAL(u64Out, UINT64_C(0xefcdab8967452301), "%#018RX64");
1385	u64Out = ASMByteSwapU64(u64Out);
1386	CHECKVAL(u64Out, u64In, "%#018RX64");
1387	u64In = 0;
1388	u64Out = ASMByteSwapU64(u64In);
1389	CHECKVAL(u64Out, u64In, "%#018RX64");
1390	u64In = ~(uint64_t)0;
1391	u64Out = ASMByteSwapU64(u64In);
1392	CHECKVAL(u64Out, u64In, "%#018RX64");
1393
1394	uint32_t u32In = UINT32_C(0x00112233);
1395	uint32_t u32Out = ASMByteSwapU32(u32In);
1396	CHECKVAL(u32In, UINT32_C(0x00112233), "%#010RX32");
1397	CHECKVAL(u32Out, UINT32_C(0x33221100), "%#010RX32");
1398	u32Out = ASMByteSwapU32(u32Out);
1399	CHECKVAL(u32Out, u32In, "%#010RX32");
1400	u32In = UINT32_C(0x12345678);
1401	u32Out = ASMByteSwapU32(u32In);
1402	CHECKVAL(u32In, UINT32_C(0x12345678), "%#010RX32");
1403	CHECKVAL(u32Out, UINT32_C(0x78563412), "%#010RX32");
1404	u32Out = ASMByteSwapU32(u32Out);
1405	CHECKVAL(u32Out, u32In, "%#010RX32");
1406	u32In = 0;
1407	u32Out = ASMByteSwapU32(u32In);
1408	CHECKVAL(u32Out, u32In, "%#010RX32");
1409	u32In = ~(uint32_t)0;
1410	u32Out = ASMByteSwapU32(u32In);
1411	CHECKVAL(u32Out, u32In, "%#010RX32");
1412
1413	uint16_t u16In = UINT16_C(0x0011);
1414	uint16_t u16Out = ASMByteSwapU16(u16In);
1415	CHECKVAL(u16In, UINT16_C(0x0011), "%#06RX16");
1416	CHECKVAL(u16Out, UINT16_C(0x1100), "%#06RX16");
1417	u16Out = ASMByteSwapU16(u16Out);
1418	CHECKVAL(u16Out, u16In, "%#06RX16");
1419	u16In = UINT16_C(0x1234);
1420	u16Out = ASMByteSwapU16(u16In);
1421	CHECKVAL(u16In, UINT16_C(0x1234), "%#06RX16");
1422	CHECKVAL(u16Out, UINT16_C(0x3412), "%#06RX16");
1423	u16Out = ASMByteSwapU16(u16Out);
1424	CHECKVAL(u16Out, u16In, "%#06RX16");
1425	u16In = 0;
1426	u16Out = ASMByteSwapU16(u16In);
1427	CHECKVAL(u16Out, u16In, "%#06RX16");
1428	u16In = ~(uint16_t)0;
1429	u16Out = ASMByteSwapU16(u16In);
1430	CHECKVAL(u16Out, u16In, "%#06RX16");
1431	}
1432
1433
1434	void tstASMBench(void)
1435	{
1436	/*
1437	* Make this static. We don't want to have this located on the stack.
1438	*/
1439	static uint8_t volatile s_u8;
1440	static int8_t volatile s_i8;
1441	static uint16_t volatile s_u16;
1442	static int16_t volatile s_i16;
1443	static uint32_t volatile s_u32;
1444	static int32_t volatile s_i32;
1445	static uint64_t volatile s_u64;
1446	static int64_t volatile s_i64;
1447	register unsigned i;
1448	const unsigned cRounds = _2M;
1449	register uint64_t u64Elapsed;
1450
1451	RTTestSub(g_hTest, "Benchmarking");
1452
1453	#if 0 && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1454	# define BENCH(op, str) \
1455	do { \
1456	RTThreadYield(); \
1457	u64Elapsed = ASMReadTSC(); \
1458	for (i = cRounds; i > 0; i--) \
1459	op; \
1460	u64Elapsed = ASMReadTSC() - u64Elapsed; \
1461	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_TICKS_PER_CALL); \
1462	} while (0)
1463	#else
1464	# define BENCH(op, str) \
1465	do { \
1466	RTThreadYield(); \
1467	u64Elapsed = RTTimeNanoTS(); \
1468	for (i = cRounds; i > 0; i--) \
1469	op; \
1470	u64Elapsed = RTTimeNanoTS() - u64Elapsed; \
1471	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_NS_PER_CALL); \
1472	} while (0)
1473	#endif
1474
1475	BENCH(s_u32 = 0, "s_u32 = 0");
1476	BENCH(ASMAtomicUoReadU8(&s_u8), "ASMAtomicUoReadU8");
1477	BENCH(ASMAtomicUoReadS8(&s_i8), "ASMAtomicUoReadS8");
1478	BENCH(ASMAtomicUoReadU16(&s_u16), "ASMAtomicUoReadU16");
1479	BENCH(ASMAtomicUoReadS16(&s_i16), "ASMAtomicUoReadS16");
1480	BENCH(ASMAtomicUoReadU32(&s_u32), "ASMAtomicUoReadU32");
1481	BENCH(ASMAtomicUoReadS32(&s_i32), "ASMAtomicUoReadS32");
1482	BENCH(ASMAtomicUoReadU64(&s_u64), "ASMAtomicUoReadU64");
1483	BENCH(ASMAtomicUoReadS64(&s_i64), "ASMAtomicUoReadS64");
1484	BENCH(ASMAtomicReadU8(&s_u8), "ASMAtomicReadU8");
1485	BENCH(ASMAtomicReadS8(&s_i8), "ASMAtomicReadS8");
1486	BENCH(ASMAtomicReadU16(&s_u16), "ASMAtomicReadU16");
1487	BENCH(ASMAtomicReadS16(&s_i16), "ASMAtomicReadS16");
1488	BENCH(ASMAtomicReadU32(&s_u32), "ASMAtomicReadU32");
1489	BENCH(ASMAtomicReadS32(&s_i32), "ASMAtomicReadS32");
1490	BENCH(ASMAtomicReadU64(&s_u64), "ASMAtomicReadU64");
1491	BENCH(ASMAtomicReadS64(&s_i64), "ASMAtomicReadS64");
1492	BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8");
1493	BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8");
1494	BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16");
1495	BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16");
1496	BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32");
1497	BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32");
1498	BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64");
1499	BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64");
1500	BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8");
1501	BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8");
1502	BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16");
1503	BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16");
1504	BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32");
1505	BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32");
1506	BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64");
1507	BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64");
1508	BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8");
1509	BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8");
1510	BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16");
1511	BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16");
1512	BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32");
1513	BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32");
1514	BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64");
1515	BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64");
1516	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32");
1517	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32");
1518	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64");
1519	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64");
1520	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg");
1521	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg");
1522	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg");
1523	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg");
1524	BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32");
1525	BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32");
1526	BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32");
1527	BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32");
1528	BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32");
1529	BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32");
1530	/* The Darwin gcc does not like this ... */
1531	#if !defined(RT_OS_DARWIN) && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1532	BENCH(s_u8 = ASMGetApicId(), "ASMGetApicId");
1533	#endif
1534
1535	#undef BENCH
1536	}
1537
1538
1539	int main(int argc, char *argv[])
1540	{
1541	int rc = RTTestInitAndCreate("tstRTInlineAsm", &g_hTest);
1542	if (rc)
1543	return rc;
1544	RTTestBanner(g_hTest);
1545
1546	/*
1547	* Execute the tests.
1548	*/
1549	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1550	tstASMCpuId();
1551	#endif
1552	#if 1
1553	tstASMAtomicXchgU8();
1554	tstASMAtomicXchgU16();
1555	tstASMAtomicXchgU32();
1556	tstASMAtomicXchgU64();
1557	tstASMAtomicXchgPtr();
1558	tstASMAtomicCmpXchgU8();
1559	tstASMAtomicCmpXchgU32();
1560	tstASMAtomicCmpXchgU64();
1561	tstASMAtomicCmpXchgExU32();
1562	tstASMAtomicCmpXchgExU64();
1563	tstASMAtomicReadU64();
1564	tstASMAtomicUoReadU64();
1565
1566	tstASMAtomicAddS32();
1567	tstASMAtomicAddS64();
1568	tstASMAtomicDecIncS32();
1569	tstASMAtomicDecIncS64();
1570	tstASMAtomicAndOrU32();
1571	tstASMAtomicAndOrU64();
1572
1573	tstASMMemZeroPage();
1574	tstASMMemIsZeroPage(g_hTest);
1575	tstASMMemZero32();
1576	tstASMMemFill32();
1577
1578	tstASMMath();
1579
1580	tstASMByteSwap();
1581
1582	tstASMBench();
1583	#endif
1584
1585	/*
1586	* Show the result.
1587	*/
1588	return RTTestSummaryAndDestroy(g_hTest);
1589	}
1590

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source: vbox/trunk/src/VBox/Runtime/testcase/tstRTInlineAsm.cpp@ 46072

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