tstRTInlineAsm.cpp@ 45849

Last change on this file since 45849 was 44528, checked in by vboxsync, 12 years ago
header (C) fixes
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1	/* $Id: tstRTInlineAsm.cpp 44528 2013-02-04 14:27:54Z vboxsync $ */
2	/** @file
3	* IPRT Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	/*******************************************************************************
28	* Header Files *
29	*******************************************************************************/
30	#include <iprt/asm.h>
31	#include <iprt/asm-math.h>
32
33	/* See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44018. Only gcc version 4.4
34	* is affected. No harm for the VBox code: If the cpuid code compiles, it works
35	* fine. */
36	#if defined(__GNUC__) && defined(RT_ARCH_X86) && defined(__PIC__)
37	# if __GNUC__ == 4 && __GNUC_MINOR__ == 4
38	# define GCC44_32BIT_PIC
39	# endif
40	#endif
41
42	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
43	# include <iprt/asm-amd64-x86.h>
44	#else
45	# include <iprt/time.h>
46	#endif
47	#include <iprt/stream.h>
48	#include <iprt/string.h>
49	#include <iprt/param.h>
50	#include <iprt/thread.h>
51	#include <iprt/test.h>
52	#include <iprt/time.h>
53
54
55
56	/*******************************************************************************
57	* Defined Constants And Macros *
58	*******************************************************************************/
59	#define CHECKVAL(val, expect, fmt) \
60	do \
61	{ \
62	if ((val) != (expect)) \
63	{ \
64	RTTestFailed(g_hTest, "%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
65	} \
66	} while (0)
67
68	#define CHECKOP(op, expect, fmt, type) \
69	do \
70	{ \
71	type val = op; \
72	if (val != (type)(expect)) \
73	{ \
74	RTTestFailed(g_hTest, "%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
75	} \
76	} while (0)
77
78	/**
79	* Calls a worker function with different worker variable storage types.
80	*/
81	#define DO_SIMPLE_TEST(name, type) \
82	do \
83	{ \
84	RTTestISub(#name); \
85	type StackVar; \
86	tst ## name ## Worker(&StackVar); \
87	\
88	type pVar = (type )RTTestGuardedAllocHead(g_hTest, sizeof(type)); \
89	RTTEST_CHECK_BREAK(g_hTest, pVar); \
90	tst ## name ## Worker(pVar); \
91	RTTestGuardedFree(g_hTest, pVar); \
92	\
93	pVar = (type *)RTTestGuardedAllocTail(g_hTest, sizeof(type)); \
94	RTTEST_CHECK_BREAK(g_hTest, pVar); \
95	tst ## name ## Worker(pVar); \
96	RTTestGuardedFree(g_hTest, pVar); \
97	} while (0)
98
99
100	/*******************************************************************************
101	* Global Variables *
102	*******************************************************************************/
103	/** The test instance. */
104	static RTTEST g_hTest;
105
106
107
108	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
109
110	const char *getCacheAss(unsigned u)
111	{
112	if (u == 0)
113	return "res0 ";
114	if (u == 1)
115	return "direct";
116	if (u >= 256)
117	return "???";
118
119	char *pszRet;
120	RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
121	return pszRet;
122	}
123
124
125	const char *getL2CacheAss(unsigned u)
126	{
127	switch (u)
128	{
129	case 0: return "off ";
130	case 1: return "direct";
131	case 2: return "2 way ";
132	case 3: return "res3 ";
133	case 4: return "4 way ";
134	case 5: return "res5 ";
135	case 6: return "8 way ";
136	case 7: return "res7 ";
137	case 8: return "16 way";
138	case 9: return "res9 ";
139	case 10: return "res10 ";
140	case 11: return "res11 ";
141	case 12: return "res12 ";
142	case 13: return "res13 ";
143	case 14: return "res14 ";
144	case 15: return "fully ";
145	default:
146	return "????";
147	}
148	}
149
150
151	/**
152	* Test and dump all possible info from the CPUID instruction.
153	*
154	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
155	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
156	*/
157	void tstASMCpuId(void)
158	{
159	RTTestISub("ASMCpuId");
160
161	unsigned iBit;
162	struct
163	{
164	uint32_t uEBX, uEAX, uEDX, uECX;
165	} s;
166	if (!ASMHasCpuId())
167	{
168	RTTestIPrintf(RTTESTLVL_ALWAYS, "warning! CPU doesn't support CPUID\n");
169	return;
170	}
171
172	/*
173	* Try the 0 function and use that for checking the ASMCpuId_* variants.
174	*/
175	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
176
177	uint32_t u32;
178
179	u32 = ASMCpuId_EAX(0);
180	CHECKVAL(u32, s.uEAX, "%x");
181	u32 = ASMCpuId_EBX(0);
182	CHECKVAL(u32, s.uEBX, "%x");
183	u32 = ASMCpuId_ECX(0);
184	CHECKVAL(u32, s.uECX, "%x");
185	u32 = ASMCpuId_EDX(0);
186	CHECKVAL(u32, s.uEDX, "%x");
187
188	uint32_t uECX2 = s.uECX - 1;
189	uint32_t uEDX2 = s.uEDX - 1;
190	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
191	CHECKVAL(uECX2, s.uECX, "%x");
192	CHECKVAL(uEDX2, s.uEDX, "%x");
193
194	/*
195	* Done testing, dump the information.
196	*/
197	RTTestIPrintf(RTTESTLVL_ALWAYS, "CPUID Dump\n");
198	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
199	const uint32_t cFunctions = s.uEAX;
200
201	/* raw dump */
202	RTTestIPrintf(RTTESTLVL_ALWAYS,
203	"\n"
204	" RAW Standard CPUIDs\n"
205	"Function eax ebx ecx edx\n");
206	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
207	{
208	ASMCpuId_Idx_ECX(iStd, 0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
209	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
210	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
211
212	/* Leaf 04 and leaf 0d output depend on the initial value of ECX
213	* The same seems to apply to invalid standard functions */
214	if (iStd > cFunctions)
215	continue;
216	if (iStd != 0x04 && iStd != 0x0b && iStd != 0x0d)
217	{
218	u32 = ASMCpuId_EAX(iStd);
219	CHECKVAL(u32, s.uEAX, "%x");
220	u32 = ASMCpuId_EBX(iStd);
221	CHECKVAL(u32, s.uEBX, "%x");
222	u32 = ASMCpuId_ECX(iStd);
223	CHECKVAL(u32, s.uECX, "%x");
224	u32 = ASMCpuId_EDX(iStd);
225	CHECKVAL(u32, s.uEDX, "%x");
226
227	uECX2 = s.uECX - 1;
228	uEDX2 = s.uEDX - 1;
229	ASMCpuId_ECX_EDX(iStd, &uECX2, &uEDX2);
230	CHECKVAL(uECX2, s.uECX, "%x");
231	CHECKVAL(uEDX2, s.uEDX, "%x");
232	}
233
234	if (iStd == 0x04)
235	for (uint32_t uECX = 1; s.uEAX & 0x1f; uECX++)
236	{
237	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
238	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
239	RTTESTI_CHECK_BREAK(uECX < 128);
240	}
241	else if (iStd == 0x0b)
242	for (uint32_t uECX = 1; (s.uEAX & 0x1f) && (s.uEBX & 0xffff); uECX++)
243	{
244	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
245	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
246	RTTESTI_CHECK_BREAK(uECX < 128);
247	}
248	else if (iStd == 0x0d)
249	for (uint32_t uECX = 1; s.uEAX != 0 \|\| s.uEBX != 0 \|\| s.uECX != 0 \|\| s.uEDX != 0; uECX++)
250	{
251	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
252	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
253	RTTESTI_CHECK_BREAK(uECX < 128);
254	}
255	}
256
257	/*
258	* Understandable output
259	*/
260	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
261	RTTestIPrintf(RTTESTLVL_ALWAYS,
262	"Name: %.04s%.04s%.04s\n"
263	"Support: 0-%u\n",
264	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
265	bool const fIntel = ASMIsIntelCpuEx(s.uEBX, s.uECX, s.uEDX);
266
267	/*
268	* Get Features.
269	*/
270	if (cFunctions >= 1)
271	{
272	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
273	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
274	RTTestIPrintf(RTTESTLVL_ALWAYS,
275	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
276	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
277	"Stepping: %d\n"
278	"Type: %d (%s)\n"
279	"APIC ID: %#04x\n"
280	"Logical CPUs: %d\n"
281	"CLFLUSH Size: %d\n"
282	"Brand ID: %#04x\n",
283	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
284	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
285	ASMGetCpuStepping(s.uEAX),
286	(s.uEAX >> 12) & 0x3, s_apszTypes[(s.uEAX >> 12) & 0x3],
287	(s.uEBX >> 24) & 0xff,
288	(s.uEBX >> 16) & 0xff,
289	(s.uEBX >> 8) & 0xff,
290	(s.uEBX >> 0) & 0xff);
291
292	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
293	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
294	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
295	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
296	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
297	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
298	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
299	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
300	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
301	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX8");
302	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
303	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
304	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SEP");
305	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
306	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
307	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
308	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
309	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
310	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
311	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSN");
312	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CLFSH");
313	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 20");
314	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DS");
315	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " ACPI");
316	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
317	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
318	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE");
319	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE2");
320	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SS");
321	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " HTT");
322	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 29");
323	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 30");
324	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 31");
325	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
326
327	/** @todo check intel docs. */
328	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
329	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE3");
330	for (iBit = 1; iBit < 13; iBit++)
331	if (s.uECX & RT_BIT(iBit))
332	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
333	if (s.uECX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX16");
334	for (iBit = 14; iBit < 32; iBit++)
335	if (s.uECX & RT_BIT(iBit))
336	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
337	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
338	}
339
340	/*
341	* Extended.
342	* Implemented after AMD specs.
343	*/
344	/** @todo check out the intel specs. */
345	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
346	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
347	{
348	RTTestIPrintf(RTTESTLVL_ALWAYS, "No extended CPUID info? Check the manual on how to detect this...\n");
349	return;
350	}
351	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
352
353	/* raw dump */
354	RTTestIPrintf(RTTESTLVL_ALWAYS,
355	"\n"
356	" RAW Extended CPUIDs\n"
357	"Function eax ebx ecx edx\n");
358	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
359	{
360	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
361	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
362	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
363
364	if (iExt > cExtFunctions)
365	continue; /* Invalid extended functions seems change the value if ECX changes */
366
367	u32 = ASMCpuId_EAX(iExt);
368	CHECKVAL(u32, s.uEAX, "%x");
369	u32 = ASMCpuId_EBX(iExt);
370	CHECKVAL(u32, s.uEBX, "%x");
371	u32 = ASMCpuId_ECX(iExt);
372	CHECKVAL(u32, s.uECX, "%x");
373	u32 = ASMCpuId_EDX(iExt);
374	CHECKVAL(u32, s.uEDX, "%x");
375
376	uECX2 = s.uECX - 1;
377	uEDX2 = s.uEDX - 1;
378	ASMCpuId_ECX_EDX(iExt, &uECX2, &uEDX2);
379	CHECKVAL(uECX2, s.uECX, "%x");
380	CHECKVAL(uEDX2, s.uEDX, "%x");
381	}
382
383	/*
384	* Understandable output
385	*/
386	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
387	RTTestIPrintf(RTTESTLVL_ALWAYS,
388	"Ext Name: %.4s%.4s%.4s\n"
389	"Ext Supports: 0x80000000-%#010x\n",
390	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
391
392	if (cExtFunctions >= 0x80000001)
393	{
394	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
395	RTTestIPrintf(RTTESTLVL_ALWAYS,
396	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
397	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
398	"Stepping: %d\n"
399	"Brand ID: %#05x\n",
400	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
401	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
402	ASMGetCpuStepping(s.uEAX),
403	s.uEBX & 0xfff);
404
405	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
406	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
407	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
408	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
409	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
410	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
411	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
412	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
413	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
414	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMPXCHG8B");
415	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
416	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
417	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SysCallSysRet");
418	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
419	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
420	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
421	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
422	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
423	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
424	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 18");
425	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 19");
426	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " NX");
427	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 21");
428	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MmxExt");
429	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
430	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
431	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FastFXSR");
432	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 26");
433	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " RDTSCP");
434	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 28");
435	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LongMode");
436	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNowExt");
437	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNow");
438	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
439
440	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
441	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LahfSahf");
442	if (s.uECX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CmpLegacy");
443	if (s.uECX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SVM");
444	if (s.uECX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3");
445	if (s.uECX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " AltMovCr8");
446	for (iBit = 5; iBit < 32; iBit++)
447	if (s.uECX & RT_BIT(iBit))
448	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
449	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
450	}
451
452	char szString[443+1] = {0};
453	if (cExtFunctions >= 0x80000002)
454	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
455	if (cExtFunctions >= 0x80000003)
456	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
457	if (cExtFunctions >= 0x80000004)
458	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
459	if (cExtFunctions >= 0x80000002)
460	RTTestIPrintf(RTTESTLVL_ALWAYS, "Full Name: %s\n", szString);
461
462	if (cExtFunctions >= 0x80000005)
463	{
464	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
465	RTTestIPrintf(RTTESTLVL_ALWAYS,
466	"TLB 2/4M Instr/Uni: %s %3d entries\n"
467	"TLB 2/4M Data: %s %3d entries\n",
468	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
469	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
470	RTTestIPrintf(RTTESTLVL_ALWAYS,
471	"TLB 4K Instr/Uni: %s %3d entries\n"
472	"TLB 4K Data: %s %3d entries\n",
473	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
474	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
475	RTTestIPrintf(RTTESTLVL_ALWAYS,
476	"L1 Instr Cache Line Size: %d bytes\n"
477	"L1 Instr Cache Lines Per Tag: %d\n"
478	"L1 Instr Cache Associativity: %s\n"
479	"L1 Instr Cache Size: %d KB\n",
480	(s.uEDX >> 0) & 0xff,
481	(s.uEDX >> 8) & 0xff,
482	getCacheAss((s.uEDX >> 16) & 0xff),
483	(s.uEDX >> 24) & 0xff);
484	RTTestIPrintf(RTTESTLVL_ALWAYS,
485	"L1 Data Cache Line Size: %d bytes\n"
486	"L1 Data Cache Lines Per Tag: %d\n"
487	"L1 Data Cache Associativity: %s\n"
488	"L1 Data Cache Size: %d KB\n",
489	(s.uECX >> 0) & 0xff,
490	(s.uECX >> 8) & 0xff,
491	getCacheAss((s.uECX >> 16) & 0xff),
492	(s.uECX >> 24) & 0xff);
493	}
494
495	if (cExtFunctions >= 0x80000006)
496	{
497	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
498	RTTestIPrintf(RTTESTLVL_ALWAYS,
499	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
500	"L2 TLB 2/4M Data: %s %4d entries\n",
501	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
502	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
503	RTTestIPrintf(RTTESTLVL_ALWAYS,
504	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
505	"L2 TLB 4K Data: %s %4d entries\n",
506	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
507	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
508	RTTestIPrintf(RTTESTLVL_ALWAYS,
509	"L2 Cache Line Size: %d bytes\n"
510	"L2 Cache Lines Per Tag: %d\n"
511	"L2 Cache Associativity: %s\n"
512	"L2 Cache Size: %d KB\n",
513	(s.uEDX >> 0) & 0xff,
514	(s.uEDX >> 8) & 0xf,
515	getL2CacheAss((s.uEDX >> 12) & 0xf),
516	(s.uEDX >> 16) & 0xffff);
517	}
518
519	if (cExtFunctions >= 0x80000007)
520	{
521	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
522	RTTestIPrintf(RTTESTLVL_ALWAYS, "APM Features: ");
523	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TS");
524	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FID");
525	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VID");
526	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TTP");
527	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TM");
528	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " STC");
529	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 6");
530	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 7");
531	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TscInvariant");
532	for (iBit = 9; iBit < 32; iBit++)
533	if (s.uEDX & RT_BIT(iBit))
534	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
535	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
536	}
537
538	if (cExtFunctions >= 0x80000008)
539	{
540	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
541	RTTestIPrintf(RTTESTLVL_ALWAYS,
542	"Physical Address Width: %d bits\n"
543	"Virtual Address Width: %d bits\n"
544	"Guest Physical Address Width: %d bits\n",
545	(s.uEAX >> 0) & 0xff,
546	(s.uEAX >> 8) & 0xff,
547	(s.uEAX >> 16) & 0xff);
548	RTTestIPrintf(RTTESTLVL_ALWAYS,
549	"Physical Core Count: %d\n",
550	((s.uECX >> 0) & 0xff) + 1);
551	if ((s.uECX >> 12) & 0xf)
552	RTTestIPrintf(RTTESTLVL_ALWAYS, "ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
553	}
554
555	if (cExtFunctions >= 0x8000000a)
556	{
557	ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
558	RTTestIPrintf(RTTESTLVL_ALWAYS,
559	"SVM Revision: %d (%#x)\n"
560	"Number of Address Space IDs: %d (%#x)\n",
561	s.uEAX & 0xff, s.uEAX & 0xff,
562	s.uEBX, s.uEBX);
563	}
564	}
565
566	#endif /* AMD64 \|\| X86 */
567
568	DECLINLINE(void) tstASMAtomicXchgU8Worker(uint8_t volatile *pu8)
569	{
570	*pu8 = 0;
571	CHECKOP(ASMAtomicXchgU8(pu8, 1), 0, "%#x", uint8_t);
572	CHECKVAL(*pu8, 1, "%#x");
573
574	CHECKOP(ASMAtomicXchgU8(pu8, 0), 1, "%#x", uint8_t);
575	CHECKVAL(*pu8, 0, "%#x");
576
577	CHECKOP(ASMAtomicXchgU8(pu8, 0xff), 0, "%#x", uint8_t);
578	CHECKVAL(*pu8, 0xff, "%#x");
579
580	CHECKOP(ASMAtomicXchgU8(pu8, 0x87), 0xffff, "%#x", uint8_t);
581	CHECKVAL(*pu8, 0x87, "%#x");
582	}
583
584
585	static void tstASMAtomicXchgU8(void)
586	{
587	DO_SIMPLE_TEST(ASMAtomicXchgU8, uint8_t);
588	}
589
590
591	DECLINLINE(void) tstASMAtomicXchgU16Worker(uint16_t volatile *pu16)
592	{
593	*pu16 = 0;
594
595	CHECKOP(ASMAtomicXchgU16(pu16, 1), 0, "%#x", uint16_t);
596	CHECKVAL(*pu16, 1, "%#x");
597
598	CHECKOP(ASMAtomicXchgU16(pu16, 0), 1, "%#x", uint16_t);
599	CHECKVAL(*pu16, 0, "%#x");
600
601	CHECKOP(ASMAtomicXchgU16(pu16, 0xffff), 0, "%#x", uint16_t);
602	CHECKVAL(*pu16, 0xffff, "%#x");
603
604	CHECKOP(ASMAtomicXchgU16(pu16, 0x8765), 0xffff, "%#x", uint16_t);
605	CHECKVAL(*pu16, 0x8765, "%#x");
606	}
607
608
609	static void tstASMAtomicXchgU16(void)
610	{
611	DO_SIMPLE_TEST(ASMAtomicXchgU16, uint16_t);
612	}
613
614
615	DECLINLINE(void) tstASMAtomicXchgU32Worker(uint32_t volatile *pu32)
616	{
617	*pu32 = 0;
618
619	CHECKOP(ASMAtomicXchgU32(pu32, 1), 0, "%#x", uint32_t);
620	CHECKVAL(*pu32, 1, "%#x");
621
622	CHECKOP(ASMAtomicXchgU32(pu32, 0), 1, "%#x", uint32_t);
623	CHECKVAL(*pu32, 0, "%#x");
624
625	CHECKOP(ASMAtomicXchgU32(pu32, ~UINT32_C(0)), 0, "%#x", uint32_t);
626	CHECKVAL(*pu32, ~UINT32_C(0), "%#x");
627
628	CHECKOP(ASMAtomicXchgU32(pu32, 0x87654321), ~UINT32_C(0), "%#x", uint32_t);
629	CHECKVAL(*pu32, 0x87654321, "%#x");
630	}
631
632
633	static void tstASMAtomicXchgU32(void)
634	{
635	DO_SIMPLE_TEST(ASMAtomicXchgU32, uint32_t);
636	}
637
638
639	DECLINLINE(void) tstASMAtomicXchgU64Worker(uint64_t volatile *pu64)
640	{
641	*pu64 = 0;
642
643	CHECKOP(ASMAtomicXchgU64(pu64, 1), UINT64_C(0), "%#llx", uint64_t);
644	CHECKVAL(*pu64, UINT64_C(1), "%#llx");
645
646	CHECKOP(ASMAtomicXchgU64(pu64, 0), UINT64_C(1), "%#llx", uint64_t);
647	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
648
649	CHECKOP(ASMAtomicXchgU64(pu64, ~UINT64_C(0)), UINT64_C(0), "%#llx", uint64_t);
650	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
651
652	CHECKOP(ASMAtomicXchgU64(pu64, UINT64_C(0xfedcba0987654321)), ~UINT64_C(0), "%#llx", uint64_t);
653	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
654	}
655
656
657	static void tstASMAtomicXchgU64(void)
658	{
659	DO_SIMPLE_TEST(ASMAtomicXchgU64, uint64_t);
660	}
661
662
663	DECLINLINE(void) tstASMAtomicXchgPtrWorker(void * volatile *ppv)
664	{
665	*ppv = NULL;
666
667	CHECKOP(ASMAtomicXchgPtr(ppv, (void )(~(uintptr_t)0)), NULL, "%p", void );
668	CHECKVAL(ppv, (void )(~(uintptr_t)0), "%p");
669
670	CHECKOP(ASMAtomicXchgPtr(ppv, (void )0x87654321), (void )(~(uintptr_t)0), "%p", void *);
671	CHECKVAL(ppv, (void )0x87654321, "%p");
672
673	CHECKOP(ASMAtomicXchgPtr(ppv, NULL), (void )0x87654321, "%p", void );
674	CHECKVAL(*ppv, NULL, "%p");
675	}
676
677
678	static void tstASMAtomicXchgPtr(void)
679	{
680	DO_SIMPLE_TEST(ASMAtomicXchgPtr, void *);
681	}
682
683
684	DECLINLINE(void) tstASMAtomicCmpXchgU8Worker(uint8_t volatile *pu8)
685	{
686	*pu8 = 0xff;
687
688	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0), false, "%d", bool);
689	CHECKVAL(*pu8, 0xff, "%x");
690
691	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0xff), true, "%d", bool);
692	CHECKVAL(*pu8, 0, "%x");
693
694	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x79, 0xff), false, "%d", bool);
695	CHECKVAL(*pu8, 0, "%x");
696
697	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x97, 0), true, "%d", bool);
698	CHECKVAL(*pu8, 0x97, "%x");
699	}
700
701
702	static void tstASMAtomicCmpXchgU8(void)
703	{
704	DO_SIMPLE_TEST(ASMAtomicCmpXchgU8, uint8_t);
705	}
706
707
708	DECLINLINE(void) tstASMAtomicCmpXchgU32Worker(uint32_t volatile *pu32)
709	{
710	*pu32 = UINT32_C(0xffffffff);
711
712	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, 0), false, "%d", bool);
713	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
714
715	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, UINT32_C(0xffffffff)), true, "%d", bool);
716	CHECKVAL(*pu32, 0, "%x");
717
718	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff)), false, "%d", bool);
719	CHECKVAL(*pu32, 0, "%x");
720
721	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), 0), true, "%d", bool);
722	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
723	}
724
725
726	static void tstASMAtomicCmpXchgU32(void)
727	{
728	DO_SIMPLE_TEST(ASMAtomicCmpXchgU32, uint32_t);
729	}
730
731
732
733	DECLINLINE(void) tstASMAtomicCmpXchgU64Worker(uint64_t volatile *pu64)
734	{
735	*pu64 = UINT64_C(0xffffffffffffff);
736
737	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, 0), false, "%d", bool);
738	CHECKVAL(*pu64, UINT64_C(0xffffffffffffff), "%#llx");
739
740	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, UINT64_C(0xffffffffffffff)), true, "%d", bool);
741	CHECKVAL(*pu64, 0, "%x");
742
743	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff)), false, "%d", bool);
744	CHECKVAL(*pu64, 0, "%x");
745
746	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000)), false, "%d", bool);
747	CHECKVAL(*pu64, 0, "%x");
748
749	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 0), true, "%d", bool);
750	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%#llx");
751	}
752
753
754	static void tstASMAtomicCmpXchgU64(void)
755	{
756	DO_SIMPLE_TEST(ASMAtomicCmpXchgU64, uint64_t);
757	}
758
759
760	DECLINLINE(void) tstASMAtomicCmpXchgExU32Worker(uint32_t volatile *pu32)
761	{
762	*pu32 = UINT32_C(0xffffffff);
763	uint32_t u32Old = UINT32_C(0x80005111);
764
765	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, 0, &u32Old), false, "%d", bool);
766	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
767	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
768
769	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0xffffffff), &u32Old), true, "%d", bool);
770	CHECKVAL(*pu32, 0, "%x");
771	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
772
773	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff), &u32Old), false, "%d", bool);
774	CHECKVAL(*pu32, 0, "%x");
775	CHECKVAL(u32Old, 0, "%x");
776
777	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), 0, &u32Old), true, "%d", bool);
778	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
779	CHECKVAL(u32Old, 0, "%x");
780
781	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0x8008efd), &u32Old), true, "%d", bool);
782	CHECKVAL(*pu32, 0, "%x");
783	CHECKVAL(u32Old, UINT32_C(0x8008efd), "%x");
784	}
785
786
787	static void tstASMAtomicCmpXchgExU32(void)
788	{
789	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU32, uint32_t);
790	}
791
792
793	DECLINLINE(void) tstASMAtomicCmpXchgExU64Worker(uint64_t volatile *pu64)
794	{
795	*pu64 = UINT64_C(0xffffffffffffffff);
796	uint64_t u64Old = UINT64_C(0x8000000051111111);
797
798	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, 0, &u64Old), false, "%d", bool);
799	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%llx");
800	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
801
802	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0xffffffffffffffff), &u64Old), true, "%d", bool);
803	CHECKVAL(*pu64, UINT64_C(0), "%llx");
804	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
805
806	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0xffffffff, &u64Old), false, "%d", bool);
807	CHECKVAL(*pu64, UINT64_C(0), "%llx");
808	CHECKVAL(u64Old, UINT64_C(0), "%llx");
809
810	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000), &u64Old), false, "%d", bool);
811	CHECKVAL(*pu64, UINT64_C(0), "%llx");
812	CHECKVAL(u64Old, UINT64_C(0), "%llx");
813
814	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0, &u64Old), true, "%d", bool);
815	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%llx");
816	CHECKVAL(u64Old, UINT64_C(0), "%llx");
817
818	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0x80040008008efd), &u64Old), true, "%d", bool);
819	CHECKVAL(*pu64, UINT64_C(0), "%llx");
820	CHECKVAL(u64Old, UINT64_C(0x80040008008efd), "%llx");
821	}
822
823
824	static void tstASMAtomicCmpXchgExU64(void)
825	{
826	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU64, uint64_t);
827	}
828
829
830	DECLINLINE(void) tstASMAtomicReadU64Worker(uint64_t volatile *pu64)
831	{
832	*pu64 = 0;
833
834	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
835	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
836
837	*pu64 = ~UINT64_C(0);
838	CHECKOP(ASMAtomicReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
839	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
840
841	*pu64 = UINT64_C(0xfedcba0987654321);
842	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
843	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
844	}
845
846
847	static void tstASMAtomicReadU64(void)
848	{
849	DO_SIMPLE_TEST(ASMAtomicReadU64, uint64_t);
850	}
851
852
853	DECLINLINE(void) tstASMAtomicUoReadU64Worker(uint64_t volatile *pu64)
854	{
855	*pu64 = 0;
856
857	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
858	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
859
860	*pu64 = ~UINT64_C(0);
861	CHECKOP(ASMAtomicUoReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
862	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
863
864	*pu64 = UINT64_C(0xfedcba0987654321);
865	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
866	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
867	}
868
869
870	static void tstASMAtomicUoReadU64(void)
871	{
872	DO_SIMPLE_TEST(ASMAtomicUoReadU64, uint64_t);
873	}
874
875
876	DECLINLINE(void) tstASMAtomicAddS32Worker(int32_t *pi32)
877	{
878	int32_t i32Rc;
879	*pi32 = 10;
880	#define MYCHECK(op, rc, val) \
881	do { \
882	i32Rc = op; \
883	if (i32Rc != (rc)) \
884	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
885	if (*pi32 != (val)) \
886	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, val); \
887	} while (0)
888	MYCHECK(ASMAtomicAddS32(pi32, 1), 10, 11);
889	MYCHECK(ASMAtomicAddS32(pi32, -2), 11, 9);
890	MYCHECK(ASMAtomicAddS32(pi32, -9), 9, 0);
891	MYCHECK(ASMAtomicAddS32(pi32, -0x7fffffff), 0, -0x7fffffff);
892	MYCHECK(ASMAtomicAddS32(pi32, 0), -0x7fffffff, -0x7fffffff);
893	MYCHECK(ASMAtomicAddS32(pi32, 0x7fffffff), -0x7fffffff, 0);
894	MYCHECK(ASMAtomicAddS32(pi32, 0), 0, 0);
895	#undef MYCHECK
896	}
897
898	static void tstASMAtomicAddS32(void)
899	{
900	DO_SIMPLE_TEST(ASMAtomicAddS32, int32_t);
901	}
902
903
904	DECLINLINE(void) tstASMAtomicAddS64Worker(int64_t volatile *pi64)
905	{
906	int64_t i64Rc;
907	*pi64 = 10;
908	#define MYCHECK(op, rc, val) \
909	do { \
910	i64Rc = op; \
911	if (i64Rc != (rc)) \
912	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %llx expected %llx\n", __FUNCTION__, __LINE__, #op, i64Rc, (int64_t)rc); \
913	if (*pi64 != (val)) \
914	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%llx expected %llx\n", __FUNCTION__, __LINE__, #op, pi64, (int64_t)(val)); \
915	} while (0)
916	MYCHECK(ASMAtomicAddS64(pi64, 1), 10, 11);
917	MYCHECK(ASMAtomicAddS64(pi64, -2), 11, 9);
918	MYCHECK(ASMAtomicAddS64(pi64, -9), 9, 0);
919	MYCHECK(ASMAtomicAddS64(pi64, -INT64_MAX), 0, -INT64_MAX);
920	MYCHECK(ASMAtomicAddS64(pi64, 0), -INT64_MAX, -INT64_MAX);
921	MYCHECK(ASMAtomicAddS64(pi64, -1), -INT64_MAX, INT64_MIN);
922	MYCHECK(ASMAtomicAddS64(pi64, INT64_MAX), INT64_MIN, -1);
923	MYCHECK(ASMAtomicAddS64(pi64, 1), -1, 0);
924	MYCHECK(ASMAtomicAddS64(pi64, 0), 0, 0);
925	#undef MYCHECK
926	}
927
928
929	static void tstASMAtomicAddS64(void)
930	{
931	DO_SIMPLE_TEST(ASMAtomicAddS64, int64_t);
932	}
933
934
935	DECLINLINE(void) tstASMAtomicDecIncS32Worker(int32_t volatile *pi32)
936	{
937	int32_t i32Rc;
938	*pi32 = 10;
939	#define MYCHECK(op, rc) \
940	do { \
941	i32Rc = op; \
942	if (i32Rc != (rc)) \
943	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
944	if (*pi32 != (rc)) \
945	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, rc); \
946	} while (0)
947	MYCHECK(ASMAtomicDecS32(pi32), 9);
948	MYCHECK(ASMAtomicDecS32(pi32), 8);
949	MYCHECK(ASMAtomicDecS32(pi32), 7);
950	MYCHECK(ASMAtomicDecS32(pi32), 6);
951	MYCHECK(ASMAtomicDecS32(pi32), 5);
952	MYCHECK(ASMAtomicDecS32(pi32), 4);
953	MYCHECK(ASMAtomicDecS32(pi32), 3);
954	MYCHECK(ASMAtomicDecS32(pi32), 2);
955	MYCHECK(ASMAtomicDecS32(pi32), 1);
956	MYCHECK(ASMAtomicDecS32(pi32), 0);
957	MYCHECK(ASMAtomicDecS32(pi32), -1);
958	MYCHECK(ASMAtomicDecS32(pi32), -2);
959	MYCHECK(ASMAtomicIncS32(pi32), -1);
960	MYCHECK(ASMAtomicIncS32(pi32), 0);
961	MYCHECK(ASMAtomicIncS32(pi32), 1);
962	MYCHECK(ASMAtomicIncS32(pi32), 2);
963	MYCHECK(ASMAtomicIncS32(pi32), 3);
964	MYCHECK(ASMAtomicDecS32(pi32), 2);
965	MYCHECK(ASMAtomicIncS32(pi32), 3);
966	MYCHECK(ASMAtomicDecS32(pi32), 2);
967	MYCHECK(ASMAtomicIncS32(pi32), 3);
968	#undef MYCHECK
969	}
970
971
972	static void tstASMAtomicDecIncS32(void)
973	{
974	DO_SIMPLE_TEST(ASMAtomicDecIncS32, int32_t);
975	}
976
977
978	DECLINLINE(void) tstASMAtomicDecIncS64Worker(int64_t volatile *pi64)
979	{
980	int64_t i64Rc;
981	*pi64 = 10;
982	#define MYCHECK(op, rc) \
983	do { \
984	i64Rc = op; \
985	if (i64Rc != (rc)) \
986	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %lld expected %lld\n", __FUNCTION__, __LINE__, #op, i64Rc, rc); \
987	if (*pi64 != (rc)) \
988	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%lld expected %lld\n", __FUNCTION__, __LINE__, #op, pi64, rc); \
989	} while (0)
990	MYCHECK(ASMAtomicDecS64(pi64), 9);
991	MYCHECK(ASMAtomicDecS64(pi64), 8);
992	MYCHECK(ASMAtomicDecS64(pi64), 7);
993	MYCHECK(ASMAtomicDecS64(pi64), 6);
994	MYCHECK(ASMAtomicDecS64(pi64), 5);
995	MYCHECK(ASMAtomicDecS64(pi64), 4);
996	MYCHECK(ASMAtomicDecS64(pi64), 3);
997	MYCHECK(ASMAtomicDecS64(pi64), 2);
998	MYCHECK(ASMAtomicDecS64(pi64), 1);
999	MYCHECK(ASMAtomicDecS64(pi64), 0);
1000	MYCHECK(ASMAtomicDecS64(pi64), -1);
1001	MYCHECK(ASMAtomicDecS64(pi64), -2);
1002	MYCHECK(ASMAtomicIncS64(pi64), -1);
1003	MYCHECK(ASMAtomicIncS64(pi64), 0);
1004	MYCHECK(ASMAtomicIncS64(pi64), 1);
1005	MYCHECK(ASMAtomicIncS64(pi64), 2);
1006	MYCHECK(ASMAtomicIncS64(pi64), 3);
1007	MYCHECK(ASMAtomicDecS64(pi64), 2);
1008	MYCHECK(ASMAtomicIncS64(pi64), 3);
1009	MYCHECK(ASMAtomicDecS64(pi64), 2);
1010	MYCHECK(ASMAtomicIncS64(pi64), 3);
1011	#undef MYCHECK
1012	}
1013
1014
1015	static void tstASMAtomicDecIncS64(void)
1016	{
1017	DO_SIMPLE_TEST(ASMAtomicDecIncS64, int64_t);
1018	}
1019
1020
1021	DECLINLINE(void) tstASMAtomicAndOrU32Worker(uint32_t volatile *pu32)
1022	{
1023	*pu32 = UINT32_C(0xffffffff);
1024
1025	ASMAtomicOrU32(pu32, UINT32_C(0xffffffff));
1026	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1027
1028	ASMAtomicAndU32(pu32, UINT32_C(0xffffffff));
1029	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1030
1031	ASMAtomicAndU32(pu32, UINT32_C(0x8f8f8f8f));
1032	CHECKVAL(*pu32, UINT32_C(0x8f8f8f8f), "%x");
1033
1034	ASMAtomicOrU32(pu32, UINT32_C(0x70707070));
1035	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1036
1037	ASMAtomicAndU32(pu32, UINT32_C(1));
1038	CHECKVAL(*pu32, UINT32_C(1), "%x");
1039
1040	ASMAtomicOrU32(pu32, UINT32_C(0x80000000));
1041	CHECKVAL(*pu32, UINT32_C(0x80000001), "%x");
1042
1043	ASMAtomicAndU32(pu32, UINT32_C(0x80000000));
1044	CHECKVAL(*pu32, UINT32_C(0x80000000), "%x");
1045
1046	ASMAtomicAndU32(pu32, UINT32_C(0));
1047	CHECKVAL(*pu32, UINT32_C(0), "%x");
1048
1049	ASMAtomicOrU32(pu32, UINT32_C(0x42424242));
1050	CHECKVAL(*pu32, UINT32_C(0x42424242), "%x");
1051	}
1052
1053
1054	static void tstASMAtomicAndOrU32(void)
1055	{
1056	DO_SIMPLE_TEST(ASMAtomicAndOrU32, uint32_t);
1057	}
1058
1059
1060	DECLINLINE(void) tstASMAtomicAndOrU64Worker(uint64_t volatile *pu64)
1061	{
1062	*pu64 = UINT64_C(0xffffffff);
1063
1064	ASMAtomicOrU64(pu64, UINT64_C(0xffffffff));
1065	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1066
1067	ASMAtomicAndU64(pu64, UINT64_C(0xffffffff));
1068	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1069
1070	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f));
1071	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f), "%x");
1072
1073	ASMAtomicOrU64(pu64, UINT64_C(0x70707070));
1074	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1075
1076	ASMAtomicAndU64(pu64, UINT64_C(1));
1077	CHECKVAL(*pu64, UINT64_C(1), "%x");
1078
1079	ASMAtomicOrU64(pu64, UINT64_C(0x80000000));
1080	CHECKVAL(*pu64, UINT64_C(0x80000001), "%x");
1081
1082	ASMAtomicAndU64(pu64, UINT64_C(0x80000000));
1083	CHECKVAL(*pu64, UINT64_C(0x80000000), "%x");
1084
1085	ASMAtomicAndU64(pu64, UINT64_C(0));
1086	CHECKVAL(*pu64, UINT64_C(0), "%x");
1087
1088	ASMAtomicOrU64(pu64, UINT64_C(0x42424242));
1089	CHECKVAL(*pu64, UINT64_C(0x42424242), "%x");
1090
1091	// Same as above, but now 64-bit wide.
1092	ASMAtomicAndU64(pu64, UINT64_C(0));
1093	CHECKVAL(*pu64, UINT64_C(0), "%x");
1094
1095	ASMAtomicOrU64(pu64, UINT64_C(0xffffffffffffffff));
1096	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1097
1098	ASMAtomicAndU64(pu64, UINT64_C(0xffffffffffffffff));
1099	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1100
1101	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f8f8f8f8f));
1102	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f8f8f8f8f), "%x");
1103
1104	ASMAtomicOrU64(pu64, UINT64_C(0x7070707070707070));
1105	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1106
1107	ASMAtomicAndU64(pu64, UINT64_C(1));
1108	CHECKVAL(*pu64, UINT64_C(1), "%x");
1109
1110	ASMAtomicOrU64(pu64, UINT64_C(0x8000000000000000));
1111	CHECKVAL(*pu64, UINT64_C(0x8000000000000001), "%x");
1112
1113	ASMAtomicAndU64(pu64, UINT64_C(0x8000000000000000));
1114	CHECKVAL(*pu64, UINT64_C(0x8000000000000000), "%x");
1115
1116	ASMAtomicAndU64(pu64, UINT64_C(0));
1117	CHECKVAL(*pu64, UINT64_C(0), "%x");
1118
1119	ASMAtomicOrU64(pu64, UINT64_C(0x4242424242424242));
1120	CHECKVAL(*pu64, UINT64_C(0x4242424242424242), "%x");
1121	}
1122
1123
1124	static void tstASMAtomicAndOrU64(void)
1125	{
1126	DO_SIMPLE_TEST(ASMAtomicAndOrU64, uint64_t);
1127	}
1128
1129
1130	typedef struct
1131	{
1132	uint8_t ab[PAGE_SIZE];
1133	} TSTPAGE;
1134
1135
1136	DECLINLINE(void) tstASMMemZeroPageWorker(TSTPAGE *pPage)
1137	{
1138	for (unsigned j = 0; j < 16; j++)
1139	{
1140	memset(pPage, 0x11 * j, sizeof(*pPage));
1141	ASMMemZeroPage(pPage);
1142	for (unsigned i = 0; i < sizeof(pPage->ab); i++)
1143	if (pPage->ab[i])
1144	RTTestFailed(g_hTest, "ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
1145	}
1146	}
1147
1148
1149	static void tstASMMemZeroPage(void)
1150	{
1151	DO_SIMPLE_TEST(ASMMemZeroPage, TSTPAGE);
1152	}
1153
1154
1155	void tstASMMemIsZeroPage(RTTEST hTest)
1156	{
1157	RTTestSub(hTest, "ASMMemIsZeroPage");
1158
1159	void *pvPage1 = RTTestGuardedAllocHead(hTest, PAGE_SIZE);
1160	void *pvPage2 = RTTestGuardedAllocTail(hTest, PAGE_SIZE);
1161	RTTESTI_CHECK_RETV(pvPage1 && pvPage2);
1162
1163	memset(pvPage1, 0, PAGE_SIZE);
1164	memset(pvPage2, 0, PAGE_SIZE);
1165	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage1));
1166	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage2));
1167
1168	memset(pvPage1, 0xff, PAGE_SIZE);
1169	memset(pvPage2, 0xff, PAGE_SIZE);
1170	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1171	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1172
1173	memset(pvPage1, 0, PAGE_SIZE);
1174	memset(pvPage2, 0, PAGE_SIZE);
1175	for (unsigned off = 0; off < PAGE_SIZE; off++)
1176	{
1177	((uint8_t *)pvPage1)[off] = 1;
1178	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1179	((uint8_t *)pvPage1)[off] = 0;
1180
1181	((uint8_t *)pvPage2)[off] = 0x80;
1182	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1183	((uint8_t *)pvPage2)[off] = 0;
1184	}
1185
1186	RTTestSubDone(hTest);
1187	}
1188
1189
1190	void tstASMMemZero32(void)
1191	{
1192	RTTestSub(g_hTest, "ASMMemFill32");
1193
1194	struct
1195	{
1196	uint64_t u64Magic1;
1197	uint8_t abPage[PAGE_SIZE - 32];
1198	uint64_t u64Magic2;
1199	} Buf1, Buf2, Buf3;
1200
1201	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1202	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
1203	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1204	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1205	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
1206	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1207	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1208	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
1209	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1210	ASMMemZero32(Buf1.abPage, sizeof(Buf1.abPage));
1211	ASMMemZero32(Buf2.abPage, sizeof(Buf2.abPage));
1212	ASMMemZero32(Buf3.abPage, sizeof(Buf3.abPage));
1213	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1214	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1215	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1216	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1217	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1218	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1219	{
1220	RTTestFailed(g_hTest, "ASMMemZero32 violated one/both magic(s)!\n");
1221	}
1222	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.abPage); i++)
1223	if (Buf1.abPage[i])
1224	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1225	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.abPage); i++)
1226	if (Buf2.abPage[i])
1227	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1228	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.abPage); i++)
1229	if (Buf3.abPage[i])
1230	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1231	}
1232
1233
1234	void tstASMMemFill32(void)
1235	{
1236	RTTestSub(g_hTest, "ASMMemFill32");
1237
1238	struct
1239	{
1240	uint64_t u64Magic1;
1241	uint32_t au32Page[PAGE_SIZE / 4];
1242	uint64_t u64Magic2;
1243	} Buf1;
1244	struct
1245	{
1246	uint64_t u64Magic1;
1247	uint32_t au32Page[(PAGE_SIZE / 4) - 3];
1248	uint64_t u64Magic2;
1249	} Buf2;
1250	struct
1251	{
1252	uint64_t u64Magic1;
1253	uint32_t au32Page[(PAGE_SIZE / 4) - 1];
1254	uint64_t u64Magic2;
1255	} Buf3;
1256
1257	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1258	memset(Buf1.au32Page, 0x55, sizeof(Buf1.au32Page));
1259	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1260	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1261	memset(Buf2.au32Page, 0x77, sizeof(Buf2.au32Page));
1262	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1263	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1264	memset(Buf3.au32Page, 0x99, sizeof(Buf3.au32Page));
1265	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1266	ASMMemFill32(Buf1.au32Page, sizeof(Buf1.au32Page), 0xdeadbeef);
1267	ASMMemFill32(Buf2.au32Page, sizeof(Buf2.au32Page), 0xcafeff01);
1268	ASMMemFill32(Buf3.au32Page, sizeof(Buf3.au32Page), 0xf00dd00f);
1269	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1270	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1271	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1272	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1273	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1274	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1275	RTTestFailed(g_hTest, "ASMMemFill32 violated one/both magic(s)!\n");
1276	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.au32Page); i++)
1277	if (Buf1.au32Page[i] != 0xdeadbeef)
1278	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf1.au32Page[i], 0xdeadbeef);
1279	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.au32Page); i++)
1280	if (Buf2.au32Page[i] != 0xcafeff01)
1281	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf2.au32Page[i], 0xcafeff01);
1282	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.au32Page); i++)
1283	if (Buf3.au32Page[i] != 0xf00dd00f)
1284	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf3.au32Page[i], 0xf00dd00f);
1285	}
1286
1287
1288
1289	void tstASMMath(void)
1290	{
1291	RTTestSub(g_hTest, "Math");
1292
1293	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
1294	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
1295
1296	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
1297	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
1298
1299	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1300	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
1301	CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
1302	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
1303	CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
1304	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1305	CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
1306	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1307	CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
1308	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
1309	CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
1310	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
1311	CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
1312	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
1313	CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
1314
1315	# if 0 /* bird: question is whether this should trap or not:
1316	*
1317	* frank: Of course it must trap:
1318	*
1319	* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
1320	*
1321	* During the following division, the quotient must fit into a 32-bit register.
1322	* Therefore the smallest valid divisor is
1323	*
1324	* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
1325	*
1326	* which is definitely greater than 0x3b9aca00.
1327	*
1328	* bird: No, the C version does not crash. So, the question is whether there's any
1329	* code depending on it not crashing.
1330	*
1331	* Of course the assembly versions of the code crash right now for the reasons you've
1332	* given, but the 32-bit MSC version does not crash.
1333	*
1334	* frank: The C version does not crash but delivers incorrect results for this case.
1335	* The reason is
1336	*
1337	* u.s.Hi = (unsigned long)(u64Hi / u32C);
1338	*
1339	* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
1340	* to 32 bit. If using this (optimized and fast) function we should just be sure that
1341	* the operands are in a valid range.
1342	*/
1343	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
1344	CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
1345	# endif
1346	#endif /* AMD64 \|\| X86 */
1347
1348	u32 = ASMModU64ByU32RetU32(UINT64_C(0x0ffffff8c65d6731), UINT32_C(0x77d7daf8));
1349	CHECKVAL(u32, UINT32_C(0x3B642451), "%#010RX32");
1350
1351	int32_t i32;
1352	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(-2));
1353	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1354	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(2));
1355	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1356	i32 = ASMModS64ByS32RetS32(INT64_C(11), INT32_C(-2));
1357	CHECKVAL(i32, INT32_C(1), "%010RI32");
1358
1359	i32 = ASMModS64ByS32RetS32(INT64_C(92233720368547758), INT32_C(2147483647));
1360	CHECKVAL(i32, INT32_C(2104533974), "%010RI32");
1361	i32 = ASMModS64ByS32RetS32(INT64_C(-92233720368547758), INT32_C(2147483647));
1362	CHECKVAL(i32, INT32_C(-2104533974), "%010RI32");
1363	}
1364
1365
1366	void tstASMByteSwap(void)
1367	{
1368	RTTestSub(g_hTest, "ASMByteSwap*");
1369
1370	uint64_t u64In = UINT64_C(0x0011223344556677);
1371	uint64_t u64Out = ASMByteSwapU64(u64In);
1372	CHECKVAL(u64In, UINT64_C(0x0011223344556677), "%#018RX64");
1373	CHECKVAL(u64Out, UINT64_C(0x7766554433221100), "%#018RX64");
1374	u64Out = ASMByteSwapU64(u64Out);
1375	CHECKVAL(u64Out, u64In, "%#018RX64");
1376	u64In = UINT64_C(0x0123456789abcdef);
1377	u64Out = ASMByteSwapU64(u64In);
1378	CHECKVAL(u64In, UINT64_C(0x0123456789abcdef), "%#018RX64");
1379	CHECKVAL(u64Out, UINT64_C(0xefcdab8967452301), "%#018RX64");
1380	u64Out = ASMByteSwapU64(u64Out);
1381	CHECKVAL(u64Out, u64In, "%#018RX64");
1382	u64In = 0;
1383	u64Out = ASMByteSwapU64(u64In);
1384	CHECKVAL(u64Out, u64In, "%#018RX64");
1385	u64In = ~(uint64_t)0;
1386	u64Out = ASMByteSwapU64(u64In);
1387	CHECKVAL(u64Out, u64In, "%#018RX64");
1388
1389	uint32_t u32In = UINT32_C(0x00112233);
1390	uint32_t u32Out = ASMByteSwapU32(u32In);
1391	CHECKVAL(u32In, UINT32_C(0x00112233), "%#010RX32");
1392	CHECKVAL(u32Out, UINT32_C(0x33221100), "%#010RX32");
1393	u32Out = ASMByteSwapU32(u32Out);
1394	CHECKVAL(u32Out, u32In, "%#010RX32");
1395	u32In = UINT32_C(0x12345678);
1396	u32Out = ASMByteSwapU32(u32In);
1397	CHECKVAL(u32In, UINT32_C(0x12345678), "%#010RX32");
1398	CHECKVAL(u32Out, UINT32_C(0x78563412), "%#010RX32");
1399	u32Out = ASMByteSwapU32(u32Out);
1400	CHECKVAL(u32Out, u32In, "%#010RX32");
1401	u32In = 0;
1402	u32Out = ASMByteSwapU32(u32In);
1403	CHECKVAL(u32Out, u32In, "%#010RX32");
1404	u32In = ~(uint32_t)0;
1405	u32Out = ASMByteSwapU32(u32In);
1406	CHECKVAL(u32Out, u32In, "%#010RX32");
1407
1408	uint16_t u16In = UINT16_C(0x0011);
1409	uint16_t u16Out = ASMByteSwapU16(u16In);
1410	CHECKVAL(u16In, UINT16_C(0x0011), "%#06RX16");
1411	CHECKVAL(u16Out, UINT16_C(0x1100), "%#06RX16");
1412	u16Out = ASMByteSwapU16(u16Out);
1413	CHECKVAL(u16Out, u16In, "%#06RX16");
1414	u16In = UINT16_C(0x1234);
1415	u16Out = ASMByteSwapU16(u16In);
1416	CHECKVAL(u16In, UINT16_C(0x1234), "%#06RX16");
1417	CHECKVAL(u16Out, UINT16_C(0x3412), "%#06RX16");
1418	u16Out = ASMByteSwapU16(u16Out);
1419	CHECKVAL(u16Out, u16In, "%#06RX16");
1420	u16In = 0;
1421	u16Out = ASMByteSwapU16(u16In);
1422	CHECKVAL(u16Out, u16In, "%#06RX16");
1423	u16In = ~(uint16_t)0;
1424	u16Out = ASMByteSwapU16(u16In);
1425	CHECKVAL(u16Out, u16In, "%#06RX16");
1426	}
1427
1428
1429	void tstASMBench(void)
1430	{
1431	/*
1432	* Make this static. We don't want to have this located on the stack.
1433	*/
1434	static uint8_t volatile s_u8;
1435	static int8_t volatile s_i8;
1436	static uint16_t volatile s_u16;
1437	static int16_t volatile s_i16;
1438	static uint32_t volatile s_u32;
1439	static int32_t volatile s_i32;
1440	static uint64_t volatile s_u64;
1441	static int64_t volatile s_i64;
1442	register unsigned i;
1443	const unsigned cRounds = _2M;
1444	register uint64_t u64Elapsed;
1445
1446	RTTestSub(g_hTest, "Benchmarking");
1447
1448	#if 0 && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1449	# define BENCH(op, str) \
1450	do { \
1451	RTThreadYield(); \
1452	u64Elapsed = ASMReadTSC(); \
1453	for (i = cRounds; i > 0; i--) \
1454	op; \
1455	u64Elapsed = ASMReadTSC() - u64Elapsed; \
1456	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_TICKS_PER_CALL); \
1457	} while (0)
1458	#else
1459	# define BENCH(op, str) \
1460	do { \
1461	RTThreadYield(); \
1462	u64Elapsed = RTTimeNanoTS(); \
1463	for (i = cRounds; i > 0; i--) \
1464	op; \
1465	u64Elapsed = RTTimeNanoTS() - u64Elapsed; \
1466	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_NS_PER_CALL); \
1467	} while (0)
1468	#endif
1469
1470	BENCH(s_u32 = 0, "s_u32 = 0");
1471	BENCH(ASMAtomicUoReadU8(&s_u8), "ASMAtomicUoReadU8");
1472	BENCH(ASMAtomicUoReadS8(&s_i8), "ASMAtomicUoReadS8");
1473	BENCH(ASMAtomicUoReadU16(&s_u16), "ASMAtomicUoReadU16");
1474	BENCH(ASMAtomicUoReadS16(&s_i16), "ASMAtomicUoReadS16");
1475	BENCH(ASMAtomicUoReadU32(&s_u32), "ASMAtomicUoReadU32");
1476	BENCH(ASMAtomicUoReadS32(&s_i32), "ASMAtomicUoReadS32");
1477	BENCH(ASMAtomicUoReadU64(&s_u64), "ASMAtomicUoReadU64");
1478	BENCH(ASMAtomicUoReadS64(&s_i64), "ASMAtomicUoReadS64");
1479	BENCH(ASMAtomicReadU8(&s_u8), "ASMAtomicReadU8");
1480	BENCH(ASMAtomicReadS8(&s_i8), "ASMAtomicReadS8");
1481	BENCH(ASMAtomicReadU16(&s_u16), "ASMAtomicReadU16");
1482	BENCH(ASMAtomicReadS16(&s_i16), "ASMAtomicReadS16");
1483	BENCH(ASMAtomicReadU32(&s_u32), "ASMAtomicReadU32");
1484	BENCH(ASMAtomicReadS32(&s_i32), "ASMAtomicReadS32");
1485	BENCH(ASMAtomicReadU64(&s_u64), "ASMAtomicReadU64");
1486	BENCH(ASMAtomicReadS64(&s_i64), "ASMAtomicReadS64");
1487	BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8");
1488	BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8");
1489	BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16");
1490	BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16");
1491	BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32");
1492	BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32");
1493	BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64");
1494	BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64");
1495	BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8");
1496	BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8");
1497	BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16");
1498	BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16");
1499	BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32");
1500	BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32");
1501	BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64");
1502	BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64");
1503	BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8");
1504	BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8");
1505	BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16");
1506	BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16");
1507	BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32");
1508	BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32");
1509	BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64");
1510	BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64");
1511	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32");
1512	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32");
1513	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64");
1514	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64");
1515	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg");
1516	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg");
1517	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg");
1518	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg");
1519	BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32");
1520	BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32");
1521	BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32");
1522	BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32");
1523	BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32");
1524	BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32");
1525	/* The Darwin gcc does not like this ... */
1526	#if !defined(RT_OS_DARWIN) && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1527	BENCH(s_u8 = ASMGetApicId(), "ASMGetApicId");
1528	#endif
1529
1530	#undef BENCH
1531	}
1532
1533
1534	int main(int argc, char *argv[])
1535	{
1536	int rc = RTTestInitAndCreate("tstRTInlineAsm", &g_hTest);
1537	if (rc)
1538	return rc;
1539	RTTestBanner(g_hTest);
1540
1541	/*
1542	* Execute the tests.
1543	*/
1544	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1545	tstASMCpuId();
1546	#endif
1547	#if 1
1548	tstASMAtomicXchgU8();
1549	tstASMAtomicXchgU16();
1550	tstASMAtomicXchgU32();
1551	tstASMAtomicXchgU64();
1552	tstASMAtomicXchgPtr();
1553	tstASMAtomicCmpXchgU8();
1554	tstASMAtomicCmpXchgU32();
1555	tstASMAtomicCmpXchgU64();
1556	tstASMAtomicCmpXchgExU32();
1557	tstASMAtomicCmpXchgExU64();
1558	tstASMAtomicReadU64();
1559	tstASMAtomicUoReadU64();
1560
1561	tstASMAtomicAddS32();
1562	tstASMAtomicAddS64();
1563	tstASMAtomicDecIncS32();
1564	tstASMAtomicDecIncS64();
1565	tstASMAtomicAndOrU32();
1566	tstASMAtomicAndOrU64();
1567
1568	tstASMMemZeroPage();
1569	tstASMMemIsZeroPage(g_hTest);
1570	tstASMMemZero32();
1571	tstASMMemFill32();
1572
1573	tstASMMath();
1574
1575	tstASMByteSwap();
1576
1577	tstASMBench();
1578	#endif
1579
1580	/*
1581	* Show the result.
1582	*/
1583	return RTTestSummaryAndDestroy(g_hTest);
1584	}
1585

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source: vbox/trunk/src/VBox/Runtime/testcase/tstRTInlineAsm.cpp@ 45849

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