| 1 | /* $Id: tstTSC.cpp 106929 2024-11-11 15:19:28Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IPRT Testcase - SMP TSC testcase.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * The contents of this file may alternatively be used under the terms
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| 26 | * of the Common Development and Distribution License Version 1.0
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| 27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | * in the VirtualBox distribution, in which case the provisions of the
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| 29 | * CDDL are applicable instead of those of the GPL.
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| 30 | *
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| 31 | * You may elect to license modified versions of this file under the
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| 32 | * terms and conditions of either the GPL or the CDDL or both.
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| 33 | *
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| 34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | */
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| 36 |
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| 37 |
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| 38 | /*********************************************************************************************************************************
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| 39 | * Header Files *
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| 40 | *********************************************************************************************************************************/
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| 41 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 42 | # include <iprt/asm-amd64-x86.h>
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| 43 | #elif defined(RT_ARCH_ARM64)
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| 44 | # include <iprt/asm-arm.h>
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| 45 | #endif
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| 46 | #include <iprt/asm.h>
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| 47 | #include <iprt/getopt.h>
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| 48 | #include <iprt/initterm.h>
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| 49 | #include <iprt/mp.h>
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| 50 | #include <iprt/stream.h>
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| 51 | #include <iprt/string.h>
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| 52 | #include <iprt/thread.h>
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| 53 | #include <iprt/time.h>
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| 54 |
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| 55 |
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| 56 | /*********************************************************************************************************************************
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| 57 | * Defined Constants And Macros *
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| 58 | *********************************************************************************************************************************/
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| 59 | /** @todo this depends on TSC frequency, which is not necessarily related
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| 60 | * to the CPU speed on arm. */
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| 61 | #define MAX_TSC_DELTA 2750 /* WARNING: This is just a guess, increase if it doesn't work for you. */
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| 62 |
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| 63 |
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| 64 | /*********************************************************************************************************************************
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| 65 | * Structures and Typedefs *
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| 66 | *********************************************************************************************************************************/
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| 67 | typedef struct TSCDATA
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| 68 | {
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| 69 | /** The TSC. */
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| 70 | uint64_t volatile TSC;
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| 71 | /** The CPU ID or APIC ID. */
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| 72 | RTCPUID volatile idCpu;
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| 73 | /** Did it succeed? */
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| 74 | bool volatile fRead;
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| 75 | /** Did it fail? */
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| 76 | bool volatile fFailed;
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| 77 | /** The thread handle. */
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| 78 | RTTHREAD Thread;
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| 79 | } TSCDATA, *PTSCDATA;
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| 80 |
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| 81 |
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| 82 | /*********************************************************************************************************************************
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| 83 | * Global Variables *
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| 84 | *********************************************************************************************************************************/
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| 85 | /** The number of CPUs waiting on their user event semaphore. */
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| 86 | static volatile uint32_t g_cWaiting;
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| 87 | /** The number of CPUs ready (in spin) to do the TSC read. */
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| 88 | static volatile uint32_t g_cReady;
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| 89 | /** The variable the CPUs are spinning on.
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| 90 | * 0: Spin.
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| 91 | * 1: Go ahead.
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| 92 | * 2: You're too late, back to square one. */
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| 93 | static volatile uint32_t g_u32Go;
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| 94 | /** The number of CPUs that managed to read the TSC. */
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| 95 | static volatile uint32_t g_cRead;
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| 96 | /** The number of CPUs that failed to read the TSC. */
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| 97 | static volatile uint32_t g_cFailed;
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| 98 |
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| 99 | /** Indicator forcing the threads to quit. */
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| 100 | static volatile bool g_fDone;
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| 101 |
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| 102 |
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| 103 | /*********************************************************************************************************************************
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| 104 | * Internal Functions *
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| 105 | *********************************************************************************************************************************/
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| 106 | static DECLCALLBACK(int) ThreadFunction(RTTHREAD Thread, void *pvUser);
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| 107 |
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| 108 |
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| 109 | /** Wrapper around RTMpCpuId/ASMGetStuff. */
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| 110 | static RTCPUID MyGetCpuId(void)
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| 111 | {
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| 112 | #if (!defined(RT_OS_LINUX) && !defined(RT_OS_DARWIN) && !defined(RT_OS_SOLARIS)) || defined(RT_ARCH_ARM64) || defined(RT_ARCH_ARM32)
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| 113 | RTCPUID idCpu = RTMpCpuId();
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| 114 | if (idCpu != NIL_RTCPUID)
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| 115 | return idCpu;
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| 116 | #endif
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| 117 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 118 | return ASMGetApicId();
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| 119 | #elif defined(RT_ARCH_ARM64)
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| 120 | return (RTCPUID)ASMGetThreadIdRoEL0();
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| 121 | #else
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| 122 | return idCpu;
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| 123 | #endif
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| 124 | }
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| 125 |
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| 126 | /**
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| 127 | * Thread function for catching the other cpus.
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| 128 | *
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| 129 | * @returns VINF_SUCCESS (we don't care).
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| 130 | * @param Thread The thread handle.
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| 131 | * @param pvUser PTSCDATA.
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| 132 | */
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| 133 | static DECLCALLBACK(int) ThreadFunction(RTTHREAD Thread, void *pvUser)
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| 134 | {
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| 135 | PTSCDATA pTscData = (PTSCDATA)pvUser;
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| 136 |
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| 137 | while (!g_fDone)
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| 138 | {
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| 139 | /*
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| 140 | * Wait.
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| 141 | */
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| 142 | ASMAtomicIncU32(&g_cWaiting);
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| 143 | RTThreadUserWait(Thread, RT_INDEFINITE_WAIT);
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| 144 | RTThreadUserReset(Thread);
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| 145 | ASMAtomicDecU32(&g_cWaiting);
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| 146 | if (g_fDone)
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| 147 | break;
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| 148 |
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| 149 | /*
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| 150 | * Spin.
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| 151 | */
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| 152 | ASMAtomicIncU32(&g_cReady);
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| 153 | while (!g_fDone)
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| 154 | {
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| 155 | const RTCPUID idCpu1 = MyGetCpuId();
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| 156 | const uint64_t TSC1 = ASMReadTSC();
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| 157 | const uint32_t u32Go = g_u32Go;
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| 158 | if (u32Go == 0)
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| 159 | continue;
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| 160 |
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| 161 | if (u32Go == 1)
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| 162 | {
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| 163 | /* do the reading. */
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| 164 | const RTCPUID idCpu2 = MyGetCpuId();
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| 165 | const uint64_t TSC2 = ASMReadTSC();
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| 166 | const RTCPUID idCpu3 = MyGetCpuId();
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| 167 | const uint64_t TSC3 = ASMReadTSC();
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| 168 | const uint8_t idCpu4 = MyGetCpuId();
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| 169 |
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| 170 | if ( idCpu1 == idCpu2
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| 171 | && idCpu1 == idCpu3
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| 172 | && idCpu1 == idCpu4
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| 173 | && TSC3 - TSC1 < MAX_TSC_DELTA
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| 174 | && TSC2 - TSC1 < TSC3 - TSC1
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| 175 | )
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| 176 | {
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| 177 | /* succeeded. */
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| 178 | pTscData->TSC = TSC2;
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| 179 | pTscData->idCpu = idCpu1;
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| 180 | pTscData->fFailed = false;
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| 181 | pTscData->fRead = true;
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| 182 | ASMAtomicIncU32(&g_cRead);
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| 183 | break;
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| 184 | }
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| 185 | }
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| 186 |
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| 187 | /* failed */
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| 188 | pTscData->fFailed = true;
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| 189 | pTscData->fRead = false;
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| 190 | ASMAtomicIncU32(&g_cFailed);
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| 191 | break;
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| 192 | }
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| 193 | }
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| 194 |
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| 195 | return VINF_SUCCESS;
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| 196 | }
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| 197 |
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| 198 | static int tstTSCCalcDrift(void)
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| 199 | {
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| 200 | /*
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| 201 | * This is only relevant to on SMP systems.
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| 202 | */
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| 203 | const unsigned cCpus = RTMpGetOnlineCount();
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| 204 | if (cCpus <= 1)
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| 205 | {
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| 206 | RTPrintf("tstTSC: SKIPPED - Only relevant on SMP systems\n");
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| 207 | return 0;
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| 208 | }
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| 209 |
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| 210 | /*
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| 211 | * Create the threads.
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| 212 | */
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| 213 | static TSCDATA s_aData[254];
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| 214 | uint32_t i;
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| 215 | if (cCpus > RT_ELEMENTS(s_aData))
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| 216 | {
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| 217 | RTPrintf("tstTSC: FAILED - too many CPUs (%u)\n", cCpus);
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| 218 | return 1;
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| 219 | }
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| 220 |
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| 221 | /* ourselves. */
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| 222 | s_aData[0].Thread = RTThreadSelf();
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| 223 |
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| 224 | /* the others */
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| 225 | for (i = 1; i < cCpus; i++)
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| 226 | {
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| 227 | int rc = RTThreadCreate(&s_aData[i].Thread, ThreadFunction, &s_aData[i], 0, RTTHREADTYPE_TIMER, RTTHREADFLAGS_WAITABLE, "OTHERCPU");
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| 228 | if (RT_FAILURE(rc))
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| 229 | {
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| 230 | RTPrintf("tstTSC: FAILURE - RTThreatCreate failed when creating thread #%u, rc=%Rrc!\n", i, rc);
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| 231 | ASMAtomicXchgSize(&g_fDone, true);
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| 232 | while (i-- > 1)
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| 233 | {
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| 234 | RTThreadUserSignal(s_aData[i].Thread);
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| 235 | RTThreadWait(s_aData[i].Thread, 5000, NULL);
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| 236 | }
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| 237 | return 1;
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| 238 | }
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| 239 | }
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| 240 |
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| 241 | /*
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| 242 | * Retry until we get lucky (or give up).
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| 243 | */
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| 244 | for (unsigned cTries = 0; ; cTries++)
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| 245 | {
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| 246 | if (cTries > 10240)
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| 247 | {
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| 248 | RTPrintf("tstTSC: FAILURE - %d attempts, giving.\n", cTries);
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| 249 | break;
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| 250 | }
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| 251 |
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| 252 | /*
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| 253 | * Wait for the other threads to get ready (brute force active wait, I'm lazy).
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| 254 | */
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| 255 | i = 0;
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| 256 | while (g_cWaiting < cCpus - 1)
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| 257 | {
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| 258 | if (i++ > _2G32)
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| 259 | break;
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| 260 | RTThreadSleep(i & 0xf);
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| 261 | }
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| 262 | if (g_cWaiting != cCpus - 1)
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| 263 | {
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| 264 | RTPrintf("tstTSC: FAILURE - threads failed to get waiting (%d != %d (i=%d))\n", g_cWaiting + 1, cCpus, i);
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| 265 | break;
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| 266 | }
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| 267 |
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| 268 | /*
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| 269 | * Send them spinning.
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| 270 | */
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| 271 | ASMAtomicXchgU32(&g_cReady, 0);
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| 272 | ASMAtomicXchgU32(&g_u32Go, 0);
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| 273 | ASMAtomicXchgU32(&g_cRead, 0);
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| 274 | ASMAtomicXchgU32(&g_cFailed, 0);
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| 275 | for (i = 1; i < cCpus; i++)
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| 276 | {
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| 277 | ASMAtomicXchgSize(&s_aData[i].fFailed, false);
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| 278 | ASMAtomicXchgSize(&s_aData[i].fRead, false);
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| 279 | ASMAtomicXchgU32(&s_aData[i].idCpu, NIL_RTCPUID);
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| 280 |
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| 281 | int rc = RTThreadUserSignal(s_aData[i].Thread);
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| 282 | if (RT_FAILURE(rc))
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| 283 | RTPrintf("tstTSC: WARNING - RTThreadUserSignal(%#u) -> rc=%Rrc!\n", i, rc);
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| 284 | }
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| 285 |
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| 286 | /* wait for them to get ready. */
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| 287 | i = 0;
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| 288 | while (g_cReady < cCpus - 1)
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| 289 | {
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| 290 | if (i++ > _2G32)
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| 291 | break;
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| 292 | }
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| 293 | if (g_cReady != cCpus - 1)
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| 294 | {
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| 295 | RTPrintf("tstTSC: FAILURE - threads failed to get ready (%d != %d, i=%d)\n", g_cWaiting + 1, cCpus, i);
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| 296 | break;
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| 297 | }
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| 298 |
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| 299 | /*
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| 300 | * Flip the "go" switch and do our readings.
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| 301 | * We give the other threads the slack it takes to two extra TSC and CPU ID reads.
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| 302 | */
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| 303 | const RTCPUID idCpu1 = MyGetCpuId();
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| 304 | const uint64_t TSC1 = ASMReadTSC();
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| 305 | ASMAtomicXchgU32(&g_u32Go, 1);
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| 306 | const RTCPUID idCpu2 = MyGetCpuId();
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| 307 | const uint64_t TSC2 = ASMReadTSC();
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| 308 | const RTCPUID idCpu3 = MyGetCpuId();
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| 309 | const uint64_t TSC3 = ASMReadTSC();
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| 310 | const RTCPUID idCpu4 = MyGetCpuId();
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| 311 | const uint64_t TSC4 = ASMReadTSC();
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| 312 | ASMAtomicXchgU32(&g_u32Go, 2);
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| 313 | const RTCPUID idCpu5 = MyGetCpuId();
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| 314 | const uint64_t TSC5 = ASMReadTSC();
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| 315 | const RTCPUID idCpu6 = MyGetCpuId();
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| 316 |
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| 317 | /* Compose our own result. */
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| 318 | if ( idCpu1 == idCpu2
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| 319 | && idCpu1 == idCpu3
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| 320 | && idCpu1 == idCpu4
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| 321 | && idCpu1 == idCpu5
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| 322 | && idCpu1 == idCpu6
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| 323 | && TSC5 - TSC1 < MAX_TSC_DELTA
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| 324 | && TSC4 - TSC1 < TSC5 - TSC1
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| 325 | && TSC3 - TSC1 < TSC4 - TSC1
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| 326 | && TSC2 - TSC1 < TSC3 - TSC1
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| 327 | )
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| 328 | {
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| 329 | /* succeeded. */
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| 330 | s_aData[0].TSC = TSC2;
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| 331 | s_aData[0].idCpu = idCpu1;
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| 332 | s_aData[0].fFailed = false;
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| 333 | s_aData[0].fRead = true;
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| 334 | ASMAtomicIncU32(&g_cRead);
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| 335 | }
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| 336 | else
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| 337 | {
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| 338 | /* failed */
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| 339 | s_aData[0].fFailed = true;
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| 340 | s_aData[0].fRead = false;
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| 341 | ASMAtomicIncU32(&g_cFailed);
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| 342 | }
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| 343 |
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| 344 | /*
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| 345 | * Wait a little while to let the other ones to finish.
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| 346 | */
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| 347 | i = 0;
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| 348 | while (g_cRead + g_cFailed < cCpus)
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| 349 | {
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| 350 | if (i++ > _2G32)
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| 351 | break;
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| 352 | if (i > _1M)
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| 353 | RTThreadSleep(i & 0xf);
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| 354 | }
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| 355 | if (g_cRead + g_cFailed != cCpus)
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| 356 | {
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| 357 | RTPrintf("tstTSC: FAILURE - threads failed to complete reading (%d + %d != %d)\n", g_cRead, g_cFailed, cCpus);
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| 358 | break;
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| 359 | }
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| 360 |
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| 361 | /*
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| 362 | * If everone succeeded, print the results.
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| 363 | */
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| 364 | if (!g_cFailed)
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| 365 | {
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| 366 | /* sort it by apic id first. */
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| 367 | bool fDone;
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| 368 | do
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| 369 | {
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| 370 | for (i = 1, fDone = true; i < cCpus; i++)
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| 371 | if (s_aData[i - 1].idCpu > s_aData[i].idCpu)
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| 372 | {
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| 373 | TSCDATA Tmp = s_aData[i - 1];
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| 374 | s_aData[i - 1] = s_aData[i];
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| 375 | s_aData[i] = Tmp;
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| 376 | fDone = false;
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| 377 | }
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| 378 | } while (!fDone);
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| 379 |
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| 380 | RTPrintf(" # ID TSC delta0 (decimal)\n"
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| 381 | "-----------------------------------------\n");
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| 382 | RTPrintf("%2d %02x %RX64\n", 0, s_aData[0].idCpu, s_aData[0].TSC);
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| 383 | for (i = 1; i < cCpus; i++)
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| 384 | RTPrintf("%2d %02x %RX64 %s%lld\n", i, s_aData[i].idCpu, s_aData[i].TSC,
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| 385 | s_aData[i].TSC > s_aData[0].TSC ? "+" : "", s_aData[i].TSC - s_aData[0].TSC);
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| 386 | RTPrintf("(Needed %u attempt%s.)\n", cTries + 1, cTries ? "s" : "");
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| 387 | break;
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| 388 | }
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| 389 | }
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| 390 |
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| 391 | /*
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| 392 | * Destroy the threads.
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| 393 | */
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| 394 | ASMAtomicXchgSize(&g_fDone, true);
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| 395 | for (i = 0; i < cCpus; i++)
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| 396 | if (s_aData[i].Thread != RTThreadSelf())
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| 397 | {
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| 398 | int rc = RTThreadUserSignal(s_aData[i].Thread);
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| 399 | if (RT_FAILURE(rc))
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| 400 | RTPrintf("tstTSC: WARNING - RTThreadUserSignal(%#u) -> rc=%Rrc! (2)\n", i, rc);
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| 401 | }
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| 402 | for (i = 0; i < cCpus; i++)
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| 403 | if (s_aData[i].Thread != RTThreadSelf())
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| 404 | {
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| 405 | int rc = RTThreadWait(s_aData[i].Thread, 5000, NULL);
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| 406 | if (RT_FAILURE(rc))
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| 407 | RTPrintf("tstTSC: WARNING - RTThreadWait(%#u) -> rc=%Rrc!\n", i, rc);
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| 408 | }
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| 409 |
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| 410 | return g_cFailed != 0 || g_cRead != cCpus;
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| 411 | }
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| 412 |
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| 413 |
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| 414 | static int tstTSCCalcFrequency(uint32_t cMsDuration)
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| 415 | {
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| 416 | /*
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| 417 | * Sample the TSC and time, sleep the requested time and calc the deltas.
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| 418 | */
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| 419 | uint64_t uNanoTS = RTTimeSystemNanoTS();
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| 420 | uint64_t uTSC = ASMReadTSC();
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| 421 | RTThreadSleep(cMsDuration);
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| 422 | uNanoTS = RTTimeSystemNanoTS() - uNanoTS;
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| 423 | uTSC = ASMReadTSC() - uTSC;
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| 424 |
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| 425 | /*
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| 426 | * Calc the frequency.
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|---|
| 427 | */
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|---|
| 428 | RTPrintf("tstTSC: %RU64 ticks in %RU64 ns\n", uTSC, uNanoTS);
|
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| 429 | uint64_t cHz = (uint64_t)((long double)uTSC / ((long double)uNanoTS / (long double)1000000000));
|
|---|
| 430 | RTPrintf("tstTSC: Frequency %RU64 Hz", cHz);
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| 431 | if (cHz > _1G)
|
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| 432 | {
|
|---|
| 433 | cHz += _1G / 20;
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| 434 | RTPrintf(" %RU64.%RU64 GHz", cHz / _1G, (cHz % _1G) / (_1G / 10));
|
|---|
| 435 | }
|
|---|
| 436 | else if (cHz > _1M)
|
|---|
| 437 | {
|
|---|
| 438 | cHz += _1M / 20;
|
|---|
| 439 | RTPrintf(" %RU64.%RU64 MHz", cHz / _1M, (cHz % _1M) / (_1M / 10));
|
|---|
| 440 | }
|
|---|
| 441 | RTPrintf("\n");
|
|---|
| 442 | return 0;
|
|---|
| 443 | }
|
|---|
| 444 |
|
|---|
| 445 |
|
|---|
| 446 | int main(int argc, char **argv)
|
|---|
| 447 | {
|
|---|
| 448 | RTR3InitExe(argc, &argv, 0);
|
|---|
| 449 |
|
|---|
| 450 | /*
|
|---|
| 451 | * Parse arguments.
|
|---|
| 452 | */
|
|---|
| 453 | bool fCalcFrequency = false;
|
|---|
| 454 | uint32_t cMsDuration = 1000; /* 1 sec */
|
|---|
| 455 | static const RTGETOPTDEF s_aOptions[] =
|
|---|
| 456 | {
|
|---|
| 457 | { "--duration", 'd', RTGETOPT_REQ_UINT32 },
|
|---|
| 458 | { "--calc-frequency", 'f', RTGETOPT_REQ_NOTHING },
|
|---|
| 459 | };
|
|---|
| 460 | int ch;
|
|---|
| 461 | RTGETOPTUNION Value;
|
|---|
| 462 | RTGETOPTSTATE GetState;
|
|---|
| 463 | RTGetOptInit(&GetState, argc, argv, s_aOptions, RT_ELEMENTS(s_aOptions), 1, 0 /* fFlags */);
|
|---|
| 464 | while ((ch = RTGetOpt(&GetState, &Value)))
|
|---|
| 465 | switch (ch)
|
|---|
| 466 | {
|
|---|
| 467 | case 'd': cMsDuration = Value.u32;
|
|---|
| 468 | break;
|
|---|
| 469 |
|
|---|
| 470 | case 'f': fCalcFrequency = true;
|
|---|
| 471 | break;
|
|---|
| 472 |
|
|---|
| 473 | case 'h':
|
|---|
| 474 | RTPrintf("usage: tstTSC\n"
|
|---|
| 475 | " or: tstTSC <-f|--calc-frequency> [--duration|-d ms]\n");
|
|---|
| 476 | return 1;
|
|---|
| 477 |
|
|---|
| 478 | case 'V':
|
|---|
| 479 | RTPrintf("$Revision: 106929 $\n");
|
|---|
| 480 | return 0;
|
|---|
| 481 |
|
|---|
| 482 | default:
|
|---|
| 483 | return RTGetOptPrintError(ch, &Value);
|
|---|
| 484 | }
|
|---|
| 485 |
|
|---|
| 486 | if (fCalcFrequency)
|
|---|
| 487 | return tstTSCCalcFrequency(cMsDuration);
|
|---|
| 488 | return tstTSCCalcDrift();
|
|---|
| 489 | }
|
|---|
| 490 |
|
|---|
