1 | /* $Id: CPUM.cpp 16665 2009-02-11 13:57:23Z vboxsync $ */
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2 | /** @file
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3 | * CPUM - CPU Monitor / Manager.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /** @page pg_cpum CPUM - CPU Monitor / Manager
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23 | *
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24 | * The CPU Monitor / Manager keeps track of all the CPU registers. It is
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25 | * also responsible for lazy FPU handling and some of the context loading
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26 | * in raw mode.
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27 | *
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28 | * There are three CPU contexts, the most important one is the guest one (GC).
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29 | * When running in raw-mode (RC) there is a special hyper context for the VMM
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30 | * part that floats around inside the guest address space. When running in
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31 | * raw-mode, CPUM also maintains a host context for saving and restoring
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32 | * registers accross world switches. This latter is done in cooperation with the
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33 | * world switcher (@see pg_vmm).
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34 | *
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35 | * @see grp_cpum
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36 | */
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37 |
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38 | /*******************************************************************************
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39 | * Header Files *
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40 | *******************************************************************************/
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41 | #define LOG_GROUP LOG_GROUP_CPUM
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42 | #include <VBox/cpum.h>
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43 | #include <VBox/cpumdis.h>
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44 | #include <VBox/pgm.h>
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45 | #include <VBox/pdm.h>
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46 | #include <VBox/mm.h>
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47 | #include <VBox/selm.h>
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48 | #include <VBox/dbgf.h>
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49 | #include <VBox/patm.h>
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50 | #include <VBox/hwaccm.h>
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51 | #include <VBox/ssm.h>
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52 | #include "CPUMInternal.h"
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53 | #include <VBox/vm.h>
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54 |
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55 | #include <VBox/param.h>
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56 | #include <VBox/dis.h>
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57 | #include <VBox/err.h>
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58 | #include <VBox/log.h>
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59 | #include <iprt/assert.h>
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60 | #include <iprt/asm.h>
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61 | #include <iprt/string.h>
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62 | #include <iprt/mp.h>
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63 | #include <iprt/cpuset.h>
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64 |
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65 |
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66 | /*******************************************************************************
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67 | * Defined Constants And Macros *
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68 | *******************************************************************************/
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69 | /** The saved state version. */
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70 | #define CPUM_SAVED_STATE_VERSION 10
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71 | /** The saved state version for the 2.1 trunk before the MSR changes. */
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72 | #define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
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73 | /** The saved state version of 2.0, used for backwards compatibility. */
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74 | #define CPUM_SAVED_STATE_VERSION_VER2_0 8
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75 | /** The saved state version of 1.6, used for backwards compatability. */
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76 | #define CPUM_SAVED_STATE_VERSION_VER1_6 6
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77 |
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78 |
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79 | /*******************************************************************************
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80 | * Structures and Typedefs *
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81 | *******************************************************************************/
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82 |
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83 | /**
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84 | * What kind of cpu info dump to perform.
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85 | */
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86 | typedef enum CPUMDUMPTYPE
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87 | {
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88 | CPUMDUMPTYPE_TERSE,
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89 | CPUMDUMPTYPE_DEFAULT,
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90 | CPUMDUMPTYPE_VERBOSE
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91 |
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92 | } CPUMDUMPTYPE;
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93 | /** Pointer to a cpu info dump type. */
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94 | typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
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95 |
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96 |
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97 | /*******************************************************************************
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98 | * Internal Functions *
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99 | *******************************************************************************/
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100 | static int cpumR3CpuIdInit(PVM pVM);
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101 | static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
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102 | static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
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103 | static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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104 | static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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105 | static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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106 | static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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107 | static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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108 | static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
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109 |
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110 |
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111 | /**
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112 | * Initializes the CPUM.
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113 | *
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114 | * @returns VBox status code.
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115 | * @param pVM The VM to operate on.
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116 | */
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117 | VMMR3DECL(int) CPUMR3Init(PVM pVM)
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118 | {
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119 | LogFlow(("CPUMR3Init\n"));
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120 |
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121 | /*
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122 | * Assert alignment and sizes.
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123 | */
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124 | AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
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125 | AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
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126 |
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127 | /*
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128 | * Setup any fixed pointers and offsets.
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129 | */
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130 | pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
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131 | pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
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132 |
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133 | /* Hidden selector registers are invalid by default. */
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134 | pVM->cpum.s.fValidHiddenSelRegs = false;
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135 |
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136 | /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
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137 | pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
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138 | Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
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139 |
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140 | /* Calculate the offset from CPUMCPU to CPUM. */
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141 | for (unsigned i=0;i<pVM->cCPUs;i++)
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142 | {
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143 | pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
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144 | Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
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145 | }
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146 |
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147 | /*
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148 | * Check that the CPU supports the minimum features we require.
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149 | */
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150 | if (!ASMHasCpuId())
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151 | {
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152 | Log(("The CPU doesn't support CPUID!\n"));
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153 | return VERR_UNSUPPORTED_CPU;
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154 | }
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155 | ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
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156 | ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
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157 |
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158 | /* Setup the CR4 AND and OR masks used in the switcher */
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159 | /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
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160 | if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
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161 | {
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162 | Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
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163 | /* No FXSAVE implies no SSE */
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164 | pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
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165 | pVM->cpum.s.CR4.OrMask = 0;
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166 | }
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167 | else
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168 | {
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169 | pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
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170 | pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
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171 | }
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172 |
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173 | if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
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174 | {
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175 | Log(("The CPU doesn't support MMX!\n"));
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176 | return VERR_UNSUPPORTED_CPU;
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177 | }
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178 | if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
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179 | {
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180 | Log(("The CPU doesn't support TSC!\n"));
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181 | return VERR_UNSUPPORTED_CPU;
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182 | }
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183 | /* Bogus on AMD? */
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184 | if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
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185 | Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
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186 |
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187 | /*
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188 | * Setup hypervisor startup values.
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189 | */
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190 |
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191 | /*
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192 | * Register saved state data item.
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193 | */
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194 | int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
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195 | NULL, cpumR3Save, NULL,
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196 | NULL, cpumR3Load, NULL);
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197 | if (RT_FAILURE(rc))
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198 | return rc;
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199 |
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200 | /* Query the CPU manufacturer. */
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201 | uint32_t uEAX, uEBX, uECX, uEDX;
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202 | ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
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203 | if ( uEAX >= 1
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204 | && uEBX == X86_CPUID_VENDOR_AMD_EBX
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205 | && uECX == X86_CPUID_VENDOR_AMD_ECX
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206 | && uEDX == X86_CPUID_VENDOR_AMD_EDX)
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207 | pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
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208 | else if ( uEAX >= 1
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209 | && uEBX == X86_CPUID_VENDOR_INTEL_EBX
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210 | && uECX == X86_CPUID_VENDOR_INTEL_ECX
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211 | && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
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212 | pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
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213 | else /** @todo Via */
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214 | pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
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215 |
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216 | /*
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217 | * Register info handlers.
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218 | */
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219 | DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
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220 | DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
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221 | DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
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222 | DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
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223 | DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
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224 | DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
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225 |
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226 | /*
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227 | * Initialize the Guest CPU state.
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228 | */
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229 | rc = cpumR3CpuIdInit(pVM);
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230 | if (RT_FAILURE(rc))
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231 | return rc;
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232 | CPUMR3Reset(pVM);
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233 | return VINF_SUCCESS;
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234 | }
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235 |
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236 |
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237 | /**
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238 | * Initializes the per-VCPU CPUM.
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239 | *
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240 | * @returns VBox status code.
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241 | * @param pVM The VM to operate on.
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242 | */
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243 | VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
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244 | {
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245 | LogFlow(("CPUMR3InitCPU\n"));
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246 | return VINF_SUCCESS;
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247 | }
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248 |
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249 |
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250 | /**
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251 | * Initializes the emulated CPU's cpuid information.
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252 | *
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253 | * @returns VBox status code.
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254 | * @param pVM The VM to operate on.
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255 | */
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256 | static int cpumR3CpuIdInit(PVM pVM)
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257 | {
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258 | PCPUM pCPUM = &pVM->cpum.s;
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259 | uint32_t i;
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260 |
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261 | /*
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262 | * Get the host CPUIDs.
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263 | */
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264 | for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
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265 | ASMCpuId_Idx_ECX(i, 0,
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266 | &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
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267 | &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
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268 | for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
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269 | ASMCpuId(0x80000000 + i,
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270 | &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
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271 | &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
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272 | for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
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273 | ASMCpuId(0xc0000000 + i,
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274 | &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
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275 | &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
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276 |
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277 |
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278 | /*
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279 | * Only report features we can support.
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280 | */
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281 | pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
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282 | | X86_CPUID_FEATURE_EDX_VME
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283 | | X86_CPUID_FEATURE_EDX_DE
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284 | | X86_CPUID_FEATURE_EDX_PSE
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285 | | X86_CPUID_FEATURE_EDX_TSC
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286 | | X86_CPUID_FEATURE_EDX_MSR
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287 | //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
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288 | | X86_CPUID_FEATURE_EDX_MCE
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289 | | X86_CPUID_FEATURE_EDX_CX8
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290 | //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
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291 | /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
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292 | //| X86_CPUID_FEATURE_EDX_SEP
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293 | | X86_CPUID_FEATURE_EDX_MTRR
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294 | | X86_CPUID_FEATURE_EDX_PGE
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295 | | X86_CPUID_FEATURE_EDX_MCA
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296 | | X86_CPUID_FEATURE_EDX_CMOV
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297 | | X86_CPUID_FEATURE_EDX_PAT
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298 | | X86_CPUID_FEATURE_EDX_PSE36
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299 | //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
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300 | | X86_CPUID_FEATURE_EDX_CLFSH
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301 | //| X86_CPUID_FEATURE_EDX_DS - no debug store.
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302 | //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
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303 | | X86_CPUID_FEATURE_EDX_MMX
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304 | | X86_CPUID_FEATURE_EDX_FXSR
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305 | | X86_CPUID_FEATURE_EDX_SSE
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306 | | X86_CPUID_FEATURE_EDX_SSE2
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307 | //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
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308 | //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
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309 | //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
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310 | //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
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311 | | 0;
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312 | pCPUM->aGuestCpuIdStd[1].ecx &= 0
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313 | #ifdef VBOX_WITH_NEW_RECOMPILER
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314 | | X86_CPUID_FEATURE_ECX_SSE3
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315 | #endif
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316 | | X86_CPUID_FEATURE_ECX_MONITOR
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317 | //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
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318 | //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
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319 | //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
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320 | //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
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321 | //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
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322 | //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
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323 | //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
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324 | /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
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325 | //| X86_CPUID_FEATURE_ECX_TPRUPDATE
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326 | /* ECX Bit 21 - x2APIC support - not yet. */
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327 | // | X86_CPUID_FEATURE_ECX_X2APIC
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328 | /* ECX Bit 23 - POPCOUNT instruction. */
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329 | //| X86_CPUID_FEATURE_ECX_POPCOUNT
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330 | | 0;
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331 |
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332 | /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
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333 | pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
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334 | | X86_CPUID_AMD_FEATURE_EDX_VME
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335 | | X86_CPUID_AMD_FEATURE_EDX_DE
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336 | | X86_CPUID_AMD_FEATURE_EDX_PSE
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337 | | X86_CPUID_AMD_FEATURE_EDX_TSC
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338 | | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
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339 | //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
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340 | //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
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341 | | X86_CPUID_AMD_FEATURE_EDX_CX8
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342 | //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
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343 | /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
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344 | //| X86_CPUID_AMD_FEATURE_EDX_SEP
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345 | | X86_CPUID_AMD_FEATURE_EDX_MTRR
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346 | | X86_CPUID_AMD_FEATURE_EDX_PGE
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347 | | X86_CPUID_AMD_FEATURE_EDX_MCA
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348 | | X86_CPUID_AMD_FEATURE_EDX_CMOV
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349 | | X86_CPUID_AMD_FEATURE_EDX_PAT
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350 | | X86_CPUID_AMD_FEATURE_EDX_PSE36
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351 | //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
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352 | //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
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353 | | X86_CPUID_AMD_FEATURE_EDX_MMX
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354 | | X86_CPUID_AMD_FEATURE_EDX_FXSR
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355 | | X86_CPUID_AMD_FEATURE_EDX_FFXSR
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356 | //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
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357 | //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
|
---|
358 | //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
|
---|
359 | | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
|
---|
360 | | X86_CPUID_AMD_FEATURE_EDX_3DNOW
|
---|
361 | | 0;
|
---|
362 | pCPUM->aGuestCpuIdExt[1].ecx &= 0
|
---|
363 | //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
|
---|
364 | //| X86_CPUID_AMD_FEATURE_ECX_CMPL
|
---|
365 | //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
|
---|
366 | //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
|
---|
367 | //| X86_CPUID_AMD_FEATURE_ECX_CR8L
|
---|
368 | //| X86_CPUID_AMD_FEATURE_ECX_ABM
|
---|
369 | //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
|
---|
370 | //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
|
---|
371 | //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
|
---|
372 | //| X86_CPUID_AMD_FEATURE_ECX_OSVW
|
---|
373 | //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
|
---|
374 | //| X86_CPUID_AMD_FEATURE_ECX_WDT
|
---|
375 | | 0;
|
---|
376 |
|
---|
377 | /*
|
---|
378 | * Hide HTT, multicode, SMP, whatever.
|
---|
379 | * (APIC-ID := 0 and #LogCpus := 0)
|
---|
380 | */
|
---|
381 | pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
|
---|
382 |
|
---|
383 | /* Cpuid 2:
|
---|
384 | * Intel: Cache and TLB information
|
---|
385 | * AMD: Reserved
|
---|
386 | * Safe to expose
|
---|
387 | */
|
---|
388 |
|
---|
389 | /* Cpuid 3:
|
---|
390 | * Intel: EAX, EBX - reserved
|
---|
391 | * ECX, EDX - Processor Serial Number if available, otherwise reserved
|
---|
392 | * AMD: Reserved
|
---|
393 | * Safe to expose
|
---|
394 | */
|
---|
395 | if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
|
---|
396 | pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
|
---|
397 |
|
---|
398 | /* Cpuid 4:
|
---|
399 | * Intel: Deterministic Cache Parameters Leaf
|
---|
400 | * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
|
---|
401 | * AMD: Reserved
|
---|
402 | * Safe to expose, except for EAX:
|
---|
403 | * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
|
---|
404 | * Bits 31-26: Maximum number of processor cores in this physical package**
|
---|
405 | */
|
---|
406 | pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
|
---|
407 | pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
|
---|
408 |
|
---|
409 | /* Cpuid 5: Monitor/mwait Leaf
|
---|
410 | * Intel: ECX, EDX - reserved
|
---|
411 | * EAX, EBX - Smallest and largest monitor line size
|
---|
412 | * AMD: EDX - reserved
|
---|
413 | * EAX, EBX - Smallest and largest monitor line size
|
---|
414 | * ECX - extensions (ignored for now)
|
---|
415 | * Safe to expose
|
---|
416 | */
|
---|
417 | if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
|
---|
418 | pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
|
---|
419 |
|
---|
420 | pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
|
---|
421 |
|
---|
422 | /*
|
---|
423 | * Determine the default.
|
---|
424 | *
|
---|
425 | * Intel returns values of the highest standard function, while AMD
|
---|
426 | * returns zeros. VIA on the other hand seems to returning nothing or
|
---|
427 | * perhaps some random garbage, we don't try to duplicate this behavior.
|
---|
428 | */
|
---|
429 | ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
|
---|
430 | &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
|
---|
431 | &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
|
---|
432 |
|
---|
433 | /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
|
---|
434 | * Safe to pass on to the guest.
|
---|
435 | *
|
---|
436 | * Intel: 0x800000005 reserved
|
---|
437 | * 0x800000006 L2 cache information
|
---|
438 | * AMD: 0x800000005 L1 cache information
|
---|
439 | * 0x800000006 L2/L3 cache information
|
---|
440 | */
|
---|
441 |
|
---|
442 | /* Cpuid 0x800000007:
|
---|
443 | * AMD: EAX, EBX, ECX - reserved
|
---|
444 | * EDX: Advanced Power Management Information
|
---|
445 | * Intel: Reserved
|
---|
446 | */
|
---|
447 | if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
|
---|
448 | {
|
---|
449 | Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
|
---|
450 |
|
---|
451 | pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
|
---|
452 |
|
---|
453 | if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
|
---|
454 | {
|
---|
455 | /* Only expose the TSC invariant capability bit to the guest. */
|
---|
456 | pCPUM->aGuestCpuIdExt[7].edx &= 0
|
---|
457 | //| X86_CPUID_AMD_ADVPOWER_EDX_TS
|
---|
458 | //| X86_CPUID_AMD_ADVPOWER_EDX_FID
|
---|
459 | //| X86_CPUID_AMD_ADVPOWER_EDX_VID
|
---|
460 | //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
|
---|
461 | //| X86_CPUID_AMD_ADVPOWER_EDX_TM
|
---|
462 | //| X86_CPUID_AMD_ADVPOWER_EDX_STC
|
---|
463 | //| X86_CPUID_AMD_ADVPOWER_EDX_MC
|
---|
464 | //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
|
---|
465 | | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
|
---|
466 | | 0;
|
---|
467 | }
|
---|
468 | else
|
---|
469 | pCPUM->aGuestCpuIdExt[7].edx = 0;
|
---|
470 | }
|
---|
471 |
|
---|
472 | /* Cpuid 0x800000008:
|
---|
473 | * AMD: EBX, EDX - reserved
|
---|
474 | * EAX: Virtual/Physical address Size
|
---|
475 | * ECX: Number of cores + APICIdCoreIdSize
|
---|
476 | * Intel: EAX: Virtual/Physical address Size
|
---|
477 | * EBX, ECX, EDX - reserved
|
---|
478 | */
|
---|
479 | if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
|
---|
480 | {
|
---|
481 | /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
|
---|
482 | pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
|
---|
483 | /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
|
---|
484 | * NC (0-7) Number of cores; 0 equals 1 core */
|
---|
485 | pCPUM->aGuestCpuIdExt[8].ecx = 0;
|
---|
486 | }
|
---|
487 |
|
---|
488 | /*
|
---|
489 | * Limit it the number of entries and fill the remaining with the defaults.
|
---|
490 | *
|
---|
491 | * The limits are masking off stuff about power saving and similar, this
|
---|
492 | * is perhaps a bit crudely done as there is probably some relatively harmless
|
---|
493 | * info too in these leaves (like words about having a constant TSC).
|
---|
494 | */
|
---|
495 | #if 0
|
---|
496 | /** @todo NT4 installation regression - investigate */
|
---|
497 | if (pCPUM->aGuestCpuIdStd[0].eax > 5)
|
---|
498 | pCPUM->aGuestCpuIdStd[0].eax = 5;
|
---|
499 | #else
|
---|
500 | if (pCPUM->aGuestCpuIdStd[0].eax > 2)
|
---|
501 | pCPUM->aGuestCpuIdStd[0].eax = 2;
|
---|
502 | #endif
|
---|
503 | for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
|
---|
504 | pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
|
---|
505 |
|
---|
506 | if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
|
---|
507 | pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
|
---|
508 | for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
|
---|
509 | ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
|
---|
510 | : 0;
|
---|
511 | i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
|
---|
512 | pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
|
---|
513 |
|
---|
514 | /*
|
---|
515 | * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
|
---|
516 | * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
|
---|
517 | * We currently don't support more than 1 processor.
|
---|
518 | */
|
---|
519 | pCPUM->aGuestCpuIdStd[4].eax = 0;
|
---|
520 |
|
---|
521 | /*
|
---|
522 | * Centaur stuff (VIA).
|
---|
523 | *
|
---|
524 | * The important part here (we think) is to make sure the 0xc0000000
|
---|
525 | * function returns 0xc0000001. As for the features, we don't currently
|
---|
526 | * let on about any of those... 0xc0000002 seems to be some
|
---|
527 | * temperature/hz/++ stuff, include it as well (static).
|
---|
528 | */
|
---|
529 | if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
|
---|
530 | && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
|
---|
531 | {
|
---|
532 | pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
|
---|
533 | pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
|
---|
534 | for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
|
---|
535 | i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
|
---|
536 | i++)
|
---|
537 | pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
|
---|
538 | }
|
---|
539 | else
|
---|
540 | for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
|
---|
541 | pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
|
---|
542 |
|
---|
543 |
|
---|
544 | /*
|
---|
545 | * Load CPUID overrides from configuration.
|
---|
546 | */
|
---|
547 | /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
|
---|
548 | * Overloads the CPUID leaf values. */
|
---|
549 | PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
|
---|
550 | uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
|
---|
551 | for (i=0;; )
|
---|
552 | {
|
---|
553 | while (cElements-- > 0)
|
---|
554 | {
|
---|
555 | PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
|
---|
556 | if (pNode)
|
---|
557 | {
|
---|
558 | uint32_t u32;
|
---|
559 | int rc = CFGMR3QueryU32(pNode, "eax", &u32);
|
---|
560 | if (RT_SUCCESS(rc))
|
---|
561 | pCpuId->eax = u32;
|
---|
562 | else
|
---|
563 | AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
|
---|
564 |
|
---|
565 | rc = CFGMR3QueryU32(pNode, "ebx", &u32);
|
---|
566 | if (RT_SUCCESS(rc))
|
---|
567 | pCpuId->ebx = u32;
|
---|
568 | else
|
---|
569 | AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
|
---|
570 |
|
---|
571 | rc = CFGMR3QueryU32(pNode, "ecx", &u32);
|
---|
572 | if (RT_SUCCESS(rc))
|
---|
573 | pCpuId->ecx = u32;
|
---|
574 | else
|
---|
575 | AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
|
---|
576 |
|
---|
577 | rc = CFGMR3QueryU32(pNode, "edx", &u32);
|
---|
578 | if (RT_SUCCESS(rc))
|
---|
579 | pCpuId->edx = u32;
|
---|
580 | else
|
---|
581 | AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
|
---|
582 | }
|
---|
583 | pCpuId++;
|
---|
584 | i++;
|
---|
585 | }
|
---|
586 |
|
---|
587 | /* next */
|
---|
588 | if ((i & UINT32_C(0xc0000000)) == 0)
|
---|
589 | {
|
---|
590 | pCpuId = &pCPUM->aGuestCpuIdExt[0];
|
---|
591 | cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
|
---|
592 | i = UINT32_C(0x80000000);
|
---|
593 | }
|
---|
594 | else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
|
---|
595 | {
|
---|
596 | pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
|
---|
597 | cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
|
---|
598 | i = UINT32_C(0xc0000000);
|
---|
599 | }
|
---|
600 | else
|
---|
601 | break;
|
---|
602 | }
|
---|
603 |
|
---|
604 | /* Check if PAE was explicitely enabled by the user. */
|
---|
605 | bool fEnable = false;
|
---|
606 | int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
|
---|
607 | if (RT_SUCCESS(rc) && fEnable)
|
---|
608 | CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
|
---|
609 |
|
---|
610 | /*
|
---|
611 | * Log the cpuid and we're good.
|
---|
612 | */
|
---|
613 | RTCPUSET OnlineSet;
|
---|
614 | LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
|
---|
615 | (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
|
---|
616 | LogRel(("************************* CPUID dump ************************\n"));
|
---|
617 | DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
|
---|
618 | LogRel(("\n"));
|
---|
619 | DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
|
---|
620 | LogRel(("******************** End of CPUID dump **********************\n"));
|
---|
621 | return VINF_SUCCESS;
|
---|
622 | }
|
---|
623 |
|
---|
624 |
|
---|
625 |
|
---|
626 |
|
---|
627 | /**
|
---|
628 | * Applies relocations to data and code managed by this
|
---|
629 | * component. This function will be called at init and
|
---|
630 | * whenever the VMM need to relocate it self inside the GC.
|
---|
631 | *
|
---|
632 | * The CPUM will update the addresses used by the switcher.
|
---|
633 | *
|
---|
634 | * @param pVM The VM.
|
---|
635 | */
|
---|
636 | VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
|
---|
637 | {
|
---|
638 | LogFlow(("CPUMR3Relocate\n"));
|
---|
639 | /*
|
---|
640 | * Switcher pointers.
|
---|
641 | */
|
---|
642 | pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
|
---|
643 | Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
|
---|
644 | }
|
---|
645 |
|
---|
646 |
|
---|
647 | /**
|
---|
648 | * Terminates the CPUM.
|
---|
649 | *
|
---|
650 | * Termination means cleaning up and freeing all resources,
|
---|
651 | * the VM it self is at this point powered off or suspended.
|
---|
652 | *
|
---|
653 | * @returns VBox status code.
|
---|
654 | * @param pVM The VM to operate on.
|
---|
655 | */
|
---|
656 | VMMR3DECL(int) CPUMR3Term(PVM pVM)
|
---|
657 | {
|
---|
658 | CPUMR3TermCPU(pVM);
|
---|
659 | return 0;
|
---|
660 | }
|
---|
661 |
|
---|
662 |
|
---|
663 | /**
|
---|
664 | * Terminates the per-VCPU CPUM.
|
---|
665 | *
|
---|
666 | * Termination means cleaning up and freeing all resources,
|
---|
667 | * the VM it self is at this point powered off or suspended.
|
---|
668 | *
|
---|
669 | * @returns VBox status code.
|
---|
670 | * @param pVM The VM to operate on.
|
---|
671 | */
|
---|
672 | VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
|
---|
673 | {
|
---|
674 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
675 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
676 | {
|
---|
677 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
|
---|
678 |
|
---|
679 | memset(pVM->aCpus[i].cpum.s.aMagic, 0, sizeof(pVM->aCpus[i].cpum.s.aMagic));
|
---|
680 | pVM->aCpus[i].cpum.s.uMagic = 0;
|
---|
681 | pCtx->dr[5] = 0;
|
---|
682 | }
|
---|
683 | #endif
|
---|
684 | return 0;
|
---|
685 | }
|
---|
686 |
|
---|
687 |
|
---|
688 | /**
|
---|
689 | * Resets the CPU.
|
---|
690 | *
|
---|
691 | * @returns VINF_SUCCESS.
|
---|
692 | * @param pVM The VM handle.
|
---|
693 | */
|
---|
694 | VMMR3DECL(void) CPUMR3Reset(PVM pVM)
|
---|
695 | {
|
---|
696 | /* @todo anything different for VCPU > 0? */
|
---|
697 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
698 | {
|
---|
699 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
|
---|
700 |
|
---|
701 | /*
|
---|
702 | * Initialize everything to ZERO first.
|
---|
703 | */
|
---|
704 | uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
|
---|
705 | memset(pCtx, 0, sizeof(*pCtx));
|
---|
706 | pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
|
---|
707 |
|
---|
708 | pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
|
---|
709 | pCtx->eip = 0x0000fff0;
|
---|
710 | pCtx->edx = 0x00000600; /* P6 processor */
|
---|
711 | pCtx->eflags.Bits.u1Reserved0 = 1;
|
---|
712 |
|
---|
713 | pCtx->cs = 0xf000;
|
---|
714 | pCtx->csHid.u64Base = UINT64_C(0xffff0000);
|
---|
715 | pCtx->csHid.u32Limit = 0x0000ffff;
|
---|
716 | pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
717 | pCtx->csHid.Attr.n.u1Present = 1;
|
---|
718 | pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
|
---|
719 |
|
---|
720 | pCtx->dsHid.u32Limit = 0x0000ffff;
|
---|
721 | pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
722 | pCtx->dsHid.Attr.n.u1Present = 1;
|
---|
723 | pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
|
---|
724 |
|
---|
725 | pCtx->esHid.u32Limit = 0x0000ffff;
|
---|
726 | pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
727 | pCtx->esHid.Attr.n.u1Present = 1;
|
---|
728 | pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
|
---|
729 |
|
---|
730 | pCtx->fsHid.u32Limit = 0x0000ffff;
|
---|
731 | pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
732 | pCtx->fsHid.Attr.n.u1Present = 1;
|
---|
733 | pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
|
---|
734 |
|
---|
735 | pCtx->gsHid.u32Limit = 0x0000ffff;
|
---|
736 | pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
737 | pCtx->gsHid.Attr.n.u1Present = 1;
|
---|
738 | pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
|
---|
739 |
|
---|
740 | pCtx->ssHid.u32Limit = 0x0000ffff;
|
---|
741 | pCtx->ssHid.Attr.n.u1Present = 1;
|
---|
742 | pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
|
---|
743 | pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
|
---|
744 |
|
---|
745 | pCtx->idtr.cbIdt = 0xffff;
|
---|
746 | pCtx->gdtr.cbGdt = 0xffff;
|
---|
747 |
|
---|
748 | pCtx->ldtrHid.u32Limit = 0xffff;
|
---|
749 | pCtx->ldtrHid.Attr.n.u1Present = 1;
|
---|
750 | pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
|
---|
751 |
|
---|
752 | pCtx->trHid.u32Limit = 0xffff;
|
---|
753 | pCtx->trHid.Attr.n.u1Present = 1;
|
---|
754 | pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
|
---|
755 |
|
---|
756 | pCtx->dr[6] = X86_DR6_INIT_VAL;
|
---|
757 | pCtx->dr[7] = X86_DR7_INIT_VAL;
|
---|
758 |
|
---|
759 | pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
|
---|
760 | pCtx->fpu.FCW = 0x37f;
|
---|
761 |
|
---|
762 | /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
|
---|
763 | pCtx->fpu.MXCSR = 0x1F80;
|
---|
764 |
|
---|
765 | /* Init PAT MSR */
|
---|
766 | pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
|
---|
767 |
|
---|
768 | /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
|
---|
769 | * The Intel docs don't mention it.
|
---|
770 | */
|
---|
771 | pCtx->msrEFER = 0;
|
---|
772 |
|
---|
773 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
774 | /* Magic marker for searching in crash dumps. */
|
---|
775 | strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
|
---|
776 | pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
|
---|
777 | pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
|
---|
778 | #endif
|
---|
779 | }
|
---|
780 | }
|
---|
781 |
|
---|
782 |
|
---|
783 | /**
|
---|
784 | * Execute state save operation.
|
---|
785 | *
|
---|
786 | * @returns VBox status code.
|
---|
787 | * @param pVM VM Handle.
|
---|
788 | * @param pSSM SSM operation handle.
|
---|
789 | */
|
---|
790 | static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
791 | {
|
---|
792 | /*
|
---|
793 | * Save.
|
---|
794 | */
|
---|
795 | SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
|
---|
796 |
|
---|
797 | SSMR3PutU32(pSSM, pVM->cCPUs);
|
---|
798 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
799 | {
|
---|
800 | SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
|
---|
801 | SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
|
---|
802 | SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
|
---|
803 | SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
|
---|
804 | }
|
---|
805 |
|
---|
806 | SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
|
---|
807 | SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
|
---|
808 |
|
---|
809 | SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
|
---|
810 | SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
|
---|
811 |
|
---|
812 | SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
|
---|
813 | SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
|
---|
814 |
|
---|
815 | SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
|
---|
816 |
|
---|
817 | /* Add the cpuid for checking that the cpu is unchanged. */
|
---|
818 | uint32_t au32CpuId[8] = {0};
|
---|
819 | ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
|
---|
820 | ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
|
---|
821 | return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
|
---|
822 | }
|
---|
823 |
|
---|
824 |
|
---|
825 | /**
|
---|
826 | * Load a version 1.6 CPUMCTX structure.
|
---|
827 | *
|
---|
828 | * @returns VBox status code.
|
---|
829 | * @param pVM VM Handle.
|
---|
830 | * @param pCpumctx16 Version 1.6 CPUMCTX
|
---|
831 | */
|
---|
832 | static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
|
---|
833 | {
|
---|
834 | #define CPUMCTX16_LOADREG(RegName) \
|
---|
835 | pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
|
---|
836 |
|
---|
837 | #define CPUMCTX16_LOADDRXREG(RegName) \
|
---|
838 | pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
|
---|
839 |
|
---|
840 | #define CPUMCTX16_LOADHIDREG(RegName) \
|
---|
841 | pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
|
---|
842 | pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
|
---|
843 | pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
|
---|
844 |
|
---|
845 | #define CPUMCTX16_LOADSEGREG(RegName) \
|
---|
846 | pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
|
---|
847 | CPUMCTX16_LOADHIDREG(RegName);
|
---|
848 |
|
---|
849 | pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
|
---|
850 |
|
---|
851 | CPUMCTX16_LOADREG(rax);
|
---|
852 | CPUMCTX16_LOADREG(rbx);
|
---|
853 | CPUMCTX16_LOADREG(rcx);
|
---|
854 | CPUMCTX16_LOADREG(rdx);
|
---|
855 | CPUMCTX16_LOADREG(rdi);
|
---|
856 | CPUMCTX16_LOADREG(rsi);
|
---|
857 | CPUMCTX16_LOADREG(rbp);
|
---|
858 | CPUMCTX16_LOADREG(esp);
|
---|
859 | CPUMCTX16_LOADREG(rip);
|
---|
860 | CPUMCTX16_LOADREG(rflags);
|
---|
861 |
|
---|
862 | CPUMCTX16_LOADSEGREG(cs);
|
---|
863 | CPUMCTX16_LOADSEGREG(ds);
|
---|
864 | CPUMCTX16_LOADSEGREG(es);
|
---|
865 | CPUMCTX16_LOADSEGREG(fs);
|
---|
866 | CPUMCTX16_LOADSEGREG(gs);
|
---|
867 | CPUMCTX16_LOADSEGREG(ss);
|
---|
868 |
|
---|
869 | CPUMCTX16_LOADREG(r8);
|
---|
870 | CPUMCTX16_LOADREG(r9);
|
---|
871 | CPUMCTX16_LOADREG(r10);
|
---|
872 | CPUMCTX16_LOADREG(r11);
|
---|
873 | CPUMCTX16_LOADREG(r12);
|
---|
874 | CPUMCTX16_LOADREG(r13);
|
---|
875 | CPUMCTX16_LOADREG(r14);
|
---|
876 | CPUMCTX16_LOADREG(r15);
|
---|
877 |
|
---|
878 | CPUMCTX16_LOADREG(cr0);
|
---|
879 | CPUMCTX16_LOADREG(cr2);
|
---|
880 | CPUMCTX16_LOADREG(cr3);
|
---|
881 | CPUMCTX16_LOADREG(cr4);
|
---|
882 |
|
---|
883 | CPUMCTX16_LOADDRXREG(0);
|
---|
884 | CPUMCTX16_LOADDRXREG(1);
|
---|
885 | CPUMCTX16_LOADDRXREG(2);
|
---|
886 | CPUMCTX16_LOADDRXREG(3);
|
---|
887 | CPUMCTX16_LOADDRXREG(4);
|
---|
888 | CPUMCTX16_LOADDRXREG(5);
|
---|
889 | CPUMCTX16_LOADDRXREG(6);
|
---|
890 | CPUMCTX16_LOADDRXREG(7);
|
---|
891 |
|
---|
892 | pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
|
---|
893 | pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
|
---|
894 | pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
|
---|
895 | pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
|
---|
896 |
|
---|
897 | CPUMCTX16_LOADREG(ldtr);
|
---|
898 | CPUMCTX16_LOADREG(tr);
|
---|
899 |
|
---|
900 | pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
|
---|
901 |
|
---|
902 | CPUMCTX16_LOADREG(msrEFER);
|
---|
903 | CPUMCTX16_LOADREG(msrSTAR);
|
---|
904 | CPUMCTX16_LOADREG(msrPAT);
|
---|
905 | CPUMCTX16_LOADREG(msrLSTAR);
|
---|
906 | CPUMCTX16_LOADREG(msrCSTAR);
|
---|
907 | CPUMCTX16_LOADREG(msrSFMASK);
|
---|
908 | CPUMCTX16_LOADREG(msrKERNELGSBASE);
|
---|
909 |
|
---|
910 | CPUMCTX16_LOADHIDREG(ldtr);
|
---|
911 | CPUMCTX16_LOADHIDREG(tr);
|
---|
912 |
|
---|
913 | #undef CPUMCTX16_LOADSEGREG
|
---|
914 | #undef CPUMCTX16_LOADHIDREG
|
---|
915 | #undef CPUMCTX16_LOADDRXREG
|
---|
916 | #undef CPUMCTX16_LOADREG
|
---|
917 | }
|
---|
918 |
|
---|
919 |
|
---|
920 | /**
|
---|
921 | * Execute state load operation.
|
---|
922 | *
|
---|
923 | * @returns VBox status code.
|
---|
924 | * @param pVM VM Handle.
|
---|
925 | * @param pSSM SSM operation handle.
|
---|
926 | * @param u32Version Data layout version.
|
---|
927 | */
|
---|
928 | static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
|
---|
929 | {
|
---|
930 | /*
|
---|
931 | * Validate version.
|
---|
932 | */
|
---|
933 | if ( u32Version != CPUM_SAVED_STATE_VERSION
|
---|
934 | && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
|
---|
935 | && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
|
---|
936 | && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
|
---|
937 | {
|
---|
938 | AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
|
---|
939 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
940 | }
|
---|
941 |
|
---|
942 | /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
|
---|
943 | if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
|
---|
944 | SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
|
---|
945 | else if (u32Version <= CPUM_SAVED_STATE_VERSION)
|
---|
946 | SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
|
---|
947 |
|
---|
948 | /*
|
---|
949 | * Restore.
|
---|
950 | */
|
---|
951 | uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
|
---|
952 | uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
|
---|
953 | SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
|
---|
954 | pVM->cpum.s.Hyper.cr3 = uCR3;
|
---|
955 | pVM->cpum.s.Hyper.esp = uESP;
|
---|
956 | if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
|
---|
957 | {
|
---|
958 | CPUMCTX_VER1_6 cpumctx16;
|
---|
959 | memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
|
---|
960 | SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
|
---|
961 |
|
---|
962 | /* Save the old cpumctx state into the new one. */
|
---|
963 | cpumR3LoadCPUM1_6(pVM, &cpumctx16);
|
---|
964 |
|
---|
965 | SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
|
---|
966 | SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
|
---|
967 | }
|
---|
968 | else
|
---|
969 | {
|
---|
970 | if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
|
---|
971 | {
|
---|
972 | int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
|
---|
973 | AssertRCReturn(rc, rc);
|
---|
974 | }
|
---|
975 |
|
---|
976 | if ( !pVM->cCPUs
|
---|
977 | || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
|
---|
978 | || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
|
---|
979 | && pVM->cCPUs != 1))
|
---|
980 | {
|
---|
981 | AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
|
---|
982 | return VERR_SSM_UNEXPECTED_DATA;
|
---|
983 | }
|
---|
984 |
|
---|
985 | for (unsigned i=0;i<pVM->cCPUs;i++)
|
---|
986 | {
|
---|
987 | SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
|
---|
988 | SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
|
---|
989 | SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
|
---|
990 | if (u32Version == CPUM_SAVED_STATE_VERSION)
|
---|
991 | SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
|
---|
992 | }
|
---|
993 | }
|
---|
994 |
|
---|
995 |
|
---|
996 | uint32_t cElements;
|
---|
997 | int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
|
---|
998 | /* Support old saved states with a smaller standard cpuid array. */
|
---|
999 | if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
|
---|
1000 | return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
|
---|
1001 | SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
|
---|
1002 |
|
---|
1003 | rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
|
---|
1004 | if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
|
---|
1005 | return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
|
---|
1006 | SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
|
---|
1007 |
|
---|
1008 | rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
|
---|
1009 | if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
|
---|
1010 | return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
|
---|
1011 | SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
|
---|
1012 |
|
---|
1013 | SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
|
---|
1014 |
|
---|
1015 | /*
|
---|
1016 | * Check that the basic cpuid id information is unchanged.
|
---|
1017 | */
|
---|
1018 | uint32_t au32CpuId[8] = {0};
|
---|
1019 | ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
|
---|
1020 | ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
|
---|
1021 | uint32_t au32CpuIdSaved[8];
|
---|
1022 | rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
|
---|
1023 | if (RT_SUCCESS(rc))
|
---|
1024 | {
|
---|
1025 | /* Ignore CPU stepping. */
|
---|
1026 | au32CpuId[0] &= 0xfffffff0;
|
---|
1027 | au32CpuIdSaved[0] &= 0xfffffff0;
|
---|
1028 |
|
---|
1029 | /* Ignore APIC ID (AMD specs). */
|
---|
1030 | au32CpuId[5] &= ~0xff000000;
|
---|
1031 | au32CpuIdSaved[5] &= ~0xff000000;
|
---|
1032 |
|
---|
1033 | /* Ignore the number of Logical CPUs (AMD specs). */
|
---|
1034 | au32CpuId[5] &= ~0x00ff0000;
|
---|
1035 | au32CpuIdSaved[5] &= ~0x00ff0000;
|
---|
1036 |
|
---|
1037 | /* do the compare */
|
---|
1038 | if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
|
---|
1039 | {
|
---|
1040 | if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
|
---|
1041 | LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
|
---|
1042 | "Saved=%.*Rhxs\n"
|
---|
1043 | "Real =%.*Rhxs\n",
|
---|
1044 | sizeof(au32CpuIdSaved), au32CpuIdSaved,
|
---|
1045 | sizeof(au32CpuId), au32CpuId));
|
---|
1046 | else
|
---|
1047 | {
|
---|
1048 | LogRel(("cpumR3Load: CpuId mismatch!\n"
|
---|
1049 | "Saved=%.*Rhxs\n"
|
---|
1050 | "Real =%.*Rhxs\n",
|
---|
1051 | sizeof(au32CpuIdSaved), au32CpuIdSaved,
|
---|
1052 | sizeof(au32CpuId), au32CpuId));
|
---|
1053 | rc = VERR_SSM_LOAD_CPUID_MISMATCH;
|
---|
1054 | }
|
---|
1055 | }
|
---|
1056 | }
|
---|
1057 |
|
---|
1058 | return rc;
|
---|
1059 | }
|
---|
1060 |
|
---|
1061 |
|
---|
1062 | /**
|
---|
1063 | * Formats the EFLAGS value into mnemonics.
|
---|
1064 | *
|
---|
1065 | * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
|
---|
1066 | * @param efl The EFLAGS value.
|
---|
1067 | */
|
---|
1068 | static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
|
---|
1069 | {
|
---|
1070 | /*
|
---|
1071 | * Format the flags.
|
---|
1072 | */
|
---|
1073 | static const struct
|
---|
1074 | {
|
---|
1075 | const char *pszSet; const char *pszClear; uint32_t fFlag;
|
---|
1076 | } s_aFlags[] =
|
---|
1077 | {
|
---|
1078 | { "vip",NULL, X86_EFL_VIP },
|
---|
1079 | { "vif",NULL, X86_EFL_VIF },
|
---|
1080 | { "ac", NULL, X86_EFL_AC },
|
---|
1081 | { "vm", NULL, X86_EFL_VM },
|
---|
1082 | { "rf", NULL, X86_EFL_RF },
|
---|
1083 | { "nt", NULL, X86_EFL_NT },
|
---|
1084 | { "ov", "nv", X86_EFL_OF },
|
---|
1085 | { "dn", "up", X86_EFL_DF },
|
---|
1086 | { "ei", "di", X86_EFL_IF },
|
---|
1087 | { "tf", NULL, X86_EFL_TF },
|
---|
1088 | { "nt", "pl", X86_EFL_SF },
|
---|
1089 | { "nz", "zr", X86_EFL_ZF },
|
---|
1090 | { "ac", "na", X86_EFL_AF },
|
---|
1091 | { "po", "pe", X86_EFL_PF },
|
---|
1092 | { "cy", "nc", X86_EFL_CF },
|
---|
1093 | };
|
---|
1094 | char *psz = pszEFlags;
|
---|
1095 | for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
|
---|
1096 | {
|
---|
1097 | const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
|
---|
1098 | if (pszAdd)
|
---|
1099 | {
|
---|
1100 | strcpy(psz, pszAdd);
|
---|
1101 | psz += strlen(pszAdd);
|
---|
1102 | *psz++ = ' ';
|
---|
1103 | }
|
---|
1104 | }
|
---|
1105 | psz[-1] = '\0';
|
---|
1106 | }
|
---|
1107 |
|
---|
1108 |
|
---|
1109 | /**
|
---|
1110 | * Formats a full register dump.
|
---|
1111 | *
|
---|
1112 | * @param pVM VM Handle.
|
---|
1113 | * @param pCtx The context to format.
|
---|
1114 | * @param pCtxCore The context core to format.
|
---|
1115 | * @param pHlp Output functions.
|
---|
1116 | * @param enmType The dump type.
|
---|
1117 | * @param pszPrefix Register name prefix.
|
---|
1118 | */
|
---|
1119 | static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
|
---|
1120 | {
|
---|
1121 | /*
|
---|
1122 | * Format the EFLAGS.
|
---|
1123 | */
|
---|
1124 | uint32_t efl = pCtxCore->eflags.u32;
|
---|
1125 | char szEFlags[80];
|
---|
1126 | cpumR3InfoFormatFlags(&szEFlags[0], efl);
|
---|
1127 |
|
---|
1128 | /*
|
---|
1129 | * Format the registers.
|
---|
1130 | */
|
---|
1131 | switch (enmType)
|
---|
1132 | {
|
---|
1133 | case CPUMDUMPTYPE_TERSE:
|
---|
1134 | if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
|
---|
1135 | pHlp->pfnPrintf(pHlp,
|
---|
1136 | "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
|
---|
1137 | "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
|
---|
1138 | "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
|
---|
1139 | "%sr14=%016RX64 %sr15=%016RX64\n"
|
---|
1140 | "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
|
---|
1141 | "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
|
---|
1142 | pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
|
---|
1143 | pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
|
---|
1144 | pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
|
---|
1145 | pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1146 | pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
|
---|
1147 | pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
|
---|
1148 | else
|
---|
1149 | pHlp->pfnPrintf(pHlp,
|
---|
1150 | "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
|
---|
1151 | "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
|
---|
1152 | "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
|
---|
1153 | pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
|
---|
1154 | pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1155 | pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
|
---|
1156 | pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
|
---|
1157 | break;
|
---|
1158 |
|
---|
1159 | case CPUMDUMPTYPE_DEFAULT:
|
---|
1160 | if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
|
---|
1161 | pHlp->pfnPrintf(pHlp,
|
---|
1162 | "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
|
---|
1163 | "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
|
---|
1164 | "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
|
---|
1165 | "%sr14=%016RX64 %sr15=%016RX64\n"
|
---|
1166 | "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
|
---|
1167 | "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
|
---|
1168 | "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
|
---|
1169 | ,
|
---|
1170 | pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
|
---|
1171 | pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
|
---|
1172 | pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
|
---|
1173 | pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1174 | pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
|
---|
1175 | pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
|
---|
1176 | pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
|
---|
1177 | pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
|
---|
1178 | else
|
---|
1179 | pHlp->pfnPrintf(pHlp,
|
---|
1180 | "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
|
---|
1181 | "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
|
---|
1182 | "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
|
---|
1183 | "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
|
---|
1184 | ,
|
---|
1185 | pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
|
---|
1186 | pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1187 | pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
|
---|
1188 | pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
|
---|
1189 | pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
|
---|
1190 | pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
|
---|
1191 | break;
|
---|
1192 |
|
---|
1193 | case CPUMDUMPTYPE_VERBOSE:
|
---|
1194 | if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
|
---|
1195 | pHlp->pfnPrintf(pHlp,
|
---|
1196 | "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
|
---|
1197 | "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
|
---|
1198 | "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
|
---|
1199 | "%sr14=%016RX64 %sr15=%016RX64\n"
|
---|
1200 | "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
|
---|
1201 | "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1202 | "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1203 | "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1204 | "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1205 | "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1206 | "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
1207 | "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
|
---|
1208 | "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
|
---|
1209 | "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
|
---|
1210 | "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
|
---|
1211 | "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
1212 | "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
1213 | "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
|
---|
1214 | ,
|
---|
1215 | pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
|
---|
1216 | pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
|
---|
1217 | pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
|
---|
1218 | pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1219 | pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
|
---|
1220 | pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
|
---|
1221 | pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
|
---|
1222 | pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
|
---|
1223 | pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
|
---|
1224 | pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
|
---|
1225 | pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
|
---|
1226 | pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
|
---|
1227 | pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
|
---|
1228 | pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
|
---|
1229 | pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
|
---|
1230 | pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
|
---|
1231 | pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
|
---|
1232 | else
|
---|
1233 | pHlp->pfnPrintf(pHlp,
|
---|
1234 | "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
|
---|
1235 | "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
|
---|
1236 | "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
|
---|
1237 | "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
|
---|
1238 | "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
|
---|
1239 | "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
|
---|
1240 | "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
|
---|
1241 | "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
|
---|
1242 | "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
|
---|
1243 | "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
1244 | "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
1245 | "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
|
---|
1246 | ,
|
---|
1247 | pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
|
---|
1248 | pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
|
---|
1249 | pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
|
---|
1250 | pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
|
---|
1251 | pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
|
---|
1252 | pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
|
---|
1253 | pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
|
---|
1254 | pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
|
---|
1255 | pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
|
---|
1256 | pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
|
---|
1257 | pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
|
---|
1258 | pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
|
---|
1259 |
|
---|
1260 | pHlp->pfnPrintf(pHlp,
|
---|
1261 | "FPU:\n"
|
---|
1262 | "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
|
---|
1263 | "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
|
---|
1264 | "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
|
---|
1265 | ,
|
---|
1266 | pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
|
---|
1267 | pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
|
---|
1268 | pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
|
---|
1269 | pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
|
---|
1270 |
|
---|
1271 | pHlp->pfnPrintf(pHlp,
|
---|
1272 | "MSR:\n"
|
---|
1273 | "%sEFER =%016RX64\n"
|
---|
1274 | "%sPAT =%016RX64\n"
|
---|
1275 | "%sSTAR =%016RX64\n"
|
---|
1276 | "%sCSTAR =%016RX64\n"
|
---|
1277 | "%sLSTAR =%016RX64\n"
|
---|
1278 | "%sSFMASK =%016RX64\n"
|
---|
1279 | "%sKERNELGSBASE =%016RX64\n",
|
---|
1280 | pszPrefix, pCtx->msrEFER,
|
---|
1281 | pszPrefix, pCtx->msrPAT,
|
---|
1282 | pszPrefix, pCtx->msrSTAR,
|
---|
1283 | pszPrefix, pCtx->msrCSTAR,
|
---|
1284 | pszPrefix, pCtx->msrLSTAR,
|
---|
1285 | pszPrefix, pCtx->msrSFMASK,
|
---|
1286 | pszPrefix, pCtx->msrKERNELGSBASE);
|
---|
1287 | break;
|
---|
1288 | }
|
---|
1289 | }
|
---|
1290 |
|
---|
1291 |
|
---|
1292 | /**
|
---|
1293 | * Display all cpu states and any other cpum info.
|
---|
1294 | *
|
---|
1295 | * @param pVM VM Handle.
|
---|
1296 | * @param pHlp The info helper functions.
|
---|
1297 | * @param pszArgs Arguments, ignored.
|
---|
1298 | */
|
---|
1299 | static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1300 | {
|
---|
1301 | cpumR3InfoGuest(pVM, pHlp, pszArgs);
|
---|
1302 | cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
|
---|
1303 | cpumR3InfoHyper(pVM, pHlp, pszArgs);
|
---|
1304 | cpumR3InfoHost(pVM, pHlp, pszArgs);
|
---|
1305 | }
|
---|
1306 |
|
---|
1307 |
|
---|
1308 | /**
|
---|
1309 | * Parses the info argument.
|
---|
1310 | *
|
---|
1311 | * The argument starts with 'verbose', 'terse' or 'default' and then
|
---|
1312 | * continues with the comment string.
|
---|
1313 | *
|
---|
1314 | * @param pszArgs The pointer to the argument string.
|
---|
1315 | * @param penmType Where to store the dump type request.
|
---|
1316 | * @param ppszComment Where to store the pointer to the comment string.
|
---|
1317 | */
|
---|
1318 | static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
|
---|
1319 | {
|
---|
1320 | if (!pszArgs)
|
---|
1321 | {
|
---|
1322 | *penmType = CPUMDUMPTYPE_DEFAULT;
|
---|
1323 | *ppszComment = "";
|
---|
1324 | }
|
---|
1325 | else
|
---|
1326 | {
|
---|
1327 | if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
|
---|
1328 | {
|
---|
1329 | pszArgs += 5;
|
---|
1330 | *penmType = CPUMDUMPTYPE_VERBOSE;
|
---|
1331 | }
|
---|
1332 | else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
|
---|
1333 | {
|
---|
1334 | pszArgs += 5;
|
---|
1335 | *penmType = CPUMDUMPTYPE_TERSE;
|
---|
1336 | }
|
---|
1337 | else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
|
---|
1338 | {
|
---|
1339 | pszArgs += 7;
|
---|
1340 | *penmType = CPUMDUMPTYPE_DEFAULT;
|
---|
1341 | }
|
---|
1342 | else
|
---|
1343 | *penmType = CPUMDUMPTYPE_DEFAULT;
|
---|
1344 | *ppszComment = RTStrStripL(pszArgs);
|
---|
1345 | }
|
---|
1346 | }
|
---|
1347 |
|
---|
1348 |
|
---|
1349 | /**
|
---|
1350 | * Display the guest cpu state.
|
---|
1351 | *
|
---|
1352 | * @param pVM VM Handle.
|
---|
1353 | * @param pHlp The info helper functions.
|
---|
1354 | * @param pszArgs Arguments, ignored.
|
---|
1355 | */
|
---|
1356 | static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1357 | {
|
---|
1358 | CPUMDUMPTYPE enmType;
|
---|
1359 | const char *pszComment;
|
---|
1360 | cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
|
---|
1361 | pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
|
---|
1362 | /* @todo SMP */
|
---|
1363 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
|
---|
1364 | cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
|
---|
1365 | }
|
---|
1366 |
|
---|
1367 |
|
---|
1368 | /**
|
---|
1369 | * Display the current guest instruction
|
---|
1370 | *
|
---|
1371 | * @param pVM VM Handle.
|
---|
1372 | * @param pHlp The info helper functions.
|
---|
1373 | * @param pszArgs Arguments, ignored.
|
---|
1374 | */
|
---|
1375 | static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1376 | {
|
---|
1377 | char szInstruction[256];
|
---|
1378 | int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
|
---|
1379 | if (RT_SUCCESS(rc))
|
---|
1380 | pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
|
---|
1381 | }
|
---|
1382 |
|
---|
1383 |
|
---|
1384 | /**
|
---|
1385 | * Display the hypervisor cpu state.
|
---|
1386 | *
|
---|
1387 | * @param pVM VM Handle.
|
---|
1388 | * @param pHlp The info helper functions.
|
---|
1389 | * @param pszArgs Arguments, ignored.
|
---|
1390 | */
|
---|
1391 | static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1392 | {
|
---|
1393 | CPUMDUMPTYPE enmType;
|
---|
1394 | const char *pszComment;
|
---|
1395 | cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
|
---|
1396 | pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
|
---|
1397 | cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
|
---|
1398 | pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
|
---|
1399 | }
|
---|
1400 |
|
---|
1401 |
|
---|
1402 | /**
|
---|
1403 | * Display the host cpu state.
|
---|
1404 | *
|
---|
1405 | * @param pVM VM Handle.
|
---|
1406 | * @param pHlp The info helper functions.
|
---|
1407 | * @param pszArgs Arguments, ignored.
|
---|
1408 | */
|
---|
1409 | static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1410 | {
|
---|
1411 | CPUMDUMPTYPE enmType;
|
---|
1412 | const char *pszComment;
|
---|
1413 | cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
|
---|
1414 | pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
|
---|
1415 |
|
---|
1416 | /*
|
---|
1417 | * Format the EFLAGS.
|
---|
1418 | */
|
---|
1419 | /* @todo SMP */
|
---|
1420 | PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
|
---|
1421 | #if HC_ARCH_BITS == 32
|
---|
1422 | uint32_t efl = pCtx->eflags.u32;
|
---|
1423 | #else
|
---|
1424 | uint64_t efl = pCtx->rflags;
|
---|
1425 | #endif
|
---|
1426 | char szEFlags[80];
|
---|
1427 | cpumR3InfoFormatFlags(&szEFlags[0], efl);
|
---|
1428 |
|
---|
1429 | /*
|
---|
1430 | * Format the registers.
|
---|
1431 | */
|
---|
1432 | #if HC_ARCH_BITS == 32
|
---|
1433 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
|
---|
1434 | if (!(pCtx->efer & MSR_K6_EFER_LMA))
|
---|
1435 | # endif
|
---|
1436 | {
|
---|
1437 | pHlp->pfnPrintf(pHlp,
|
---|
1438 | "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
|
---|
1439 | "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
|
---|
1440 | "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
|
---|
1441 | "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
|
---|
1442 | "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
|
---|
1443 | "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
|
---|
1444 | ,
|
---|
1445 | /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
|
---|
1446 | /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
|
---|
1447 | (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
|
---|
1448 | pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
|
---|
1449 | pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
|
---|
1450 | (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
|
---|
1451 | pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
|
---|
1452 | }
|
---|
1453 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
|
---|
1454 | else
|
---|
1455 | # endif
|
---|
1456 | #endif
|
---|
1457 | #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
---|
1458 | {
|
---|
1459 | pHlp->pfnPrintf(pHlp,
|
---|
1460 | "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
|
---|
1461 | "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
|
---|
1462 | "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
|
---|
1463 | " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
|
---|
1464 | "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
|
---|
1465 | "r14=%016RX64 r15=%016RX64\n"
|
---|
1466 | "iopl=%d %31s\n"
|
---|
1467 | "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
|
---|
1468 | "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
|
---|
1469 | "cr4=%016RX64 ldtr=%04x tr=%04x\n"
|
---|
1470 | "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
|
---|
1471 | "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
|
---|
1472 | "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
|
---|
1473 | "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
|
---|
1474 | "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
|
---|
1475 | ,
|
---|
1476 | /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
|
---|
1477 | pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
|
---|
1478 | /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
|
---|
1479 | /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
|
---|
1480 | pCtx->r11, pCtx->r12, pCtx->r13,
|
---|
1481 | pCtx->r14, pCtx->r15,
|
---|
1482 | X86_EFL_GET_IOPL(efl), szEFlags,
|
---|
1483 | (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
|
---|
1484 | pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
|
---|
1485 | pCtx->cr4, pCtx->ldtr, pCtx->tr,
|
---|
1486 | pCtx->dr0, pCtx->dr1, pCtx->dr2,
|
---|
1487 | pCtx->dr3, pCtx->dr6, pCtx->dr7,
|
---|
1488 | pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
|
---|
1489 | pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
|
---|
1490 | pCtx->FSbase, pCtx->GSbase, pCtx->efer);
|
---|
1491 | }
|
---|
1492 | #endif
|
---|
1493 | }
|
---|
1494 |
|
---|
1495 |
|
---|
1496 | /**
|
---|
1497 | * Get L1 cache / TLS associativity.
|
---|
1498 | */
|
---|
1499 | static const char *getCacheAss(unsigned u, char *pszBuf)
|
---|
1500 | {
|
---|
1501 | if (u == 0)
|
---|
1502 | return "res0 ";
|
---|
1503 | if (u == 1)
|
---|
1504 | return "direct";
|
---|
1505 | if (u >= 256)
|
---|
1506 | return "???";
|
---|
1507 |
|
---|
1508 | RTStrPrintf(pszBuf, 16, "%d way", u);
|
---|
1509 | return pszBuf;
|
---|
1510 | }
|
---|
1511 |
|
---|
1512 |
|
---|
1513 | /**
|
---|
1514 | * Get L2 cache soociativity.
|
---|
1515 | */
|
---|
1516 | const char *getL2CacheAss(unsigned u)
|
---|
1517 | {
|
---|
1518 | switch (u)
|
---|
1519 | {
|
---|
1520 | case 0: return "off ";
|
---|
1521 | case 1: return "direct";
|
---|
1522 | case 2: return "2 way ";
|
---|
1523 | case 3: return "res3 ";
|
---|
1524 | case 4: return "4 way ";
|
---|
1525 | case 5: return "res5 ";
|
---|
1526 | case 6: return "8 way "; case 7: return "res7 ";
|
---|
1527 | case 8: return "16 way";
|
---|
1528 | case 9: return "res9 ";
|
---|
1529 | case 10: return "res10 ";
|
---|
1530 | case 11: return "res11 ";
|
---|
1531 | case 12: return "res12 ";
|
---|
1532 | case 13: return "res13 ";
|
---|
1533 | case 14: return "res14 ";
|
---|
1534 | case 15: return "fully ";
|
---|
1535 | default:
|
---|
1536 | return "????";
|
---|
1537 | }
|
---|
1538 | }
|
---|
1539 |
|
---|
1540 |
|
---|
1541 | /**
|
---|
1542 | * Display the guest CpuId leaves.
|
---|
1543 | *
|
---|
1544 | * @param pVM VM Handle.
|
---|
1545 | * @param pHlp The info helper functions.
|
---|
1546 | * @param pszArgs "terse", "default" or "verbose".
|
---|
1547 | */
|
---|
1548 | static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1549 | {
|
---|
1550 | /*
|
---|
1551 | * Parse the argument.
|
---|
1552 | */
|
---|
1553 | unsigned iVerbosity = 1;
|
---|
1554 | if (pszArgs)
|
---|
1555 | {
|
---|
1556 | pszArgs = RTStrStripL(pszArgs);
|
---|
1557 | if (!strcmp(pszArgs, "terse"))
|
---|
1558 | iVerbosity--;
|
---|
1559 | else if (!strcmp(pszArgs, "verbose"))
|
---|
1560 | iVerbosity++;
|
---|
1561 | }
|
---|
1562 |
|
---|
1563 | /*
|
---|
1564 | * Start cracking.
|
---|
1565 | */
|
---|
1566 | CPUMCPUID Host;
|
---|
1567 | CPUMCPUID Guest;
|
---|
1568 | unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
|
---|
1569 |
|
---|
1570 | pHlp->pfnPrintf(pHlp,
|
---|
1571 | " RAW Standard CPUIDs\n"
|
---|
1572 | " Function eax ebx ecx edx\n");
|
---|
1573 | for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
|
---|
1574 | {
|
---|
1575 | Guest = pVM->cpum.s.aGuestCpuIdStd[i];
|
---|
1576 | ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
1577 |
|
---|
1578 | pHlp->pfnPrintf(pHlp,
|
---|
1579 | "Gst: %08x %08x %08x %08x %08x%s\n"
|
---|
1580 | "Hst: %08x %08x %08x %08x\n",
|
---|
1581 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
|
---|
1582 | i <= cStdMax ? "" : "*",
|
---|
1583 | Host.eax, Host.ebx, Host.ecx, Host.edx);
|
---|
1584 | }
|
---|
1585 |
|
---|
1586 | /*
|
---|
1587 | * If verbose, decode it.
|
---|
1588 | */
|
---|
1589 | if (iVerbosity)
|
---|
1590 | {
|
---|
1591 | Guest = pVM->cpum.s.aGuestCpuIdStd[0];
|
---|
1592 | pHlp->pfnPrintf(pHlp,
|
---|
1593 | "Name: %.04s%.04s%.04s\n"
|
---|
1594 | "Supports: 0-%x\n",
|
---|
1595 | &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
|
---|
1596 | }
|
---|
1597 |
|
---|
1598 | /*
|
---|
1599 | * Get Features.
|
---|
1600 | */
|
---|
1601 | bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
|
---|
1602 | pVM->cpum.s.aGuestCpuIdStd[0].ecx,
|
---|
1603 | pVM->cpum.s.aGuestCpuIdStd[0].edx);
|
---|
1604 | if (cStdMax >= 1 && iVerbosity)
|
---|
1605 | {
|
---|
1606 | Guest = pVM->cpum.s.aGuestCpuIdStd[1];
|
---|
1607 | uint32_t uEAX = Guest.eax;
|
---|
1608 |
|
---|
1609 | pHlp->pfnPrintf(pHlp,
|
---|
1610 | "Family: %d \tExtended: %d \tEffective: %d\n"
|
---|
1611 | "Model: %d \tExtended: %d \tEffective: %d\n"
|
---|
1612 | "Stepping: %d\n"
|
---|
1613 | "APIC ID: %#04x\n"
|
---|
1614 | "Logical CPUs: %d\n"
|
---|
1615 | "CLFLUSH Size: %d\n"
|
---|
1616 | "Brand ID: %#04x\n",
|
---|
1617 | (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
|
---|
1618 | (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
|
---|
1619 | ASMGetCpuStepping(uEAX),
|
---|
1620 | (Guest.ebx >> 24) & 0xff,
|
---|
1621 | (Guest.ebx >> 16) & 0xff,
|
---|
1622 | (Guest.ebx >> 8) & 0xff,
|
---|
1623 | (Guest.ebx >> 0) & 0xff);
|
---|
1624 | if (iVerbosity == 1)
|
---|
1625 | {
|
---|
1626 | uint32_t uEDX = Guest.edx;
|
---|
1627 | pHlp->pfnPrintf(pHlp, "Features EDX: ");
|
---|
1628 | if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
|
---|
1629 | if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
|
---|
1630 | if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
|
---|
1631 | if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
|
---|
1632 | if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
|
---|
1633 | if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
|
---|
1634 | if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
|
---|
1635 | if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
|
---|
1636 | if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
|
---|
1637 | if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
|
---|
1638 | if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
|
---|
1639 | if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
|
---|
1640 | if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
|
---|
1641 | if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
|
---|
1642 | if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
|
---|
1643 | if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
|
---|
1644 | if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
|
---|
1645 | if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
|
---|
1646 | if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
|
---|
1647 | if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
|
---|
1648 | if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
|
---|
1649 | if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
|
---|
1650 | if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
|
---|
1651 | if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
|
---|
1652 | if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
|
---|
1653 | if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
|
---|
1654 | if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
|
---|
1655 | if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
|
---|
1656 | if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
|
---|
1657 | if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
|
---|
1658 | if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
|
---|
1659 | if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
|
---|
1660 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
1661 |
|
---|
1662 | uint32_t uECX = Guest.ecx;
|
---|
1663 | pHlp->pfnPrintf(pHlp, "Features ECX: ");
|
---|
1664 | if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
|
---|
1665 | if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
|
---|
1666 | if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
|
---|
1667 | if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
|
---|
1668 | if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
|
---|
1669 | if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
|
---|
1670 | if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
|
---|
1671 | if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
|
---|
1672 | if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
|
---|
1673 | if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
|
---|
1674 | if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
|
---|
1675 | if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
|
---|
1676 | if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
|
---|
1677 | if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
|
---|
1678 | for (unsigned iBit = 14; iBit < 32; iBit++)
|
---|
1679 | if (uECX & RT_BIT(iBit))
|
---|
1680 | pHlp->pfnPrintf(pHlp, " %d", iBit);
|
---|
1681 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
1682 | }
|
---|
1683 | else
|
---|
1684 | {
|
---|
1685 | ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
1686 |
|
---|
1687 | X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
|
---|
1688 | X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
|
---|
1689 | X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
|
---|
1690 | X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
|
---|
1691 |
|
---|
1692 | pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
|
---|
1693 | pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
|
---|
1694 | pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
|
---|
1695 | pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
|
---|
1696 | pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
|
---|
1697 | pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
|
---|
1698 | pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
|
---|
1699 | pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
|
---|
1700 | pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
|
---|
1701 | pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
|
---|
1702 | pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
|
---|
1703 | pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
|
---|
1704 | pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
|
---|
1705 | pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
|
---|
1706 | pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
|
---|
1707 | pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
|
---|
1708 | pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
|
---|
1709 | pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
|
---|
1710 | pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
|
---|
1711 | pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
|
---|
1712 | pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
|
---|
1713 | pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
|
---|
1714 | pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
|
---|
1715 | pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
|
---|
1716 | pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
|
---|
1717 | pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
|
---|
1718 | pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
|
---|
1719 | pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
|
---|
1720 | pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
|
---|
1721 | pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
|
---|
1722 | pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
|
---|
1723 | pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
|
---|
1724 | pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
|
---|
1725 |
|
---|
1726 | pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
|
---|
1727 | pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
|
---|
1728 | pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
|
---|
1729 | pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
|
---|
1730 | pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
|
---|
1731 | pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
|
---|
1732 | pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
|
---|
1733 | pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
|
---|
1734 | pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
|
---|
1735 | pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
|
---|
1736 | pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
|
---|
1737 | pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
|
---|
1738 | pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
|
---|
1739 | pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
|
---|
1740 | }
|
---|
1741 | }
|
---|
1742 | if (cStdMax >= 2 && iVerbosity)
|
---|
1743 | {
|
---|
1744 | /** @todo */
|
---|
1745 | }
|
---|
1746 |
|
---|
1747 | /*
|
---|
1748 | * Extended.
|
---|
1749 | * Implemented after AMD specs.
|
---|
1750 | */
|
---|
1751 | unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
|
---|
1752 |
|
---|
1753 | pHlp->pfnPrintf(pHlp,
|
---|
1754 | "\n"
|
---|
1755 | " RAW Extended CPUIDs\n"
|
---|
1756 | " Function eax ebx ecx edx\n");
|
---|
1757 | for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
|
---|
1758 | {
|
---|
1759 | Guest = pVM->cpum.s.aGuestCpuIdExt[i];
|
---|
1760 | ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
1761 |
|
---|
1762 | pHlp->pfnPrintf(pHlp,
|
---|
1763 | "Gst: %08x %08x %08x %08x %08x%s\n"
|
---|
1764 | "Hst: %08x %08x %08x %08x\n",
|
---|
1765 | 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
|
---|
1766 | i <= cExtMax ? "" : "*",
|
---|
1767 | Host.eax, Host.ebx, Host.ecx, Host.edx);
|
---|
1768 | }
|
---|
1769 |
|
---|
1770 | /*
|
---|
1771 | * Understandable output
|
---|
1772 | */
|
---|
1773 | if (iVerbosity)
|
---|
1774 | {
|
---|
1775 | Guest = pVM->cpum.s.aGuestCpuIdExt[0];
|
---|
1776 | pHlp->pfnPrintf(pHlp,
|
---|
1777 | "Ext Name: %.4s%.4s%.4s\n"
|
---|
1778 | "Ext Supports: 0x80000000-%#010x\n",
|
---|
1779 | &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
|
---|
1780 | }
|
---|
1781 |
|
---|
1782 | if (iVerbosity && cExtMax >= 1)
|
---|
1783 | {
|
---|
1784 | Guest = pVM->cpum.s.aGuestCpuIdExt[1];
|
---|
1785 | uint32_t uEAX = Guest.eax;
|
---|
1786 | pHlp->pfnPrintf(pHlp,
|
---|
1787 | "Family: %d \tExtended: %d \tEffective: %d\n"
|
---|
1788 | "Model: %d \tExtended: %d \tEffective: %d\n"
|
---|
1789 | "Stepping: %d\n"
|
---|
1790 | "Brand ID: %#05x\n",
|
---|
1791 | (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
|
---|
1792 | (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
|
---|
1793 | ASMGetCpuStepping(uEAX),
|
---|
1794 | Guest.ebx & 0xfff);
|
---|
1795 |
|
---|
1796 | if (iVerbosity == 1)
|
---|
1797 | {
|
---|
1798 | uint32_t uEDX = Guest.edx;
|
---|
1799 | pHlp->pfnPrintf(pHlp, "Features EDX: ");
|
---|
1800 | if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
|
---|
1801 | if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
|
---|
1802 | if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
|
---|
1803 | if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
|
---|
1804 | if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
|
---|
1805 | if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
|
---|
1806 | if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
|
---|
1807 | if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
|
---|
1808 | if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
|
---|
1809 | if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
|
---|
1810 | if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
|
---|
1811 | if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
|
---|
1812 | if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
|
---|
1813 | if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
|
---|
1814 | if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
|
---|
1815 | if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
|
---|
1816 | if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
|
---|
1817 | if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
|
---|
1818 | if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
|
---|
1819 | if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
|
---|
1820 | if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
|
---|
1821 | if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
|
---|
1822 | if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
|
---|
1823 | if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
|
---|
1824 | if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
|
---|
1825 | if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
|
---|
1826 | if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
|
---|
1827 | if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
|
---|
1828 | if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
|
---|
1829 | if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
|
---|
1830 | if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
|
---|
1831 | if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
|
---|
1832 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
1833 |
|
---|
1834 | uint32_t uECX = Guest.ecx;
|
---|
1835 | pHlp->pfnPrintf(pHlp, "Features ECX: ");
|
---|
1836 | if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
|
---|
1837 | if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
|
---|
1838 | if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
|
---|
1839 | if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
|
---|
1840 | if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
|
---|
1841 | if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
|
---|
1842 | if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
|
---|
1843 | if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
|
---|
1844 | if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
|
---|
1845 | if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
|
---|
1846 | if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
|
---|
1847 | if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
|
---|
1848 | if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
|
---|
1849 | if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
|
---|
1850 | for (unsigned iBit = 5; iBit < 32; iBit++)
|
---|
1851 | if (uECX & RT_BIT(iBit))
|
---|
1852 | pHlp->pfnPrintf(pHlp, " %d", iBit);
|
---|
1853 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
1854 | }
|
---|
1855 | else
|
---|
1856 | {
|
---|
1857 | ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
1858 |
|
---|
1859 | uint32_t uEdxGst = Guest.edx;
|
---|
1860 | uint32_t uEdxHst = Host.edx;
|
---|
1861 | pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
|
---|
1862 | pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
|
---|
1863 | pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
|
---|
1864 | pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
|
---|
1865 | pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
|
---|
1866 | pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
|
---|
1867 | pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
|
---|
1868 | pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
|
---|
1869 | pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
|
---|
1870 | pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
|
---|
1871 | pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
|
---|
1872 | pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
|
---|
1873 | pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
|
---|
1874 | pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
|
---|
1875 | pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
|
---|
1876 | pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
|
---|
1877 | pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
|
---|
1878 | pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
|
---|
1879 | pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
|
---|
1880 | pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
|
---|
1881 | pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
|
---|
1882 | pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
|
---|
1883 | pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
|
---|
1884 | pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
|
---|
1885 | pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
|
---|
1886 | pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
|
---|
1887 | pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
|
---|
1888 | pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
|
---|
1889 | pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
|
---|
1890 | pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
|
---|
1891 | pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
|
---|
1892 | pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
|
---|
1893 | pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
|
---|
1894 |
|
---|
1895 | uint32_t uEcxGst = Guest.ecx;
|
---|
1896 | uint32_t uEcxHst = Host.ecx;
|
---|
1897 | pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
|
---|
1898 | pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
|
---|
1899 | pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
|
---|
1900 | pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
|
---|
1901 | pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
|
---|
1902 | pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
|
---|
1903 | pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
|
---|
1904 | pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
|
---|
1905 | pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
|
---|
1906 | pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
|
---|
1907 | pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
|
---|
1908 | pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
|
---|
1909 | pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
|
---|
1910 | pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
|
---|
1911 | pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
|
---|
1912 | }
|
---|
1913 | }
|
---|
1914 |
|
---|
1915 | if (iVerbosity && cExtMax >= 2)
|
---|
1916 | {
|
---|
1917 | char szString[4*4*3+1] = {0};
|
---|
1918 | uint32_t *pu32 = (uint32_t *)szString;
|
---|
1919 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
|
---|
1920 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
|
---|
1921 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
|
---|
1922 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
|
---|
1923 | if (cExtMax >= 3)
|
---|
1924 | {
|
---|
1925 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
|
---|
1926 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
|
---|
1927 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
|
---|
1928 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
|
---|
1929 | }
|
---|
1930 | if (cExtMax >= 4)
|
---|
1931 | {
|
---|
1932 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
|
---|
1933 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
|
---|
1934 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
|
---|
1935 | *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
|
---|
1936 | }
|
---|
1937 | pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
|
---|
1938 | }
|
---|
1939 |
|
---|
1940 | if (iVerbosity && cExtMax >= 5)
|
---|
1941 | {
|
---|
1942 | uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
|
---|
1943 | uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
|
---|
1944 | uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
|
---|
1945 | uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
|
---|
1946 | char sz1[32];
|
---|
1947 | char sz2[32];
|
---|
1948 |
|
---|
1949 | pHlp->pfnPrintf(pHlp,
|
---|
1950 | "TLB 2/4M Instr/Uni: %s %3d entries\n"
|
---|
1951 | "TLB 2/4M Data: %s %3d entries\n",
|
---|
1952 | getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
|
---|
1953 | getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
|
---|
1954 | pHlp->pfnPrintf(pHlp,
|
---|
1955 | "TLB 4K Instr/Uni: %s %3d entries\n"
|
---|
1956 | "TLB 4K Data: %s %3d entries\n",
|
---|
1957 | getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
|
---|
1958 | getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
|
---|
1959 | pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
|
---|
1960 | "L1 Instr Cache Lines Per Tag: %d\n"
|
---|
1961 | "L1 Instr Cache Associativity: %s\n"
|
---|
1962 | "L1 Instr Cache Size: %d KB\n",
|
---|
1963 | (uEDX >> 0) & 0xff,
|
---|
1964 | (uEDX >> 8) & 0xff,
|
---|
1965 | getCacheAss((uEDX >> 16) & 0xff, sz1),
|
---|
1966 | (uEDX >> 24) & 0xff);
|
---|
1967 | pHlp->pfnPrintf(pHlp,
|
---|
1968 | "L1 Data Cache Line Size: %d bytes\n"
|
---|
1969 | "L1 Data Cache Lines Per Tag: %d\n"
|
---|
1970 | "L1 Data Cache Associativity: %s\n"
|
---|
1971 | "L1 Data Cache Size: %d KB\n",
|
---|
1972 | (uECX >> 0) & 0xff,
|
---|
1973 | (uECX >> 8) & 0xff,
|
---|
1974 | getCacheAss((uECX >> 16) & 0xff, sz1),
|
---|
1975 | (uECX >> 24) & 0xff);
|
---|
1976 | }
|
---|
1977 |
|
---|
1978 | if (iVerbosity && cExtMax >= 6)
|
---|
1979 | {
|
---|
1980 | uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
|
---|
1981 | uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
|
---|
1982 | uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
|
---|
1983 |
|
---|
1984 | pHlp->pfnPrintf(pHlp,
|
---|
1985 | "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
|
---|
1986 | "L2 TLB 2/4M Data: %s %4d entries\n",
|
---|
1987 | getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
|
---|
1988 | getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
|
---|
1989 | pHlp->pfnPrintf(pHlp,
|
---|
1990 | "L2 TLB 4K Instr/Uni: %s %4d entries\n"
|
---|
1991 | "L2 TLB 4K Data: %s %4d entries\n",
|
---|
1992 | getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
|
---|
1993 | getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
|
---|
1994 | pHlp->pfnPrintf(pHlp,
|
---|
1995 | "L2 Cache Line Size: %d bytes\n"
|
---|
1996 | "L2 Cache Lines Per Tag: %d\n"
|
---|
1997 | "L2 Cache Associativity: %s\n"
|
---|
1998 | "L2 Cache Size: %d KB\n",
|
---|
1999 | (uEDX >> 0) & 0xff,
|
---|
2000 | (uEDX >> 8) & 0xf,
|
---|
2001 | getL2CacheAss((uEDX >> 12) & 0xf),
|
---|
2002 | (uEDX >> 16) & 0xffff);
|
---|
2003 | }
|
---|
2004 |
|
---|
2005 | if (iVerbosity && cExtMax >= 7)
|
---|
2006 | {
|
---|
2007 | uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
|
---|
2008 |
|
---|
2009 | pHlp->pfnPrintf(pHlp, "APM Features: ");
|
---|
2010 | if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
|
---|
2011 | if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
|
---|
2012 | if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
|
---|
2013 | if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
|
---|
2014 | if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
|
---|
2015 | if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
|
---|
2016 | for (unsigned iBit = 6; iBit < 32; iBit++)
|
---|
2017 | if (uEDX & RT_BIT(iBit))
|
---|
2018 | pHlp->pfnPrintf(pHlp, " %d", iBit);
|
---|
2019 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
2020 | }
|
---|
2021 |
|
---|
2022 | if (iVerbosity && cExtMax >= 8)
|
---|
2023 | {
|
---|
2024 | uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
|
---|
2025 | uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
|
---|
2026 |
|
---|
2027 | pHlp->pfnPrintf(pHlp,
|
---|
2028 | "Physical Address Width: %d bits\n"
|
---|
2029 | "Virtual Address Width: %d bits\n",
|
---|
2030 | (uEAX >> 0) & 0xff,
|
---|
2031 | (uEAX >> 8) & 0xff);
|
---|
2032 | pHlp->pfnPrintf(pHlp,
|
---|
2033 | "Physical Core Count: %d\n",
|
---|
2034 | (uECX >> 0) & 0xff);
|
---|
2035 | }
|
---|
2036 |
|
---|
2037 |
|
---|
2038 | /*
|
---|
2039 | * Centaur.
|
---|
2040 | */
|
---|
2041 | unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
|
---|
2042 |
|
---|
2043 | pHlp->pfnPrintf(pHlp,
|
---|
2044 | "\n"
|
---|
2045 | " RAW Centaur CPUIDs\n"
|
---|
2046 | " Function eax ebx ecx edx\n");
|
---|
2047 | for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
|
---|
2048 | {
|
---|
2049 | Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
|
---|
2050 | ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
2051 |
|
---|
2052 | pHlp->pfnPrintf(pHlp,
|
---|
2053 | "Gst: %08x %08x %08x %08x %08x%s\n"
|
---|
2054 | "Hst: %08x %08x %08x %08x\n",
|
---|
2055 | 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
|
---|
2056 | i <= cCentaurMax ? "" : "*",
|
---|
2057 | Host.eax, Host.ebx, Host.ecx, Host.edx);
|
---|
2058 | }
|
---|
2059 |
|
---|
2060 | /*
|
---|
2061 | * Understandable output
|
---|
2062 | */
|
---|
2063 | if (iVerbosity)
|
---|
2064 | {
|
---|
2065 | Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
|
---|
2066 | pHlp->pfnPrintf(pHlp,
|
---|
2067 | "Centaur Supports: 0xc0000000-%#010x\n",
|
---|
2068 | Guest.eax);
|
---|
2069 | }
|
---|
2070 |
|
---|
2071 | if (iVerbosity && cCentaurMax >= 1)
|
---|
2072 | {
|
---|
2073 | ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
|
---|
2074 | uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
|
---|
2075 | uint32_t uEdxHst = Host.edx;
|
---|
2076 |
|
---|
2077 | if (iVerbosity == 1)
|
---|
2078 | {
|
---|
2079 | pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
|
---|
2080 | if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
|
---|
2081 | if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
|
---|
2082 | if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
|
---|
2083 | if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
|
---|
2084 | if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
|
---|
2085 | if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
|
---|
2086 | if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
|
---|
2087 | if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
|
---|
2088 | /* possibly indicating MM/HE and MM/HE-E on older chips... */
|
---|
2089 | if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
|
---|
2090 | if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
|
---|
2091 | if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
|
---|
2092 | if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
|
---|
2093 | if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
|
---|
2094 | if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
|
---|
2095 | for (unsigned iBit = 14; iBit < 32; iBit++)
|
---|
2096 | if (uEdxGst & RT_BIT(iBit))
|
---|
2097 | pHlp->pfnPrintf(pHlp, " %d", iBit);
|
---|
2098 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
2099 | }
|
---|
2100 | else
|
---|
2101 | {
|
---|
2102 | pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
|
---|
2103 | pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
|
---|
2104 | pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
|
---|
2105 | pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
|
---|
2106 | pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
|
---|
2107 | pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
|
---|
2108 | pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
|
---|
2109 | pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
|
---|
2110 | pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
|
---|
2111 | /* possibly indicating MM/HE and MM/HE-E on older chips... */
|
---|
2112 | pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
|
---|
2113 | pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
|
---|
2114 | pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
|
---|
2115 | pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
|
---|
2116 | pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
|
---|
2117 | pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
|
---|
2118 | for (unsigned iBit = 14; iBit < 32; iBit++)
|
---|
2119 | if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
|
---|
2120 | pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
|
---|
2121 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
2122 | }
|
---|
2123 | }
|
---|
2124 | }
|
---|
2125 |
|
---|
2126 |
|
---|
2127 | /**
|
---|
2128 | * Structure used when disassembling and instructions in DBGF.
|
---|
2129 | * This is used so the reader function can get the stuff it needs.
|
---|
2130 | */
|
---|
2131 | typedef struct CPUMDISASSTATE
|
---|
2132 | {
|
---|
2133 | /** Pointer to the CPU structure. */
|
---|
2134 | PDISCPUSTATE pCpu;
|
---|
2135 | /** The VM handle. */
|
---|
2136 | PVM pVM;
|
---|
2137 | /** Pointer to the first byte in the segemnt. */
|
---|
2138 | RTGCUINTPTR GCPtrSegBase;
|
---|
2139 | /** Pointer to the byte after the end of the segment. (might have wrapped!) */
|
---|
2140 | RTGCUINTPTR GCPtrSegEnd;
|
---|
2141 | /** The size of the segment minus 1. */
|
---|
2142 | RTGCUINTPTR cbSegLimit;
|
---|
2143 | /** Pointer to the current page - R3 Ptr. */
|
---|
2144 | void const *pvPageR3;
|
---|
2145 | /** Pointer to the current page - GC Ptr. */
|
---|
2146 | RTGCPTR pvPageGC;
|
---|
2147 | /** The lock information that PGMPhysReleasePageMappingLock needs. */
|
---|
2148 | PGMPAGEMAPLOCK PageMapLock;
|
---|
2149 | /** Whether the PageMapLock is valid or not. */
|
---|
2150 | bool fLocked;
|
---|
2151 | /** 64 bits mode or not. */
|
---|
2152 | bool f64Bits;
|
---|
2153 | } CPUMDISASSTATE, *PCPUMDISASSTATE;
|
---|
2154 |
|
---|
2155 |
|
---|
2156 | /**
|
---|
2157 | * Instruction reader.
|
---|
2158 | *
|
---|
2159 | * @returns VBox status code.
|
---|
2160 | * @param PtrSrc Address to read from.
|
---|
2161 | * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
|
---|
2162 | * @param pu8Dst Where to store the bytes.
|
---|
2163 | * @param cbRead Number of bytes to read.
|
---|
2164 | * @param uDisCpu Pointer to the disassembler cpu state.
|
---|
2165 | * In this context it's always pointer to the Core of a DBGFDISASSTATE.
|
---|
2166 | */
|
---|
2167 | static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
|
---|
2168 | {
|
---|
2169 | PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
|
---|
2170 | PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
|
---|
2171 | Assert(cbRead > 0);
|
---|
2172 | for (;;)
|
---|
2173 | {
|
---|
2174 | RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
|
---|
2175 |
|
---|
2176 | /* Need to update the page translation? */
|
---|
2177 | if ( !pState->pvPageR3
|
---|
2178 | || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
|
---|
2179 | {
|
---|
2180 | int rc = VINF_SUCCESS;
|
---|
2181 |
|
---|
2182 | /* translate the address */
|
---|
2183 | pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
|
---|
2184 | if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
|
---|
2185 | && !HWACCMIsEnabled(pState->pVM))
|
---|
2186 | {
|
---|
2187 | pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
|
---|
2188 | if (!pState->pvPageR3)
|
---|
2189 | rc = VERR_INVALID_POINTER;
|
---|
2190 | }
|
---|
2191 | else
|
---|
2192 | {
|
---|
2193 | /* Release mapping lock previously acquired. */
|
---|
2194 | if (pState->fLocked)
|
---|
2195 | PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
|
---|
2196 | rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
|
---|
2197 | pState->fLocked = RT_SUCCESS_NP(rc);
|
---|
2198 | }
|
---|
2199 | if (RT_FAILURE(rc))
|
---|
2200 | {
|
---|
2201 | pState->pvPageR3 = NULL;
|
---|
2202 | return rc;
|
---|
2203 | }
|
---|
2204 | }
|
---|
2205 |
|
---|
2206 | /* check the segemnt limit */
|
---|
2207 | if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
|
---|
2208 | return VERR_OUT_OF_SELECTOR_BOUNDS;
|
---|
2209 |
|
---|
2210 | /* calc how much we can read */
|
---|
2211 | uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
|
---|
2212 | if (!pState->f64Bits)
|
---|
2213 | {
|
---|
2214 | RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
|
---|
2215 | if (cb > cbSeg && cbSeg)
|
---|
2216 | cb = cbSeg;
|
---|
2217 | }
|
---|
2218 | if (cb > cbRead)
|
---|
2219 | cb = cbRead;
|
---|
2220 |
|
---|
2221 | /* read and advance */
|
---|
2222 | memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
|
---|
2223 | cbRead -= cb;
|
---|
2224 | if (!cbRead)
|
---|
2225 | return VINF_SUCCESS;
|
---|
2226 | pu8Dst += cb;
|
---|
2227 | PtrSrc += cb;
|
---|
2228 | }
|
---|
2229 | }
|
---|
2230 |
|
---|
2231 |
|
---|
2232 | /**
|
---|
2233 | * Disassemble an instruction and return the information in the provided structure.
|
---|
2234 | *
|
---|
2235 | * @returns VBox status code.
|
---|
2236 | * @param pVM VM Handle
|
---|
2237 | * @param pCtx CPU context
|
---|
2238 | * @param GCPtrPC Program counter (relative to CS) to disassemble from.
|
---|
2239 | * @param pCpu Disassembly state
|
---|
2240 | * @param pszPrefix String prefix for logging (debug only)
|
---|
2241 | *
|
---|
2242 | */
|
---|
2243 | VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
|
---|
2244 | {
|
---|
2245 | CPUMDISASSTATE State;
|
---|
2246 | int rc;
|
---|
2247 |
|
---|
2248 | const PGMMODE enmMode = PGMGetGuestMode(pVM);
|
---|
2249 | State.pCpu = pCpu;
|
---|
2250 | State.pvPageGC = 0;
|
---|
2251 | State.pvPageR3 = NULL;
|
---|
2252 | State.pVM = pVM;
|
---|
2253 | State.fLocked = false;
|
---|
2254 | State.f64Bits = false;
|
---|
2255 |
|
---|
2256 | /*
|
---|
2257 | * Get selector information.
|
---|
2258 | */
|
---|
2259 | if ( (pCtx->cr0 & X86_CR0_PE)
|
---|
2260 | && pCtx->eflags.Bits.u1VM == 0)
|
---|
2261 | {
|
---|
2262 | if (CPUMAreHiddenSelRegsValid(pVM))
|
---|
2263 | {
|
---|
2264 | State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
|
---|
2265 | State.GCPtrSegBase = pCtx->csHid.u64Base;
|
---|
2266 | State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
|
---|
2267 | State.cbSegLimit = pCtx->csHid.u32Limit;
|
---|
2268 | pCpu->mode = (State.f64Bits)
|
---|
2269 | ? CPUMODE_64BIT
|
---|
2270 | : pCtx->csHid.Attr.n.u1DefBig
|
---|
2271 | ? CPUMODE_32BIT
|
---|
2272 | : CPUMODE_16BIT;
|
---|
2273 | }
|
---|
2274 | else
|
---|
2275 | {
|
---|
2276 | SELMSELINFO SelInfo;
|
---|
2277 |
|
---|
2278 | rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
|
---|
2279 | if (!RT_SUCCESS(rc))
|
---|
2280 | {
|
---|
2281 | AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
|
---|
2282 | return rc;
|
---|
2283 | }
|
---|
2284 |
|
---|
2285 | /*
|
---|
2286 | * Validate the selector.
|
---|
2287 | */
|
---|
2288 | rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
|
---|
2289 | if (!RT_SUCCESS(rc))
|
---|
2290 | {
|
---|
2291 | AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
|
---|
2292 | return rc;
|
---|
2293 | }
|
---|
2294 | State.GCPtrSegBase = SelInfo.GCPtrBase;
|
---|
2295 | State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
|
---|
2296 | State.cbSegLimit = SelInfo.cbLimit;
|
---|
2297 | pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
|
---|
2298 | }
|
---|
2299 | }
|
---|
2300 | else
|
---|
2301 | {
|
---|
2302 | /* real or V86 mode */
|
---|
2303 | pCpu->mode = CPUMODE_16BIT;
|
---|
2304 | State.GCPtrSegBase = pCtx->cs * 16;
|
---|
2305 | State.GCPtrSegEnd = 0xFFFFFFFF;
|
---|
2306 | State.cbSegLimit = 0xFFFFFFFF;
|
---|
2307 | }
|
---|
2308 |
|
---|
2309 | /*
|
---|
2310 | * Disassemble the instruction.
|
---|
2311 | */
|
---|
2312 | pCpu->pfnReadBytes = cpumR3DisasInstrRead;
|
---|
2313 | pCpu->apvUserData[0] = &State;
|
---|
2314 |
|
---|
2315 | uint32_t cbInstr;
|
---|
2316 | #ifndef LOG_ENABLED
|
---|
2317 | rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
|
---|
2318 | if (RT_SUCCESS(rc))
|
---|
2319 | {
|
---|
2320 | #else
|
---|
2321 | char szOutput[160];
|
---|
2322 | rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
|
---|
2323 | if (RT_SUCCESS(rc))
|
---|
2324 | {
|
---|
2325 | /* log it */
|
---|
2326 | if (pszPrefix)
|
---|
2327 | Log(("%s: %s", pszPrefix, szOutput));
|
---|
2328 | else
|
---|
2329 | Log(("%s", szOutput));
|
---|
2330 | #endif
|
---|
2331 | rc = VINF_SUCCESS;
|
---|
2332 | }
|
---|
2333 | else
|
---|
2334 | Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
|
---|
2335 |
|
---|
2336 | /* Release mapping lock acquired in cpumR3DisasInstrRead. */
|
---|
2337 | if (State.fLocked)
|
---|
2338 | PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
|
---|
2339 |
|
---|
2340 | return rc;
|
---|
2341 | }
|
---|
2342 |
|
---|
2343 | #ifdef DEBUG
|
---|
2344 |
|
---|
2345 | /**
|
---|
2346 | * Disassemble an instruction and dump it to the log
|
---|
2347 | *
|
---|
2348 | * @returns VBox status code.
|
---|
2349 | * @param pVM VM Handle
|
---|
2350 | * @param pCtx CPU context
|
---|
2351 | * @param pc GC instruction pointer
|
---|
2352 | * @param pszPrefix String prefix for logging
|
---|
2353 | *
|
---|
2354 | * @deprecated Use DBGFR3DisasInstrCurrentLog().
|
---|
2355 | */
|
---|
2356 | VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
|
---|
2357 | {
|
---|
2358 | DISCPUSTATE Cpu;
|
---|
2359 | CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
|
---|
2360 | }
|
---|
2361 |
|
---|
2362 |
|
---|
2363 | /**
|
---|
2364 | * Disassemble an instruction and dump it to the log
|
---|
2365 | *
|
---|
2366 | * @returns VBox status code.
|
---|
2367 | * @param pVM VM Handle
|
---|
2368 | * @param pCtx CPU context
|
---|
2369 | * @param pc GC instruction pointer
|
---|
2370 | * @param pszPrefix String prefix for logging
|
---|
2371 | * @param nrInstructions
|
---|
2372 | *
|
---|
2373 | * @deprecated Create new DBGFR3Disas function to do this.
|
---|
2374 | */
|
---|
2375 | VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
|
---|
2376 | {
|
---|
2377 | for (int i = 0; i < nrInstructions; i++)
|
---|
2378 | {
|
---|
2379 | DISCPUSTATE cpu;
|
---|
2380 |
|
---|
2381 | CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
|
---|
2382 | pc += cpu.opsize;
|
---|
2383 | }
|
---|
2384 | }
|
---|
2385 |
|
---|
2386 |
|
---|
2387 | /**
|
---|
2388 | * Debug helper - Saves guest context on raw mode entry (for fatal dump)
|
---|
2389 | *
|
---|
2390 | * @internal
|
---|
2391 | */
|
---|
2392 | VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
|
---|
2393 | {
|
---|
2394 | /* @todo SMP */
|
---|
2395 | pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
|
---|
2396 | }
|
---|
2397 |
|
---|
2398 | #endif /* DEBUG */
|
---|
2399 |
|
---|
2400 | /**
|
---|
2401 | * API for controlling a few of the CPU features found in CR4.
|
---|
2402 | *
|
---|
2403 | * Currently only X86_CR4_TSD is accepted as input.
|
---|
2404 | *
|
---|
2405 | * @returns VBox status code.
|
---|
2406 | *
|
---|
2407 | * @param pVM The VM handle.
|
---|
2408 | * @param fOr The CR4 OR mask.
|
---|
2409 | * @param fAnd The CR4 AND mask.
|
---|
2410 | */
|
---|
2411 | VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
|
---|
2412 | {
|
---|
2413 | AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
|
---|
2414 | AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
|
---|
2415 |
|
---|
2416 | pVM->cpum.s.CR4.OrMask &= fAnd;
|
---|
2417 | pVM->cpum.s.CR4.OrMask |= fOr;
|
---|
2418 |
|
---|
2419 | return VINF_SUCCESS;
|
---|
2420 | }
|
---|
2421 |
|
---|