VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 17049

Last change on this file since 17049 was 17034, checked in by vboxsync, 16 years ago

CPUMR3Reset: AMD specs stats that TR.Attr is set to 16-bit busy (Intel docs says Present+R/W, which doesn't make a lot of sense as it would then be indicating LDT, unless they meant Present+R/W+Accessed which ends up as the same as AMD).
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File size: 110.3 KB
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1/* $Id: CPUM.cpp 17034 2009-02-23 21:05:34Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
125 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126
127 /*
128 * Setup any fixed pointers and offsets.
129 */
130 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
131 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
132
133 /* Hidden selector registers are invalid by default. */
134 pVM->cpum.s.fValidHiddenSelRegs = false;
135
136 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
137 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
138 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
139
140 /* Calculate the offset from CPUMCPU to CPUM. */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
144 Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
145 }
146
147 /*
148 * Check that the CPU supports the minimum features we require.
149 */
150 if (!ASMHasCpuId())
151 {
152 Log(("The CPU doesn't support CPUID!\n"));
153 return VERR_UNSUPPORTED_CPU;
154 }
155 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
156 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
157
158 /* Setup the CR4 AND and OR masks used in the switcher */
159 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
160 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
161 {
162 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
163 /* No FXSAVE implies no SSE */
164 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
165 pVM->cpum.s.CR4.OrMask = 0;
166 }
167 else
168 {
169 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
170 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
171 }
172
173 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
174 {
175 Log(("The CPU doesn't support MMX!\n"));
176 return VERR_UNSUPPORTED_CPU;
177 }
178 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
179 {
180 Log(("The CPU doesn't support TSC!\n"));
181 return VERR_UNSUPPORTED_CPU;
182 }
183 /* Bogus on AMD? */
184 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
185 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
186
187 /*
188 * Setup hypervisor startup values.
189 */
190
191 /*
192 * Register saved state data item.
193 */
194 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
195 NULL, cpumR3Save, NULL,
196 NULL, cpumR3Load, NULL);
197 if (RT_FAILURE(rc))
198 return rc;
199
200 /* Query the CPU manufacturer. */
201 uint32_t uEAX, uEBX, uECX, uEDX;
202 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203 if ( uEAX >= 1
204 && uEBX == X86_CPUID_VENDOR_AMD_EBX
205 && uECX == X86_CPUID_VENDOR_AMD_ECX
206 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
207 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
208 else if ( uEAX >= 1
209 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
210 && uECX == X86_CPUID_VENDOR_INTEL_ECX
211 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
212 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
213 else /** @todo Via */
214 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
215
216 /*
217 * Register info handlers.
218 */
219 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
220 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
221 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
222 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
223 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
224 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
225
226 /*
227 * Initialize the Guest CPU state.
228 */
229 rc = cpumR3CpuIdInit(pVM);
230 if (RT_FAILURE(rc))
231 return rc;
232 CPUMR3Reset(pVM);
233 return VINF_SUCCESS;
234}
235
236
237/**
238 * Initializes the per-VCPU CPUM.
239 *
240 * @returns VBox status code.
241 * @param pVM The VM to operate on.
242 */
243VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
244{
245 LogFlow(("CPUMR3InitCPU\n"));
246 return VINF_SUCCESS;
247}
248
249
250/**
251 * Initializes the emulated CPU's cpuid information.
252 *
253 * @returns VBox status code.
254 * @param pVM The VM to operate on.
255 */
256static int cpumR3CpuIdInit(PVM pVM)
257{
258 PCPUM pCPUM = &pVM->cpum.s;
259 uint32_t i;
260
261 /*
262 * Get the host CPUIDs.
263 */
264 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
265 ASMCpuId_Idx_ECX(i, 0,
266 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
267 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
268 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
269 ASMCpuId(0x80000000 + i,
270 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
271 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
272 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
273 ASMCpuId(0xc0000000 + i,
274 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
275 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
276
277
278 /*
279 * Only report features we can support.
280 */
281 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
282 | X86_CPUID_FEATURE_EDX_VME
283 | X86_CPUID_FEATURE_EDX_DE
284 | X86_CPUID_FEATURE_EDX_PSE
285 | X86_CPUID_FEATURE_EDX_TSC
286 | X86_CPUID_FEATURE_EDX_MSR
287 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
288 | X86_CPUID_FEATURE_EDX_MCE
289 | X86_CPUID_FEATURE_EDX_CX8
290 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
291 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
292 //| X86_CPUID_FEATURE_EDX_SEP
293 | X86_CPUID_FEATURE_EDX_MTRR
294 | X86_CPUID_FEATURE_EDX_PGE
295 | X86_CPUID_FEATURE_EDX_MCA
296 | X86_CPUID_FEATURE_EDX_CMOV
297 | X86_CPUID_FEATURE_EDX_PAT
298 | X86_CPUID_FEATURE_EDX_PSE36
299 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
300 | X86_CPUID_FEATURE_EDX_CLFSH
301 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
302 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
303 | X86_CPUID_FEATURE_EDX_MMX
304 | X86_CPUID_FEATURE_EDX_FXSR
305 | X86_CPUID_FEATURE_EDX_SSE
306 | X86_CPUID_FEATURE_EDX_SSE2
307 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
308 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
309 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
310 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
311 | 0;
312 pCPUM->aGuestCpuIdStd[1].ecx &= 0
313#ifdef VBOX_WITH_NEW_RECOMPILER
314 | X86_CPUID_FEATURE_ECX_SSE3
315#endif
316 | X86_CPUID_FEATURE_ECX_MONITOR
317 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
318 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
319 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
320 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
321 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
322 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
323 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
324 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
325 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
326 /* ECX Bit 21 - x2APIC support - not yet. */
327 // | X86_CPUID_FEATURE_ECX_X2APIC
328 /* ECX Bit 23 - POPCOUNT instruction. */
329 //| X86_CPUID_FEATURE_ECX_POPCOUNT
330 | 0;
331
332 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
333 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
334 | X86_CPUID_AMD_FEATURE_EDX_VME
335 | X86_CPUID_AMD_FEATURE_EDX_DE
336 | X86_CPUID_AMD_FEATURE_EDX_PSE
337 | X86_CPUID_AMD_FEATURE_EDX_TSC
338 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
339 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
340 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
341 | X86_CPUID_AMD_FEATURE_EDX_CX8
342 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
343 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
344 //| X86_CPUID_AMD_FEATURE_EDX_SEP
345 | X86_CPUID_AMD_FEATURE_EDX_MTRR
346 | X86_CPUID_AMD_FEATURE_EDX_PGE
347 | X86_CPUID_AMD_FEATURE_EDX_MCA
348 | X86_CPUID_AMD_FEATURE_EDX_CMOV
349 | X86_CPUID_AMD_FEATURE_EDX_PAT
350 | X86_CPUID_AMD_FEATURE_EDX_PSE36
351 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
352 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
353 | X86_CPUID_AMD_FEATURE_EDX_MMX
354 | X86_CPUID_AMD_FEATURE_EDX_FXSR
355 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
356 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
357 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
358 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
359 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
360 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
361 | 0;
362 pCPUM->aGuestCpuIdExt[1].ecx &= 0
363 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
364 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
365 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
366 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
367 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
368 //| X86_CPUID_AMD_FEATURE_ECX_ABM
369 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
370 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
371 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
372 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
373 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
374 //| X86_CPUID_AMD_FEATURE_ECX_WDT
375 | 0;
376
377 /*
378 * Hide HTT, multicode, SMP, whatever.
379 * (APIC-ID := 0 and #LogCpus := 0)
380 */
381 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
382
383 /* Cpuid 2:
384 * Intel: Cache and TLB information
385 * AMD: Reserved
386 * Safe to expose
387 */
388
389 /* Cpuid 3:
390 * Intel: EAX, EBX - reserved
391 * ECX, EDX - Processor Serial Number if available, otherwise reserved
392 * AMD: Reserved
393 * Safe to expose
394 */
395 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
396 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
397
398 /* Cpuid 4:
399 * Intel: Deterministic Cache Parameters Leaf
400 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
401 * AMD: Reserved
402 * Safe to expose, except for EAX:
403 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
404 * Bits 31-26: Maximum number of processor cores in this physical package**
405 */
406 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
407 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
408
409 /* Cpuid 5: Monitor/mwait Leaf
410 * Intel: ECX, EDX - reserved
411 * EAX, EBX - Smallest and largest monitor line size
412 * AMD: EDX - reserved
413 * EAX, EBX - Smallest and largest monitor line size
414 * ECX - extensions (ignored for now)
415 * Safe to expose
416 */
417 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
418 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
419
420 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
421
422 /*
423 * Determine the default.
424 *
425 * Intel returns values of the highest standard function, while AMD
426 * returns zeros. VIA on the other hand seems to returning nothing or
427 * perhaps some random garbage, we don't try to duplicate this behavior.
428 */
429 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
430 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
431 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
432
433 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
434 * Safe to pass on to the guest.
435 *
436 * Intel: 0x800000005 reserved
437 * 0x800000006 L2 cache information
438 * AMD: 0x800000005 L1 cache information
439 * 0x800000006 L2/L3 cache information
440 */
441
442 /* Cpuid 0x800000007:
443 * AMD: EAX, EBX, ECX - reserved
444 * EDX: Advanced Power Management Information
445 * Intel: Reserved
446 */
447 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
448 {
449 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
450
451 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
452
453 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
454 {
455 /* Only expose the TSC invariant capability bit to the guest. */
456 pCPUM->aGuestCpuIdExt[7].edx &= 0
457 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
458 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
459 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
460 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
461 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
462 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
463 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
464 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
465 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
466 | 0;
467 }
468 else
469 pCPUM->aGuestCpuIdExt[7].edx = 0;
470 }
471
472 /* Cpuid 0x800000008:
473 * AMD: EBX, EDX - reserved
474 * EAX: Virtual/Physical address Size
475 * ECX: Number of cores + APICIdCoreIdSize
476 * Intel: EAX: Virtual/Physical address Size
477 * EBX, ECX, EDX - reserved
478 */
479 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
480 {
481 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
482 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
483 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
484 * NC (0-7) Number of cores; 0 equals 1 core */
485 pCPUM->aGuestCpuIdExt[8].ecx = 0;
486 }
487
488 /*
489 * Limit it the number of entries and fill the remaining with the defaults.
490 *
491 * The limits are masking off stuff about power saving and similar, this
492 * is perhaps a bit crudely done as there is probably some relatively harmless
493 * info too in these leaves (like words about having a constant TSC).
494 */
495#if 0
496 /** @todo NT4 installation regression - investigate */
497 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
498 pCPUM->aGuestCpuIdStd[0].eax = 5;
499#else
500 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
501 pCPUM->aGuestCpuIdStd[0].eax = 2;
502#endif
503 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
504 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
505
506 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
507 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
508 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
509 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
510 : 0;
511 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
512 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
513
514 /*
515 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
516 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
517 * We currently don't support more than 1 processor.
518 */
519 pCPUM->aGuestCpuIdStd[4].eax = 0;
520
521 /*
522 * Centaur stuff (VIA).
523 *
524 * The important part here (we think) is to make sure the 0xc0000000
525 * function returns 0xc0000001. As for the features, we don't currently
526 * let on about any of those... 0xc0000002 seems to be some
527 * temperature/hz/++ stuff, include it as well (static).
528 */
529 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
530 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
531 {
532 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
533 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
534 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
535 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
536 i++)
537 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
538 }
539 else
540 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
541 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
542
543
544 /*
545 * Load CPUID overrides from configuration.
546 */
547 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
548 * Overloads the CPUID leaf values. */
549 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
550 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
551 for (i=0;; )
552 {
553 while (cElements-- > 0)
554 {
555 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
556 if (pNode)
557 {
558 uint32_t u32;
559 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
560 if (RT_SUCCESS(rc))
561 pCpuId->eax = u32;
562 else
563 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
564
565 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
566 if (RT_SUCCESS(rc))
567 pCpuId->ebx = u32;
568 else
569 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
570
571 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
572 if (RT_SUCCESS(rc))
573 pCpuId->ecx = u32;
574 else
575 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
576
577 rc = CFGMR3QueryU32(pNode, "edx", &u32);
578 if (RT_SUCCESS(rc))
579 pCpuId->edx = u32;
580 else
581 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
582 }
583 pCpuId++;
584 i++;
585 }
586
587 /* next */
588 if ((i & UINT32_C(0xc0000000)) == 0)
589 {
590 pCpuId = &pCPUM->aGuestCpuIdExt[0];
591 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
592 i = UINT32_C(0x80000000);
593 }
594 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
595 {
596 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
597 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
598 i = UINT32_C(0xc0000000);
599 }
600 else
601 break;
602 }
603
604 /* Check if PAE was explicitely enabled by the user. */
605 bool fEnable = false;
606 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
607 if (RT_SUCCESS(rc) && fEnable)
608 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
609
610 /*
611 * Log the cpuid and we're good.
612 */
613 RTCPUSET OnlineSet;
614 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
615 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
616 LogRel(("************************* CPUID dump ************************\n"));
617 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
618 LogRel(("\n"));
619 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
620 LogRel(("******************** End of CPUID dump **********************\n"));
621 return VINF_SUCCESS;
622}
623
624
625
626
627/**
628 * Applies relocations to data and code managed by this
629 * component. This function will be called at init and
630 * whenever the VMM need to relocate it self inside the GC.
631 *
632 * The CPUM will update the addresses used by the switcher.
633 *
634 * @param pVM The VM.
635 */
636VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
637{
638 LogFlow(("CPUMR3Relocate\n"));
639 /*
640 * Switcher pointers.
641 */
642 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
643 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
644}
645
646
647/**
648 * Terminates the CPUM.
649 *
650 * Termination means cleaning up and freeing all resources,
651 * the VM it self is at this point powered off or suspended.
652 *
653 * @returns VBox status code.
654 * @param pVM The VM to operate on.
655 */
656VMMR3DECL(int) CPUMR3Term(PVM pVM)
657{
658 CPUMR3TermCPU(pVM);
659 return 0;
660}
661
662
663/**
664 * Terminates the per-VCPU CPUM.
665 *
666 * Termination means cleaning up and freeing all resources,
667 * the VM it self is at this point powered off or suspended.
668 *
669 * @returns VBox status code.
670 * @param pVM The VM to operate on.
671 */
672VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
673{
674#ifdef VBOX_WITH_CRASHDUMP_MAGIC
675 for (unsigned i=0;i<pVM->cCPUs;i++)
676 {
677 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
678
679 memset(pVM->aCpus[i].cpum.s.aMagic, 0, sizeof(pVM->aCpus[i].cpum.s.aMagic));
680 pVM->aCpus[i].cpum.s.uMagic = 0;
681 pCtx->dr[5] = 0;
682 }
683#endif
684 return 0;
685}
686
687
688/**
689 * Resets the CPU.
690 *
691 * @returns VINF_SUCCESS.
692 * @param pVM The VM handle.
693 */
694VMMR3DECL(void) CPUMR3Reset(PVM pVM)
695{
696 /* @todo anything different for VCPU > 0? */
697 for (unsigned i=0;i<pVM->cCPUs;i++)
698 {
699 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
700
701 /*
702 * Initialize everything to ZERO first.
703 */
704 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
705 memset(pCtx, 0, sizeof(*pCtx));
706 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
707
708 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
709 pCtx->eip = 0x0000fff0;
710 pCtx->edx = 0x00000600; /* P6 processor */
711 pCtx->eflags.Bits.u1Reserved0 = 1;
712
713 pCtx->cs = 0xf000;
714 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
715 pCtx->csHid.u32Limit = 0x0000ffff;
716 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
717 pCtx->csHid.Attr.n.u1Present = 1;
718 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
719
720 pCtx->dsHid.u32Limit = 0x0000ffff;
721 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
722 pCtx->dsHid.Attr.n.u1Present = 1;
723 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
724
725 pCtx->esHid.u32Limit = 0x0000ffff;
726 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
727 pCtx->esHid.Attr.n.u1Present = 1;
728 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
729
730 pCtx->fsHid.u32Limit = 0x0000ffff;
731 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
732 pCtx->fsHid.Attr.n.u1Present = 1;
733 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
734
735 pCtx->gsHid.u32Limit = 0x0000ffff;
736 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
737 pCtx->gsHid.Attr.n.u1Present = 1;
738 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
739
740 pCtx->ssHid.u32Limit = 0x0000ffff;
741 pCtx->ssHid.Attr.n.u1Present = 1;
742 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
743 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
744
745 pCtx->idtr.cbIdt = 0xffff;
746 pCtx->gdtr.cbGdt = 0xffff;
747
748 pCtx->ldtrHid.u32Limit = 0xffff;
749 pCtx->ldtrHid.Attr.n.u1Present = 1;
750 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
751
752 pCtx->trHid.u32Limit = 0xffff;
753 pCtx->trHid.Attr.n.u1Present = 1;
754 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
755
756 pCtx->dr[6] = X86_DR6_INIT_VAL;
757 pCtx->dr[7] = X86_DR7_INIT_VAL;
758
759 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
760 pCtx->fpu.FCW = 0x37f;
761
762 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
763 pCtx->fpu.MXCSR = 0x1F80;
764
765 /* Init PAT MSR */
766 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
767
768 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
769 * The Intel docs don't mention it.
770 */
771 pCtx->msrEFER = 0;
772
773#ifdef VBOX_WITH_CRASHDUMP_MAGIC
774 /* Magic marker for searching in crash dumps. */
775 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
776 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
777 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
778#endif
779 }
780}
781
782
783/**
784 * Execute state save operation.
785 *
786 * @returns VBox status code.
787 * @param pVM VM Handle.
788 * @param pSSM SSM operation handle.
789 */
790static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
791{
792 /*
793 * Save.
794 */
795 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
796
797 SSMR3PutU32(pSSM, pVM->cCPUs);
798 for (unsigned i=0;i<pVM->cCPUs;i++)
799 {
800 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
801 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
802 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
803 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
804 }
805
806 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
807 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
808
809 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
810 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
811
812 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
813 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
814
815 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
816
817 /* Add the cpuid for checking that the cpu is unchanged. */
818 uint32_t au32CpuId[8] = {0};
819 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
820 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
821 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
822}
823
824
825/**
826 * Load a version 1.6 CPUMCTX structure.
827 *
828 * @returns VBox status code.
829 * @param pVM VM Handle.
830 * @param pCpumctx16 Version 1.6 CPUMCTX
831 */
832static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
833{
834#define CPUMCTX16_LOADREG(RegName) \
835 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
836
837#define CPUMCTX16_LOADDRXREG(RegName) \
838 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
839
840#define CPUMCTX16_LOADHIDREG(RegName) \
841 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
842 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
843 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
844
845#define CPUMCTX16_LOADSEGREG(RegName) \
846 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
847 CPUMCTX16_LOADHIDREG(RegName);
848
849 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
850
851 CPUMCTX16_LOADREG(rax);
852 CPUMCTX16_LOADREG(rbx);
853 CPUMCTX16_LOADREG(rcx);
854 CPUMCTX16_LOADREG(rdx);
855 CPUMCTX16_LOADREG(rdi);
856 CPUMCTX16_LOADREG(rsi);
857 CPUMCTX16_LOADREG(rbp);
858 CPUMCTX16_LOADREG(esp);
859 CPUMCTX16_LOADREG(rip);
860 CPUMCTX16_LOADREG(rflags);
861
862 CPUMCTX16_LOADSEGREG(cs);
863 CPUMCTX16_LOADSEGREG(ds);
864 CPUMCTX16_LOADSEGREG(es);
865 CPUMCTX16_LOADSEGREG(fs);
866 CPUMCTX16_LOADSEGREG(gs);
867 CPUMCTX16_LOADSEGREG(ss);
868
869 CPUMCTX16_LOADREG(r8);
870 CPUMCTX16_LOADREG(r9);
871 CPUMCTX16_LOADREG(r10);
872 CPUMCTX16_LOADREG(r11);
873 CPUMCTX16_LOADREG(r12);
874 CPUMCTX16_LOADREG(r13);
875 CPUMCTX16_LOADREG(r14);
876 CPUMCTX16_LOADREG(r15);
877
878 CPUMCTX16_LOADREG(cr0);
879 CPUMCTX16_LOADREG(cr2);
880 CPUMCTX16_LOADREG(cr3);
881 CPUMCTX16_LOADREG(cr4);
882
883 CPUMCTX16_LOADDRXREG(0);
884 CPUMCTX16_LOADDRXREG(1);
885 CPUMCTX16_LOADDRXREG(2);
886 CPUMCTX16_LOADDRXREG(3);
887 CPUMCTX16_LOADDRXREG(4);
888 CPUMCTX16_LOADDRXREG(5);
889 CPUMCTX16_LOADDRXREG(6);
890 CPUMCTX16_LOADDRXREG(7);
891
892 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
893 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
894 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
895 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
896
897 CPUMCTX16_LOADREG(ldtr);
898 CPUMCTX16_LOADREG(tr);
899
900 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
901
902 CPUMCTX16_LOADREG(msrEFER);
903 CPUMCTX16_LOADREG(msrSTAR);
904 CPUMCTX16_LOADREG(msrPAT);
905 CPUMCTX16_LOADREG(msrLSTAR);
906 CPUMCTX16_LOADREG(msrCSTAR);
907 CPUMCTX16_LOADREG(msrSFMASK);
908 CPUMCTX16_LOADREG(msrKERNELGSBASE);
909
910 CPUMCTX16_LOADHIDREG(ldtr);
911 CPUMCTX16_LOADHIDREG(tr);
912
913#undef CPUMCTX16_LOADSEGREG
914#undef CPUMCTX16_LOADHIDREG
915#undef CPUMCTX16_LOADDRXREG
916#undef CPUMCTX16_LOADREG
917}
918
919
920/**
921 * Execute state load operation.
922 *
923 * @returns VBox status code.
924 * @param pVM VM Handle.
925 * @param pSSM SSM operation handle.
926 * @param u32Version Data layout version.
927 */
928static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
929{
930 /*
931 * Validate version.
932 */
933 if ( u32Version != CPUM_SAVED_STATE_VERSION
934 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
935 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
936 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
937 {
938 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
939 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
940 }
941
942 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
943 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
944 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
945 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
946 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
947
948 /*
949 * Restore.
950 */
951 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
952 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
953 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
954 pVM->cpum.s.Hyper.cr3 = uCR3;
955 pVM->cpum.s.Hyper.esp = uESP;
956 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
957 {
958 CPUMCTX_VER1_6 cpumctx16;
959 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
960 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
961
962 /* Save the old cpumctx state into the new one. */
963 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
964
965 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
966 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
967 }
968 else
969 {
970 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
971 {
972 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
973 AssertRCReturn(rc, rc);
974 }
975
976 if ( !pVM->cCPUs
977 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
978 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
979 && pVM->cCPUs != 1))
980 {
981 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
982 return VERR_SSM_UNEXPECTED_DATA;
983 }
984
985 for (unsigned i=0;i<pVM->cCPUs;i++)
986 {
987 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
988 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
989 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
990 if (u32Version == CPUM_SAVED_STATE_VERSION)
991 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
992 }
993 }
994
995
996 uint32_t cElements;
997 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
998 /* Support old saved states with a smaller standard cpuid array. */
999 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1000 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1001 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1002
1003 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1004 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1005 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1006 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1007
1008 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1009 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1010 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1011 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1012
1013 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1014
1015 /*
1016 * Check that the basic cpuid id information is unchanged.
1017 * @todo we should check the 64 bits capabilities too!
1018 */
1019 uint32_t au32CpuId[8] = {0};
1020 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1021 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1022 uint32_t au32CpuIdSaved[8];
1023 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1024 if (RT_SUCCESS(rc))
1025 {
1026 /* Ignore CPU stepping. */
1027 au32CpuId[4] &= 0xfffffff0;
1028 au32CpuIdSaved[4] &= 0xfffffff0;
1029
1030 /* Ignore APIC ID (AMD specs). */
1031 au32CpuId[5] &= ~0xff000000;
1032 au32CpuIdSaved[5] &= ~0xff000000;
1033
1034 /* Ignore the number of Logical CPUs (AMD specs). */
1035 au32CpuId[5] &= ~0x00ff0000;
1036 au32CpuIdSaved[5] &= ~0x00ff0000;
1037
1038 /* do the compare */
1039 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1040 {
1041 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1042 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1043 "Saved=%.*Rhxs\n"
1044 "Real =%.*Rhxs\n",
1045 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1046 sizeof(au32CpuId), au32CpuId));
1047 else
1048 {
1049 LogRel(("cpumR3Load: CpuId mismatch!\n"
1050 "Saved=%.*Rhxs\n"
1051 "Real =%.*Rhxs\n",
1052 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1053 sizeof(au32CpuId), au32CpuId));
1054 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1055 }
1056 }
1057 }
1058
1059 return rc;
1060}
1061
1062
1063/**
1064 * Formats the EFLAGS value into mnemonics.
1065 *
1066 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1067 * @param efl The EFLAGS value.
1068 */
1069static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1070{
1071 /*
1072 * Format the flags.
1073 */
1074 static const struct
1075 {
1076 const char *pszSet; const char *pszClear; uint32_t fFlag;
1077 } s_aFlags[] =
1078 {
1079 { "vip",NULL, X86_EFL_VIP },
1080 { "vif",NULL, X86_EFL_VIF },
1081 { "ac", NULL, X86_EFL_AC },
1082 { "vm", NULL, X86_EFL_VM },
1083 { "rf", NULL, X86_EFL_RF },
1084 { "nt", NULL, X86_EFL_NT },
1085 { "ov", "nv", X86_EFL_OF },
1086 { "dn", "up", X86_EFL_DF },
1087 { "ei", "di", X86_EFL_IF },
1088 { "tf", NULL, X86_EFL_TF },
1089 { "nt", "pl", X86_EFL_SF },
1090 { "nz", "zr", X86_EFL_ZF },
1091 { "ac", "na", X86_EFL_AF },
1092 { "po", "pe", X86_EFL_PF },
1093 { "cy", "nc", X86_EFL_CF },
1094 };
1095 char *psz = pszEFlags;
1096 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1097 {
1098 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1099 if (pszAdd)
1100 {
1101 strcpy(psz, pszAdd);
1102 psz += strlen(pszAdd);
1103 *psz++ = ' ';
1104 }
1105 }
1106 psz[-1] = '\0';
1107}
1108
1109
1110/**
1111 * Formats a full register dump.
1112 *
1113 * @param pVM VM Handle.
1114 * @param pCtx The context to format.
1115 * @param pCtxCore The context core to format.
1116 * @param pHlp Output functions.
1117 * @param enmType The dump type.
1118 * @param pszPrefix Register name prefix.
1119 */
1120static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1121{
1122 /*
1123 * Format the EFLAGS.
1124 */
1125 uint32_t efl = pCtxCore->eflags.u32;
1126 char szEFlags[80];
1127 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1128
1129 /*
1130 * Format the registers.
1131 */
1132 switch (enmType)
1133 {
1134 case CPUMDUMPTYPE_TERSE:
1135 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1136 pHlp->pfnPrintf(pHlp,
1137 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1138 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1139 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1140 "%sr14=%016RX64 %sr15=%016RX64\n"
1141 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1142 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1143 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1144 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1145 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1146 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1147 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1148 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1149 else
1150 pHlp->pfnPrintf(pHlp,
1151 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1152 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1153 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1154 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1155 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1156 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1157 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1158 break;
1159
1160 case CPUMDUMPTYPE_DEFAULT:
1161 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1162 pHlp->pfnPrintf(pHlp,
1163 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1164 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1165 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1166 "%sr14=%016RX64 %sr15=%016RX64\n"
1167 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1168 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1169 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1170 ,
1171 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1172 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1173 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1174 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1175 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1176 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1177 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1178 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1179 else
1180 pHlp->pfnPrintf(pHlp,
1181 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1182 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1183 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1184 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1185 ,
1186 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1187 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1188 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1189 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1190 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1191 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1192 break;
1193
1194 case CPUMDUMPTYPE_VERBOSE:
1195 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1196 pHlp->pfnPrintf(pHlp,
1197 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1198 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1199 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1200 "%sr14=%016RX64 %sr15=%016RX64\n"
1201 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1202 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1203 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1204 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1205 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1206 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1207 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1208 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1209 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1210 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1211 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1212 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1213 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1214 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1215 ,
1216 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1217 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1218 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1219 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1220 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1221 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1222 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1223 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1224 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1225 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1226 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1227 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1228 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1229 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1230 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1231 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1232 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1233 else
1234 pHlp->pfnPrintf(pHlp,
1235 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1236 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1237 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1238 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1239 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1240 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1241 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1242 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1243 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1244 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1245 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1246 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1247 ,
1248 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1249 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1250 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1251 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1252 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1253 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1254 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1255 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1256 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1257 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1258 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1259 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1260
1261 pHlp->pfnPrintf(pHlp,
1262 "FPU:\n"
1263 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1264 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1265 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1266 ,
1267 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1268 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1269 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1270 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1271
1272 pHlp->pfnPrintf(pHlp,
1273 "MSR:\n"
1274 "%sEFER =%016RX64\n"
1275 "%sPAT =%016RX64\n"
1276 "%sSTAR =%016RX64\n"
1277 "%sCSTAR =%016RX64\n"
1278 "%sLSTAR =%016RX64\n"
1279 "%sSFMASK =%016RX64\n"
1280 "%sKERNELGSBASE =%016RX64\n",
1281 pszPrefix, pCtx->msrEFER,
1282 pszPrefix, pCtx->msrPAT,
1283 pszPrefix, pCtx->msrSTAR,
1284 pszPrefix, pCtx->msrCSTAR,
1285 pszPrefix, pCtx->msrLSTAR,
1286 pszPrefix, pCtx->msrSFMASK,
1287 pszPrefix, pCtx->msrKERNELGSBASE);
1288 break;
1289 }
1290}
1291
1292
1293/**
1294 * Display all cpu states and any other cpum info.
1295 *
1296 * @param pVM VM Handle.
1297 * @param pHlp The info helper functions.
1298 * @param pszArgs Arguments, ignored.
1299 */
1300static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1301{
1302 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1303 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1304 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1305 cpumR3InfoHost(pVM, pHlp, pszArgs);
1306}
1307
1308
1309/**
1310 * Parses the info argument.
1311 *
1312 * The argument starts with 'verbose', 'terse' or 'default' and then
1313 * continues with the comment string.
1314 *
1315 * @param pszArgs The pointer to the argument string.
1316 * @param penmType Where to store the dump type request.
1317 * @param ppszComment Where to store the pointer to the comment string.
1318 */
1319static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1320{
1321 if (!pszArgs)
1322 {
1323 *penmType = CPUMDUMPTYPE_DEFAULT;
1324 *ppszComment = "";
1325 }
1326 else
1327 {
1328 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1329 {
1330 pszArgs += 5;
1331 *penmType = CPUMDUMPTYPE_VERBOSE;
1332 }
1333 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1334 {
1335 pszArgs += 5;
1336 *penmType = CPUMDUMPTYPE_TERSE;
1337 }
1338 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1339 {
1340 pszArgs += 7;
1341 *penmType = CPUMDUMPTYPE_DEFAULT;
1342 }
1343 else
1344 *penmType = CPUMDUMPTYPE_DEFAULT;
1345 *ppszComment = RTStrStripL(pszArgs);
1346 }
1347}
1348
1349
1350/**
1351 * Display the guest cpu state.
1352 *
1353 * @param pVM VM Handle.
1354 * @param pHlp The info helper functions.
1355 * @param pszArgs Arguments, ignored.
1356 */
1357static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1358{
1359 CPUMDUMPTYPE enmType;
1360 const char *pszComment;
1361 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1362 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1363 /* @todo SMP */
1364 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
1365 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1366}
1367
1368
1369/**
1370 * Display the current guest instruction
1371 *
1372 * @param pVM VM Handle.
1373 * @param pHlp The info helper functions.
1374 * @param pszArgs Arguments, ignored.
1375 */
1376static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1377{
1378 char szInstruction[256];
1379 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1380 if (RT_SUCCESS(rc))
1381 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1382}
1383
1384
1385/**
1386 * Display the hypervisor cpu state.
1387 *
1388 * @param pVM VM Handle.
1389 * @param pHlp The info helper functions.
1390 * @param pszArgs Arguments, ignored.
1391 */
1392static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1393{
1394 CPUMDUMPTYPE enmType;
1395 const char *pszComment;
1396 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1397 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1398 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1399 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1400}
1401
1402
1403/**
1404 * Display the host cpu state.
1405 *
1406 * @param pVM VM Handle.
1407 * @param pHlp The info helper functions.
1408 * @param pszArgs Arguments, ignored.
1409 */
1410static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1411{
1412 CPUMDUMPTYPE enmType;
1413 const char *pszComment;
1414 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1415 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1416
1417 /*
1418 * Format the EFLAGS.
1419 */
1420 /* @todo SMP */
1421 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1422#if HC_ARCH_BITS == 32
1423 uint32_t efl = pCtx->eflags.u32;
1424#else
1425 uint64_t efl = pCtx->rflags;
1426#endif
1427 char szEFlags[80];
1428 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1429
1430 /*
1431 * Format the registers.
1432 */
1433#if HC_ARCH_BITS == 32
1434# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1435 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1436# endif
1437 {
1438 pHlp->pfnPrintf(pHlp,
1439 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1440 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1441 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1442 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1443 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1444 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1445 ,
1446 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1447 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1448 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1449 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1450 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1451 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1452 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1453 }
1454# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1455 else
1456# endif
1457#endif
1458#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1459 {
1460 pHlp->pfnPrintf(pHlp,
1461 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1462 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1463 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1464 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1465 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1466 "r14=%016RX64 r15=%016RX64\n"
1467 "iopl=%d %31s\n"
1468 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1469 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1470 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1471 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1472 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1473 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1474 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1475 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1476 ,
1477 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1478 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1479 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1480 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1481 pCtx->r11, pCtx->r12, pCtx->r13,
1482 pCtx->r14, pCtx->r15,
1483 X86_EFL_GET_IOPL(efl), szEFlags,
1484 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1485 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1486 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1487 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1488 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1489 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1490 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1491 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1492 }
1493#endif
1494}
1495
1496
1497/**
1498 * Get L1 cache / TLS associativity.
1499 */
1500static const char *getCacheAss(unsigned u, char *pszBuf)
1501{
1502 if (u == 0)
1503 return "res0 ";
1504 if (u == 1)
1505 return "direct";
1506 if (u >= 256)
1507 return "???";
1508
1509 RTStrPrintf(pszBuf, 16, "%d way", u);
1510 return pszBuf;
1511}
1512
1513
1514/**
1515 * Get L2 cache soociativity.
1516 */
1517const char *getL2CacheAss(unsigned u)
1518{
1519 switch (u)
1520 {
1521 case 0: return "off ";
1522 case 1: return "direct";
1523 case 2: return "2 way ";
1524 case 3: return "res3 ";
1525 case 4: return "4 way ";
1526 case 5: return "res5 ";
1527 case 6: return "8 way "; case 7: return "res7 ";
1528 case 8: return "16 way";
1529 case 9: return "res9 ";
1530 case 10: return "res10 ";
1531 case 11: return "res11 ";
1532 case 12: return "res12 ";
1533 case 13: return "res13 ";
1534 case 14: return "res14 ";
1535 case 15: return "fully ";
1536 default:
1537 return "????";
1538 }
1539}
1540
1541
1542/**
1543 * Display the guest CpuId leaves.
1544 *
1545 * @param pVM VM Handle.
1546 * @param pHlp The info helper functions.
1547 * @param pszArgs "terse", "default" or "verbose".
1548 */
1549static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1550{
1551 /*
1552 * Parse the argument.
1553 */
1554 unsigned iVerbosity = 1;
1555 if (pszArgs)
1556 {
1557 pszArgs = RTStrStripL(pszArgs);
1558 if (!strcmp(pszArgs, "terse"))
1559 iVerbosity--;
1560 else if (!strcmp(pszArgs, "verbose"))
1561 iVerbosity++;
1562 }
1563
1564 /*
1565 * Start cracking.
1566 */
1567 CPUMCPUID Host;
1568 CPUMCPUID Guest;
1569 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1570
1571 pHlp->pfnPrintf(pHlp,
1572 " RAW Standard CPUIDs\n"
1573 " Function eax ebx ecx edx\n");
1574 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1575 {
1576 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1577 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1578
1579 pHlp->pfnPrintf(pHlp,
1580 "Gst: %08x %08x %08x %08x %08x%s\n"
1581 "Hst: %08x %08x %08x %08x\n",
1582 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1583 i <= cStdMax ? "" : "*",
1584 Host.eax, Host.ebx, Host.ecx, Host.edx);
1585 }
1586
1587 /*
1588 * If verbose, decode it.
1589 */
1590 if (iVerbosity)
1591 {
1592 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1593 pHlp->pfnPrintf(pHlp,
1594 "Name: %.04s%.04s%.04s\n"
1595 "Supports: 0-%x\n",
1596 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1597 }
1598
1599 /*
1600 * Get Features.
1601 */
1602 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1603 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1604 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1605 if (cStdMax >= 1 && iVerbosity)
1606 {
1607 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1608 uint32_t uEAX = Guest.eax;
1609
1610 pHlp->pfnPrintf(pHlp,
1611 "Family: %d \tExtended: %d \tEffective: %d\n"
1612 "Model: %d \tExtended: %d \tEffective: %d\n"
1613 "Stepping: %d\n"
1614 "APIC ID: %#04x\n"
1615 "Logical CPUs: %d\n"
1616 "CLFLUSH Size: %d\n"
1617 "Brand ID: %#04x\n",
1618 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1619 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1620 ASMGetCpuStepping(uEAX),
1621 (Guest.ebx >> 24) & 0xff,
1622 (Guest.ebx >> 16) & 0xff,
1623 (Guest.ebx >> 8) & 0xff,
1624 (Guest.ebx >> 0) & 0xff);
1625 if (iVerbosity == 1)
1626 {
1627 uint32_t uEDX = Guest.edx;
1628 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1629 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1630 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1631 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1632 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1633 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1634 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1635 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1636 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1637 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1638 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1639 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1640 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1641 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1642 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1643 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1644 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1645 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1646 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1647 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1648 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1649 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1650 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1651 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1652 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1653 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1654 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1655 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1656 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1657 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1658 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1659 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1660 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1661 pHlp->pfnPrintf(pHlp, "\n");
1662
1663 uint32_t uECX = Guest.ecx;
1664 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1665 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1666 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1667 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1668 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1669 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1670 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1671 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1672 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1673 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1674 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1675 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1676 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1677 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1678 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1679 for (unsigned iBit = 14; iBit < 32; iBit++)
1680 if (uECX & RT_BIT(iBit))
1681 pHlp->pfnPrintf(pHlp, " %d", iBit);
1682 pHlp->pfnPrintf(pHlp, "\n");
1683 }
1684 else
1685 {
1686 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1687
1688 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1689 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1690 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1691 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1692
1693 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1694 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1695 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1696 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1697 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1698 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1699 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1700 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1701 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1702 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1703 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1704 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1705 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1706 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1707 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1708 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1709 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1710 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1711 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1712 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1713 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1714 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1715 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1716 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1717 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1718 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1719 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1720 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1721 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1722 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1723 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1724 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1725 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1726
1727 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1728 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1729 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1730 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1731 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1732 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1733 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1734 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1735 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1736 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1737 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1738 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1739 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1740 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1741 }
1742 }
1743 if (cStdMax >= 2 && iVerbosity)
1744 {
1745 /** @todo */
1746 }
1747
1748 /*
1749 * Extended.
1750 * Implemented after AMD specs.
1751 */
1752 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1753
1754 pHlp->pfnPrintf(pHlp,
1755 "\n"
1756 " RAW Extended CPUIDs\n"
1757 " Function eax ebx ecx edx\n");
1758 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1759 {
1760 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1761 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1762
1763 pHlp->pfnPrintf(pHlp,
1764 "Gst: %08x %08x %08x %08x %08x%s\n"
1765 "Hst: %08x %08x %08x %08x\n",
1766 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1767 i <= cExtMax ? "" : "*",
1768 Host.eax, Host.ebx, Host.ecx, Host.edx);
1769 }
1770
1771 /*
1772 * Understandable output
1773 */
1774 if (iVerbosity)
1775 {
1776 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1777 pHlp->pfnPrintf(pHlp,
1778 "Ext Name: %.4s%.4s%.4s\n"
1779 "Ext Supports: 0x80000000-%#010x\n",
1780 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1781 }
1782
1783 if (iVerbosity && cExtMax >= 1)
1784 {
1785 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1786 uint32_t uEAX = Guest.eax;
1787 pHlp->pfnPrintf(pHlp,
1788 "Family: %d \tExtended: %d \tEffective: %d\n"
1789 "Model: %d \tExtended: %d \tEffective: %d\n"
1790 "Stepping: %d\n"
1791 "Brand ID: %#05x\n",
1792 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1793 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1794 ASMGetCpuStepping(uEAX),
1795 Guest.ebx & 0xfff);
1796
1797 if (iVerbosity == 1)
1798 {
1799 uint32_t uEDX = Guest.edx;
1800 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1801 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1802 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1803 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1804 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1805 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1806 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1807 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1808 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1809 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1810 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1811 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1812 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1813 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1814 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1815 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1816 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1817 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1818 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1819 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1820 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1821 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1822 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1823 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1824 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1825 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1826 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1827 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1828 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1829 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1830 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1831 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1832 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1833 pHlp->pfnPrintf(pHlp, "\n");
1834
1835 uint32_t uECX = Guest.ecx;
1836 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1837 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1838 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1839 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1840 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1841 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1842 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1843 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1844 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1845 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1846 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1847 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1848 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1849 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1850 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1851 for (unsigned iBit = 5; iBit < 32; iBit++)
1852 if (uECX & RT_BIT(iBit))
1853 pHlp->pfnPrintf(pHlp, " %d", iBit);
1854 pHlp->pfnPrintf(pHlp, "\n");
1855 }
1856 else
1857 {
1858 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1859
1860 uint32_t uEdxGst = Guest.edx;
1861 uint32_t uEdxHst = Host.edx;
1862 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1863 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1864 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1865 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1866 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1867 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1868 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1869 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1870 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1871 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1872 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1873 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1874 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1875 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1876 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1877 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1878 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1879 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1880 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1881 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1882 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1883 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1884 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1885 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1886 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1887 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1888 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1889 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1890 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1891 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1892 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1893 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1894 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1895
1896 uint32_t uEcxGst = Guest.ecx;
1897 uint32_t uEcxHst = Host.ecx;
1898 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1899 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1900 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1901 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1902 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1903 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1904 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1905 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1906 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1907 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1908 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1909 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1910 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1911 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1912 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1913 }
1914 }
1915
1916 if (iVerbosity && cExtMax >= 2)
1917 {
1918 char szString[4*4*3+1] = {0};
1919 uint32_t *pu32 = (uint32_t *)szString;
1920 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1921 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1922 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1923 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1924 if (cExtMax >= 3)
1925 {
1926 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1927 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1928 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1929 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1930 }
1931 if (cExtMax >= 4)
1932 {
1933 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1934 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1935 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1936 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1937 }
1938 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1939 }
1940
1941 if (iVerbosity && cExtMax >= 5)
1942 {
1943 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1944 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1945 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1946 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1947 char sz1[32];
1948 char sz2[32];
1949
1950 pHlp->pfnPrintf(pHlp,
1951 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1952 "TLB 2/4M Data: %s %3d entries\n",
1953 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1954 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1955 pHlp->pfnPrintf(pHlp,
1956 "TLB 4K Instr/Uni: %s %3d entries\n"
1957 "TLB 4K Data: %s %3d entries\n",
1958 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1959 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1960 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1961 "L1 Instr Cache Lines Per Tag: %d\n"
1962 "L1 Instr Cache Associativity: %s\n"
1963 "L1 Instr Cache Size: %d KB\n",
1964 (uEDX >> 0) & 0xff,
1965 (uEDX >> 8) & 0xff,
1966 getCacheAss((uEDX >> 16) & 0xff, sz1),
1967 (uEDX >> 24) & 0xff);
1968 pHlp->pfnPrintf(pHlp,
1969 "L1 Data Cache Line Size: %d bytes\n"
1970 "L1 Data Cache Lines Per Tag: %d\n"
1971 "L1 Data Cache Associativity: %s\n"
1972 "L1 Data Cache Size: %d KB\n",
1973 (uECX >> 0) & 0xff,
1974 (uECX >> 8) & 0xff,
1975 getCacheAss((uECX >> 16) & 0xff, sz1),
1976 (uECX >> 24) & 0xff);
1977 }
1978
1979 if (iVerbosity && cExtMax >= 6)
1980 {
1981 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1982 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1983 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1984
1985 pHlp->pfnPrintf(pHlp,
1986 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1987 "L2 TLB 2/4M Data: %s %4d entries\n",
1988 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1989 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1990 pHlp->pfnPrintf(pHlp,
1991 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1992 "L2 TLB 4K Data: %s %4d entries\n",
1993 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1994 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1995 pHlp->pfnPrintf(pHlp,
1996 "L2 Cache Line Size: %d bytes\n"
1997 "L2 Cache Lines Per Tag: %d\n"
1998 "L2 Cache Associativity: %s\n"
1999 "L2 Cache Size: %d KB\n",
2000 (uEDX >> 0) & 0xff,
2001 (uEDX >> 8) & 0xf,
2002 getL2CacheAss((uEDX >> 12) & 0xf),
2003 (uEDX >> 16) & 0xffff);
2004 }
2005
2006 if (iVerbosity && cExtMax >= 7)
2007 {
2008 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2009
2010 pHlp->pfnPrintf(pHlp, "APM Features: ");
2011 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2012 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2013 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2014 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2015 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2016 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2017 for (unsigned iBit = 6; iBit < 32; iBit++)
2018 if (uEDX & RT_BIT(iBit))
2019 pHlp->pfnPrintf(pHlp, " %d", iBit);
2020 pHlp->pfnPrintf(pHlp, "\n");
2021 }
2022
2023 if (iVerbosity && cExtMax >= 8)
2024 {
2025 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2026 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2027
2028 pHlp->pfnPrintf(pHlp,
2029 "Physical Address Width: %d bits\n"
2030 "Virtual Address Width: %d bits\n",
2031 (uEAX >> 0) & 0xff,
2032 (uEAX >> 8) & 0xff);
2033 pHlp->pfnPrintf(pHlp,
2034 "Physical Core Count: %d\n",
2035 (uECX >> 0) & 0xff);
2036 }
2037
2038
2039 /*
2040 * Centaur.
2041 */
2042 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2043
2044 pHlp->pfnPrintf(pHlp,
2045 "\n"
2046 " RAW Centaur CPUIDs\n"
2047 " Function eax ebx ecx edx\n");
2048 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2049 {
2050 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2051 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2052
2053 pHlp->pfnPrintf(pHlp,
2054 "Gst: %08x %08x %08x %08x %08x%s\n"
2055 "Hst: %08x %08x %08x %08x\n",
2056 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2057 i <= cCentaurMax ? "" : "*",
2058 Host.eax, Host.ebx, Host.ecx, Host.edx);
2059 }
2060
2061 /*
2062 * Understandable output
2063 */
2064 if (iVerbosity)
2065 {
2066 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2067 pHlp->pfnPrintf(pHlp,
2068 "Centaur Supports: 0xc0000000-%#010x\n",
2069 Guest.eax);
2070 }
2071
2072 if (iVerbosity && cCentaurMax >= 1)
2073 {
2074 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2075 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2076 uint32_t uEdxHst = Host.edx;
2077
2078 if (iVerbosity == 1)
2079 {
2080 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2081 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2082 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2083 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2084 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2085 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2086 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2087 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2088 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2089 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2090 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2091 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2092 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2093 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2094 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2095 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2096 for (unsigned iBit = 14; iBit < 32; iBit++)
2097 if (uEdxGst & RT_BIT(iBit))
2098 pHlp->pfnPrintf(pHlp, " %d", iBit);
2099 pHlp->pfnPrintf(pHlp, "\n");
2100 }
2101 else
2102 {
2103 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2104 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2105 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2106 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2107 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2108 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2109 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2110 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2111 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2112 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2113 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2114 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2115 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2116 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2117 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2118 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2119 for (unsigned iBit = 14; iBit < 32; iBit++)
2120 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2121 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2122 pHlp->pfnPrintf(pHlp, "\n");
2123 }
2124 }
2125}
2126
2127
2128/**
2129 * Structure used when disassembling and instructions in DBGF.
2130 * This is used so the reader function can get the stuff it needs.
2131 */
2132typedef struct CPUMDISASSTATE
2133{
2134 /** Pointer to the CPU structure. */
2135 PDISCPUSTATE pCpu;
2136 /** The VM handle. */
2137 PVM pVM;
2138 /** Pointer to the first byte in the segemnt. */
2139 RTGCUINTPTR GCPtrSegBase;
2140 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2141 RTGCUINTPTR GCPtrSegEnd;
2142 /** The size of the segment minus 1. */
2143 RTGCUINTPTR cbSegLimit;
2144 /** Pointer to the current page - R3 Ptr. */
2145 void const *pvPageR3;
2146 /** Pointer to the current page - GC Ptr. */
2147 RTGCPTR pvPageGC;
2148 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2149 PGMPAGEMAPLOCK PageMapLock;
2150 /** Whether the PageMapLock is valid or not. */
2151 bool fLocked;
2152 /** 64 bits mode or not. */
2153 bool f64Bits;
2154} CPUMDISASSTATE, *PCPUMDISASSTATE;
2155
2156
2157/**
2158 * Instruction reader.
2159 *
2160 * @returns VBox status code.
2161 * @param PtrSrc Address to read from.
2162 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2163 * @param pu8Dst Where to store the bytes.
2164 * @param cbRead Number of bytes to read.
2165 * @param uDisCpu Pointer to the disassembler cpu state.
2166 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2167 */
2168static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2169{
2170 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2171 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2172 Assert(cbRead > 0);
2173 for (;;)
2174 {
2175 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2176
2177 /* Need to update the page translation? */
2178 if ( !pState->pvPageR3
2179 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2180 {
2181 int rc = VINF_SUCCESS;
2182
2183 /* translate the address */
2184 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2185 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2186 && !HWACCMIsEnabled(pState->pVM))
2187 {
2188 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2189 if (!pState->pvPageR3)
2190 rc = VERR_INVALID_POINTER;
2191 }
2192 else
2193 {
2194 /* Release mapping lock previously acquired. */
2195 if (pState->fLocked)
2196 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2197 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2198 pState->fLocked = RT_SUCCESS_NP(rc);
2199 }
2200 if (RT_FAILURE(rc))
2201 {
2202 pState->pvPageR3 = NULL;
2203 return rc;
2204 }
2205 }
2206
2207 /* check the segemnt limit */
2208 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2209 return VERR_OUT_OF_SELECTOR_BOUNDS;
2210
2211 /* calc how much we can read */
2212 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2213 if (!pState->f64Bits)
2214 {
2215 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2216 if (cb > cbSeg && cbSeg)
2217 cb = cbSeg;
2218 }
2219 if (cb > cbRead)
2220 cb = cbRead;
2221
2222 /* read and advance */
2223 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2224 cbRead -= cb;
2225 if (!cbRead)
2226 return VINF_SUCCESS;
2227 pu8Dst += cb;
2228 PtrSrc += cb;
2229 }
2230}
2231
2232
2233/**
2234 * Disassemble an instruction and return the information in the provided structure.
2235 *
2236 * @returns VBox status code.
2237 * @param pVM VM Handle
2238 * @param pCtx CPU context
2239 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2240 * @param pCpu Disassembly state
2241 * @param pszPrefix String prefix for logging (debug only)
2242 *
2243 */
2244VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2245{
2246 CPUMDISASSTATE State;
2247 int rc;
2248
2249 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2250 State.pCpu = pCpu;
2251 State.pvPageGC = 0;
2252 State.pvPageR3 = NULL;
2253 State.pVM = pVM;
2254 State.fLocked = false;
2255 State.f64Bits = false;
2256
2257 /*
2258 * Get selector information.
2259 */
2260 if ( (pCtx->cr0 & X86_CR0_PE)
2261 && pCtx->eflags.Bits.u1VM == 0)
2262 {
2263 if (CPUMAreHiddenSelRegsValid(pVM))
2264 {
2265 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2266 State.GCPtrSegBase = pCtx->csHid.u64Base;
2267 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2268 State.cbSegLimit = pCtx->csHid.u32Limit;
2269 pCpu->mode = (State.f64Bits)
2270 ? CPUMODE_64BIT
2271 : pCtx->csHid.Attr.n.u1DefBig
2272 ? CPUMODE_32BIT
2273 : CPUMODE_16BIT;
2274 }
2275 else
2276 {
2277 SELMSELINFO SelInfo;
2278
2279 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2280 if (!RT_SUCCESS(rc))
2281 {
2282 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2283 return rc;
2284 }
2285
2286 /*
2287 * Validate the selector.
2288 */
2289 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2290 if (!RT_SUCCESS(rc))
2291 {
2292 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2293 return rc;
2294 }
2295 State.GCPtrSegBase = SelInfo.GCPtrBase;
2296 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2297 State.cbSegLimit = SelInfo.cbLimit;
2298 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2299 }
2300 }
2301 else
2302 {
2303 /* real or V86 mode */
2304 pCpu->mode = CPUMODE_16BIT;
2305 State.GCPtrSegBase = pCtx->cs * 16;
2306 State.GCPtrSegEnd = 0xFFFFFFFF;
2307 State.cbSegLimit = 0xFFFFFFFF;
2308 }
2309
2310 /*
2311 * Disassemble the instruction.
2312 */
2313 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2314 pCpu->apvUserData[0] = &State;
2315
2316 uint32_t cbInstr;
2317#ifndef LOG_ENABLED
2318 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2319 if (RT_SUCCESS(rc))
2320 {
2321#else
2322 char szOutput[160];
2323 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2324 if (RT_SUCCESS(rc))
2325 {
2326 /* log it */
2327 if (pszPrefix)
2328 Log(("%s: %s", pszPrefix, szOutput));
2329 else
2330 Log(("%s", szOutput));
2331#endif
2332 rc = VINF_SUCCESS;
2333 }
2334 else
2335 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2336
2337 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2338 if (State.fLocked)
2339 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2340
2341 return rc;
2342}
2343
2344#ifdef DEBUG
2345
2346/**
2347 * Disassemble an instruction and dump it to the log
2348 *
2349 * @returns VBox status code.
2350 * @param pVM VM Handle
2351 * @param pCtx CPU context
2352 * @param pc GC instruction pointer
2353 * @param pszPrefix String prefix for logging
2354 *
2355 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2356 */
2357VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2358{
2359 DISCPUSTATE Cpu;
2360 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2361}
2362
2363
2364/**
2365 * Disassemble an instruction and dump it to the log
2366 *
2367 * @returns VBox status code.
2368 * @param pVM VM Handle
2369 * @param pCtx CPU context
2370 * @param pc GC instruction pointer
2371 * @param pszPrefix String prefix for logging
2372 * @param nrInstructions
2373 *
2374 * @deprecated Create new DBGFR3Disas function to do this.
2375 */
2376VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2377{
2378 for (int i = 0; i < nrInstructions; i++)
2379 {
2380 DISCPUSTATE cpu;
2381
2382 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2383 pc += cpu.opsize;
2384 }
2385}
2386
2387
2388/**
2389 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2390 *
2391 * @internal
2392 */
2393VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2394{
2395 /* @todo SMP */
2396 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2397}
2398
2399#endif /* DEBUG */
2400
2401/**
2402 * API for controlling a few of the CPU features found in CR4.
2403 *
2404 * Currently only X86_CR4_TSD is accepted as input.
2405 *
2406 * @returns VBox status code.
2407 *
2408 * @param pVM The VM handle.
2409 * @param fOr The CR4 OR mask.
2410 * @param fAnd The CR4 AND mask.
2411 */
2412VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2413{
2414 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2415 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2416
2417 pVM->cpum.s.CR4.OrMask &= fAnd;
2418 pVM->cpum.s.CR4.OrMask |= fOr;
2419
2420 return VINF_SUCCESS;
2421}
2422
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