VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 19167

Last change on this file since 19167 was 19075, checked in by vboxsync, 16 years ago

CPUMGetGuestCpuIdStdRCPtr -> R3
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 113.1 KB
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1/* $Id: CPUM.cpp 19075 2009-04-21 13:11:03Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319#ifdef VBOX_WITH_NEW_RECOMPILER
320 | X86_CPUID_FEATURE_ECX_SSE3
321#endif
322 | X86_CPUID_FEATURE_ECX_MONITOR
323 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
324 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
325 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
326 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
327 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
328 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
329 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
330 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
331 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
332 /* ECX Bit 21 - x2APIC support - not yet. */
333 // | X86_CPUID_FEATURE_ECX_X2APIC
334 /* ECX Bit 23 - POPCOUNT instruction. */
335 //| X86_CPUID_FEATURE_ECX_POPCOUNT
336 | 0;
337
338 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
339 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
340 | X86_CPUID_AMD_FEATURE_EDX_VME
341 | X86_CPUID_AMD_FEATURE_EDX_DE
342 | X86_CPUID_AMD_FEATURE_EDX_PSE
343 | X86_CPUID_AMD_FEATURE_EDX_TSC
344 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
345 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
346 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
347 | X86_CPUID_AMD_FEATURE_EDX_CX8
348 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
349 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
350 //| X86_CPUID_AMD_FEATURE_EDX_SEP
351 | X86_CPUID_AMD_FEATURE_EDX_MTRR
352 | X86_CPUID_AMD_FEATURE_EDX_PGE
353 | X86_CPUID_AMD_FEATURE_EDX_MCA
354 | X86_CPUID_AMD_FEATURE_EDX_CMOV
355 | X86_CPUID_AMD_FEATURE_EDX_PAT
356 | X86_CPUID_AMD_FEATURE_EDX_PSE36
357 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
358 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
359 | X86_CPUID_AMD_FEATURE_EDX_MMX
360 | X86_CPUID_AMD_FEATURE_EDX_FXSR
361 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
362 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
363 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
364 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
367 | 0;
368 pCPUM->aGuestCpuIdExt[1].ecx &= 0
369 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
370 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
371 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
372 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
373 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
374 //| X86_CPUID_AMD_FEATURE_ECX_ABM
375 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
376 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
377 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
378 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
379 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
380 //| X86_CPUID_AMD_FEATURE_ECX_WDT
381 | 0;
382
383 /*
384 * Hide HTT, multicode, SMP, whatever.
385 * (APIC-ID := 0 and #LogCpus := 0)
386 */
387 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
388#ifdef VBOX_WITH_MULTI_CORE
389 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
390 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
391
392 if (pVM->cCPUs > 1)
393 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
394#endif
395
396 /* Cpuid 2:
397 * Intel: Cache and TLB information
398 * AMD: Reserved
399 * Safe to expose
400 */
401
402 /* Cpuid 3:
403 * Intel: EAX, EBX - reserved
404 * ECX, EDX - Processor Serial Number if available, otherwise reserved
405 * AMD: Reserved
406 * Safe to expose
407 */
408 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
409 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
410
411 /* Cpuid 4:
412 * Intel: Deterministic Cache Parameters Leaf
413 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
414 * AMD: Reserved
415 * Safe to expose, except for EAX:
416 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
417 * Bits 31-26: Maximum number of processor cores in this physical package**
418 * @Note These SMP values are constant regardless of ECX
419 */
420 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
421 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
422#ifdef VBOX_WITH_MULTI_CORE
423 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
424 {
425 /* One logical processor with possibly multiple cores. */
426 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
427 }
428#endif
429
430 /* Cpuid 5: Monitor/mwait Leaf
431 * Intel: ECX, EDX - reserved
432 * EAX, EBX - Smallest and largest monitor line size
433 * AMD: EDX - reserved
434 * EAX, EBX - Smallest and largest monitor line size
435 * ECX - extensions (ignored for now)
436 * Safe to expose
437 */
438 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
439 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
440
441 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
442
443 /*
444 * Determine the default.
445 *
446 * Intel returns values of the highest standard function, while AMD
447 * returns zeros. VIA on the other hand seems to returning nothing or
448 * perhaps some random garbage, we don't try to duplicate this behavior.
449 */
450 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
451 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
452 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
453
454 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
455 * Safe to pass on to the guest.
456 *
457 * Intel: 0x800000005 reserved
458 * 0x800000006 L2 cache information
459 * AMD: 0x800000005 L1 cache information
460 * 0x800000006 L2/L3 cache information
461 */
462
463 /* Cpuid 0x800000007:
464 * AMD: EAX, EBX, ECX - reserved
465 * EDX: Advanced Power Management Information
466 * Intel: Reserved
467 */
468 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
469 {
470 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
471
472 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
473
474 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
475 {
476 /* Only expose the TSC invariant capability bit to the guest. */
477 pCPUM->aGuestCpuIdExt[7].edx &= 0
478 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
479 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
480 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
481 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
482 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
483 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
484 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
485 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
486 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
487 | 0;
488 }
489 else
490 pCPUM->aGuestCpuIdExt[7].edx = 0;
491 }
492
493 /* Cpuid 0x800000008:
494 * AMD: EBX, EDX - reserved
495 * EAX: Virtual/Physical address Size
496 * ECX: Number of cores + APICIdCoreIdSize
497 * Intel: EAX: Virtual/Physical address Size
498 * EBX, ECX, EDX - reserved
499 */
500 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
501 {
502 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
503 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
504 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
505 * NC (0-7) Number of cores; 0 equals 1 core */
506 pCPUM->aGuestCpuIdExt[8].ecx = 0;
507#ifdef VBOX_WITH_MULTI_CORE
508 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
509 {
510
511 }
512#endif
513 }
514
515 /*
516 * Limit it the number of entries and fill the remaining with the defaults.
517 *
518 * The limits are masking off stuff about power saving and similar, this
519 * is perhaps a bit crudely done as there is probably some relatively harmless
520 * info too in these leaves (like words about having a constant TSC).
521 */
522#if 0
523 /** @todo NT4 installation regression - investigate */
524 /** Note from Intel manuals:
525 * CPUID leaves > 3 < 80000000 are visible only when
526 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
527 *
528 */
529 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
530 pCPUM->aGuestCpuIdStd[0].eax = 5;
531#else
532 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
533 pCPUM->aGuestCpuIdStd[0].eax = 2;
534#endif
535 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
536 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
537
538 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
539 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
540 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
541 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
542 : 0;
543 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
544 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
545
546 /*
547 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
548 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
549 * We currently don't support more than 1 processor.
550 */
551 pCPUM->aGuestCpuIdStd[4].eax = 0;
552
553 /*
554 * Centaur stuff (VIA).
555 *
556 * The important part here (we think) is to make sure the 0xc0000000
557 * function returns 0xc0000001. As for the features, we don't currently
558 * let on about any of those... 0xc0000002 seems to be some
559 * temperature/hz/++ stuff, include it as well (static).
560 */
561 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
562 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
563 {
564 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
565 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
566 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
567 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
568 i++)
569 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
570 }
571 else
572 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
573 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
574
575
576 /*
577 * Load CPUID overrides from configuration.
578 */
579 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
580 * Overloads the CPUID leaf values. */
581 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
582 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
583 for (i=0;; )
584 {
585 while (cElements-- > 0)
586 {
587 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
588 if (pNode)
589 {
590 uint32_t u32;
591 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
592 if (RT_SUCCESS(rc))
593 pCpuId->eax = u32;
594 else
595 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
596
597 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
598 if (RT_SUCCESS(rc))
599 pCpuId->ebx = u32;
600 else
601 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
602
603 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
604 if (RT_SUCCESS(rc))
605 pCpuId->ecx = u32;
606 else
607 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
608
609 rc = CFGMR3QueryU32(pNode, "edx", &u32);
610 if (RT_SUCCESS(rc))
611 pCpuId->edx = u32;
612 else
613 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
614 }
615 pCpuId++;
616 i++;
617 }
618
619 /* next */
620 if ((i & UINT32_C(0xc0000000)) == 0)
621 {
622 pCpuId = &pCPUM->aGuestCpuIdExt[0];
623 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
624 i = UINT32_C(0x80000000);
625 }
626 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
627 {
628 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
629 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
630 i = UINT32_C(0xc0000000);
631 }
632 else
633 break;
634 }
635
636 /* Check if PAE was explicitely enabled by the user. */
637 bool fEnable = false;
638 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
639 if (RT_SUCCESS(rc) && fEnable)
640 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
641
642 /*
643 * Log the cpuid and we're good.
644 */
645 RTCPUSET OnlineSet;
646 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
647 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
648 LogRel(("************************* CPUID dump ************************\n"));
649 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
650 LogRel(("\n"));
651 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
652 LogRel(("******************** End of CPUID dump **********************\n"));
653 return VINF_SUCCESS;
654}
655
656
657
658
659/**
660 * Applies relocations to data and code managed by this
661 * component. This function will be called at init and
662 * whenever the VMM need to relocate it self inside the GC.
663 *
664 * The CPUM will update the addresses used by the switcher.
665 *
666 * @param pVM The VM.
667 */
668VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
669{
670 LogFlow(("CPUMR3Relocate\n"));
671 for (unsigned i=0;i<pVM->cCPUs;i++)
672 {
673 PVMCPU pVCpu = &pVM->aCpus[i];
674 /*
675 * Switcher pointers.
676 */
677 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
678 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
679 }
680}
681
682
683/**
684 * Terminates the CPUM.
685 *
686 * Termination means cleaning up and freeing all resources,
687 * the VM it self is at this point powered off or suspended.
688 *
689 * @returns VBox status code.
690 * @param pVM The VM to operate on.
691 */
692VMMR3DECL(int) CPUMR3Term(PVM pVM)
693{
694 CPUMR3TermCPU(pVM);
695 return 0;
696}
697
698
699/**
700 * Terminates the per-VCPU CPUM.
701 *
702 * Termination means cleaning up and freeing all resources,
703 * the VM it self is at this point powered off or suspended.
704 *
705 * @returns VBox status code.
706 * @param pVM The VM to operate on.
707 */
708VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
709{
710#ifdef VBOX_WITH_CRASHDUMP_MAGIC
711 for (unsigned i=0;i<pVM->cCPUs;i++)
712 {
713 PVMCPU pVCpu = &pVM->aCpus[i];
714 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
715
716 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
717 pVCpu->cpum.s.uMagic = 0;
718 pCtx->dr[5] = 0;
719 }
720#endif
721 return 0;
722}
723
724
725/**
726 * Resets the CPU.
727 *
728 * @returns VINF_SUCCESS.
729 * @param pVM The VM handle.
730 */
731VMMR3DECL(void) CPUMR3Reset(PVM pVM)
732{
733 /* @todo anything different for VCPU > 0? */
734 for (unsigned i=0;i<pVM->cCPUs;i++)
735 {
736 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
737
738 /*
739 * Initialize everything to ZERO first.
740 */
741 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
742 memset(pCtx, 0, sizeof(*pCtx));
743 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
744
745 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
746 pCtx->eip = 0x0000fff0;
747 pCtx->edx = 0x00000600; /* P6 processor */
748 pCtx->eflags.Bits.u1Reserved0 = 1;
749
750 pCtx->cs = 0xf000;
751 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
752 pCtx->csHid.u32Limit = 0x0000ffff;
753 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
754 pCtx->csHid.Attr.n.u1Present = 1;
755 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
756
757 pCtx->dsHid.u32Limit = 0x0000ffff;
758 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
759 pCtx->dsHid.Attr.n.u1Present = 1;
760 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
761
762 pCtx->esHid.u32Limit = 0x0000ffff;
763 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
764 pCtx->esHid.Attr.n.u1Present = 1;
765 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
766
767 pCtx->fsHid.u32Limit = 0x0000ffff;
768 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
769 pCtx->fsHid.Attr.n.u1Present = 1;
770 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
771
772 pCtx->gsHid.u32Limit = 0x0000ffff;
773 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
774 pCtx->gsHid.Attr.n.u1Present = 1;
775 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
776
777 pCtx->ssHid.u32Limit = 0x0000ffff;
778 pCtx->ssHid.Attr.n.u1Present = 1;
779 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
780 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
781
782 pCtx->idtr.cbIdt = 0xffff;
783 pCtx->gdtr.cbGdt = 0xffff;
784
785 pCtx->ldtrHid.u32Limit = 0xffff;
786 pCtx->ldtrHid.Attr.n.u1Present = 1;
787 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
788
789 pCtx->trHid.u32Limit = 0xffff;
790 pCtx->trHid.Attr.n.u1Present = 1;
791 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
792
793 pCtx->dr[6] = X86_DR6_INIT_VAL;
794 pCtx->dr[7] = X86_DR7_INIT_VAL;
795
796 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
797 pCtx->fpu.FCW = 0x37f;
798
799 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
800 pCtx->fpu.MXCSR = 0x1F80;
801
802 /* Init PAT MSR */
803 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
804
805 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
806 * The Intel docs don't mention it.
807 */
808 pCtx->msrEFER = 0;
809
810#ifdef VBOX_WITH_CRASHDUMP_MAGIC
811 /* Magic marker for searching in crash dumps. */
812 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
813 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
814 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
815#endif
816 }
817}
818
819
820/**
821 * Execute state save operation.
822 *
823 * @returns VBox status code.
824 * @param pVM VM Handle.
825 * @param pSSM SSM operation handle.
826 */
827static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
828{
829 /*
830 * Save.
831 */
832 for (unsigned i=0;i<pVM->cCPUs;i++)
833 {
834 PVMCPU pVCpu = &pVM->aCpus[i];
835
836 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
837 }
838
839 SSMR3PutU32(pSSM, pVM->cCPUs);
840 for (unsigned i=0;i<pVM->cCPUs;i++)
841 {
842 PVMCPU pVCpu = &pVM->aCpus[i];
843
844 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
845 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
846 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
847 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
848 }
849
850 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
851 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
852
853 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
854 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
855
856 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
857 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
858
859 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
860
861 /* Add the cpuid for checking that the cpu is unchanged. */
862 uint32_t au32CpuId[8] = {0};
863 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
864 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
865 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
866}
867
868
869/**
870 * Load a version 1.6 CPUMCTX structure.
871 *
872 * @returns VBox status code.
873 * @param pVM VM Handle.
874 * @param pCpumctx16 Version 1.6 CPUMCTX
875 */
876static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
877{
878#define CPUMCTX16_LOADREG(RegName) \
879 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
880
881#define CPUMCTX16_LOADDRXREG(RegName) \
882 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
883
884#define CPUMCTX16_LOADHIDREG(RegName) \
885 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
886 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
887 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
888
889#define CPUMCTX16_LOADSEGREG(RegName) \
890 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
891 CPUMCTX16_LOADHIDREG(RegName);
892
893 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
894
895 CPUMCTX16_LOADREG(rax);
896 CPUMCTX16_LOADREG(rbx);
897 CPUMCTX16_LOADREG(rcx);
898 CPUMCTX16_LOADREG(rdx);
899 CPUMCTX16_LOADREG(rdi);
900 CPUMCTX16_LOADREG(rsi);
901 CPUMCTX16_LOADREG(rbp);
902 CPUMCTX16_LOADREG(esp);
903 CPUMCTX16_LOADREG(rip);
904 CPUMCTX16_LOADREG(rflags);
905
906 CPUMCTX16_LOADSEGREG(cs);
907 CPUMCTX16_LOADSEGREG(ds);
908 CPUMCTX16_LOADSEGREG(es);
909 CPUMCTX16_LOADSEGREG(fs);
910 CPUMCTX16_LOADSEGREG(gs);
911 CPUMCTX16_LOADSEGREG(ss);
912
913 CPUMCTX16_LOADREG(r8);
914 CPUMCTX16_LOADREG(r9);
915 CPUMCTX16_LOADREG(r10);
916 CPUMCTX16_LOADREG(r11);
917 CPUMCTX16_LOADREG(r12);
918 CPUMCTX16_LOADREG(r13);
919 CPUMCTX16_LOADREG(r14);
920 CPUMCTX16_LOADREG(r15);
921
922 CPUMCTX16_LOADREG(cr0);
923 CPUMCTX16_LOADREG(cr2);
924 CPUMCTX16_LOADREG(cr3);
925 CPUMCTX16_LOADREG(cr4);
926
927 CPUMCTX16_LOADDRXREG(0);
928 CPUMCTX16_LOADDRXREG(1);
929 CPUMCTX16_LOADDRXREG(2);
930 CPUMCTX16_LOADDRXREG(3);
931 CPUMCTX16_LOADDRXREG(4);
932 CPUMCTX16_LOADDRXREG(5);
933 CPUMCTX16_LOADDRXREG(6);
934 CPUMCTX16_LOADDRXREG(7);
935
936 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
937 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
938 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
939 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
940
941 CPUMCTX16_LOADREG(ldtr);
942 CPUMCTX16_LOADREG(tr);
943
944 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
945
946 CPUMCTX16_LOADREG(msrEFER);
947 CPUMCTX16_LOADREG(msrSTAR);
948 CPUMCTX16_LOADREG(msrPAT);
949 CPUMCTX16_LOADREG(msrLSTAR);
950 CPUMCTX16_LOADREG(msrCSTAR);
951 CPUMCTX16_LOADREG(msrSFMASK);
952 CPUMCTX16_LOADREG(msrKERNELGSBASE);
953
954 CPUMCTX16_LOADHIDREG(ldtr);
955 CPUMCTX16_LOADHIDREG(tr);
956
957#undef CPUMCTX16_LOADSEGREG
958#undef CPUMCTX16_LOADHIDREG
959#undef CPUMCTX16_LOADDRXREG
960#undef CPUMCTX16_LOADREG
961}
962
963
964/**
965 * Execute state load operation.
966 *
967 * @returns VBox status code.
968 * @param pVM VM Handle.
969 * @param pSSM SSM operation handle.
970 * @param u32Version Data layout version.
971 */
972static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
973{
974 /*
975 * Validate version.
976 */
977 if ( u32Version != CPUM_SAVED_STATE_VERSION
978 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
979 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
980 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
981 {
982 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
983 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
984 }
985
986 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
987 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
988 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
989 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
990 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
991
992 /*
993 * Restore.
994 */
995 for (unsigned i=0;i<pVM->cCPUs;i++)
996 {
997 PVMCPU pVCpu = &pVM->aCpus[i];
998 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
999 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1000
1001 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1002 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1003 pVCpu->cpum.s.Hyper.esp = uESP;
1004 }
1005
1006 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1007 {
1008 CPUMCTX_VER1_6 cpumctx16;
1009 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1010 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1011
1012 /* Save the old cpumctx state into the new one. */
1013 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1014
1015 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1016 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1017 }
1018 else
1019 {
1020 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1021 {
1022 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1023 AssertRCReturn(rc, rc);
1024 }
1025
1026 if ( !pVM->cCPUs
1027 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
1028 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1029 && pVM->cCPUs != 1))
1030 {
1031 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1032 return VERR_SSM_UNEXPECTED_DATA;
1033 }
1034
1035 for (unsigned i=0;i<pVM->cCPUs;i++)
1036 {
1037 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1038 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1039 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1040 if (u32Version == CPUM_SAVED_STATE_VERSION)
1041 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1042 }
1043 }
1044
1045
1046 uint32_t cElements;
1047 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1048 /* Support old saved states with a smaller standard cpuid array. */
1049 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1050 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1051 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1052
1053 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1054 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1055 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1056 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1057
1058 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1059 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1060 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1061 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1062
1063 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1064
1065 /*
1066 * Check that the basic cpuid id information is unchanged.
1067 * @todo we should check the 64 bits capabilities too!
1068 */
1069 uint32_t au32CpuId[8] = {0};
1070 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1071 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1072 uint32_t au32CpuIdSaved[8];
1073 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1074 if (RT_SUCCESS(rc))
1075 {
1076 /* Ignore CPU stepping. */
1077 au32CpuId[4] &= 0xfffffff0;
1078 au32CpuIdSaved[4] &= 0xfffffff0;
1079
1080 /* Ignore APIC ID (AMD specs). */
1081 au32CpuId[5] &= ~0xff000000;
1082 au32CpuIdSaved[5] &= ~0xff000000;
1083
1084 /* Ignore the number of Logical CPUs (AMD specs). */
1085 au32CpuId[5] &= ~0x00ff0000;
1086 au32CpuIdSaved[5] &= ~0x00ff0000;
1087
1088 /* do the compare */
1089 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1090 {
1091 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1092 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1093 "Saved=%.*Rhxs\n"
1094 "Real =%.*Rhxs\n",
1095 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1096 sizeof(au32CpuId), au32CpuId));
1097 else
1098 {
1099 LogRel(("cpumR3Load: CpuId mismatch!\n"
1100 "Saved=%.*Rhxs\n"
1101 "Real =%.*Rhxs\n",
1102 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1103 sizeof(au32CpuId), au32CpuId));
1104 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1105 }
1106 }
1107 }
1108
1109 return rc;
1110}
1111
1112
1113/**
1114 * Formats the EFLAGS value into mnemonics.
1115 *
1116 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1117 * @param efl The EFLAGS value.
1118 */
1119static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1120{
1121 /*
1122 * Format the flags.
1123 */
1124 static const struct
1125 {
1126 const char *pszSet; const char *pszClear; uint32_t fFlag;
1127 } s_aFlags[] =
1128 {
1129 { "vip",NULL, X86_EFL_VIP },
1130 { "vif",NULL, X86_EFL_VIF },
1131 { "ac", NULL, X86_EFL_AC },
1132 { "vm", NULL, X86_EFL_VM },
1133 { "rf", NULL, X86_EFL_RF },
1134 { "nt", NULL, X86_EFL_NT },
1135 { "ov", "nv", X86_EFL_OF },
1136 { "dn", "up", X86_EFL_DF },
1137 { "ei", "di", X86_EFL_IF },
1138 { "tf", NULL, X86_EFL_TF },
1139 { "nt", "pl", X86_EFL_SF },
1140 { "nz", "zr", X86_EFL_ZF },
1141 { "ac", "na", X86_EFL_AF },
1142 { "po", "pe", X86_EFL_PF },
1143 { "cy", "nc", X86_EFL_CF },
1144 };
1145 char *psz = pszEFlags;
1146 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1147 {
1148 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1149 if (pszAdd)
1150 {
1151 strcpy(psz, pszAdd);
1152 psz += strlen(pszAdd);
1153 *psz++ = ' ';
1154 }
1155 }
1156 psz[-1] = '\0';
1157}
1158
1159
1160/**
1161 * Formats a full register dump.
1162 *
1163 * @param pVM VM Handle.
1164 * @param pCtx The context to format.
1165 * @param pCtxCore The context core to format.
1166 * @param pHlp Output functions.
1167 * @param enmType The dump type.
1168 * @param pszPrefix Register name prefix.
1169 */
1170static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1171{
1172 /*
1173 * Format the EFLAGS.
1174 */
1175 uint32_t efl = pCtxCore->eflags.u32;
1176 char szEFlags[80];
1177 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1178
1179 /*
1180 * Format the registers.
1181 */
1182 switch (enmType)
1183 {
1184 case CPUMDUMPTYPE_TERSE:
1185 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1186 pHlp->pfnPrintf(pHlp,
1187 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1188 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1189 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1190 "%sr14=%016RX64 %sr15=%016RX64\n"
1191 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1192 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1193 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1194 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1195 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1196 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1197 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1198 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1199 else
1200 pHlp->pfnPrintf(pHlp,
1201 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1202 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1203 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1204 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1205 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1206 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1207 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1208 break;
1209
1210 case CPUMDUMPTYPE_DEFAULT:
1211 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1212 pHlp->pfnPrintf(pHlp,
1213 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1214 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1215 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1216 "%sr14=%016RX64 %sr15=%016RX64\n"
1217 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1218 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1219 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1220 ,
1221 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1222 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1223 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1224 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1225 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1226 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1227 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1228 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1229 else
1230 pHlp->pfnPrintf(pHlp,
1231 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1232 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1233 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1234 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1235 ,
1236 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1237 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1238 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1239 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1240 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1241 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1242 break;
1243
1244 case CPUMDUMPTYPE_VERBOSE:
1245 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1246 pHlp->pfnPrintf(pHlp,
1247 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1248 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1249 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1250 "%sr14=%016RX64 %sr15=%016RX64\n"
1251 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1252 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1253 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1254 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1255 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1256 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1257 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1258 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1259 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1260 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1261 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1262 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1263 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1264 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1265 ,
1266 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1267 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1268 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1269 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1270 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1271 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1272 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1273 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1274 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1275 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1276 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1277 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1278 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1279 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1280 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1281 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1282 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1283 else
1284 pHlp->pfnPrintf(pHlp,
1285 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1286 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1287 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1288 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1289 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1290 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1291 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1292 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1293 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1294 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1295 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1296 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1297 ,
1298 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1299 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1300 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1301 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1302 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1303 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1304 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1305 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1306 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1307 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1308 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1309 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1310
1311 pHlp->pfnPrintf(pHlp,
1312 "FPU:\n"
1313 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1314 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1315 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1316 ,
1317 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1318 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1319 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1320 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1321
1322 pHlp->pfnPrintf(pHlp,
1323 "MSR:\n"
1324 "%sEFER =%016RX64\n"
1325 "%sPAT =%016RX64\n"
1326 "%sSTAR =%016RX64\n"
1327 "%sCSTAR =%016RX64\n"
1328 "%sLSTAR =%016RX64\n"
1329 "%sSFMASK =%016RX64\n"
1330 "%sKERNELGSBASE =%016RX64\n",
1331 pszPrefix, pCtx->msrEFER,
1332 pszPrefix, pCtx->msrPAT,
1333 pszPrefix, pCtx->msrSTAR,
1334 pszPrefix, pCtx->msrCSTAR,
1335 pszPrefix, pCtx->msrLSTAR,
1336 pszPrefix, pCtx->msrSFMASK,
1337 pszPrefix, pCtx->msrKERNELGSBASE);
1338 break;
1339 }
1340}
1341
1342
1343/**
1344 * Display all cpu states and any other cpum info.
1345 *
1346 * @param pVM VM Handle.
1347 * @param pHlp The info helper functions.
1348 * @param pszArgs Arguments, ignored.
1349 */
1350static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1351{
1352 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1353 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1354 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1355 cpumR3InfoHost(pVM, pHlp, pszArgs);
1356}
1357
1358
1359/**
1360 * Parses the info argument.
1361 *
1362 * The argument starts with 'verbose', 'terse' or 'default' and then
1363 * continues with the comment string.
1364 *
1365 * @param pszArgs The pointer to the argument string.
1366 * @param penmType Where to store the dump type request.
1367 * @param ppszComment Where to store the pointer to the comment string.
1368 */
1369static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1370{
1371 if (!pszArgs)
1372 {
1373 *penmType = CPUMDUMPTYPE_DEFAULT;
1374 *ppszComment = "";
1375 }
1376 else
1377 {
1378 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1379 {
1380 pszArgs += 5;
1381 *penmType = CPUMDUMPTYPE_VERBOSE;
1382 }
1383 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1384 {
1385 pszArgs += 5;
1386 *penmType = CPUMDUMPTYPE_TERSE;
1387 }
1388 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1389 {
1390 pszArgs += 7;
1391 *penmType = CPUMDUMPTYPE_DEFAULT;
1392 }
1393 else
1394 *penmType = CPUMDUMPTYPE_DEFAULT;
1395 *ppszComment = RTStrStripL(pszArgs);
1396 }
1397}
1398
1399
1400/**
1401 * Display the guest cpu state.
1402 *
1403 * @param pVM VM Handle.
1404 * @param pHlp The info helper functions.
1405 * @param pszArgs Arguments, ignored.
1406 */
1407static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1408{
1409 CPUMDUMPTYPE enmType;
1410 const char *pszComment;
1411 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1412 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1413
1414 /* @todo SMP support! */
1415 PVMCPU pVCpu = &pVM->aCpus[0];
1416 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1417 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1418}
1419
1420
1421/**
1422 * Display the current guest instruction
1423 *
1424 * @param pVM VM Handle.
1425 * @param pHlp The info helper functions.
1426 * @param pszArgs Arguments, ignored.
1427 */
1428static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1429{
1430 char szInstruction[256];
1431 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1432 if (RT_SUCCESS(rc))
1433 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1434}
1435
1436
1437/**
1438 * Display the hypervisor cpu state.
1439 *
1440 * @param pVM VM Handle.
1441 * @param pHlp The info helper functions.
1442 * @param pszArgs Arguments, ignored.
1443 */
1444static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1445{
1446 CPUMDUMPTYPE enmType;
1447 const char *pszComment;
1448 /* @todo SMP */
1449 PVMCPU pVCpu = &pVM->aCpus[0];
1450
1451 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1452 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1453 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1454 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1455}
1456
1457
1458/**
1459 * Display the host cpu state.
1460 *
1461 * @param pVM VM Handle.
1462 * @param pHlp The info helper functions.
1463 * @param pszArgs Arguments, ignored.
1464 */
1465static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1466{
1467 CPUMDUMPTYPE enmType;
1468 const char *pszComment;
1469 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1470 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1471
1472 /*
1473 * Format the EFLAGS.
1474 */
1475 /* @todo SMP */
1476 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1477#if HC_ARCH_BITS == 32
1478 uint32_t efl = pCtx->eflags.u32;
1479#else
1480 uint64_t efl = pCtx->rflags;
1481#endif
1482 char szEFlags[80];
1483 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1484
1485 /*
1486 * Format the registers.
1487 */
1488#if HC_ARCH_BITS == 32
1489# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1490 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1491# endif
1492 {
1493 pHlp->pfnPrintf(pHlp,
1494 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1495 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1496 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1497 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1498 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1499 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1500 ,
1501 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1502 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1503 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1504 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1505 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1506 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1507 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1508 }
1509# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1510 else
1511# endif
1512#endif
1513#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1514 {
1515 pHlp->pfnPrintf(pHlp,
1516 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1517 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1518 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1519 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1520 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1521 "r14=%016RX64 r15=%016RX64\n"
1522 "iopl=%d %31s\n"
1523 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1524 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1525 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1526 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1527 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1528 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1529 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1530 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1531 ,
1532 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1533 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1534 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1535 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1536 pCtx->r11, pCtx->r12, pCtx->r13,
1537 pCtx->r14, pCtx->r15,
1538 X86_EFL_GET_IOPL(efl), szEFlags,
1539 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1540 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1541 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1542 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1543 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1544 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1545 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1546 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1547 }
1548#endif
1549}
1550
1551
1552/**
1553 * Get L1 cache / TLS associativity.
1554 */
1555static const char *getCacheAss(unsigned u, char *pszBuf)
1556{
1557 if (u == 0)
1558 return "res0 ";
1559 if (u == 1)
1560 return "direct";
1561 if (u >= 256)
1562 return "???";
1563
1564 RTStrPrintf(pszBuf, 16, "%d way", u);
1565 return pszBuf;
1566}
1567
1568
1569/**
1570 * Get L2 cache soociativity.
1571 */
1572const char *getL2CacheAss(unsigned u)
1573{
1574 switch (u)
1575 {
1576 case 0: return "off ";
1577 case 1: return "direct";
1578 case 2: return "2 way ";
1579 case 3: return "res3 ";
1580 case 4: return "4 way ";
1581 case 5: return "res5 ";
1582 case 6: return "8 way "; case 7: return "res7 ";
1583 case 8: return "16 way";
1584 case 9: return "res9 ";
1585 case 10: return "res10 ";
1586 case 11: return "res11 ";
1587 case 12: return "res12 ";
1588 case 13: return "res13 ";
1589 case 14: return "res14 ";
1590 case 15: return "fully ";
1591 default:
1592 return "????";
1593 }
1594}
1595
1596
1597/**
1598 * Display the guest CpuId leaves.
1599 *
1600 * @param pVM VM Handle.
1601 * @param pHlp The info helper functions.
1602 * @param pszArgs "terse", "default" or "verbose".
1603 */
1604static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1605{
1606 /*
1607 * Parse the argument.
1608 */
1609 unsigned iVerbosity = 1;
1610 if (pszArgs)
1611 {
1612 pszArgs = RTStrStripL(pszArgs);
1613 if (!strcmp(pszArgs, "terse"))
1614 iVerbosity--;
1615 else if (!strcmp(pszArgs, "verbose"))
1616 iVerbosity++;
1617 }
1618
1619 /*
1620 * Start cracking.
1621 */
1622 CPUMCPUID Host;
1623 CPUMCPUID Guest;
1624 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1625
1626 pHlp->pfnPrintf(pHlp,
1627 " RAW Standard CPUIDs\n"
1628 " Function eax ebx ecx edx\n");
1629 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1630 {
1631 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1632 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1633
1634 pHlp->pfnPrintf(pHlp,
1635 "Gst: %08x %08x %08x %08x %08x%s\n"
1636 "Hst: %08x %08x %08x %08x\n",
1637 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1638 i <= cStdMax ? "" : "*",
1639 Host.eax, Host.ebx, Host.ecx, Host.edx);
1640 }
1641
1642 /*
1643 * If verbose, decode it.
1644 */
1645 if (iVerbosity)
1646 {
1647 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1648 pHlp->pfnPrintf(pHlp,
1649 "Name: %.04s%.04s%.04s\n"
1650 "Supports: 0-%x\n",
1651 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1652 }
1653
1654 /*
1655 * Get Features.
1656 */
1657 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1658 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1659 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1660 if (cStdMax >= 1 && iVerbosity)
1661 {
1662 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1663 uint32_t uEAX = Guest.eax;
1664
1665 pHlp->pfnPrintf(pHlp,
1666 "Family: %d \tExtended: %d \tEffective: %d\n"
1667 "Model: %d \tExtended: %d \tEffective: %d\n"
1668 "Stepping: %d\n"
1669 "APIC ID: %#04x\n"
1670 "Logical CPUs: %d\n"
1671 "CLFLUSH Size: %d\n"
1672 "Brand ID: %#04x\n",
1673 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1674 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1675 ASMGetCpuStepping(uEAX),
1676 (Guest.ebx >> 24) & 0xff,
1677 (Guest.ebx >> 16) & 0xff,
1678 (Guest.ebx >> 8) & 0xff,
1679 (Guest.ebx >> 0) & 0xff);
1680 if (iVerbosity == 1)
1681 {
1682 uint32_t uEDX = Guest.edx;
1683 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1684 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1685 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1686 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1687 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1688 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1689 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1690 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1691 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1692 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1693 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1694 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1695 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1696 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1697 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1698 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1699 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1700 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1701 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1702 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1703 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1704 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1705 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1706 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1707 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1708 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1709 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1710 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1711 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1712 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1713 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1714 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1715 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1716 pHlp->pfnPrintf(pHlp, "\n");
1717
1718 uint32_t uECX = Guest.ecx;
1719 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1720 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1721 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1722 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1723 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1724 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1725 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1726 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1727 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1728 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1729 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1730 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1731 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1732 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1733 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1734 for (unsigned iBit = 14; iBit < 32; iBit++)
1735 if (uECX & RT_BIT(iBit))
1736 pHlp->pfnPrintf(pHlp, " %d", iBit);
1737 pHlp->pfnPrintf(pHlp, "\n");
1738 }
1739 else
1740 {
1741 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1742
1743 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1744 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1745 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1746 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1747
1748 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1749 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1750 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1751 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1752 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1753 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1754 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1755 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1756 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1757 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1758 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1759 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1760 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1761 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1762 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1763 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1764 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1765 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1766 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1767 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1768 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1769 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1770 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1771 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1772 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1773 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1774 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1775 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1776 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1777 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1778 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1779 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1780 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1781
1782 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1783 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1784 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1785 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1786 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1787 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1788 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1789 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1790 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1791 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1792 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1793 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1794 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1795 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1796 }
1797 }
1798 if (cStdMax >= 2 && iVerbosity)
1799 {
1800 /** @todo */
1801 }
1802
1803 /*
1804 * Extended.
1805 * Implemented after AMD specs.
1806 */
1807 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1808
1809 pHlp->pfnPrintf(pHlp,
1810 "\n"
1811 " RAW Extended CPUIDs\n"
1812 " Function eax ebx ecx edx\n");
1813 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1814 {
1815 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1816 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1817
1818 pHlp->pfnPrintf(pHlp,
1819 "Gst: %08x %08x %08x %08x %08x%s\n"
1820 "Hst: %08x %08x %08x %08x\n",
1821 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1822 i <= cExtMax ? "" : "*",
1823 Host.eax, Host.ebx, Host.ecx, Host.edx);
1824 }
1825
1826 /*
1827 * Understandable output
1828 */
1829 if (iVerbosity)
1830 {
1831 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1832 pHlp->pfnPrintf(pHlp,
1833 "Ext Name: %.4s%.4s%.4s\n"
1834 "Ext Supports: 0x80000000-%#010x\n",
1835 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1836 }
1837
1838 if (iVerbosity && cExtMax >= 1)
1839 {
1840 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1841 uint32_t uEAX = Guest.eax;
1842 pHlp->pfnPrintf(pHlp,
1843 "Family: %d \tExtended: %d \tEffective: %d\n"
1844 "Model: %d \tExtended: %d \tEffective: %d\n"
1845 "Stepping: %d\n"
1846 "Brand ID: %#05x\n",
1847 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1848 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1849 ASMGetCpuStepping(uEAX),
1850 Guest.ebx & 0xfff);
1851
1852 if (iVerbosity == 1)
1853 {
1854 uint32_t uEDX = Guest.edx;
1855 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1856 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1857 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1858 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1859 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1860 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1861 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1862 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1863 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1864 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1865 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1866 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1867 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1868 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1869 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1870 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1871 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1872 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1873 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1874 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1875 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1876 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1877 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1878 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1879 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1880 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1881 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1882 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1883 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1884 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1885 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1886 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1887 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1888 pHlp->pfnPrintf(pHlp, "\n");
1889
1890 uint32_t uECX = Guest.ecx;
1891 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1892 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1893 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1894 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1895 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1896 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1897 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1898 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1899 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1900 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1901 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1902 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1903 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1904 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1905 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1906 for (unsigned iBit = 5; iBit < 32; iBit++)
1907 if (uECX & RT_BIT(iBit))
1908 pHlp->pfnPrintf(pHlp, " %d", iBit);
1909 pHlp->pfnPrintf(pHlp, "\n");
1910 }
1911 else
1912 {
1913 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1914
1915 uint32_t uEdxGst = Guest.edx;
1916 uint32_t uEdxHst = Host.edx;
1917 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1918 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1919 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1920 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1921 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1922 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1923 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1924 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1925 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1926 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1927 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1928 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1929 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1930 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1931 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1932 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1933 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1934 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1935 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1936 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1937 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1938 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1939 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1940 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1941 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1942 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1943 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1944 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1945 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1946 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1947 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1948 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1949 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1950
1951 uint32_t uEcxGst = Guest.ecx;
1952 uint32_t uEcxHst = Host.ecx;
1953 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1954 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1955 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1956 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1957 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1958 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1959 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1960 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1961 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1962 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1963 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1964 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1965 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1966 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1967 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1968 }
1969 }
1970
1971 if (iVerbosity && cExtMax >= 2)
1972 {
1973 char szString[4*4*3+1] = {0};
1974 uint32_t *pu32 = (uint32_t *)szString;
1975 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1976 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1977 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1978 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1979 if (cExtMax >= 3)
1980 {
1981 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1982 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1983 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1984 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1985 }
1986 if (cExtMax >= 4)
1987 {
1988 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1989 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1990 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1991 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1992 }
1993 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1994 }
1995
1996 if (iVerbosity && cExtMax >= 5)
1997 {
1998 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1999 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2000 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2001 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2002 char sz1[32];
2003 char sz2[32];
2004
2005 pHlp->pfnPrintf(pHlp,
2006 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2007 "TLB 2/4M Data: %s %3d entries\n",
2008 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2009 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2010 pHlp->pfnPrintf(pHlp,
2011 "TLB 4K Instr/Uni: %s %3d entries\n"
2012 "TLB 4K Data: %s %3d entries\n",
2013 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2014 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2015 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2016 "L1 Instr Cache Lines Per Tag: %d\n"
2017 "L1 Instr Cache Associativity: %s\n"
2018 "L1 Instr Cache Size: %d KB\n",
2019 (uEDX >> 0) & 0xff,
2020 (uEDX >> 8) & 0xff,
2021 getCacheAss((uEDX >> 16) & 0xff, sz1),
2022 (uEDX >> 24) & 0xff);
2023 pHlp->pfnPrintf(pHlp,
2024 "L1 Data Cache Line Size: %d bytes\n"
2025 "L1 Data Cache Lines Per Tag: %d\n"
2026 "L1 Data Cache Associativity: %s\n"
2027 "L1 Data Cache Size: %d KB\n",
2028 (uECX >> 0) & 0xff,
2029 (uECX >> 8) & 0xff,
2030 getCacheAss((uECX >> 16) & 0xff, sz1),
2031 (uECX >> 24) & 0xff);
2032 }
2033
2034 if (iVerbosity && cExtMax >= 6)
2035 {
2036 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2037 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2038 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2039
2040 pHlp->pfnPrintf(pHlp,
2041 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2042 "L2 TLB 2/4M Data: %s %4d entries\n",
2043 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2044 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2045 pHlp->pfnPrintf(pHlp,
2046 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2047 "L2 TLB 4K Data: %s %4d entries\n",
2048 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2049 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2050 pHlp->pfnPrintf(pHlp,
2051 "L2 Cache Line Size: %d bytes\n"
2052 "L2 Cache Lines Per Tag: %d\n"
2053 "L2 Cache Associativity: %s\n"
2054 "L2 Cache Size: %d KB\n",
2055 (uEDX >> 0) & 0xff,
2056 (uEDX >> 8) & 0xf,
2057 getL2CacheAss((uEDX >> 12) & 0xf),
2058 (uEDX >> 16) & 0xffff);
2059 }
2060
2061 if (iVerbosity && cExtMax >= 7)
2062 {
2063 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2064
2065 pHlp->pfnPrintf(pHlp, "APM Features: ");
2066 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2067 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2068 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2069 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2070 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2071 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2072 for (unsigned iBit = 6; iBit < 32; iBit++)
2073 if (uEDX & RT_BIT(iBit))
2074 pHlp->pfnPrintf(pHlp, " %d", iBit);
2075 pHlp->pfnPrintf(pHlp, "\n");
2076 }
2077
2078 if (iVerbosity && cExtMax >= 8)
2079 {
2080 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2081 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2082
2083 pHlp->pfnPrintf(pHlp,
2084 "Physical Address Width: %d bits\n"
2085 "Virtual Address Width: %d bits\n",
2086 (uEAX >> 0) & 0xff,
2087 (uEAX >> 8) & 0xff);
2088 pHlp->pfnPrintf(pHlp,
2089 "Physical Core Count: %d\n",
2090 (uECX >> 0) & 0xff);
2091 }
2092
2093
2094 /*
2095 * Centaur.
2096 */
2097 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2098
2099 pHlp->pfnPrintf(pHlp,
2100 "\n"
2101 " RAW Centaur CPUIDs\n"
2102 " Function eax ebx ecx edx\n");
2103 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2104 {
2105 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2106 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2107
2108 pHlp->pfnPrintf(pHlp,
2109 "Gst: %08x %08x %08x %08x %08x%s\n"
2110 "Hst: %08x %08x %08x %08x\n",
2111 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2112 i <= cCentaurMax ? "" : "*",
2113 Host.eax, Host.ebx, Host.ecx, Host.edx);
2114 }
2115
2116 /*
2117 * Understandable output
2118 */
2119 if (iVerbosity)
2120 {
2121 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2122 pHlp->pfnPrintf(pHlp,
2123 "Centaur Supports: 0xc0000000-%#010x\n",
2124 Guest.eax);
2125 }
2126
2127 if (iVerbosity && cCentaurMax >= 1)
2128 {
2129 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2130 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2131 uint32_t uEdxHst = Host.edx;
2132
2133 if (iVerbosity == 1)
2134 {
2135 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2136 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2137 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2138 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2139 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2140 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2141 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2142 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2143 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2144 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2145 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2146 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2147 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2148 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2149 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2150 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2151 for (unsigned iBit = 14; iBit < 32; iBit++)
2152 if (uEdxGst & RT_BIT(iBit))
2153 pHlp->pfnPrintf(pHlp, " %d", iBit);
2154 pHlp->pfnPrintf(pHlp, "\n");
2155 }
2156 else
2157 {
2158 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2159 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2160 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2161 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2162 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2163 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2164 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2165 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2166 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2167 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2168 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2169 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2170 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2171 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2172 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2173 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2174 for (unsigned iBit = 14; iBit < 32; iBit++)
2175 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2176 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2177 pHlp->pfnPrintf(pHlp, "\n");
2178 }
2179 }
2180}
2181
2182
2183/**
2184 * Structure used when disassembling and instructions in DBGF.
2185 * This is used so the reader function can get the stuff it needs.
2186 */
2187typedef struct CPUMDISASSTATE
2188{
2189 /** Pointer to the CPU structure. */
2190 PDISCPUSTATE pCpu;
2191 /** The VM handle. */
2192 PVM pVM;
2193 /** The VMCPU handle. */
2194 PVMCPU pVCpu;
2195 /** Pointer to the first byte in the segemnt. */
2196 RTGCUINTPTR GCPtrSegBase;
2197 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2198 RTGCUINTPTR GCPtrSegEnd;
2199 /** The size of the segment minus 1. */
2200 RTGCUINTPTR cbSegLimit;
2201 /** Pointer to the current page - R3 Ptr. */
2202 void const *pvPageR3;
2203 /** Pointer to the current page - GC Ptr. */
2204 RTGCPTR pvPageGC;
2205 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2206 PGMPAGEMAPLOCK PageMapLock;
2207 /** Whether the PageMapLock is valid or not. */
2208 bool fLocked;
2209 /** 64 bits mode or not. */
2210 bool f64Bits;
2211} CPUMDISASSTATE, *PCPUMDISASSTATE;
2212
2213
2214/**
2215 * Instruction reader.
2216 *
2217 * @returns VBox status code.
2218 * @param PtrSrc Address to read from.
2219 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2220 * @param pu8Dst Where to store the bytes.
2221 * @param cbRead Number of bytes to read.
2222 * @param uDisCpu Pointer to the disassembler cpu state.
2223 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2224 */
2225static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2226{
2227 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2228 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2229 Assert(cbRead > 0);
2230 for (;;)
2231 {
2232 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2233
2234 /* Need to update the page translation? */
2235 if ( !pState->pvPageR3
2236 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2237 {
2238 int rc = VINF_SUCCESS;
2239
2240 /* translate the address */
2241 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2242 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2243 && !HWACCMIsEnabled(pState->pVM))
2244 {
2245 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2246 if (!pState->pvPageR3)
2247 rc = VERR_INVALID_POINTER;
2248 }
2249 else
2250 {
2251 /* Release mapping lock previously acquired. */
2252 if (pState->fLocked)
2253 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2254 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2255 pState->fLocked = RT_SUCCESS_NP(rc);
2256 }
2257 if (RT_FAILURE(rc))
2258 {
2259 pState->pvPageR3 = NULL;
2260 return rc;
2261 }
2262 }
2263
2264 /* check the segemnt limit */
2265 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2266 return VERR_OUT_OF_SELECTOR_BOUNDS;
2267
2268 /* calc how much we can read */
2269 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2270 if (!pState->f64Bits)
2271 {
2272 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2273 if (cb > cbSeg && cbSeg)
2274 cb = cbSeg;
2275 }
2276 if (cb > cbRead)
2277 cb = cbRead;
2278
2279 /* read and advance */
2280 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2281 cbRead -= cb;
2282 if (!cbRead)
2283 return VINF_SUCCESS;
2284 pu8Dst += cb;
2285 PtrSrc += cb;
2286 }
2287}
2288
2289
2290/**
2291 * Disassemble an instruction and return the information in the provided structure.
2292 *
2293 * @returns VBox status code.
2294 * @param pVM VM Handle
2295 * @param pVCpu VMCPU Handle
2296 * @param pCtx CPU context
2297 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2298 * @param pCpu Disassembly state
2299 * @param pszPrefix String prefix for logging (debug only)
2300 *
2301 */
2302VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2303{
2304 CPUMDISASSTATE State;
2305 int rc;
2306
2307 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2308 State.pCpu = pCpu;
2309 State.pvPageGC = 0;
2310 State.pvPageR3 = NULL;
2311 State.pVM = pVM;
2312 State.pVCpu = pVCpu;
2313 State.fLocked = false;
2314 State.f64Bits = false;
2315
2316 /*
2317 * Get selector information.
2318 */
2319 if ( (pCtx->cr0 & X86_CR0_PE)
2320 && pCtx->eflags.Bits.u1VM == 0)
2321 {
2322 if (CPUMAreHiddenSelRegsValid(pVM))
2323 {
2324 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2325 State.GCPtrSegBase = pCtx->csHid.u64Base;
2326 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2327 State.cbSegLimit = pCtx->csHid.u32Limit;
2328 pCpu->mode = (State.f64Bits)
2329 ? CPUMODE_64BIT
2330 : pCtx->csHid.Attr.n.u1DefBig
2331 ? CPUMODE_32BIT
2332 : CPUMODE_16BIT;
2333 }
2334 else
2335 {
2336 SELMSELINFO SelInfo;
2337
2338 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2339 if (!RT_SUCCESS(rc))
2340 {
2341 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2342 return rc;
2343 }
2344
2345 /*
2346 * Validate the selector.
2347 */
2348 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2349 if (!RT_SUCCESS(rc))
2350 {
2351 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2352 return rc;
2353 }
2354 State.GCPtrSegBase = SelInfo.GCPtrBase;
2355 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2356 State.cbSegLimit = SelInfo.cbLimit;
2357 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2358 }
2359 }
2360 else
2361 {
2362 /* real or V86 mode */
2363 pCpu->mode = CPUMODE_16BIT;
2364 State.GCPtrSegBase = pCtx->cs * 16;
2365 State.GCPtrSegEnd = 0xFFFFFFFF;
2366 State.cbSegLimit = 0xFFFFFFFF;
2367 }
2368
2369 /*
2370 * Disassemble the instruction.
2371 */
2372 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2373 pCpu->apvUserData[0] = &State;
2374
2375 uint32_t cbInstr;
2376#ifndef LOG_ENABLED
2377 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2378 if (RT_SUCCESS(rc))
2379 {
2380#else
2381 char szOutput[160];
2382 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2383 if (RT_SUCCESS(rc))
2384 {
2385 /* log it */
2386 if (pszPrefix)
2387 Log(("%s: %s", pszPrefix, szOutput));
2388 else
2389 Log(("%s", szOutput));
2390#endif
2391 rc = VINF_SUCCESS;
2392 }
2393 else
2394 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2395
2396 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2397 if (State.fLocked)
2398 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2399
2400 return rc;
2401}
2402
2403#ifdef DEBUG
2404
2405/**
2406 * Disassemble an instruction and dump it to the log
2407 *
2408 * @returns VBox status code.
2409 * @param pVM VM Handle
2410 * @param pVCpu VMCPU Handle
2411 * @param pCtx CPU context
2412 * @param pc GC instruction pointer
2413 * @param pszPrefix String prefix for logging
2414 *
2415 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2416 */
2417VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2418{
2419 DISCPUSTATE Cpu;
2420 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2421}
2422
2423
2424/**
2425 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2426 *
2427 * @internal
2428 */
2429VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2430{
2431 /* @todo SMP support!! */
2432 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2433}
2434
2435#endif /* DEBUG */
2436
2437/**
2438 * API for controlling a few of the CPU features found in CR4.
2439 *
2440 * Currently only X86_CR4_TSD is accepted as input.
2441 *
2442 * @returns VBox status code.
2443 *
2444 * @param pVM The VM handle.
2445 * @param fOr The CR4 OR mask.
2446 * @param fAnd The CR4 AND mask.
2447 */
2448VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2449{
2450 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2451 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2452
2453 pVM->cpum.s.CR4.OrMask &= fAnd;
2454 pVM->cpum.s.CR4.OrMask |= fOr;
2455
2456 return VINF_SUCCESS;
2457}
2458
2459
2460/**
2461 * Gets a pointer to the array of standard CPUID leafs.
2462 *
2463 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2464 *
2465 * @returns Pointer to the standard CPUID leafs (read-only).
2466 * @param pVM The VM handle.
2467 * @remark Intended for PATM.
2468 */
2469VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2470{
2471 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2472}
2473
2474
2475/**
2476 * Gets a pointer to the array of extended CPUID leafs.
2477 *
2478 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2479 *
2480 * @returns Pointer to the extended CPUID leafs (read-only).
2481 * @param pVM The VM handle.
2482 * @remark Intended for PATM.
2483 */
2484VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2485{
2486 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2487}
2488
2489
2490/**
2491 * Gets a pointer to the array of centaur CPUID leafs.
2492 *
2493 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2494 *
2495 * @returns Pointer to the centaur CPUID leafs (read-only).
2496 * @param pVM The VM handle.
2497 * @remark Intended for PATM.
2498 */
2499VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2500{
2501 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2502}
2503
2504
2505/**
2506 * Gets a pointer to the default CPUID leaf.
2507 *
2508 * @returns Pointer to the default CPUID leaf (read-only).
2509 * @param pVM The VM handle.
2510 * @remark Intended for PATM.
2511 */
2512VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2513{
2514 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2515}
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