CPUM.cpp@ 24332

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1	/* $Id: CPUM.cpp 24328 2009-11-04 13:22:47Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/pdm.h>
46	#include <VBox/mm.h>
47	#include <VBox/selm.h>
48	#include <VBox/dbgf.h>
49	#include <VBox/patm.h>
50	#include <VBox/hwaccm.h>
51	#include <VBox/ssm.h>
52	#include "CPUMInternal.h"
53	#include <VBox/vm.h>
54
55	#include <VBox/param.h>
56	#include <VBox/dis.h>
57	#include <VBox/err.h>
58	#include <VBox/log.h>
59	#include <iprt/assert.h>
60	#include <iprt/asm.h>
61	#include <iprt/string.h>
62	#include <iprt/mp.h>
63	#include <iprt/cpuset.h>
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The current saved state version. */
70	#ifdef VBOX_WITH_LIVE_MIGRATION
71	#define CPUM_SAVED_STATE_VERSION 11
72	#else
73	#define CPUM_SAVED_STATE_VERSION 10
74	#endif
75	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
76	* changes. */
77	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78	/** The saved state version for the 2.1 trunk before the MSR changes. */
79	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80	/** The saved state version of 2.0, used for backwards compatibility. */
81	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82	/** The saved state version of 1.6, used for backwards compatability. */
83	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86	/*******************************************************************************
87	* Structures and Typedefs *
88	*******************************************************************************/
89
90	/**
91	* What kind of cpu info dump to perform.
92	*/
93	typedef enum CPUMDUMPTYPE
94	{
95	CPUMDUMPTYPE_TERSE,
96	CPUMDUMPTYPE_DEFAULT,
97	CPUMDUMPTYPE_VERBOSE
98	} CPUMDUMPTYPE;
99	/** Pointer to a cpu info dump type. */
100	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
101
102
103	/*******************************************************************************
104	* Internal Functions *
105	*******************************************************************************/
106	static int cpumR3CpuIdInit(PVM pVM);
107	#ifdef VBOX_WITH_LIVE_MIGRATION
108	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
109	#endif
110	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
111	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
112	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
116	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
117	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
118
119
120	/**
121	* Initializes the CPUM.
122	*
123	* @returns VBox status code.
124	* @param pVM The VM to operate on.
125	*/
126	VMMR3DECL(int) CPUMR3Init(PVM pVM)
127	{
128	LogFlow(("CPUMR3Init\n"));
129
130	/*
131	* Assert alignment and sizes.
132	*/
133	AssertCompileMemberAlignment(VM, cpum.s, 32);
134	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
135	AssertCompileSizeAlignment(CPUMCTX, 64);
136	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
137	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
138	AssertCompileMemberAlignment(VM, cpum, 64);
139	AssertCompileMemberAlignment(VM, aCpus, 64);
140	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
141	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
142
143	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
144	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
145	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
146
147	/* Calculate the offset from CPUMCPU to CPUM. */
148	for (VMCPUID i = 0; i < pVM->cCpus; i++)
149	{
150	PVMCPU pVCpu = &pVM->aCpus[i];
151
152	/*
153	* Setup any fixed pointers and offsets.
154	*/
155	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
156	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
157
158	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
159	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
160	}
161
162	/*
163	* Check that the CPU supports the minimum features we require.
164	*/
165	if (!ASMHasCpuId())
166	{
167	Log(("The CPU doesn't support CPUID!\n"));
168	return VERR_UNSUPPORTED_CPU;
169	}
170	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
171	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
172
173	/* Setup the CR4 AND and OR masks used in the switcher */
174	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
175	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
176	{
177	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
178	/* No FXSAVE implies no SSE */
179	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = 0;
181	}
182	else
183	{
184	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
185	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
186	}
187
188	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
189	{
190	Log(("The CPU doesn't support MMX!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
194	{
195	Log(("The CPU doesn't support TSC!\n"));
196	return VERR_UNSUPPORTED_CPU;
197	}
198	/* Bogus on AMD? */
199	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
200	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
201
202	/*
203	* Setup hypervisor startup values.
204	*/
205
206	/*
207	* Register saved state data item.
208	*/
209	#ifdef VBOX_WITH_LIVE_MIGRATION
210	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
211	NULL, cpumR3LiveExec, NULL,
212	NULL, cpumR3SaveExec, NULL,
213	NULL, cpumR3LoadExec, NULL);
214	#else
215	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
216	NULL, NULL, NULL,
217	NULL, cpumR3SaveExec, NULL,
218	NULL, cpumR3LoadExec, NULL);
219	#endif
220	if (RT_FAILURE(rc))
221	return rc;
222
223	/* Query the CPU manufacturer. */
224	uint32_t uEAX, uEBX, uECX, uEDX;
225	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
226	if ( uEAX >= 1
227	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
228	&& uECX == X86_CPUID_VENDOR_AMD_ECX
229	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
230	{
231	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_AMD;
232	}
233	else if ( uEAX >= 1
234	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
235	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
236	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
237	{
238	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_INTEL;
239	}
240	else /** @todo Via */
241	{
242	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_UNKNOWN;
243	}
244
245	/*
246	* Register info handlers.
247	*/
248	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
249	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
250	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
251	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
252	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
253	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
254
255	/*
256	* Initialize the Guest CPU state.
257	*/
258	rc = cpumR3CpuIdInit(pVM);
259	if (RT_FAILURE(rc))
260	return rc;
261	CPUMR3Reset(pVM);
262	return VINF_SUCCESS;
263	}
264
265
266	/**
267	* Initializes the per-VCPU CPUM.
268	*
269	* @returns VBox status code.
270	* @param pVM The VM to operate on.
271	*/
272	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
273	{
274	LogFlow(("CPUMR3InitCPU\n"));
275	return VINF_SUCCESS;
276	}
277
278
279	/**
280	* Initializes the emulated CPU's cpuid information.
281	*
282	* @returns VBox status code.
283	* @param pVM The VM to operate on.
284	*/
285	static int cpumR3CpuIdInit(PVM pVM)
286	{
287	PCPUM pCPUM = &pVM->cpum.s;
288	uint32_t i;
289
290	/*
291	* Get the host CPUIDs.
292	*/
293	for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
294	{
295	ASMCpuId_Idx_ECX(i, 0,
296	&pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
297	&pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
298
299	/* Load standard CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
300	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
301	if (pLeaf)
302	{
303	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdStd[i].eax);
304	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdStd[i].ebx);
305	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdStd[i].ecx);
306	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdStd[i].edx);
307	}
308	}
309	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
310	{
311	ASMCpuId(0x80000000 + i,
312	&pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
313	&pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
314
315	/* Load extended CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
316	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
317	if (pLeaf)
318	{
319	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdExt[i].eax);
320	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdExt[i].ebx);
321	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdExt[i].ecx);
322	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdExt[i].edx);
323	}
324	}
325	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
326	{
327	ASMCpuId(0xc0000000 + i,
328	&pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
329	&pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
330
331	/* Load Centaur CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
332	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
333	if (pLeaf)
334	{
335	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdCentaur[i].eax);
336	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdCentaur[i].ebx);
337	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdCentaur[i].ecx);
338	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdCentaur[i].edx);
339	}
340	}
341
342	/*
343	* Only report features we can support.
344	*/
345	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
346	\| X86_CPUID_FEATURE_EDX_VME
347	\| X86_CPUID_FEATURE_EDX_DE
348	\| X86_CPUID_FEATURE_EDX_PSE
349	\| X86_CPUID_FEATURE_EDX_TSC
350	\| X86_CPUID_FEATURE_EDX_MSR
351	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
352	\| X86_CPUID_FEATURE_EDX_MCE
353	\| X86_CPUID_FEATURE_EDX_CX8
354	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
355	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
356	//\| X86_CPUID_FEATURE_EDX_SEP
357	\| X86_CPUID_FEATURE_EDX_MTRR
358	\| X86_CPUID_FEATURE_EDX_PGE
359	\| X86_CPUID_FEATURE_EDX_MCA
360	\| X86_CPUID_FEATURE_EDX_CMOV
361	\| X86_CPUID_FEATURE_EDX_PAT
362	\| X86_CPUID_FEATURE_EDX_PSE36
363	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
364	\| X86_CPUID_FEATURE_EDX_CLFSH
365	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
366	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
367	\| X86_CPUID_FEATURE_EDX_MMX
368	\| X86_CPUID_FEATURE_EDX_FXSR
369	\| X86_CPUID_FEATURE_EDX_SSE
370	\| X86_CPUID_FEATURE_EDX_SSE2
371	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
372	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
373	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
374	//\| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
375	\| 0;
376	pCPUM->aGuestCpuIdStd[1].ecx &= 0
377	\| X86_CPUID_FEATURE_ECX_SSE3
378	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
379	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
380	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
381	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
382	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
383	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
384	//\| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
385	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
386	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
387	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
388	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
389	/* ECX Bit 21 - x2APIC support - not yet. */
390	// \| X86_CPUID_FEATURE_ECX_X2APIC
391	/* ECX Bit 23 - POPCOUNT instruction. */
392	//\| X86_CPUID_FEATURE_ECX_POPCOUNT
393	\| 0;
394
395	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
396	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
397	\| X86_CPUID_AMD_FEATURE_EDX_VME
398	\| X86_CPUID_AMD_FEATURE_EDX_DE
399	\| X86_CPUID_AMD_FEATURE_EDX_PSE
400	\| X86_CPUID_AMD_FEATURE_EDX_TSC
401	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
402	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
403	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
404	\| X86_CPUID_AMD_FEATURE_EDX_CX8
405	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
406	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
407	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
408	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
409	\| X86_CPUID_AMD_FEATURE_EDX_PGE
410	\| X86_CPUID_AMD_FEATURE_EDX_MCA
411	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
412	\| X86_CPUID_AMD_FEATURE_EDX_PAT
413	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
414	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
415	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
416	\| X86_CPUID_AMD_FEATURE_EDX_MMX
417	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
418	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
419	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
420	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
421	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
422	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
423	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
424	\| 0;
425	pCPUM->aGuestCpuIdExt[1].ecx &= 0
426	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
427	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
428	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
429	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
430	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
431	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
432	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
433	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
434	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
435	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
436	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
437	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
438	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
439	\| 0;
440
441	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
442	if (pCPUM->fSyntheticCpu)
443	{
444	const char szVendor[13] = "VirtualBox ";
445	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
446
447	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
448
449	/* Limit the nr of standard leaves; 5 for monitor/mwait */
450	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
451
452	/* 0: Vendor */
453	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
454	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
455	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
456
457	/* 1.eax: Version information. family : model : stepping */
458	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
459
460	/* Leaves 2 - 4 are Intel only - zero them out */
461	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
462	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
463	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
464
465	/* Leaf 5 = monitor/mwait */
466
467	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
468	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
469	/* AMD only - set to zero. */
470	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
471
472	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
473	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
474
475	/* 0x800000002-4: Processor Name String Identifier. */
476	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
477	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
478	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
479	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
480	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
481	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
482	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
483	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
484	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
485	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
486	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
487	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
488
489	/* 0x800000005-7 - reserved -> zero */
490	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
491	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
492	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
493
494	/* 0x800000008: only the max virtual and physical address size. */
495	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
496	}
497
498	/*
499	* Hide HTT, multicode, SMP, whatever.
500	* (APIC-ID := 0 and #LogCpus := 0)
501	*/
502	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
503	#ifdef VBOX_WITH_MULTI_CORE
504	if ( pVM->cCpus > 1
505	&& pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
506	{
507	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
508	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
509	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
510	}
511	#endif
512
513	/* Cpuid 2:
514	* Intel: Cache and TLB information
515	* AMD: Reserved
516	* Safe to expose
517	*/
518
519	/* Cpuid 3:
520	* Intel: EAX, EBX - reserved
521	* ECX, EDX - Processor Serial Number if available, otherwise reserved
522	* AMD: Reserved
523	* Safe to expose
524	*/
525	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
526	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
527
528	/* Cpuid 4:
529	* Intel: Deterministic Cache Parameters Leaf
530	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
531	* AMD: Reserved
532	* Safe to expose, except for EAX:
533	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
534	* Bits 31-26: Maximum number of processor cores in this physical package**
535	* @Note These SMP values are constant regardless of ECX
536	*/
537	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
538	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
539	#ifdef VBOX_WITH_MULTI_CORE
540	if ( pVM->cCpus > 1
541	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
542	{
543	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
544	/* One logical processor with possibly multiple cores. */
545	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
546	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
547	}
548	#endif
549
550	/* Cpuid 5: Monitor/mwait Leaf
551	* Intel: ECX, EDX - reserved
552	* EAX, EBX - Smallest and largest monitor line size
553	* AMD: EDX - reserved
554	* EAX, EBX - Smallest and largest monitor line size
555	* ECX - extensions (ignored for now)
556	* Safe to expose
557	*/
558	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
559	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
560
561	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
562
563	/*
564	* Determine the default.
565	*
566	* Intel returns values of the highest standard function, while AMD
567	* returns zeros. VIA on the other hand seems to returning nothing or
568	* perhaps some random garbage, we don't try to duplicate this behavior.
569	*/
570	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
571	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
572	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
573
574	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
575	* Safe to pass on to the guest.
576	*
577	* Intel: 0x800000005 reserved
578	* 0x800000006 L2 cache information
579	* AMD: 0x800000005 L1 cache information
580	* 0x800000006 L2/L3 cache information
581	*/
582
583	/* Cpuid 0x800000007:
584	* AMD: EAX, EBX, ECX - reserved
585	* EDX: Advanced Power Management Information
586	* Intel: Reserved
587	*/
588	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
589	{
590	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
591
592	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
593
594	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
595	{
596	/* Only expose the TSC invariant capability bit to the guest. */
597	pCPUM->aGuestCpuIdExt[7].edx &= 0
598	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
599	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
600	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
601	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
602	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
603	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
604	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
605	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
606	#if 1
607	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
608	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
609	*/
610	#else
611	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
612	#endif
613	\| 0;
614	}
615	else
616	pCPUM->aGuestCpuIdExt[7].edx = 0;
617	}
618
619	/* Cpuid 0x800000008:
620	* AMD: EBX, EDX - reserved
621	* EAX: Virtual/Physical address Size
622	* ECX: Number of cores + APICIdCoreIdSize
623	* Intel: EAX: Virtual/Physical address Size
624	* EBX, ECX, EDX - reserved
625	*/
626	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
627	{
628	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
629	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
630	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
631	* NC (0-7) Number of cores; 0 equals 1 core */
632	pCPUM->aGuestCpuIdExt[8].ecx = 0;
633	#ifdef VBOX_WITH_MULTI_CORE
634	if ( pVM->cCpus > 1
635	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
636	{
637	/* Legacy method to determine the number of cores. */
638	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
639	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
640
641	}
642	#endif
643	}
644
645	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
646	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
647	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
648	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
649	*/
650	bool fNt4LeafLimit;
651	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
652	if (fNt4LeafLimit)
653	pCPUM->aGuestCpuIdStd[0].eax = 3;
654
655	/*
656	* Limit it the number of entries and fill the remaining with the defaults.
657	*
658	* The limits are masking off stuff about power saving and similar, this
659	* is perhaps a bit crudely done as there is probably some relatively harmless
660	* info too in these leaves (like words about having a constant TSC).
661	*/
662	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
663	pCPUM->aGuestCpuIdStd[0].eax = 5;
664
665	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
666	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
667
668	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
669	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
670	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
671	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
672	: 0;
673	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
674	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
675
676	/*
677	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
678	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
679	* of processors from (cpuid(4).eax >> 26) + 1.
680	*/
681	if (pVM->cCpus == 1)
682	pCPUM->aGuestCpuIdStd[4].eax = 0;
683
684	/*
685	* Centaur stuff (VIA).
686	*
687	* The important part here (we think) is to make sure the 0xc0000000
688	* function returns 0xc0000001. As for the features, we don't currently
689	* let on about any of those... 0xc0000002 seems to be some
690	* temperature/hz/++ stuff, include it as well (static).
691	*/
692	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
693	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
694	{
695	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
696	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
697	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
698	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
699	i++)
700	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
701	}
702	else
703	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
704	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
705
706
707	/*
708	* Load CPUID overrides from configuration.
709	* @note Kind of redundant now, but allows unchanged overrides
710	*/
711	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
712	* Overloads the CPUID leaf values. */
713	PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
714	uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
715	for (i=0;; )
716	{
717	while (cElements-- > 0)
718	{
719	PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
720	if (pNode)
721	{
722	uint32_t u32;
723	int rc = CFGMR3QueryU32(pNode, "eax", &u32);
724	if (RT_SUCCESS(rc))
725	pCpuId->eax = u32;
726	else
727	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
728
729	rc = CFGMR3QueryU32(pNode, "ebx", &u32);
730	if (RT_SUCCESS(rc))
731	pCpuId->ebx = u32;
732	else
733	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
734
735	rc = CFGMR3QueryU32(pNode, "ecx", &u32);
736	if (RT_SUCCESS(rc))
737	pCpuId->ecx = u32;
738	else
739	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
740
741	rc = CFGMR3QueryU32(pNode, "edx", &u32);
742	if (RT_SUCCESS(rc))
743	pCpuId->edx = u32;
744	else
745	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
746	}
747	pCpuId++;
748	i++;
749	}
750
751	/* next */
752	if ((i & UINT32_C(0xc0000000)) == 0)
753	{
754	pCpuId = &pCPUM->aGuestCpuIdExt[0];
755	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
756	i = UINT32_C(0x80000000);
757	}
758	else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
759	{
760	pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
761	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
762	i = UINT32_C(0xc0000000);
763	}
764	else
765	break;
766	}
767
768	/* Check if PAE was explicitely enabled by the user. */
769	bool fEnable = false;
770	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
771	if (RT_SUCCESS(rc) && fEnable)
772	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
773
774	/*
775	* Log the cpuid and we're good.
776	*/
777	RTCPUSET OnlineSet;
778	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
779	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
780	LogRel(("*********************** CPUID dump **********************\n"));
781	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
782	LogRel(("\n"));
783	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
784	LogRel(("****************** End of CPUID dump ********************\n"));
785	return VINF_SUCCESS;
786	}
787
788
789
790
791	/**
792	* Applies relocations to data and code managed by this
793	* component. This function will be called at init and
794	* whenever the VMM need to relocate it self inside the GC.
795	*
796	* The CPUM will update the addresses used by the switcher.
797	*
798	* @param pVM The VM.
799	*/
800	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
801	{
802	LogFlow(("CPUMR3Relocate\n"));
803	for (VMCPUID i = 0; i < pVM->cCpus; i++)
804	{
805	/*
806	* Switcher pointers.
807	*/
808	PVMCPU pVCpu = &pVM->aCpus[i];
809	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
810	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
811	}
812	}
813
814
815	/**
816	* Terminates the CPUM.
817	*
818	* Termination means cleaning up and freeing all resources,
819	* the VM it self is at this point powered off or suspended.
820	*
821	* @returns VBox status code.
822	* @param pVM The VM to operate on.
823	*/
824	VMMR3DECL(int) CPUMR3Term(PVM pVM)
825	{
826	CPUMR3TermCPU(pVM);
827	return 0;
828	}
829
830
831	/**
832	* Terminates the per-VCPU CPUM.
833	*
834	* Termination means cleaning up and freeing all resources,
835	* the VM it self is at this point powered off or suspended.
836	*
837	* @returns VBox status code.
838	* @param pVM The VM to operate on.
839	*/
840	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
841	{
842	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
847
848	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
849	pVCpu->cpum.s.uMagic = 0;
850	pCtx->dr[5] = 0;
851	}
852	#endif
853	return 0;
854	}
855
856	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
857	{
858	/* @todo anything different for VCPU > 0? */
859	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
860
861	/*
862	* Initialize everything to ZERO first.
863	*/
864	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
865	memset(pCtx, 0, sizeof(*pCtx));
866	pVCpu->cpum.s.fUseFlags = fUseFlags;
867
868	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
869	pCtx->eip = 0x0000fff0;
870	pCtx->edx = 0x00000600; /* P6 processor */
871	pCtx->eflags.Bits.u1Reserved0 = 1;
872
873	pCtx->cs = 0xf000;
874	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
875	pCtx->csHid.u32Limit = 0x0000ffff;
876	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
877	pCtx->csHid.Attr.n.u1Present = 1;
878	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
879
880	pCtx->dsHid.u32Limit = 0x0000ffff;
881	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
882	pCtx->dsHid.Attr.n.u1Present = 1;
883	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
884
885	pCtx->esHid.u32Limit = 0x0000ffff;
886	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
887	pCtx->esHid.Attr.n.u1Present = 1;
888	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
889
890	pCtx->fsHid.u32Limit = 0x0000ffff;
891	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
892	pCtx->fsHid.Attr.n.u1Present = 1;
893	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
894
895	pCtx->gsHid.u32Limit = 0x0000ffff;
896	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
897	pCtx->gsHid.Attr.n.u1Present = 1;
898	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
899
900	pCtx->ssHid.u32Limit = 0x0000ffff;
901	pCtx->ssHid.Attr.n.u1Present = 1;
902	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
903	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
904
905	pCtx->idtr.cbIdt = 0xffff;
906	pCtx->gdtr.cbGdt = 0xffff;
907
908	pCtx->ldtrHid.u32Limit = 0xffff;
909	pCtx->ldtrHid.Attr.n.u1Present = 1;
910	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
911
912	pCtx->trHid.u32Limit = 0xffff;
913	pCtx->trHid.Attr.n.u1Present = 1;
914	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
915
916	pCtx->dr[6] = X86_DR6_INIT_VAL;
917	pCtx->dr[7] = X86_DR7_INIT_VAL;
918
919	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
920	pCtx->fpu.FCW = 0x37f;
921
922	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
923	pCtx->fpu.MXCSR = 0x1F80;
924
925	/* Init PAT MSR */
926	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
927
928	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
929	* The Intel docs don't mention it.
930	*/
931	pCtx->msrEFER = 0;
932	}
933
934	/**
935	* Resets the CPU.
936	*
937	* @returns VINF_SUCCESS.
938	* @param pVM The VM handle.
939	*/
940	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
941	{
942	for (VMCPUID i = 0; i < pVM->cCpus; i++)
943	{
944	CPUMR3ResetCpu(&pVM->aCpus[i]);
945
946	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
947	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
948
949	/* Magic marker for searching in crash dumps. */
950	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
951	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
952	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
953	#endif
954	}
955	}
956
957	#ifdef VBOX_WITH_LIVE_MIGRATION
958
959	/**
960	* Called both in pass 0 and the final pass.
961	*
962	* @param pVM The VM handle.
963	* @param pSSM The saved state handle.
964	*/
965	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
966	{
967	/*
968	* Save all the CPU ID leaves here so we can check them for compatability
969	* upon loading.
970	*/
971	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
972	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
973
974	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
975	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
976
977	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
978	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
979
980	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
981
982	/*
983	* Save a good portion of the raw CPU IDs as well as they may come in
984	* handy when validating features for raw mode.
985	*/
986	CPUMCPUID aRawStd[8];
987	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
988	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
989	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
990	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
991
992	CPUMCPUID aRawExt[16];
993	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
994	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
995	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
996	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
997	}
998
999
1000	/**
1001	* Loads the CPU ID leaves saved by pass 0.
1002	*
1003	* @returns VBox status code.
1004	* @param pVM The VM handle.
1005	* @param pSSM The saved state handle.
1006	* @param uVersion The format version.
1007	*/
1008	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1009	{
1010	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1011
1012	/*
1013	* Load them into stack buffers first.
1014	*/
1015	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1016	uint32_t cGuestCpuIdStd;
1017	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1018	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1019	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1020	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1021
1022	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1023	uint32_t cGuestCpuIdExt;
1024	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1025	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1026	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1027	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1028
1029	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1030	uint32_t cGuestCpuIdCentaur;
1031	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1032	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1033	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1034	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1035
1036	CPUMCPUID GuestCpuIdDef;
1037	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1038	AssertRCReturn(rc, rc);
1039
1040	CPUMCPUID aRawStd[8];
1041	uint32_t cRawStd;
1042	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1043	if (cRawStd > RT_ELEMENTS(aRawStd))
1044	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1045	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1046
1047	CPUMCPUID aRawExt[16];
1048	uint32_t cRawExt;
1049	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1050	if (cRawExt > RT_ELEMENTS(aRawExt))
1051	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1052	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1053	AssertRCReturn(rc, rc);
1054
1055	/*
1056	* Note that we support restoring less than the current amount of standard
1057	* leaves because we've been allowed more is newer version of VBox.
1058	*
1059	* So, pad new entries with the default.
1060	*/
1061	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1062	aGuestCpuIdStd[i] = GuestCpuIdDef;
1063
1064	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1065	aGuestCpuIdExt[i] = GuestCpuIdDef;
1066
1067	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1068	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1069
1070	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1071	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1072
1073	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1074	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1075
1076	/*
1077	* Get the raw CPU IDs for the current host.
1078	*/
1079	CPUMCPUID aHostRawStd[8];
1080	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1081	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1082
1083	CPUMCPUID aHostRawExt[16];
1084	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1085	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1086
1087	/*
1088	* Now for the fun part...
1089	*/
1090
1091
1092	/*
1093	* We're good, commit the CPU ID leaves.
1094	*/
1095	memcmp(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1096	memcmp(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1097	memcmp(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1098	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1099
1100	return VINF_SUCCESS;
1101	}
1102
1103
1104	/**
1105	* Pass 0 live exec callback.
1106	*
1107	* @returns VINF_SSM_DONT_CALL_AGAIN.
1108	* @param pVM The VM handle.
1109	* @param pSSM The saved state handle.
1110	* @param uPass The pass (0).
1111	*/
1112	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1113	{
1114	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1115	cpumR3SaveCpuId(pVM, pSSM);
1116	return VINF_SSM_DONT_CALL_AGAIN;
1117	}
1118
1119	#endif /* VBOX_WITH_LIVE_MIGRATION */
1120
1121	/**
1122	* Execute state save operation.
1123	*
1124	* @returns VBox status code.
1125	* @param pVM VM Handle.
1126	* @param pSSM SSM operation handle.
1127	*/
1128	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1129	{
1130	/*
1131	* Save.
1132	*/
1133	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1134	{
1135	PVMCPU pVCpu = &pVM->aCpus[i];
1136
1137	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1138	}
1139
1140	SSMR3PutU32(pSSM, pVM->cCpus);
1141	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1142	{
1143	PVMCPU pVCpu = &pVM->aCpus[i];
1144
1145	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1146	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1147	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1148	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1149	}
1150
1151	#ifdef VBOX_WITH_LIVE_MIGRATION
1152	cpumR3SaveCpuId(pVM, pSSM);
1153	return VINF_SUCCESS;
1154	#else
1155
1156	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1157	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1158
1159	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1160	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1161
1162	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1163	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1164
1165	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1166
1167	/* Add the cpuid for checking that the cpu is unchanged. */
1168	uint32_t au32CpuId[8] = {0};
1169	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1170	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1171	return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
1172	#endif
1173	}
1174
1175
1176	/**
1177	* Load a version 1.6 CPUMCTX structure.
1178	*
1179	* @returns VBox status code.
1180	* @param pVM VM Handle.
1181	* @param pCpumctx16 Version 1.6 CPUMCTX
1182	*/
1183	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1184	{
1185	#define CPUMCTX16_LOADREG(RegName) \
1186	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1187
1188	#define CPUMCTX16_LOADDRXREG(RegName) \
1189	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1190
1191	#define CPUMCTX16_LOADHIDREG(RegName) \
1192	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1193	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1194	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1195
1196	#define CPUMCTX16_LOADSEGREG(RegName) \
1197	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1198	CPUMCTX16_LOADHIDREG(RegName);
1199
1200	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1201
1202	CPUMCTX16_LOADREG(rax);
1203	CPUMCTX16_LOADREG(rbx);
1204	CPUMCTX16_LOADREG(rcx);
1205	CPUMCTX16_LOADREG(rdx);
1206	CPUMCTX16_LOADREG(rdi);
1207	CPUMCTX16_LOADREG(rsi);
1208	CPUMCTX16_LOADREG(rbp);
1209	CPUMCTX16_LOADREG(esp);
1210	CPUMCTX16_LOADREG(rip);
1211	CPUMCTX16_LOADREG(rflags);
1212
1213	CPUMCTX16_LOADSEGREG(cs);
1214	CPUMCTX16_LOADSEGREG(ds);
1215	CPUMCTX16_LOADSEGREG(es);
1216	CPUMCTX16_LOADSEGREG(fs);
1217	CPUMCTX16_LOADSEGREG(gs);
1218	CPUMCTX16_LOADSEGREG(ss);
1219
1220	CPUMCTX16_LOADREG(r8);
1221	CPUMCTX16_LOADREG(r9);
1222	CPUMCTX16_LOADREG(r10);
1223	CPUMCTX16_LOADREG(r11);
1224	CPUMCTX16_LOADREG(r12);
1225	CPUMCTX16_LOADREG(r13);
1226	CPUMCTX16_LOADREG(r14);
1227	CPUMCTX16_LOADREG(r15);
1228
1229	CPUMCTX16_LOADREG(cr0);
1230	CPUMCTX16_LOADREG(cr2);
1231	CPUMCTX16_LOADREG(cr3);
1232	CPUMCTX16_LOADREG(cr4);
1233
1234	CPUMCTX16_LOADDRXREG(0);
1235	CPUMCTX16_LOADDRXREG(1);
1236	CPUMCTX16_LOADDRXREG(2);
1237	CPUMCTX16_LOADDRXREG(3);
1238	CPUMCTX16_LOADDRXREG(4);
1239	CPUMCTX16_LOADDRXREG(5);
1240	CPUMCTX16_LOADDRXREG(6);
1241	CPUMCTX16_LOADDRXREG(7);
1242
1243	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1244	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1245	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1246	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1247
1248	CPUMCTX16_LOADREG(ldtr);
1249	CPUMCTX16_LOADREG(tr);
1250
1251	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1252
1253	CPUMCTX16_LOADREG(msrEFER);
1254	CPUMCTX16_LOADREG(msrSTAR);
1255	CPUMCTX16_LOADREG(msrPAT);
1256	CPUMCTX16_LOADREG(msrLSTAR);
1257	CPUMCTX16_LOADREG(msrCSTAR);
1258	CPUMCTX16_LOADREG(msrSFMASK);
1259	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1260
1261	CPUMCTX16_LOADHIDREG(ldtr);
1262	CPUMCTX16_LOADHIDREG(tr);
1263
1264	#undef CPUMCTX16_LOADSEGREG
1265	#undef CPUMCTX16_LOADHIDREG
1266	#undef CPUMCTX16_LOADDRXREG
1267	#undef CPUMCTX16_LOADREG
1268	}
1269
1270
1271	/**
1272	* Execute state load operation.
1273	*
1274	* @returns VBox status code.
1275	* @param pVM VM Handle.
1276	* @param pSSM SSM operation handle.
1277	* @param uVersion Data layout version.
1278	* @param uPass The data pass.
1279	*/
1280	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1281	{
1282	/*
1283	* Validate version.
1284	*/
1285	if ( uVersion != CPUM_SAVED_STATE_VERSION
1286	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1287	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1288	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1289	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1290	{
1291	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1292	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1293	}
1294
1295	if (uPass == SSM_PASS_FINAL)
1296	{
1297	/*
1298	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1299	* really old SSM file versions.)
1300	*/
1301	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1302	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1303	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1304	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1305
1306	/*
1307	* Restore.
1308	*/
1309	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1310	{
1311	PVMCPU pVCpu = &pVM->aCpus[i];
1312	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1313	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1314
1315	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1316	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1317	pVCpu->cpum.s.Hyper.esp = uESP;
1318	}
1319
1320	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1321	{
1322	CPUMCTX_VER1_6 cpumctx16;
1323	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1324	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1325
1326	/* Save the old cpumctx state into the new one. */
1327	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1328
1329	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1330	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1331	}
1332	else
1333	{
1334	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1335	{
1336	uint32_t cCpus;
1337	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1338	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1339	VERR_SSM_UNEXPECTED_DATA);
1340	}
1341	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1342	\|\| pVM->cCpus == 1,
1343	("cCpus=%u\n", pVM->cCpus),
1344	VERR_SSM_UNEXPECTED_DATA);
1345
1346	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1347	{
1348	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1349	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1350	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1351	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1352	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1353	}
1354	}
1355	}
1356
1357	#ifdef VBOX_WITH_LIVE_MIGRATION
1358	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1359	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1360
1361	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1362	* actually required. */
1363	#endif
1364
1365	/*
1366	* Restore the CPUID leaves.
1367	*
1368	* Note that we support restoring less than the current amount of standard
1369	* leaves because we've been allowed more is newer version of VBox.
1370	*/
1371	uint32_t cElements;
1372	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1373	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1374	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1375	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1376
1377	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1378	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1379	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1380	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1381
1382	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1383	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1384	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1385	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1386
1387	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1388
1389	/*
1390	* Check that the basic cpuid id information is unchanged.
1391	*/
1392	/** @todo we should check the 64 bits capabilities too! */
1393	uint32_t au32CpuId[8] = {0};
1394	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1395	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1396	uint32_t au32CpuIdSaved[8];
1397	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1398	if (RT_SUCCESS(rc))
1399	{
1400	/* Ignore CPU stepping. */
1401	au32CpuId[4] &= 0xfffffff0;
1402	au32CpuIdSaved[4] &= 0xfffffff0;
1403
1404	/* Ignore APIC ID (AMD specs). */
1405	au32CpuId[5] &= ~0xff000000;
1406	au32CpuIdSaved[5] &= ~0xff000000;
1407
1408	/* Ignore the number of Logical CPUs (AMD specs). */
1409	au32CpuId[5] &= ~0x00ff0000;
1410	au32CpuIdSaved[5] &= ~0x00ff0000;
1411
1412	/* Ignore some advanced capability bits, that we don't expose to the guest. */
1413	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1414	\| X86_CPUID_FEATURE_ECX_VMX
1415	\| X86_CPUID_FEATURE_ECX_SMX
1416	\| X86_CPUID_FEATURE_ECX_EST
1417	\| X86_CPUID_FEATURE_ECX_TM2
1418	\| X86_CPUID_FEATURE_ECX_CNTXID
1419	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1420	\| X86_CPUID_FEATURE_ECX_PDCM
1421	\| X86_CPUID_FEATURE_ECX_DCA
1422	\| X86_CPUID_FEATURE_ECX_X2APIC
1423	);
1424	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1425	\| X86_CPUID_FEATURE_ECX_VMX
1426	\| X86_CPUID_FEATURE_ECX_SMX
1427	\| X86_CPUID_FEATURE_ECX_EST
1428	\| X86_CPUID_FEATURE_ECX_TM2
1429	\| X86_CPUID_FEATURE_ECX_CNTXID
1430	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1431	\| X86_CPUID_FEATURE_ECX_PDCM
1432	\| X86_CPUID_FEATURE_ECX_DCA
1433	\| X86_CPUID_FEATURE_ECX_X2APIC
1434	);
1435
1436	/* Make sure we don't forget to update the masks when enabling
1437	* features in the future.
1438	*/
1439	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1440	( X86_CPUID_FEATURE_ECX_DTES64
1441	\| X86_CPUID_FEATURE_ECX_VMX
1442	\| X86_CPUID_FEATURE_ECX_SMX
1443	\| X86_CPUID_FEATURE_ECX_EST
1444	\| X86_CPUID_FEATURE_ECX_TM2
1445	\| X86_CPUID_FEATURE_ECX_CNTXID
1446	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1447	\| X86_CPUID_FEATURE_ECX_PDCM
1448	\| X86_CPUID_FEATURE_ECX_DCA
1449	\| X86_CPUID_FEATURE_ECX_X2APIC
1450	)));
1451	/* do the compare */
1452	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1453	{
1454	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1455	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1456	"Saved=%.*Rhxs\n"
1457	"Real =%.*Rhxs\n",
1458	sizeof(au32CpuIdSaved), au32CpuIdSaved,
1459	sizeof(au32CpuId), au32CpuId));
1460	else
1461	{
1462	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1463	"Saved=%.*Rhxs\n"
1464	"Real =%.*Rhxs\n",
1465	sizeof(au32CpuIdSaved), au32CpuIdSaved,
1466	sizeof(au32CpuId), au32CpuId));
1467	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1468	}
1469	}
1470	}
1471
1472	return rc;
1473	}
1474
1475
1476	/**
1477	* Formats the EFLAGS value into mnemonics.
1478	*
1479	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1480	* @param efl The EFLAGS value.
1481	*/
1482	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1483	{
1484	/*
1485	* Format the flags.
1486	*/
1487	static const struct
1488	{
1489	const char pszSet; const char pszClear; uint32_t fFlag;
1490	} s_aFlags[] =
1491	{
1492	{ "vip",NULL, X86_EFL_VIP },
1493	{ "vif",NULL, X86_EFL_VIF },
1494	{ "ac", NULL, X86_EFL_AC },
1495	{ "vm", NULL, X86_EFL_VM },
1496	{ "rf", NULL, X86_EFL_RF },
1497	{ "nt", NULL, X86_EFL_NT },
1498	{ "ov", "nv", X86_EFL_OF },
1499	{ "dn", "up", X86_EFL_DF },
1500	{ "ei", "di", X86_EFL_IF },
1501	{ "tf", NULL, X86_EFL_TF },
1502	{ "nt", "pl", X86_EFL_SF },
1503	{ "nz", "zr", X86_EFL_ZF },
1504	{ "ac", "na", X86_EFL_AF },
1505	{ "po", "pe", X86_EFL_PF },
1506	{ "cy", "nc", X86_EFL_CF },
1507	};
1508	char *psz = pszEFlags;
1509	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1510	{
1511	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1512	if (pszAdd)
1513	{
1514	strcpy(psz, pszAdd);
1515	psz += strlen(pszAdd);
1516	*psz++ = ' ';
1517	}
1518	}
1519	psz[-1] = '\0';
1520	}
1521
1522
1523	/**
1524	* Formats a full register dump.
1525	*
1526	* @param pVM VM Handle.
1527	* @param pCtx The context to format.
1528	* @param pCtxCore The context core to format.
1529	* @param pHlp Output functions.
1530	* @param enmType The dump type.
1531	* @param pszPrefix Register name prefix.
1532	*/
1533	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1534	{
1535	/*
1536	* Format the EFLAGS.
1537	*/
1538	uint32_t efl = pCtxCore->eflags.u32;
1539	char szEFlags[80];
1540	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1541
1542	/*
1543	* Format the registers.
1544	*/
1545	switch (enmType)
1546	{
1547	case CPUMDUMPTYPE_TERSE:
1548	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1549	pHlp->pfnPrintf(pHlp,
1550	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1551	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1552	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1553	"%sr14=%016RX64 %sr15=%016RX64\n"
1554	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1555	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1556	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1557	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1558	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1559	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1560	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1561	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1562	else
1563	pHlp->pfnPrintf(pHlp,
1564	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1565	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1566	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1567	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1568	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1569	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1570	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1571	break;
1572
1573	case CPUMDUMPTYPE_DEFAULT:
1574	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1575	pHlp->pfnPrintf(pHlp,
1576	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1577	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1578	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1579	"%sr14=%016RX64 %sr15=%016RX64\n"
1580	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1581	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1582	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1583	,
1584	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1585	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1586	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1587	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1588	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1589	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1590	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1591	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1592	else
1593	pHlp->pfnPrintf(pHlp,
1594	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1595	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1596	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1597	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1598	,
1599	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1600	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1601	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1602	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1603	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1604	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1605	break;
1606
1607	case CPUMDUMPTYPE_VERBOSE:
1608	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1609	pHlp->pfnPrintf(pHlp,
1610	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1611	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1612	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1613	"%sr14=%016RX64 %sr15=%016RX64\n"
1614	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1615	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1616	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1617	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1618	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1619	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1620	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1621	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1622	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1623	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1624	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1625	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1626	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1627	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1628	,
1629	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1630	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1631	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1632	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1633	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1634	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1635	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1636	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1637	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1638	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1639	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1640	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1641	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1642	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1643	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1644	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1645	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1646	else
1647	pHlp->pfnPrintf(pHlp,
1648	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1649	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1650	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1651	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1652	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1653	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1654	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1655	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1656	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1657	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1658	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1659	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1660	,
1661	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1662	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1663	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1664	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1665	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1666	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1667	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1668	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1669	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1670	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1671	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1672	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1673
1674	pHlp->pfnPrintf(pHlp,
1675	"FPU:\n"
1676	"%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1677	"%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1678	"%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1679	,
1680	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1681	pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1682	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1683	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1684
1685	pHlp->pfnPrintf(pHlp,
1686	"MSR:\n"
1687	"%sEFER =%016RX64\n"
1688	"%sPAT =%016RX64\n"
1689	"%sSTAR =%016RX64\n"
1690	"%sCSTAR =%016RX64\n"
1691	"%sLSTAR =%016RX64\n"
1692	"%sSFMASK =%016RX64\n"
1693	"%sKERNELGSBASE =%016RX64\n",
1694	pszPrefix, pCtx->msrEFER,
1695	pszPrefix, pCtx->msrPAT,
1696	pszPrefix, pCtx->msrSTAR,
1697	pszPrefix, pCtx->msrCSTAR,
1698	pszPrefix, pCtx->msrLSTAR,
1699	pszPrefix, pCtx->msrSFMASK,
1700	pszPrefix, pCtx->msrKERNELGSBASE);
1701	break;
1702	}
1703	}
1704
1705
1706	/**
1707	* Display all cpu states and any other cpum info.
1708	*
1709	* @param pVM VM Handle.
1710	* @param pHlp The info helper functions.
1711	* @param pszArgs Arguments, ignored.
1712	*/
1713	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1714	{
1715	cpumR3InfoGuest(pVM, pHlp, pszArgs);
1716	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1717	cpumR3InfoHyper(pVM, pHlp, pszArgs);
1718	cpumR3InfoHost(pVM, pHlp, pszArgs);
1719	}
1720
1721
1722	/**
1723	* Parses the info argument.
1724	*
1725	* The argument starts with 'verbose', 'terse' or 'default' and then
1726	* continues with the comment string.
1727	*
1728	* @param pszArgs The pointer to the argument string.
1729	* @param penmType Where to store the dump type request.
1730	* @param ppszComment Where to store the pointer to the comment string.
1731	*/
1732	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
1733	{
1734	if (!pszArgs)
1735	{
1736	*penmType = CPUMDUMPTYPE_DEFAULT;
1737	*ppszComment = "";
1738	}
1739	else
1740	{
1741	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1742	{
1743	pszArgs += 5;
1744	*penmType = CPUMDUMPTYPE_VERBOSE;
1745	}
1746	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1747	{
1748	pszArgs += 5;
1749	*penmType = CPUMDUMPTYPE_TERSE;
1750	}
1751	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1752	{
1753	pszArgs += 7;
1754	*penmType = CPUMDUMPTYPE_DEFAULT;
1755	}
1756	else
1757	*penmType = CPUMDUMPTYPE_DEFAULT;
1758	*ppszComment = RTStrStripL(pszArgs);
1759	}
1760	}
1761
1762
1763	/**
1764	* Display the guest cpu state.
1765	*
1766	* @param pVM VM Handle.
1767	* @param pHlp The info helper functions.
1768	* @param pszArgs Arguments, ignored.
1769	*/
1770	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1771	{
1772	CPUMDUMPTYPE enmType;
1773	const char *pszComment;
1774	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1775
1776	/* @todo SMP support! */
1777	PVMCPU pVCpu = VMMGetCpu(pVM);
1778	if (!pVCpu)
1779	pVCpu = &pVM->aCpus[0];
1780
1781	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1782
1783	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1784	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1785	}
1786
1787
1788	/**
1789	* Display the current guest instruction
1790	*
1791	* @param pVM VM Handle.
1792	* @param pHlp The info helper functions.
1793	* @param pszArgs Arguments, ignored.
1794	*/
1795	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1796	{
1797	char szInstruction[256];
1798	/* @todo SMP support! */
1799	PVMCPU pVCpu = VMMGetCpu(pVM);
1800	if (!pVCpu)
1801	pVCpu = &pVM->aCpus[0];
1802
1803	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1804	if (RT_SUCCESS(rc))
1805	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1806	}
1807
1808
1809	/**
1810	* Display the hypervisor cpu state.
1811	*
1812	* @param pVM VM Handle.
1813	* @param pHlp The info helper functions.
1814	* @param pszArgs Arguments, ignored.
1815	*/
1816	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1817	{
1818	CPUMDUMPTYPE enmType;
1819	const char *pszComment;
1820	/* @todo SMP */
1821	PVMCPU pVCpu = &pVM->aCpus[0];
1822
1823	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1824	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1825	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1826	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1827	}
1828
1829
1830	/**
1831	* Display the host cpu state.
1832	*
1833	* @param pVM VM Handle.
1834	* @param pHlp The info helper functions.
1835	* @param pszArgs Arguments, ignored.
1836	*/
1837	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1838	{
1839	CPUMDUMPTYPE enmType;
1840	const char *pszComment;
1841	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1842	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1843
1844	/*
1845	* Format the EFLAGS.
1846	*/
1847	/* @todo SMP */
1848	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1849	#if HC_ARCH_BITS == 32
1850	uint32_t efl = pCtx->eflags.u32;
1851	#else
1852	uint64_t efl = pCtx->rflags;
1853	#endif
1854	char szEFlags[80];
1855	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1856
1857	/*
1858	* Format the registers.
1859	*/
1860	#if HC_ARCH_BITS == 32
1861	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1862	if (!(pCtx->efer & MSR_K6_EFER_LMA))
1863	# endif
1864	{
1865	pHlp->pfnPrintf(pHlp,
1866	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1867	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1868	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1869	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1870	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1871	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1872	,
1873	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
1874	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1875	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1876	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
1877	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1878	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1879	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1880	}
1881	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1882	else
1883	# endif
1884	#endif
1885	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1886	{
1887	pHlp->pfnPrintf(pHlp,
1888	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1889	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1890	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1891	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1892	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1893	"r14=%016RX64 r15=%016RX64\n"
1894	"iopl=%d %31s\n"
1895	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1896	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1897	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
1898	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1899	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1900	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1901	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1902	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1903	,
1904	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
1905	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1906	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
1907	/pCtx->r8, pCtx->r9,/ pCtx->r10,
1908	pCtx->r11, pCtx->r12, pCtx->r13,
1909	pCtx->r14, pCtx->r15,
1910	X86_EFL_GET_IOPL(efl), szEFlags,
1911	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1912	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
1913	pCtx->cr4, pCtx->ldtr, pCtx->tr,
1914	pCtx->dr0, pCtx->dr1, pCtx->dr2,
1915	pCtx->dr3, pCtx->dr6, pCtx->dr7,
1916	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1917	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1918	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1919	}
1920	#endif
1921	}
1922
1923
1924	/**
1925	* Get L1 cache / TLS associativity.
1926	*/
1927	static const char getCacheAss(unsigned u, char pszBuf)
1928	{
1929	if (u == 0)
1930	return "res0 ";
1931	if (u == 1)
1932	return "direct";
1933	if (u >= 256)
1934	return "???";
1935
1936	RTStrPrintf(pszBuf, 16, "%d way", u);
1937	return pszBuf;
1938	}
1939
1940
1941	/**
1942	* Get L2 cache soociativity.
1943	*/
1944	const char *getL2CacheAss(unsigned u)
1945	{
1946	switch (u)
1947	{
1948	case 0: return "off ";
1949	case 1: return "direct";
1950	case 2: return "2 way ";
1951	case 3: return "res3 ";
1952	case 4: return "4 way ";
1953	case 5: return "res5 ";
1954	case 6: return "8 way "; case 7: return "res7 ";
1955	case 8: return "16 way";
1956	case 9: return "res9 ";
1957	case 10: return "res10 ";
1958	case 11: return "res11 ";
1959	case 12: return "res12 ";
1960	case 13: return "res13 ";
1961	case 14: return "res14 ";
1962	case 15: return "fully ";
1963	default:
1964	return "????";
1965	}
1966	}
1967
1968
1969	/**
1970	* Display the guest CpuId leaves.
1971	*
1972	* @param pVM VM Handle.
1973	* @param pHlp The info helper functions.
1974	* @param pszArgs "terse", "default" or "verbose".
1975	*/
1976	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1977	{
1978	/*
1979	* Parse the argument.
1980	*/
1981	unsigned iVerbosity = 1;
1982	if (pszArgs)
1983	{
1984	pszArgs = RTStrStripL(pszArgs);
1985	if (!strcmp(pszArgs, "terse"))
1986	iVerbosity--;
1987	else if (!strcmp(pszArgs, "verbose"))
1988	iVerbosity++;
1989	}
1990
1991	/*
1992	* Start cracking.
1993	*/
1994	CPUMCPUID Host;
1995	CPUMCPUID Guest;
1996	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1997
1998	pHlp->pfnPrintf(pHlp,
1999	" RAW Standard CPUIDs\n"
2000	" Function eax ebx ecx edx\n");
2001	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2002	{
2003	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2004	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2005
2006	pHlp->pfnPrintf(pHlp,
2007	"Gst: %08x %08x %08x %08x %08x%s\n"
2008	"Hst: %08x %08x %08x %08x\n",
2009	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2010	i <= cStdMax ? "" : "*",
2011	Host.eax, Host.ebx, Host.ecx, Host.edx);
2012	}
2013
2014	/*
2015	* If verbose, decode it.
2016	*/
2017	if (iVerbosity)
2018	{
2019	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2020	pHlp->pfnPrintf(pHlp,
2021	"Name: %.04s%.04s%.04s\n"
2022	"Supports: 0-%x\n",
2023	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2024	}
2025
2026	/*
2027	* Get Features.
2028	*/
2029	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2030	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2031	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2032	if (cStdMax >= 1 && iVerbosity)
2033	{
2034	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2035	uint32_t uEAX = Guest.eax;
2036
2037	pHlp->pfnPrintf(pHlp,
2038	"Family: %d \tExtended: %d \tEffective: %d\n"
2039	"Model: %d \tExtended: %d \tEffective: %d\n"
2040	"Stepping: %d\n"
2041	"APIC ID: %#04x\n"
2042	"Logical CPUs: %d\n"
2043	"CLFLUSH Size: %d\n"
2044	"Brand ID: %#04x\n",
2045	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2046	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2047	ASMGetCpuStepping(uEAX),
2048	(Guest.ebx >> 24) & 0xff,
2049	(Guest.ebx >> 16) & 0xff,
2050	(Guest.ebx >> 8) & 0xff,
2051	(Guest.ebx >> 0) & 0xff);
2052	if (iVerbosity == 1)
2053	{
2054	uint32_t uEDX = Guest.edx;
2055	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2056	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2057	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2058	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2059	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2060	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2061	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2062	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2063	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2064	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2065	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2066	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2067	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2068	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2069	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2070	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2071	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2072	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2073	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2074	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2075	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2076	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2077	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2078	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2079	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2080	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2081	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2082	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2083	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2084	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2085	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2086	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2087	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2088	pHlp->pfnPrintf(pHlp, "\n");
2089
2090	uint32_t uECX = Guest.ecx;
2091	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2092	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2093	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
2094	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
2095	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2096	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2097	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2098	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
2099	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2100	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2101	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
2102	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2103	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2104	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
2105	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2106	for (unsigned iBit = 14; iBit < 32; iBit++)
2107	if (uECX & RT_BIT(iBit))
2108	pHlp->pfnPrintf(pHlp, " %d", iBit);
2109	pHlp->pfnPrintf(pHlp, "\n");
2110	}
2111	else
2112	{
2113	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2114
2115	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2116	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2117	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2118	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2119
2120	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2121	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2122	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2123	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2124	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2125	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2126	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2127	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2128	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2129	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2130	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2131	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2132	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2133	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2134	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2135	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2136	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2137	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2138	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2139	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2140	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2141	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2142	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2143	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2144	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2145	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2146	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2147	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2148	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2149	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2150	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2151	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2152	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2153
2154	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2155	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2156	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2157	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2158	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2159	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2160	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2161	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2162	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2163	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2164	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2165	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
2166	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2167	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2168	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2169	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2170	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2171	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2172	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2173	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2174	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2175	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2176	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
2177	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2178	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2179	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2180	}
2181	}
2182	if (cStdMax >= 2 && iVerbosity)
2183	{
2184	/** @todo */
2185	}
2186
2187	/*
2188	* Extended.
2189	* Implemented after AMD specs.
2190	*/
2191	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2192
2193	pHlp->pfnPrintf(pHlp,
2194	"\n"
2195	" RAW Extended CPUIDs\n"
2196	" Function eax ebx ecx edx\n");
2197	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2198	{
2199	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2200	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2201
2202	pHlp->pfnPrintf(pHlp,
2203	"Gst: %08x %08x %08x %08x %08x%s\n"
2204	"Hst: %08x %08x %08x %08x\n",
2205	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2206	i <= cExtMax ? "" : "*",
2207	Host.eax, Host.ebx, Host.ecx, Host.edx);
2208	}
2209
2210	/*
2211	* Understandable output
2212	*/
2213	if (iVerbosity)
2214	{
2215	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2216	pHlp->pfnPrintf(pHlp,
2217	"Ext Name: %.4s%.4s%.4s\n"
2218	"Ext Supports: 0x80000000-%#010x\n",
2219	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2220	}
2221
2222	if (iVerbosity && cExtMax >= 1)
2223	{
2224	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2225	uint32_t uEAX = Guest.eax;
2226	pHlp->pfnPrintf(pHlp,
2227	"Family: %d \tExtended: %d \tEffective: %d\n"
2228	"Model: %d \tExtended: %d \tEffective: %d\n"
2229	"Stepping: %d\n"
2230	"Brand ID: %#05x\n",
2231	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2232	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2233	ASMGetCpuStepping(uEAX),
2234	Guest.ebx & 0xfff);
2235
2236	if (iVerbosity == 1)
2237	{
2238	uint32_t uEDX = Guest.edx;
2239	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2240	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2241	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2242	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2243	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2244	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2245	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2246	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2247	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2248	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2249	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2250	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2251	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2252	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2253	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2254	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2255	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2256	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2257	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2258	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2259	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2260	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2261	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2262	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2263	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2264	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2265	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2266	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2267	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2268	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2269	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2270	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2271	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2272	pHlp->pfnPrintf(pHlp, "\n");
2273
2274	uint32_t uECX = Guest.ecx;
2275	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2276	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2277	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2278	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2279	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2280	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2281	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2282	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2283	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2284	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2285	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2286	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2287	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2288	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2289	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2290	for (unsigned iBit = 5; iBit < 32; iBit++)
2291	if (uECX & RT_BIT(iBit))
2292	pHlp->pfnPrintf(pHlp, " %d", iBit);
2293	pHlp->pfnPrintf(pHlp, "\n");
2294	}
2295	else
2296	{
2297	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2298
2299	uint32_t uEdxGst = Guest.edx;
2300	uint32_t uEdxHst = Host.edx;
2301	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2302	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2303	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2304	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2305	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2306	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2307	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2308	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2309	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2310	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2311	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2312	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2313	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2314	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2315	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2316	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2317	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2318	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2319	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2320	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2321	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2322	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2323	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2324	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2325	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2326	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2327	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2328	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2329	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2330	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2331	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2332	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2333	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2334
2335	uint32_t uEcxGst = Guest.ecx;
2336	uint32_t uEcxHst = Host.ecx;
2337	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2338	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2339	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2340	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2341	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2342	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2343	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2344	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2345	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2346	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2347	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2348	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2349	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2350	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2351	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2352	}
2353	}
2354
2355	if (iVerbosity && cExtMax >= 2)
2356	{
2357	char szString[443+1] = {0};
2358	uint32_t pu32 = (uint32_t )szString;
2359	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2360	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2361	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2362	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2363	if (cExtMax >= 3)
2364	{
2365	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2366	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2367	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2368	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2369	}
2370	if (cExtMax >= 4)
2371	{
2372	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2373	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2374	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2375	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2376	}
2377	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2378	}
2379
2380	if (iVerbosity && cExtMax >= 5)
2381	{
2382	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2383	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2384	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2385	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2386	char sz1[32];
2387	char sz2[32];
2388
2389	pHlp->pfnPrintf(pHlp,
2390	"TLB 2/4M Instr/Uni: %s %3d entries\n"
2391	"TLB 2/4M Data: %s %3d entries\n",
2392	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2393	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2394	pHlp->pfnPrintf(pHlp,
2395	"TLB 4K Instr/Uni: %s %3d entries\n"
2396	"TLB 4K Data: %s %3d entries\n",
2397	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2398	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2399	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2400	"L1 Instr Cache Lines Per Tag: %d\n"
2401	"L1 Instr Cache Associativity: %s\n"
2402	"L1 Instr Cache Size: %d KB\n",
2403	(uEDX >> 0) & 0xff,
2404	(uEDX >> 8) & 0xff,
2405	getCacheAss((uEDX >> 16) & 0xff, sz1),
2406	(uEDX >> 24) & 0xff);
2407	pHlp->pfnPrintf(pHlp,
2408	"L1 Data Cache Line Size: %d bytes\n"
2409	"L1 Data Cache Lines Per Tag: %d\n"
2410	"L1 Data Cache Associativity: %s\n"
2411	"L1 Data Cache Size: %d KB\n",
2412	(uECX >> 0) & 0xff,
2413	(uECX >> 8) & 0xff,
2414	getCacheAss((uECX >> 16) & 0xff, sz1),
2415	(uECX >> 24) & 0xff);
2416	}
2417
2418	if (iVerbosity && cExtMax >= 6)
2419	{
2420	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2421	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2422	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2423
2424	pHlp->pfnPrintf(pHlp,
2425	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2426	"L2 TLB 2/4M Data: %s %4d entries\n",
2427	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2428	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2429	pHlp->pfnPrintf(pHlp,
2430	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
2431	"L2 TLB 4K Data: %s %4d entries\n",
2432	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2433	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2434	pHlp->pfnPrintf(pHlp,
2435	"L2 Cache Line Size: %d bytes\n"
2436	"L2 Cache Lines Per Tag: %d\n"
2437	"L2 Cache Associativity: %s\n"
2438	"L2 Cache Size: %d KB\n",
2439	(uEDX >> 0) & 0xff,
2440	(uEDX >> 8) & 0xf,
2441	getL2CacheAss((uEDX >> 12) & 0xf),
2442	(uEDX >> 16) & 0xffff);
2443	}
2444
2445	if (iVerbosity && cExtMax >= 7)
2446	{
2447	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2448
2449	pHlp->pfnPrintf(pHlp, "APM Features: ");
2450	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2451	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2452	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2453	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2454	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2455	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2456	for (unsigned iBit = 6; iBit < 32; iBit++)
2457	if (uEDX & RT_BIT(iBit))
2458	pHlp->pfnPrintf(pHlp, " %d", iBit);
2459	pHlp->pfnPrintf(pHlp, "\n");
2460	}
2461
2462	if (iVerbosity && cExtMax >= 8)
2463	{
2464	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2465	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2466
2467	pHlp->pfnPrintf(pHlp,
2468	"Physical Address Width: %d bits\n"
2469	"Virtual Address Width: %d bits\n",
2470	(uEAX >> 0) & 0xff,
2471	(uEAX >> 8) & 0xff);
2472	pHlp->pfnPrintf(pHlp,
2473	"Physical Core Count: %d\n",
2474	(uECX >> 0) & 0xff);
2475	}
2476
2477
2478	/*
2479	* Centaur.
2480	*/
2481	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2482
2483	pHlp->pfnPrintf(pHlp,
2484	"\n"
2485	" RAW Centaur CPUIDs\n"
2486	" Function eax ebx ecx edx\n");
2487	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2488	{
2489	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2490	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2491
2492	pHlp->pfnPrintf(pHlp,
2493	"Gst: %08x %08x %08x %08x %08x%s\n"
2494	"Hst: %08x %08x %08x %08x\n",
2495	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2496	i <= cCentaurMax ? "" : "*",
2497	Host.eax, Host.ebx, Host.ecx, Host.edx);
2498	}
2499
2500	/*
2501	* Understandable output
2502	*/
2503	if (iVerbosity)
2504	{
2505	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2506	pHlp->pfnPrintf(pHlp,
2507	"Centaur Supports: 0xc0000000-%#010x\n",
2508	Guest.eax);
2509	}
2510
2511	if (iVerbosity && cCentaurMax >= 1)
2512	{
2513	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2514	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2515	uint32_t uEdxHst = Host.edx;
2516
2517	if (iVerbosity == 1)
2518	{
2519	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2520	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2521	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2522	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2523	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2524	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2525	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2526	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2527	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2528	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2529	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2530	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2531	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2532	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2533	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2534	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2535	for (unsigned iBit = 14; iBit < 32; iBit++)
2536	if (uEdxGst & RT_BIT(iBit))
2537	pHlp->pfnPrintf(pHlp, " %d", iBit);
2538	pHlp->pfnPrintf(pHlp, "\n");
2539	}
2540	else
2541	{
2542	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2543	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2544	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2545	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2546	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2547	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2548	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2549	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2550	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2551	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2552	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2553	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2554	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2555	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2556	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2557	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2558	for (unsigned iBit = 14; iBit < 32; iBit++)
2559	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
2560	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2561	pHlp->pfnPrintf(pHlp, "\n");
2562	}
2563	}
2564	}
2565
2566
2567	/**
2568	* Structure used when disassembling and instructions in DBGF.
2569	* This is used so the reader function can get the stuff it needs.
2570	*/
2571	typedef struct CPUMDISASSTATE
2572	{
2573	/** Pointer to the CPU structure. */
2574	PDISCPUSTATE pCpu;
2575	/** The VM handle. */
2576	PVM pVM;
2577	/** The VMCPU handle. */
2578	PVMCPU pVCpu;
2579	/** Pointer to the first byte in the segemnt. */
2580	RTGCUINTPTR GCPtrSegBase;
2581	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2582	RTGCUINTPTR GCPtrSegEnd;
2583	/** The size of the segment minus 1. */
2584	RTGCUINTPTR cbSegLimit;
2585	/** Pointer to the current page - R3 Ptr. */
2586	void const *pvPageR3;
2587	/** Pointer to the current page - GC Ptr. */
2588	RTGCPTR pvPageGC;
2589	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2590	PGMPAGEMAPLOCK PageMapLock;
2591	/** Whether the PageMapLock is valid or not. */
2592	bool fLocked;
2593	/** 64 bits mode or not. */
2594	bool f64Bits;
2595	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2596
2597
2598	/**
2599	* Instruction reader.
2600	*
2601	* @returns VBox status code.
2602	* @param PtrSrc Address to read from.
2603	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2604	* @param pu8Dst Where to store the bytes.
2605	* @param cbRead Number of bytes to read.
2606	* @param uDisCpu Pointer to the disassembler cpu state.
2607	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
2608	*/
2609	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
2610	{
2611	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2612	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2613	Assert(cbRead > 0);
2614	for (;;)
2615	{
2616	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2617
2618	/* Need to update the page translation? */
2619	if ( !pState->pvPageR3
2620	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2621	{
2622	int rc = VINF_SUCCESS;
2623
2624	/* translate the address */
2625	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2626	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2627	&& !HWACCMIsEnabled(pState->pVM))
2628	{
2629	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2630	if (!pState->pvPageR3)
2631	rc = VERR_INVALID_POINTER;
2632	}
2633	else
2634	{
2635	/* Release mapping lock previously acquired. */
2636	if (pState->fLocked)
2637	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2638	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2639	pState->fLocked = RT_SUCCESS_NP(rc);
2640	}
2641	if (RT_FAILURE(rc))
2642	{
2643	pState->pvPageR3 = NULL;
2644	return rc;
2645	}
2646	}
2647
2648	/* check the segemnt limit */
2649	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2650	return VERR_OUT_OF_SELECTOR_BOUNDS;
2651
2652	/* calc how much we can read */
2653	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2654	if (!pState->f64Bits)
2655	{
2656	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2657	if (cb > cbSeg && cbSeg)
2658	cb = cbSeg;
2659	}
2660	if (cb > cbRead)
2661	cb = cbRead;
2662
2663	/* read and advance */
2664	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2665	cbRead -= cb;
2666	if (!cbRead)
2667	return VINF_SUCCESS;
2668	pu8Dst += cb;
2669	PtrSrc += cb;
2670	}
2671	}
2672
2673
2674	/**
2675	* Disassemble an instruction and return the information in the provided structure.
2676	*
2677	* @returns VBox status code.
2678	* @param pVM VM Handle
2679	* @param pVCpu VMCPU Handle
2680	* @param pCtx CPU context
2681	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2682	* @param pCpu Disassembly state
2683	* @param pszPrefix String prefix for logging (debug only)
2684	*
2685	*/
2686	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2687	{
2688	CPUMDISASSTATE State;
2689	int rc;
2690
2691	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2692	State.pCpu = pCpu;
2693	State.pvPageGC = 0;
2694	State.pvPageR3 = NULL;
2695	State.pVM = pVM;
2696	State.pVCpu = pVCpu;
2697	State.fLocked = false;
2698	State.f64Bits = false;
2699
2700	/*
2701	* Get selector information.
2702	*/
2703	if ( (pCtx->cr0 & X86_CR0_PE)
2704	&& pCtx->eflags.Bits.u1VM == 0)
2705	{
2706	if (CPUMAreHiddenSelRegsValid(pVM))
2707	{
2708	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2709	State.GCPtrSegBase = pCtx->csHid.u64Base;
2710	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2711	State.cbSegLimit = pCtx->csHid.u32Limit;
2712	pCpu->mode = (State.f64Bits)
2713	? CPUMODE_64BIT
2714	: pCtx->csHid.Attr.n.u1DefBig
2715	? CPUMODE_32BIT
2716	: CPUMODE_16BIT;
2717	}
2718	else
2719	{
2720	DBGFSELINFO SelInfo;
2721
2722	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2723	if (RT_FAILURE(rc))
2724	{
2725	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2726	return rc;
2727	}
2728
2729	/*
2730	* Validate the selector.
2731	*/
2732	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2733	if (RT_FAILURE(rc))
2734	{
2735	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2736	return rc;
2737	}
2738	State.GCPtrSegBase = SelInfo.GCPtrBase;
2739	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2740	State.cbSegLimit = SelInfo.cbLimit;
2741	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2742	}
2743	}
2744	else
2745	{
2746	/* real or V86 mode */
2747	pCpu->mode = CPUMODE_16BIT;
2748	State.GCPtrSegBase = pCtx->cs * 16;
2749	State.GCPtrSegEnd = 0xFFFFFFFF;
2750	State.cbSegLimit = 0xFFFFFFFF;
2751	}
2752
2753	/*
2754	* Disassemble the instruction.
2755	*/
2756	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2757	pCpu->apvUserData[0] = &State;
2758
2759	uint32_t cbInstr;
2760	#ifndef LOG_ENABLED
2761	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2762	if (RT_SUCCESS(rc))
2763	{
2764	#else
2765	char szOutput[160];
2766	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2767	if (RT_SUCCESS(rc))
2768	{
2769	/* log it */
2770	if (pszPrefix)
2771	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2772	else
2773	Log(("%s", szOutput));
2774	#endif
2775	rc = VINF_SUCCESS;
2776	}
2777	else
2778	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2779
2780	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2781	if (State.fLocked)
2782	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2783
2784	return rc;
2785	}
2786
2787	#ifdef DEBUG
2788
2789	/**
2790	* Disassemble an instruction and dump it to the log
2791	*
2792	* @returns VBox status code.
2793	* @param pVM VM Handle
2794	* @param pVCpu VMCPU Handle
2795	* @param pCtx CPU context
2796	* @param pc GC instruction pointer
2797	* @param pszPrefix String prefix for logging
2798	*
2799	* @deprecated Use DBGFR3DisasInstrCurrentLog().
2800	*/
2801	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2802	{
2803	DISCPUSTATE Cpu;
2804	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2805	}
2806
2807
2808	/**
2809	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
2810	*
2811	* @internal
2812	*/
2813	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2814	{
2815	/* @todo SMP support!! */
2816	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2817	}
2818
2819	#endif /* DEBUG */
2820
2821	/**
2822	* API for controlling a few of the CPU features found in CR4.
2823	*
2824	* Currently only X86_CR4_TSD is accepted as input.
2825	*
2826	* @returns VBox status code.
2827	*
2828	* @param pVM The VM handle.
2829	* @param fOr The CR4 OR mask.
2830	* @param fAnd The CR4 AND mask.
2831	*/
2832	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2833	{
2834	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2835	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2836
2837	pVM->cpum.s.CR4.OrMask &= fAnd;
2838	pVM->cpum.s.CR4.OrMask \|= fOr;
2839
2840	return VINF_SUCCESS;
2841	}
2842
2843
2844	/**
2845	* Gets a pointer to the array of standard CPUID leaves.
2846	*
2847	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2848	*
2849	* @returns Pointer to the standard CPUID leaves (read-only).
2850	* @param pVM The VM handle.
2851	* @remark Intended for PATM.
2852	*/
2853	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2854	{
2855	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2856	}
2857
2858
2859	/**
2860	* Gets a pointer to the array of extended CPUID leaves.
2861	*
2862	* CPUMGetGuestCpuIdExtMax() give the size of the array.
2863	*
2864	* @returns Pointer to the extended CPUID leaves (read-only).
2865	* @param pVM The VM handle.
2866	* @remark Intended for PATM.
2867	*/
2868	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2869	{
2870	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2871	}
2872
2873
2874	/**
2875	* Gets a pointer to the array of centaur CPUID leaves.
2876	*
2877	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2878	*
2879	* @returns Pointer to the centaur CPUID leaves (read-only).
2880	* @param pVM The VM handle.
2881	* @remark Intended for PATM.
2882	*/
2883	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2884	{
2885	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2886	}
2887
2888
2889	/**
2890	* Gets a pointer to the default CPUID leaf.
2891	*
2892	* @returns Pointer to the default CPUID leaf (read-only).
2893	* @param pVM The VM handle.
2894	* @remark Intended for PATM.
2895	*/
2896	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2897	{
2898	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2899	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 24332

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