CPUM.cpp@ 26871

Last change on this file since 26871 was 26664, checked in by vboxsync, 15 years ago
CPUM: use symbolic constants for wait extensions
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1	/* $Id: CPUM.cpp 26664 2010-02-19 15:16:39Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/mm.h>
46	#include <VBox/selm.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/patm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The current saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatability. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detech the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Initializes the per-VCPU CPUM.
244	*
245	* @returns VBox status code.
246	* @param pVM The VM to operate on.
247	*/
248	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
249	{
250	LogFlow(("CPUMR3InitCPU\n"));
251	return VINF_SUCCESS;
252	}
253
254
255	/**
256	* Detect the CPU vendor give n the
257	*
258	* @returns The vendor.
259	* @param uEAX EAX from CPUID(0).
260	* @param uEBX EBX from CPUID(0).
261	* @param uECX ECX from CPUID(0).
262	* @param uEDX EDX from CPUID(0).
263	*/
264	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
265	{
266	if ( uEAX >= 1
267	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
268	&& uECX == X86_CPUID_VENDOR_AMD_ECX
269	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
270	return CPUMCPUVENDOR_AMD;
271
272	if ( uEAX >= 1
273	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
274	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
275	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
276	return CPUMCPUVENDOR_INTEL;
277
278	/** @todo detect the other buggers... */
279	return CPUMCPUVENDOR_UNKNOWN;
280	}
281
282
283	/**
284	* Fetches overrides for a CPUID leaf.
285	*
286	* @returns VBox status code.
287	* @param pLeaf The leaf to load the overrides into.
288	* @param pCfgNode The CFGM node containing the overrides
289	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
290	* @param iLeaf The CPUID leaf number.
291	*/
292	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
293	{
294	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
295	if (pLeafNode)
296	{
297	uint32_t u32;
298	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
299	if (RT_SUCCESS(rc))
300	pLeaf->eax = u32;
301	else
302	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
303
304	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
305	if (RT_SUCCESS(rc))
306	pLeaf->ebx = u32;
307	else
308	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
309
310	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
311	if (RT_SUCCESS(rc))
312	pLeaf->ecx = u32;
313	else
314	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
315
316	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
317	if (RT_SUCCESS(rc))
318	pLeaf->edx = u32;
319	else
320	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
321
322	}
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Load the overrides for a set of CPUID leafs.
329	*
330	* @returns VBox status code.
331	* @param paLeafs The leaf array.
332	* @param cLeafs The number of leafs.
333	* @param uStart The start leaf number.
334	* @param pCfgNode The CFGM node containing the overrides
335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
336	*/
337	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
338	{
339	for (uint32_t i = 0; i < cLeafs; i++)
340	{
341	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
342	if (RT_FAILURE(rc))
343	return rc;
344	}
345
346	return VINF_SUCCESS;
347	}
348
349	/**
350	* Init a set of host CPUID leafs.
351	*
352	* @returns VBox status code.
353	* @param paLeafs The leaf array.
354	* @param cLeafs The number of leafs.
355	* @param uStart The start leaf number.
356	* @param pCfgNode The /CPUM/HostCPUID/ node.
357	*/
358	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
359	{
360	/* Using the ECX variant for all of them can't hurt... */
361	for (uint32_t i = 0; i < cLeafs; i++)
362	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
363
364	/* Load CPUID leaf override; we currently don't care if the caller
365	specifies features the host CPU doesn't support. */
366	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
367	}
368
369
370	/**
371	* Initializes the emulated CPU's cpuid information.
372	*
373	* @returns VBox status code.
374	* @param pVM The VM to operate on.
375	*/
376	static int cpumR3CpuIdInit(PVM pVM)
377	{
378	PCPUM pCPUM = &pVM->cpum.s;
379	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
380	uint32_t i;
381	int rc;
382
383	/*
384	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
385	*/
386	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
387	* Overrides the host CPUID leaf values used for calculating the guest CPUID
388	* leafs. This can be used to preserve the CPUID values when moving a VM to
389	* a different machine. Another use is restricting (or extending) the
390	* feature set exposed to the guest. */
391	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
392	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
393	AssertRCReturn(rc, rc);
394	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
395	AssertRCReturn(rc, rc);
396	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
397	AssertRCReturn(rc, rc);
398
399	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
400	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
401
402	/*
403	* Only report features we can support.
404	*/
405	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
406	\| X86_CPUID_FEATURE_EDX_VME
407	\| X86_CPUID_FEATURE_EDX_DE
408	\| X86_CPUID_FEATURE_EDX_PSE
409	\| X86_CPUID_FEATURE_EDX_TSC
410	\| X86_CPUID_FEATURE_EDX_MSR
411	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
412	\| X86_CPUID_FEATURE_EDX_MCE
413	\| X86_CPUID_FEATURE_EDX_CX8
414	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
415	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
416	//\| X86_CPUID_FEATURE_EDX_SEP
417	\| X86_CPUID_FEATURE_EDX_MTRR
418	\| X86_CPUID_FEATURE_EDX_PGE
419	\| X86_CPUID_FEATURE_EDX_MCA
420	\| X86_CPUID_FEATURE_EDX_CMOV
421	\| X86_CPUID_FEATURE_EDX_PAT
422	\| X86_CPUID_FEATURE_EDX_PSE36
423	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
424	\| X86_CPUID_FEATURE_EDX_CLFSH
425	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
426	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
427	\| X86_CPUID_FEATURE_EDX_MMX
428	\| X86_CPUID_FEATURE_EDX_FXSR
429	\| X86_CPUID_FEATURE_EDX_SSE
430	\| X86_CPUID_FEATURE_EDX_SSE2
431	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
432	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
433	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
434	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
435	\| 0;
436	pCPUM->aGuestCpuIdStd[1].ecx &= 0
437	\| X86_CPUID_FEATURE_ECX_SSE3
438	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
439	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
440	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
441	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
442	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
443	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
444	\| X86_CPUID_FEATURE_ECX_SSSE3
445	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
446	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
447	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
448	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
449	/* ECX Bit 21 - x2APIC support - not yet. */
450	// \| X86_CPUID_FEATURE_ECX_X2APIC
451	/* ECX Bit 23 - POPCNT instruction. */
452	//\| X86_CPUID_FEATURE_ECX_POPCNT
453	\| 0;
454
455	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
456	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
457	\| X86_CPUID_AMD_FEATURE_EDX_VME
458	\| X86_CPUID_AMD_FEATURE_EDX_DE
459	\| X86_CPUID_AMD_FEATURE_EDX_PSE
460	\| X86_CPUID_AMD_FEATURE_EDX_TSC
461	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
462	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
463	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
464	\| X86_CPUID_AMD_FEATURE_EDX_CX8
465	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
467	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
468	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
469	\| X86_CPUID_AMD_FEATURE_EDX_PGE
470	\| X86_CPUID_AMD_FEATURE_EDX_MCA
471	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
472	\| X86_CPUID_AMD_FEATURE_EDX_PAT
473	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
474	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
475	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
476	\| X86_CPUID_AMD_FEATURE_EDX_MMX
477	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
478	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
479	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
480	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
481	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
484	\| 0;
485	pCPUM->aGuestCpuIdExt[1].ecx &= 0
486	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
487	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
488	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
489	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
490	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
491	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
492	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
493	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
494	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
495	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
496	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
497	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
498	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
499	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
500	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
501	\| 0;
502
503	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
504	if (pCPUM->fSyntheticCpu)
505	{
506	const char szVendor[13] = "VirtualBox ";
507	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
508
509	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
510
511	/* Limit the nr of standard leaves; 5 for monitor/mwait */
512	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
513
514	/* 0: Vendor */
515	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
516	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
517	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
518
519	/* 1.eax: Version information. family : model : stepping */
520	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
521
522	/* Leaves 2 - 4 are Intel only - zero them out */
523	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
524	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
525	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
526
527	/* Leaf 5 = monitor/mwait */
528
529	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
530	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
531	/* AMD only - set to zero. */
532	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
533
534	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
535	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
536
537	/* 0x800000002-4: Processor Name String Identifier. */
538	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
539	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
540	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
541	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
542	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
543	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
544	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
545	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
546	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
547	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
548	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
549	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
550
551	/* 0x800000005-7 - reserved -> zero */
552	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
553	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
554	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
555
556	/* 0x800000008: only the max virtual and physical address size. */
557	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
558	}
559
560	/*
561	* Hide HTT, multicode, SMP, whatever.
562	* (APIC-ID := 0 and #LogCpus := 0)
563	*/
564	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
565	#ifdef VBOX_WITH_MULTI_CORE
566	if (pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
567	{
568	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
569	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
570	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
571	}
572	#endif
573
574	/* Cpuid 2:
575	* Intel: Cache and TLB information
576	* AMD: Reserved
577	* Safe to expose
578	*/
579
580	/* Cpuid 3:
581	* Intel: EAX, EBX - reserved
582	* ECX, EDX - Processor Serial Number if available, otherwise reserved
583	* AMD: Reserved
584	* Safe to expose
585	*/
586	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
587	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
588
589	/* Cpuid 4:
590	* Intel: Deterministic Cache Parameters Leaf
591	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
592	* AMD: Reserved
593	* Safe to expose, except for EAX:
594	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
595	* Bits 31-26: Maximum number of processor cores in this physical package**
596	* Note: These SMP values are constant regardless of ECX
597	*/
598	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
599	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
600	#ifdef VBOX_WITH_MULTI_CORE
601	if ( pVM->cCpus > 1
602	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
603	{
604	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
605	/* One logical processor with possibly multiple cores. */
606	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
607	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
608	}
609	#endif
610
611	/* Cpuid 5: Monitor/mwait Leaf
612	* Intel: ECX, EDX - reserved
613	* EAX, EBX - Smallest and largest monitor line size
614	* AMD: EDX - reserved
615	* EAX, EBX - Smallest and largest monitor line size
616	* ECX - extensions (ignored for now)
617	* Safe to expose
618	*/
619	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
620	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
621
622	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
623	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
624	* Expose MWAIT extended features to the guest.
625	* For now we expose just MWAIT break on interrupt feature (bit 1)
626	*/
627	bool fMWaitExtensions;
628	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
629	if (fMWaitExtensions)
630	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
631
632	/*
633	* Determine the default.
634	*
635	* Intel returns values of the highest standard function, while AMD
636	* returns zeros. VIA on the other hand seems to returning nothing or
637	* perhaps some random garbage, we don't try to duplicate this behavior.
638	*/
639	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
640	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
641	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
642
643	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
644	* Safe to pass on to the guest.
645	*
646	* Intel: 0x800000005 reserved
647	* 0x800000006 L2 cache information
648	* AMD: 0x800000005 L1 cache information
649	* 0x800000006 L2/L3 cache information
650	*/
651
652	/* Cpuid 0x800000007:
653	* AMD: EAX, EBX, ECX - reserved
654	* EDX: Advanced Power Management Information
655	* Intel: Reserved
656	*/
657	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
658	{
659	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
660
661	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
662
663	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
664	{
665	/* Only expose the TSC invariant capability bit to the guest. */
666	pCPUM->aGuestCpuIdExt[7].edx &= 0
667	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
668	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
669	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
670	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
671	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
672	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
673	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
674	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
675	#if 1
676	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
677	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
678	*/
679	#else
680	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
681	#endif
682	\| 0;
683	}
684	else
685	pCPUM->aGuestCpuIdExt[7].edx = 0;
686	}
687
688	/* Cpuid 0x800000008:
689	* AMD: EBX, EDX - reserved
690	* EAX: Virtual/Physical address Size
691	* ECX: Number of cores + APICIdCoreIdSize
692	* Intel: EAX: Virtual/Physical address Size
693	* EBX, ECX, EDX - reserved
694	*/
695	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
696	{
697	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
698	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
699	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
700	* NC (0-7) Number of cores; 0 equals 1 core */
701	pCPUM->aGuestCpuIdExt[8].ecx = 0;
702	#ifdef VBOX_WITH_MULTI_CORE
703	if ( pVM->cCpus > 1
704	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
705	{
706	/* Legacy method to determine the number of cores. */
707	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
708	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
709
710	}
711	#endif
712	}
713
714	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
715	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
716	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
717	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
718	*/
719	bool fNt4LeafLimit;
720	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
721	if (fNt4LeafLimit)
722	pCPUM->aGuestCpuIdStd[0].eax = 3;
723
724	/*
725	* Limit it the number of entries and fill the remaining with the defaults.
726	*
727	* The limits are masking off stuff about power saving and similar, this
728	* is perhaps a bit crudely done as there is probably some relatively harmless
729	* info too in these leaves (like words about having a constant TSC).
730	*/
731	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
732	pCPUM->aGuestCpuIdStd[0].eax = 5;
733
734	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
735	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
736
737	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
738	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
739	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
740	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
741	: 0;
742	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
743	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
744
745	/*
746	* Centaur stuff (VIA).
747	*
748	* The important part here (we think) is to make sure the 0xc0000000
749	* function returns 0xc0000001. As for the features, we don't currently
750	* let on about any of those... 0xc0000002 seems to be some
751	* temperature/hz/++ stuff, include it as well (static).
752	*/
753	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
754	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
755	{
756	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
757	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
758	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
759	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
760	i++)
761	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
762	}
763	else
764	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
765	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
766
767
768	/*
769	* Load CPUID overrides from configuration.
770	* Note: Kind of redundant now, but allows unchanged overrides
771	*/
772	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
773	* Overrides the CPUID leaf values. */
774	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
775	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
776	AssertRCReturn(rc, rc);
777	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
778	AssertRCReturn(rc, rc);
779	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
780	AssertRCReturn(rc, rc);
781
782	/*
783	* Check if PAE was explicitely enabled by the user.
784	*/
785	bool fEnable;
786	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
787	if (fEnable)
788	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
789
790	/*
791	* Log the cpuid and we're good.
792	*/
793	RTCPUSET OnlineSet;
794	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
795	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
796	LogRel(("*********************** CPUID dump **********************\n"));
797	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
798	LogRel(("\n"));
799	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
800	LogRel(("****************** End of CPUID dump ********************\n"));
801	return VINF_SUCCESS;
802	}
803
804
805
806
807	/**
808	* Applies relocations to data and code managed by this
809	* component. This function will be called at init and
810	* whenever the VMM need to relocate it self inside the GC.
811	*
812	* The CPUM will update the addresses used by the switcher.
813	*
814	* @param pVM The VM.
815	*/
816	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
817	{
818	LogFlow(("CPUMR3Relocate\n"));
819	for (VMCPUID i = 0; i < pVM->cCpus; i++)
820	{
821	/*
822	* Switcher pointers.
823	*/
824	PVMCPU pVCpu = &pVM->aCpus[i];
825	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
826	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
827
828	}
829	}
830
831
832	/**
833	* Apply late CPUM property changes based on the fHWVirtEx setting
834	*
835	* @param pVM The VM to operate on.
836	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
837	*/
838	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
839	{
840	/*
841	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
842	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
843	* of processors from (cpuid(4).eax >> 26) + 1.
844	*
845	* Note: this code is obsolete, but let's keep it here for reference.
846	* Purpose is valid when we artifically cap the max std id to less than 4.
847	*/
848	if (!fHWVirtExEnabled)
849	{
850	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
851	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
852	}
853	}
854
855	/**
856	* Terminates the CPUM.
857	*
858	* Termination means cleaning up and freeing all resources,
859	* the VM it self is at this point powered off or suspended.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM to operate on.
863	*/
864	VMMR3DECL(int) CPUMR3Term(PVM pVM)
865	{
866	CPUMR3TermCPU(pVM);
867	return 0;
868	}
869
870
871	/**
872	* Terminates the per-VCPU CPUM.
873	*
874	* Termination means cleaning up and freeing all resources,
875	* the VM it self is at this point powered off or suspended.
876	*
877	* @returns VBox status code.
878	* @param pVM The VM to operate on.
879	*/
880	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
881	{
882	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
883	for (VMCPUID i = 0; i < pVM->cCpus; i++)
884	{
885	PVMCPU pVCpu = &pVM->aCpus[i];
886	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
887
888	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
889	pVCpu->cpum.s.uMagic = 0;
890	pCtx->dr[5] = 0;
891	}
892	#endif
893	return 0;
894	}
895
896
897	/**
898	* Resets a virtual CPU.
899	*
900	* Used by CPUMR3Reset and CPU hot plugging.
901	*
902	* @param pVCpu The virtual CPU handle.
903	*/
904	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
905	{
906	/** @todo anything different for VCPU > 0? */
907	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
908
909	/*
910	* Initialize everything to ZERO first.
911	*/
912	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
913	memset(pCtx, 0, sizeof(*pCtx));
914	pVCpu->cpum.s.fUseFlags = fUseFlags;
915
916	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
917	pCtx->eip = 0x0000fff0;
918	pCtx->edx = 0x00000600; /* P6 processor */
919	pCtx->eflags.Bits.u1Reserved0 = 1;
920
921	pCtx->cs = 0xf000;
922	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
923	pCtx->csHid.u32Limit = 0x0000ffff;
924	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
925	pCtx->csHid.Attr.n.u1Present = 1;
926	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
927
928	pCtx->dsHid.u32Limit = 0x0000ffff;
929	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
930	pCtx->dsHid.Attr.n.u1Present = 1;
931	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
932
933	pCtx->esHid.u32Limit = 0x0000ffff;
934	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
935	pCtx->esHid.Attr.n.u1Present = 1;
936	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
937
938	pCtx->fsHid.u32Limit = 0x0000ffff;
939	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
940	pCtx->fsHid.Attr.n.u1Present = 1;
941	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
942
943	pCtx->gsHid.u32Limit = 0x0000ffff;
944	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
945	pCtx->gsHid.Attr.n.u1Present = 1;
946	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
947
948	pCtx->ssHid.u32Limit = 0x0000ffff;
949	pCtx->ssHid.Attr.n.u1Present = 1;
950	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
951	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
952
953	pCtx->idtr.cbIdt = 0xffff;
954	pCtx->gdtr.cbGdt = 0xffff;
955
956	pCtx->ldtrHid.u32Limit = 0xffff;
957	pCtx->ldtrHid.Attr.n.u1Present = 1;
958	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
959
960	pCtx->trHid.u32Limit = 0xffff;
961	pCtx->trHid.Attr.n.u1Present = 1;
962	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
963
964	pCtx->dr[6] = X86_DR6_INIT_VAL;
965	pCtx->dr[7] = X86_DR7_INIT_VAL;
966
967	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
968	pCtx->fpu.FCW = 0x37f;
969
970	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
971	pCtx->fpu.MXCSR = 0x1F80;
972
973	/* Init PAT MSR */
974	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
975
976	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
977	* The Intel docs don't mention it.
978	*/
979	pCtx->msrEFER = 0;
980	}
981
982
983	/**
984	* Resets the CPU.
985	*
986	* @returns VINF_SUCCESS.
987	* @param pVM The VM handle.
988	*/
989	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
990	{
991	for (VMCPUID i = 0; i < pVM->cCpus; i++)
992	{
993	CPUMR3ResetCpu(&pVM->aCpus[i]);
994
995	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
996	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
997
998	/* Magic marker for searching in crash dumps. */
999	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1000	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1001	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1002	#endif
1003	}
1004	}
1005
1006
1007	/**
1008	* Called both in pass 0 and the final pass.
1009	*
1010	* @param pVM The VM handle.
1011	* @param pSSM The saved state handle.
1012	*/
1013	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1014	{
1015	/*
1016	* Save all the CPU ID leaves here so we can check them for compatability
1017	* upon loading.
1018	*/
1019	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1020	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1021
1022	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1023	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1024
1025	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1026	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1027
1028	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1029
1030	/*
1031	* Save a good portion of the raw CPU IDs as well as they may come in
1032	* handy when validating features for raw mode.
1033	*/
1034	CPUMCPUID aRawStd[16];
1035	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1036	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1037	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1038	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1039
1040	CPUMCPUID aRawExt[32];
1041	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1042	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1043	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1044	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1045	}
1046
1047
1048	/**
1049	* Loads the CPU ID leaves saved by pass 0.
1050	*
1051	* @returns VBox status code.
1052	* @param pVM The VM handle.
1053	* @param pSSM The saved state handle.
1054	* @param uVersion The format version.
1055	*/
1056	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1057	{
1058	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1059
1060	/*
1061	* Define a bunch of macros for simplifying the code.
1062	*/
1063	/* Generic expression + failure message. */
1064	#define CPUID_CHECK_RET(expr, fmt) \
1065	do { \
1066	if (!(expr)) \
1067	{ \
1068	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1069	if (fStrictCpuIdChecks) \
1070	{ \
1071	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1072	RTStrFree(pszMsg); \
1073	return rcCpuid; \
1074	} \
1075	LogRel(("CPUM: %s\n", pszMsg)); \
1076	RTStrFree(pszMsg); \
1077	} \
1078	} while (0)
1079	#define CPUID_CHECK_WRN(expr, fmt) \
1080	do { \
1081	if (!(expr)) \
1082	LogRel(fmt); \
1083	} while (0)
1084
1085	/* For comparing two values and bitch if they differs. */
1086	#define CPUID_CHECK2_RET(what, host, saved) \
1087	do { \
1088	if ((host) != (saved)) \
1089	{ \
1090	if (fStrictCpuIdChecks) \
1091	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1092	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1093	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1094	} \
1095	} while (0)
1096	#define CPUID_CHECK2_WRN(what, host, saved) \
1097	do { \
1098	if ((host) != (saved)) \
1099	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1100	} while (0)
1101
1102	/* For checking raw cpu features (raw mode). */
1103	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1104	do { \
1105	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1106	{ \
1107	if (fStrictCpuIdChecks) \
1108	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1109	N_(#bit " mismatch: host=%d saved=%d"), \
1110	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1111	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1112	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1113	} \
1114	} while (0)
1115	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1116	do { \
1117	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1118	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1119	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1120	} while (0)
1121	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1122
1123	/* For checking guest features. */
1124	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1125	do { \
1126	if ( (aGuestCpuId##set [1].reg & bit) \
1127	&& !(aHostRaw##set [1].reg & bit) \
1128	&& !(aHostOverride##set [1].reg & bit) \
1129	&& !(aGuestOverride##set [1].reg & bit) \
1130	) \
1131	{ \
1132	if (fStrictCpuIdChecks) \
1133	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1134	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1135	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1136	} \
1137	} while (0)
1138	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1139	do { \
1140	if ( (aGuestCpuId##set [1].reg & bit) \
1141	&& !(aHostRaw##set [1].reg & bit) \
1142	&& !(aHostOverride##set [1].reg & bit) \
1143	&& !(aGuestOverride##set [1].reg & bit) \
1144	) \
1145	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1146	} while (0)
1147	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1148	do { \
1149	if ( (aGuestCpuId##set [1].reg & bit) \
1150	&& !(aHostRaw##set [1].reg & bit) \
1151	&& !(aHostOverride##set [1].reg & bit) \
1152	&& !(aGuestOverride##set [1].reg & bit) \
1153	) \
1154	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1155	} while (0)
1156	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1157
1158	/* For checking guest features if AMD guest CPU. */
1159	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1160	do { \
1161	if ( (aGuestCpuId##set [1].reg & bit) \
1162	&& fGuestAmd \
1163	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1164	&& !(aHostOverride##set [1].reg & bit) \
1165	&& !(aGuestOverride##set [1].reg & bit) \
1166	) \
1167	{ \
1168	if (fStrictCpuIdChecks) \
1169	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1170	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1171	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1172	} \
1173	} while (0)
1174	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1175	do { \
1176	if ( (aGuestCpuId##set [1].reg & bit) \
1177	&& fGuestAmd \
1178	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1179	&& !(aHostOverride##set [1].reg & bit) \
1180	&& !(aGuestOverride##set [1].reg & bit) \
1181	) \
1182	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1183	} while (0)
1184	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1185	do { \
1186	if ( (aGuestCpuId##set [1].reg & bit) \
1187	&& fGuestAmd \
1188	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1189	&& !(aHostOverride##set [1].reg & bit) \
1190	&& !(aGuestOverride##set [1].reg & bit) \
1191	) \
1192	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1193	} while (0)
1194	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1195
1196	/* For checking AMD features which have a corresponding bit in the standard
1197	range. (Intel defines very few bits in the extended feature sets.) */
1198	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1199	do { \
1200	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1201	&& !(fHostAmd \
1202	? aHostRawExt[1].reg & (ExtBit) \
1203	: aHostRawStd[1].reg & (StdBit)) \
1204	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1205	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1206	) \
1207	{ \
1208	if (fStrictCpuIdChecks) \
1209	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1210	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1211	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1212	} \
1213	} while (0)
1214	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1215	do { \
1216	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1217	&& !(fHostAmd \
1218	? aHostRawExt[1].reg & (ExtBit) \
1219	: aHostRawStd[1].reg & (StdBit)) \
1220	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1221	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1222	) \
1223	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1224	} while (0)
1225	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1226	do { \
1227	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1228	&& !(fHostAmd \
1229	? aHostRawExt[1].reg & (ExtBit) \
1230	: aHostRawStd[1].reg & (StdBit)) \
1231	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1232	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1233	) \
1234	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1235	} while (0)
1236	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1237
1238	/*
1239	* Load them into stack buffers first.
1240	*/
1241	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1242	uint32_t cGuestCpuIdStd;
1243	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1244	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1245	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1246	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1247
1248	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1249	uint32_t cGuestCpuIdExt;
1250	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1251	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1252	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1253	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1254
1255	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1256	uint32_t cGuestCpuIdCentaur;
1257	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1258	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1259	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1260	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1261
1262	CPUMCPUID GuestCpuIdDef;
1263	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1264	AssertRCReturn(rc, rc);
1265
1266	CPUMCPUID aRawStd[16];
1267	uint32_t cRawStd;
1268	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1269	if (cRawStd > RT_ELEMENTS(aRawStd))
1270	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1271	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1272
1273	CPUMCPUID aRawExt[32];
1274	uint32_t cRawExt;
1275	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1276	if (cRawExt > RT_ELEMENTS(aRawExt))
1277	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1278	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1279	AssertRCReturn(rc, rc);
1280
1281	/*
1282	* Note that we support restoring less than the current amount of standard
1283	* leaves because we've been allowed more is newer version of VBox.
1284	*
1285	* So, pad new entries with the default.
1286	*/
1287	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1288	aGuestCpuIdStd[i] = GuestCpuIdDef;
1289
1290	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1291	aGuestCpuIdExt[i] = GuestCpuIdDef;
1292
1293	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1294	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1295
1296	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1297	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1298
1299	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1300	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1301
1302	/*
1303	* Get the raw CPU IDs for the current host.
1304	*/
1305	CPUMCPUID aHostRawStd[16];
1306	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1307	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1308
1309	CPUMCPUID aHostRawExt[32];
1310	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1311	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1312
1313	/*
1314	* Get the host and guest overrides so we don't reject the state because
1315	* some feature was enabled thru these interfaces.
1316	* Note! We currently only need the feature leafs, so skip rest.
1317	*/
1318	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1319	CPUMCPUID aGuestOverrideStd[2];
1320	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1321	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1322
1323	CPUMCPUID aGuestOverrideExt[2];
1324	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1325	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1326
1327	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1328	CPUMCPUID aHostOverrideStd[2];
1329	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1330	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1331
1332	CPUMCPUID aHostOverrideExt[2];
1333	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1334	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1335
1336	/*
1337	* This can be skipped.
1338	*/
1339	bool fStrictCpuIdChecks;
1340	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1341
1342
1343
1344	/*
1345	* For raw-mode we'll require that the CPUs are very similar since we don't
1346	* intercept CPUID instructions for user mode applications.
1347	*/
1348	if (!HWACCMIsEnabled(pVM))
1349	{
1350	/* CPUID(0) */
1351	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1352	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1353	&& aHostRawStd[0].edx == aRawStd[0].edx,
1354	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1355	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1356	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1357	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1358	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1359	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1360
1361	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1362
1363	/* CPUID(1).eax */
1364	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1365	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1366	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1367
1368	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1369	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1370	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1371
1372	/* CPUID(1).ecx */
1373	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1374	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1375	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1376	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1377	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1378	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1379	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1380	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1381	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1382	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1383	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1384	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1385	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1386	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1387	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1388	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1389	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1390	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1391	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1392	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1393	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1394	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1395	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1396	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1397	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1398	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1399	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1400	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1401	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1402	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1403	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1404	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1405
1406	/* CPUID(1).edx */
1407	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1408	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1409	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1410	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1411	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1412	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1413	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1414	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1415	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1416	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1417	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1418	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1419	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1420	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1421	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1422	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1423	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1424	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1425	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1426	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1427	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1428	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1429	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1430	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1431	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1432	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1433	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1434	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1435	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1436	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1437	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1438	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1439
1440	/* CPUID(2) - config, mostly about caches. ignore. */
1441	/* CPUID(3) - processor serial number. ignore. */
1442	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1443	/* CPUID(5) - mwait/monitor config. ignore. */
1444	/* CPUID(6) - power management. ignore. */
1445	/* CPUID(7) - ???. ignore. */
1446	/* CPUID(8) - ???. ignore. */
1447	/* CPUID(9) - DCA. ignore for now. */
1448	/* CPUID(a) - PeMo info. ignore for now. */
1449	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1450
1451	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1452	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1453	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1454	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1455	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1456	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1457	{
1458	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1459	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1460	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1461	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1462	}
1463
1464	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1465	Note! Intel have/is marking many of the fields here as reserved. We
1466	will verify them as if it's an AMD CPU. */
1467	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1468	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1469	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1470	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1471	{
1472	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1473	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1474	&& aHostRawExt[0].edx == aRawExt[0].edx,
1475	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1476	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1477	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1478	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1479
1480	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1481	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1482	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1483	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1484	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1485	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1486
1487	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1488	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1489	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1490	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1491
1492	/* CPUID(0x80000001).ecx */
1493	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1494	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1495	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1496	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1497	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1498	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1499	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1500	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1501	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1502	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1503	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1504	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1505	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1506	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1507	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1508	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1509	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1510	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1511	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1512	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1513	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1514	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1515	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1516	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1517	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1518	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1519	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1520	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1521	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1522	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1523	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1524	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1525
1526	/* CPUID(0x80000001).edx */
1527	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1528	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1529	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1530	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1531	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1532	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1533	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1534	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1535	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1536	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1537	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1538	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1539	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1540	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1541	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1542	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1543	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1544	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1545	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1546	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1547	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1548	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1549	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1550	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1551	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1552	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1553	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1554	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1555	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1556	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1557	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1558	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1559
1560	/** @todo verify the rest as well. */
1561	}
1562	}
1563
1564
1565
1566	/*
1567	* Verify that we can support the features already exposed to the guest on
1568	* this host.
1569	*
1570	* Most of the features we're emulating requires intercepting instruction
1571	* and doing it the slow way, so there is no need to warn when they aren't
1572	* present in the host CPU. Thus we use IGN instead of EMU on these.
1573	*
1574	* Trailing comments:
1575	* "EMU" - Possible to emulate, could be lots of work and very slow.
1576	* "EMU?" - Can this be emulated?
1577	*/
1578	/* CPUID(1).ecx */
1579	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1580	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1581	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1582	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1583	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1584	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1585	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1586	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1587	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1588	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1589	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1590	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1591	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1592	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1593	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1594	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1595	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1596	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1597	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1598	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1599	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1600	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1601	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1602	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1603	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1604	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1605	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1606	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1607	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1608	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1609	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1610	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1611
1612	/* CPUID(1).edx */
1613	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1614	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1615	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1616	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1617	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1618	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1619	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1620	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1621	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1622	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1623	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1624	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1625	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1626	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1627	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1628	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1629	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1630	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1631	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1632	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1633	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1634	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1635	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1636	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1637	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1638	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1639	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1640	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1641	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1642	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1643	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1644	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1645
1646	/* CPUID(0x80000000). */
1647	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1648	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1649	{
1650	/** @todo deal with no 0x80000001 on the host. */
1651	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1652	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1653
1654	/* CPUID(0x80000001).ecx */
1655	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1656	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1657	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1658	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1659	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1660	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1661	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1662	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1663	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1664	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1665	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1666	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1667	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1668	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1669	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1670	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1671	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1672	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1673	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1674	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1675	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1676	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1677	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1678	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1679	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1680	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1681	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1682	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1683	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1684	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1685	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1686	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1687
1688	/* CPUID(0x80000001).edx */
1689	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1690	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1691	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1692	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1693	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1694	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1695	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1696	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1697	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1698	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1699	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1700	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1701	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1702	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1703	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1704	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1705	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1706	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1707	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1708	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1709	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1710	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1711	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1712	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1713	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1714	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1715	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1716	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1717	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1718	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1719	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1720	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1721	}
1722
1723	/*
1724	* We're good, commit the CPU ID leaves.
1725	*/
1726	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1727	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1728	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1729	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1730
1731	#undef CPUID_CHECK_RET
1732	#undef CPUID_CHECK_WRN
1733	#undef CPUID_CHECK2_RET
1734	#undef CPUID_CHECK2_WRN
1735	#undef CPUID_RAW_FEATURE_RET
1736	#undef CPUID_RAW_FEATURE_WRN
1737	#undef CPUID_RAW_FEATURE_IGN
1738	#undef CPUID_GST_FEATURE_RET
1739	#undef CPUID_GST_FEATURE_WRN
1740	#undef CPUID_GST_FEATURE_EMU
1741	#undef CPUID_GST_FEATURE_IGN
1742	#undef CPUID_GST_FEATURE2_RET
1743	#undef CPUID_GST_FEATURE2_WRN
1744	#undef CPUID_GST_FEATURE2_EMU
1745	#undef CPUID_GST_FEATURE2_IGN
1746	#undef CPUID_GST_AMD_FEATURE_RET
1747	#undef CPUID_GST_AMD_FEATURE_WRN
1748	#undef CPUID_GST_AMD_FEATURE_EMU
1749	#undef CPUID_GST_AMD_FEATURE_IGN
1750
1751	return VINF_SUCCESS;
1752	}
1753
1754
1755	/**
1756	* Pass 0 live exec callback.
1757	*
1758	* @returns VINF_SSM_DONT_CALL_AGAIN.
1759	* @param pVM The VM handle.
1760	* @param pSSM The saved state handle.
1761	* @param uPass The pass (0).
1762	*/
1763	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1764	{
1765	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1766	cpumR3SaveCpuId(pVM, pSSM);
1767	return VINF_SSM_DONT_CALL_AGAIN;
1768	}
1769
1770
1771	/**
1772	* Execute state save operation.
1773	*
1774	* @returns VBox status code.
1775	* @param pVM VM Handle.
1776	* @param pSSM SSM operation handle.
1777	*/
1778	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1779	{
1780	/*
1781	* Save.
1782	*/
1783	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1784	{
1785	PVMCPU pVCpu = &pVM->aCpus[i];
1786
1787	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1788	}
1789
1790	SSMR3PutU32(pSSM, pVM->cCpus);
1791	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1792	{
1793	PVMCPU pVCpu = &pVM->aCpus[i];
1794
1795	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1796	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1797	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1798	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1799	}
1800
1801	cpumR3SaveCpuId(pVM, pSSM);
1802	return VINF_SUCCESS;
1803	}
1804
1805
1806	/**
1807	* Load a version 1.6 CPUMCTX structure.
1808	*
1809	* @returns VBox status code.
1810	* @param pVM VM Handle.
1811	* @param pCpumctx16 Version 1.6 CPUMCTX
1812	*/
1813	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1814	{
1815	#define CPUMCTX16_LOADREG(RegName) \
1816	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1817
1818	#define CPUMCTX16_LOADDRXREG(RegName) \
1819	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1820
1821	#define CPUMCTX16_LOADHIDREG(RegName) \
1822	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1823	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1824	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1825
1826	#define CPUMCTX16_LOADSEGREG(RegName) \
1827	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1828	CPUMCTX16_LOADHIDREG(RegName);
1829
1830	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1831
1832	CPUMCTX16_LOADREG(rax);
1833	CPUMCTX16_LOADREG(rbx);
1834	CPUMCTX16_LOADREG(rcx);
1835	CPUMCTX16_LOADREG(rdx);
1836	CPUMCTX16_LOADREG(rdi);
1837	CPUMCTX16_LOADREG(rsi);
1838	CPUMCTX16_LOADREG(rbp);
1839	CPUMCTX16_LOADREG(esp);
1840	CPUMCTX16_LOADREG(rip);
1841	CPUMCTX16_LOADREG(rflags);
1842
1843	CPUMCTX16_LOADSEGREG(cs);
1844	CPUMCTX16_LOADSEGREG(ds);
1845	CPUMCTX16_LOADSEGREG(es);
1846	CPUMCTX16_LOADSEGREG(fs);
1847	CPUMCTX16_LOADSEGREG(gs);
1848	CPUMCTX16_LOADSEGREG(ss);
1849
1850	CPUMCTX16_LOADREG(r8);
1851	CPUMCTX16_LOADREG(r9);
1852	CPUMCTX16_LOADREG(r10);
1853	CPUMCTX16_LOADREG(r11);
1854	CPUMCTX16_LOADREG(r12);
1855	CPUMCTX16_LOADREG(r13);
1856	CPUMCTX16_LOADREG(r14);
1857	CPUMCTX16_LOADREG(r15);
1858
1859	CPUMCTX16_LOADREG(cr0);
1860	CPUMCTX16_LOADREG(cr2);
1861	CPUMCTX16_LOADREG(cr3);
1862	CPUMCTX16_LOADREG(cr4);
1863
1864	CPUMCTX16_LOADDRXREG(0);
1865	CPUMCTX16_LOADDRXREG(1);
1866	CPUMCTX16_LOADDRXREG(2);
1867	CPUMCTX16_LOADDRXREG(3);
1868	CPUMCTX16_LOADDRXREG(4);
1869	CPUMCTX16_LOADDRXREG(5);
1870	CPUMCTX16_LOADDRXREG(6);
1871	CPUMCTX16_LOADDRXREG(7);
1872
1873	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1874	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1875	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1876	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1877
1878	CPUMCTX16_LOADREG(ldtr);
1879	CPUMCTX16_LOADREG(tr);
1880
1881	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1882
1883	CPUMCTX16_LOADREG(msrEFER);
1884	CPUMCTX16_LOADREG(msrSTAR);
1885	CPUMCTX16_LOADREG(msrPAT);
1886	CPUMCTX16_LOADREG(msrLSTAR);
1887	CPUMCTX16_LOADREG(msrCSTAR);
1888	CPUMCTX16_LOADREG(msrSFMASK);
1889	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1890
1891	CPUMCTX16_LOADHIDREG(ldtr);
1892	CPUMCTX16_LOADHIDREG(tr);
1893
1894	#undef CPUMCTX16_LOADSEGREG
1895	#undef CPUMCTX16_LOADHIDREG
1896	#undef CPUMCTX16_LOADDRXREG
1897	#undef CPUMCTX16_LOADREG
1898	}
1899
1900
1901	/**
1902	* @copydoc FNSSMINTLOADPREP
1903	*/
1904	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1905	{
1906	pVM->cpum.s.fPendingRestore = true;
1907	return VINF_SUCCESS;
1908	}
1909
1910
1911	/**
1912	* @copydoc FNSSMINTLOADEXEC
1913	*/
1914	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1915	{
1916	/*
1917	* Validate version.
1918	*/
1919	if ( uVersion != CPUM_SAVED_STATE_VERSION
1920	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1921	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1922	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1923	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1924	{
1925	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1926	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1927	}
1928
1929	if (uPass == SSM_PASS_FINAL)
1930	{
1931	/*
1932	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1933	* really old SSM file versions.)
1934	*/
1935	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1936	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1937	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1938	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1939
1940	/*
1941	* Restore.
1942	*/
1943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1944	{
1945	PVMCPU pVCpu = &pVM->aCpus[i];
1946	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1947	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1948
1949	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1950	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1951	pVCpu->cpum.s.Hyper.esp = uESP;
1952	}
1953
1954	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1955	{
1956	CPUMCTX_VER1_6 cpumctx16;
1957	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1958	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1959
1960	/* Save the old cpumctx state into the new one. */
1961	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1962
1963	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1964	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1965	}
1966	else
1967	{
1968	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1969	{
1970	uint32_t cCpus;
1971	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1972	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1973	VERR_SSM_UNEXPECTED_DATA);
1974	}
1975	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1976	\|\| pVM->cCpus == 1,
1977	("cCpus=%u\n", pVM->cCpus),
1978	VERR_SSM_UNEXPECTED_DATA);
1979
1980	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1981	{
1982	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1983	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1984	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1985	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1986	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1987	}
1988	}
1989	}
1990
1991	pVM->cpum.s.fPendingRestore = false;
1992
1993	/*
1994	* Guest CPUIDs.
1995	*/
1996	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1997	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1998
1999	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2000	* actually required. */
2001
2002	/*
2003	* Restore the CPUID leaves.
2004	*
2005	* Note that we support restoring less than the current amount of standard
2006	* leaves because we've been allowed more is newer version of VBox.
2007	*/
2008	uint32_t cElements;
2009	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2010	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2011	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2012	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2013
2014	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2015	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2016	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2017	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2018
2019	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2020	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2021	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2022	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2023
2024	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2025
2026	/*
2027	* Check that the basic cpuid id information is unchanged.
2028	*/
2029	/** @todo we should check the 64 bits capabilities too! */
2030	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2031	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2032	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2033	uint32_t au32CpuIdSaved[8];
2034	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2035	if (RT_SUCCESS(rc))
2036	{
2037	/* Ignore CPU stepping. */
2038	au32CpuId[4] &= 0xfffffff0;
2039	au32CpuIdSaved[4] &= 0xfffffff0;
2040
2041	/* Ignore APIC ID (AMD specs). */
2042	au32CpuId[5] &= ~0xff000000;
2043	au32CpuIdSaved[5] &= ~0xff000000;
2044
2045	/* Ignore the number of Logical CPUs (AMD specs). */
2046	au32CpuId[5] &= ~0x00ff0000;
2047	au32CpuIdSaved[5] &= ~0x00ff0000;
2048
2049	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2050	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2051	\| X86_CPUID_FEATURE_ECX_VMX
2052	\| X86_CPUID_FEATURE_ECX_SMX
2053	\| X86_CPUID_FEATURE_ECX_EST
2054	\| X86_CPUID_FEATURE_ECX_TM2
2055	\| X86_CPUID_FEATURE_ECX_CNTXID
2056	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2057	\| X86_CPUID_FEATURE_ECX_PDCM
2058	\| X86_CPUID_FEATURE_ECX_DCA
2059	\| X86_CPUID_FEATURE_ECX_X2APIC
2060	);
2061	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2062	\| X86_CPUID_FEATURE_ECX_VMX
2063	\| X86_CPUID_FEATURE_ECX_SMX
2064	\| X86_CPUID_FEATURE_ECX_EST
2065	\| X86_CPUID_FEATURE_ECX_TM2
2066	\| X86_CPUID_FEATURE_ECX_CNTXID
2067	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2068	\| X86_CPUID_FEATURE_ECX_PDCM
2069	\| X86_CPUID_FEATURE_ECX_DCA
2070	\| X86_CPUID_FEATURE_ECX_X2APIC
2071	);
2072
2073	/* Make sure we don't forget to update the masks when enabling
2074	* features in the future.
2075	*/
2076	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2077	( X86_CPUID_FEATURE_ECX_DTES64
2078	\| X86_CPUID_FEATURE_ECX_VMX
2079	\| X86_CPUID_FEATURE_ECX_SMX
2080	\| X86_CPUID_FEATURE_ECX_EST
2081	\| X86_CPUID_FEATURE_ECX_TM2
2082	\| X86_CPUID_FEATURE_ECX_CNTXID
2083	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2084	\| X86_CPUID_FEATURE_ECX_PDCM
2085	\| X86_CPUID_FEATURE_ECX_DCA
2086	\| X86_CPUID_FEATURE_ECX_X2APIC
2087	)));
2088	/* do the compare */
2089	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2090	{
2091	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2092	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2093	"Saved=%.*Rhxs\n"
2094	"Real =%.*Rhxs\n",
2095	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2096	sizeof(au32CpuId), au32CpuId));
2097	else
2098	{
2099	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2100	"Saved=%.*Rhxs\n"
2101	"Real =%.*Rhxs\n",
2102	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2103	sizeof(au32CpuId), au32CpuId));
2104	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2105	}
2106	}
2107	}
2108
2109	return rc;
2110	}
2111
2112
2113	/**
2114	* @copydoc FNSSMINTLOADPREP
2115	*/
2116	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2117	{
2118	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2119	return VINF_SUCCESS;
2120
2121	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2122	if (pVM->cpum.s.fPendingRestore)
2123	{
2124	LogRel(("CPUM: Missing state!\n"));
2125	return VERR_INTERNAL_ERROR_2;
2126	}
2127
2128	return VINF_SUCCESS;
2129	}
2130
2131
2132	/**
2133	* Checks if the CPUM state restore is still pending.
2134	*
2135	* @returns true / false.
2136	* @param pVM The VM handle.
2137	*/
2138	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2139	{
2140	return pVM->cpum.s.fPendingRestore;
2141	}
2142
2143
2144	/**
2145	* Formats the EFLAGS value into mnemonics.
2146	*
2147	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2148	* @param efl The EFLAGS value.
2149	*/
2150	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2151	{
2152	/*
2153	* Format the flags.
2154	*/
2155	static const struct
2156	{
2157	const char pszSet; const char pszClear; uint32_t fFlag;
2158	} s_aFlags[] =
2159	{
2160	{ "vip",NULL, X86_EFL_VIP },
2161	{ "vif",NULL, X86_EFL_VIF },
2162	{ "ac", NULL, X86_EFL_AC },
2163	{ "vm", NULL, X86_EFL_VM },
2164	{ "rf", NULL, X86_EFL_RF },
2165	{ "nt", NULL, X86_EFL_NT },
2166	{ "ov", "nv", X86_EFL_OF },
2167	{ "dn", "up", X86_EFL_DF },
2168	{ "ei", "di", X86_EFL_IF },
2169	{ "tf", NULL, X86_EFL_TF },
2170	{ "nt", "pl", X86_EFL_SF },
2171	{ "nz", "zr", X86_EFL_ZF },
2172	{ "ac", "na", X86_EFL_AF },
2173	{ "po", "pe", X86_EFL_PF },
2174	{ "cy", "nc", X86_EFL_CF },
2175	};
2176	char *psz = pszEFlags;
2177	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2178	{
2179	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2180	if (pszAdd)
2181	{
2182	strcpy(psz, pszAdd);
2183	psz += strlen(pszAdd);
2184	*psz++ = ' ';
2185	}
2186	}
2187	psz[-1] = '\0';
2188	}
2189
2190
2191	/**
2192	* Formats a full register dump.
2193	*
2194	* @param pVM VM Handle.
2195	* @param pCtx The context to format.
2196	* @param pCtxCore The context core to format.
2197	* @param pHlp Output functions.
2198	* @param enmType The dump type.
2199	* @param pszPrefix Register name prefix.
2200	*/
2201	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2202	{
2203	/*
2204	* Format the EFLAGS.
2205	*/
2206	uint32_t efl = pCtxCore->eflags.u32;
2207	char szEFlags[80];
2208	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2209
2210	/*
2211	* Format the registers.
2212	*/
2213	switch (enmType)
2214	{
2215	case CPUMDUMPTYPE_TERSE:
2216	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2217	pHlp->pfnPrintf(pHlp,
2218	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2219	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2220	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2221	"%sr14=%016RX64 %sr15=%016RX64\n"
2222	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2223	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2224	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2225	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2226	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2227	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2228	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2229	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2230	else
2231	pHlp->pfnPrintf(pHlp,
2232	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2233	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2234	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2235	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2236	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2237	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2238	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2239	break;
2240
2241	case CPUMDUMPTYPE_DEFAULT:
2242	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2243	pHlp->pfnPrintf(pHlp,
2244	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2245	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2246	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2247	"%sr14=%016RX64 %sr15=%016RX64\n"
2248	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2249	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2250	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2251	,
2252	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2253	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2254	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2255	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2256	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2257	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2258	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2259	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2260	else
2261	pHlp->pfnPrintf(pHlp,
2262	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2263	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2264	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2265	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2266	,
2267	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2268	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2269	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2270	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2271	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2272	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2273	break;
2274
2275	case CPUMDUMPTYPE_VERBOSE:
2276	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2277	pHlp->pfnPrintf(pHlp,
2278	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2279	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2280	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2281	"%sr14=%016RX64 %sr15=%016RX64\n"
2282	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2283	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2284	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2285	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2286	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2287	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2288	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2289	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2290	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2291	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2292	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2293	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2294	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2295	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2296	,
2297	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2298	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2299	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2300	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2301	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2302	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2303	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2304	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2305	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2306	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2307	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2308	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2309	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2310	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2311	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2312	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2313	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2314	else
2315	pHlp->pfnPrintf(pHlp,
2316	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2317	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2318	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2319	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2320	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2321	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2322	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2323	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2324	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2325	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2326	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2327	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2328	,
2329	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2330	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2331	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2332	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2333	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2334	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2335	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2336	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2337	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2338	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2339	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2340	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2341
2342	pHlp->pfnPrintf(pHlp,
2343	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2344	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2345	,
2346	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2347	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2348	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2349	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2350	);
2351	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2352	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2353	{
2354	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2355	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2356	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2357	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2358	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2359	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2360	/** @todo This isn't entirenly correct and needs more work! */
2361	pHlp->pfnPrintf(pHlp,
2362	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2363	pszPrefix, iST, pszPrefix, iFPR,
2364	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2365	uTag, chSign, iInteger, u64Fraction, uExponent);
2366	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2367	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2368	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2369	else
2370	pHlp->pfnPrintf(pHlp, "\n");
2371	}
2372	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2373	pHlp->pfnPrintf(pHlp,
2374	iXMM & 1
2375	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2376	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2377	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2378	pCtx->fpu.aXMM[iXMM].au32[3],
2379	pCtx->fpu.aXMM[iXMM].au32[2],
2380	pCtx->fpu.aXMM[iXMM].au32[1],
2381	pCtx->fpu.aXMM[iXMM].au32[0]);
2382	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2383	if (pCtx->fpu.au32RsrvdRest[i])
2384	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2385	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2386
2387	pHlp->pfnPrintf(pHlp,
2388	"%sEFER =%016RX64\n"
2389	"%sPAT =%016RX64\n"
2390	"%sSTAR =%016RX64\n"
2391	"%sCSTAR =%016RX64\n"
2392	"%sLSTAR =%016RX64\n"
2393	"%sSFMASK =%016RX64\n"
2394	"%sKERNELGSBASE =%016RX64\n",
2395	pszPrefix, pCtx->msrEFER,
2396	pszPrefix, pCtx->msrPAT,
2397	pszPrefix, pCtx->msrSTAR,
2398	pszPrefix, pCtx->msrCSTAR,
2399	pszPrefix, pCtx->msrLSTAR,
2400	pszPrefix, pCtx->msrSFMASK,
2401	pszPrefix, pCtx->msrKERNELGSBASE);
2402	break;
2403	}
2404	}
2405
2406
2407	/**
2408	* Display all cpu states and any other cpum info.
2409	*
2410	* @param pVM VM Handle.
2411	* @param pHlp The info helper functions.
2412	* @param pszArgs Arguments, ignored.
2413	*/
2414	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2415	{
2416	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2417	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2418	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2419	cpumR3InfoHost(pVM, pHlp, pszArgs);
2420	}
2421
2422
2423	/**
2424	* Parses the info argument.
2425	*
2426	* The argument starts with 'verbose', 'terse' or 'default' and then
2427	* continues with the comment string.
2428	*
2429	* @param pszArgs The pointer to the argument string.
2430	* @param penmType Where to store the dump type request.
2431	* @param ppszComment Where to store the pointer to the comment string.
2432	*/
2433	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2434	{
2435	if (!pszArgs)
2436	{
2437	*penmType = CPUMDUMPTYPE_DEFAULT;
2438	*ppszComment = "";
2439	}
2440	else
2441	{
2442	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2443	{
2444	pszArgs += 5;
2445	*penmType = CPUMDUMPTYPE_VERBOSE;
2446	}
2447	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2448	{
2449	pszArgs += 5;
2450	*penmType = CPUMDUMPTYPE_TERSE;
2451	}
2452	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2453	{
2454	pszArgs += 7;
2455	*penmType = CPUMDUMPTYPE_DEFAULT;
2456	}
2457	else
2458	*penmType = CPUMDUMPTYPE_DEFAULT;
2459	*ppszComment = RTStrStripL(pszArgs);
2460	}
2461	}
2462
2463
2464	/**
2465	* Display the guest cpu state.
2466	*
2467	* @param pVM VM Handle.
2468	* @param pHlp The info helper functions.
2469	* @param pszArgs Arguments, ignored.
2470	*/
2471	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2472	{
2473	CPUMDUMPTYPE enmType;
2474	const char *pszComment;
2475	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2476
2477	/* @todo SMP support! */
2478	PVMCPU pVCpu = VMMGetCpu(pVM);
2479	if (!pVCpu)
2480	pVCpu = &pVM->aCpus[0];
2481
2482	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2483
2484	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2485	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2486	}
2487
2488
2489	/**
2490	* Display the current guest instruction
2491	*
2492	* @param pVM VM Handle.
2493	* @param pHlp The info helper functions.
2494	* @param pszArgs Arguments, ignored.
2495	*/
2496	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2497	{
2498	char szInstruction[256];
2499	/* @todo SMP support! */
2500	PVMCPU pVCpu = VMMGetCpu(pVM);
2501	if (!pVCpu)
2502	pVCpu = &pVM->aCpus[0];
2503
2504	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2505	if (RT_SUCCESS(rc))
2506	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2507	}
2508
2509
2510	/**
2511	* Display the hypervisor cpu state.
2512	*
2513	* @param pVM VM Handle.
2514	* @param pHlp The info helper functions.
2515	* @param pszArgs Arguments, ignored.
2516	*/
2517	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2518	{
2519	CPUMDUMPTYPE enmType;
2520	const char *pszComment;
2521	/* @todo SMP */
2522	PVMCPU pVCpu = &pVM->aCpus[0];
2523
2524	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2525	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2526	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2527	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2528	}
2529
2530
2531	/**
2532	* Display the host cpu state.
2533	*
2534	* @param pVM VM Handle.
2535	* @param pHlp The info helper functions.
2536	* @param pszArgs Arguments, ignored.
2537	*/
2538	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2539	{
2540	CPUMDUMPTYPE enmType;
2541	const char *pszComment;
2542	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2543	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2544
2545	/*
2546	* Format the EFLAGS.
2547	*/
2548	/* @todo SMP */
2549	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2550	#if HC_ARCH_BITS == 32
2551	uint32_t efl = pCtx->eflags.u32;
2552	#else
2553	uint64_t efl = pCtx->rflags;
2554	#endif
2555	char szEFlags[80];
2556	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2557
2558	/*
2559	* Format the registers.
2560	*/
2561	#if HC_ARCH_BITS == 32
2562	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2563	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2564	# endif
2565	{
2566	pHlp->pfnPrintf(pHlp,
2567	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2568	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2569	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2570	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2571	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2572	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2573	,
2574	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2575	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2576	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2577	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2578	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2579	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2580	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2581	}
2582	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2583	else
2584	# endif
2585	#endif
2586	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2587	{
2588	pHlp->pfnPrintf(pHlp,
2589	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2590	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2591	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2592	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2593	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2594	"r14=%016RX64 r15=%016RX64\n"
2595	"iopl=%d %31s\n"
2596	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2597	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2598	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2599	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2600	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2601	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2602	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2603	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2604	,
2605	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2606	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2607	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2608	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2609	pCtx->r11, pCtx->r12, pCtx->r13,
2610	pCtx->r14, pCtx->r15,
2611	X86_EFL_GET_IOPL(efl), szEFlags,
2612	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2613	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2614	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2615	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2616	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2617	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2618	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2619	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2620	}
2621	#endif
2622	}
2623
2624
2625	/**
2626	* Get L1 cache / TLS associativity.
2627	*/
2628	static const char getCacheAss(unsigned u, char pszBuf)
2629	{
2630	if (u == 0)
2631	return "res0 ";
2632	if (u == 1)
2633	return "direct";
2634	if (u >= 256)
2635	return "???";
2636
2637	RTStrPrintf(pszBuf, 16, "%d way", u);
2638	return pszBuf;
2639	}
2640
2641
2642	/**
2643	* Get L2 cache soociativity.
2644	*/
2645	const char *getL2CacheAss(unsigned u)
2646	{
2647	switch (u)
2648	{
2649	case 0: return "off ";
2650	case 1: return "direct";
2651	case 2: return "2 way ";
2652	case 3: return "res3 ";
2653	case 4: return "4 way ";
2654	case 5: return "res5 ";
2655	case 6: return "8 way "; case 7: return "res7 ";
2656	case 8: return "16 way";
2657	case 9: return "res9 ";
2658	case 10: return "res10 ";
2659	case 11: return "res11 ";
2660	case 12: return "res12 ";
2661	case 13: return "res13 ";
2662	case 14: return "res14 ";
2663	case 15: return "fully ";
2664	default:
2665	return "????";
2666	}
2667	}
2668
2669
2670	/**
2671	* Display the guest CpuId leaves.
2672	*
2673	* @param pVM VM Handle.
2674	* @param pHlp The info helper functions.
2675	* @param pszArgs "terse", "default" or "verbose".
2676	*/
2677	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2678	{
2679	/*
2680	* Parse the argument.
2681	*/
2682	unsigned iVerbosity = 1;
2683	if (pszArgs)
2684	{
2685	pszArgs = RTStrStripL(pszArgs);
2686	if (!strcmp(pszArgs, "terse"))
2687	iVerbosity--;
2688	else if (!strcmp(pszArgs, "verbose"))
2689	iVerbosity++;
2690	}
2691
2692	/*
2693	* Start cracking.
2694	*/
2695	CPUMCPUID Host;
2696	CPUMCPUID Guest;
2697	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2698
2699	pHlp->pfnPrintf(pHlp,
2700	" RAW Standard CPUIDs\n"
2701	" Function eax ebx ecx edx\n");
2702	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2703	{
2704	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2705	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2706
2707	pHlp->pfnPrintf(pHlp,
2708	"Gst: %08x %08x %08x %08x %08x%s\n"
2709	"Hst: %08x %08x %08x %08x\n",
2710	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2711	i <= cStdMax ? "" : "*",
2712	Host.eax, Host.ebx, Host.ecx, Host.edx);
2713	}
2714
2715	/*
2716	* If verbose, decode it.
2717	*/
2718	if (iVerbosity)
2719	{
2720	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2721	pHlp->pfnPrintf(pHlp,
2722	"Name: %.04s%.04s%.04s\n"
2723	"Supports: 0-%x\n",
2724	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2725	}
2726
2727	/*
2728	* Get Features.
2729	*/
2730	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2731	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2732	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2733	if (cStdMax >= 1 && iVerbosity)
2734	{
2735	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2736	uint32_t uEAX = Guest.eax;
2737
2738	pHlp->pfnPrintf(pHlp,
2739	"Family: %d \tExtended: %d \tEffective: %d\n"
2740	"Model: %d \tExtended: %d \tEffective: %d\n"
2741	"Stepping: %d\n"
2742	"Type: %d\n"
2743	"APIC ID: %#04x\n"
2744	"Logical CPUs: %d\n"
2745	"CLFLUSH Size: %d\n"
2746	"Brand ID: %#04x\n",
2747	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2748	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2749	ASMGetCpuStepping(uEAX),
2750	(uEAX >> 12) & 3,
2751	(Guest.ebx >> 24) & 0xff,
2752	(Guest.ebx >> 16) & 0xff,
2753	(Guest.ebx >> 8) & 0xff,
2754	(Guest.ebx >> 0) & 0xff);
2755	if (iVerbosity == 1)
2756	{
2757	uint32_t uEDX = Guest.edx;
2758	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2759	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2760	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2761	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2762	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2763	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2764	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2765	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2766	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2767	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2768	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2769	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2770	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2771	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2772	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2773	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2774	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2775	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2776	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2777	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2778	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2779	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2780	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2781	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2782	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2783	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2784	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2785	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2786	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2787	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2788	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2789	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2790	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2791	pHlp->pfnPrintf(pHlp, "\n");
2792
2793	uint32_t uECX = Guest.ecx;
2794	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2795	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2796	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2797	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2798	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2799	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2800	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2801	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2802	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2803	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2804	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2805	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2806	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2807	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2808	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2809	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2810	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2811	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2812	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2813	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2814	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2815	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2816	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2817	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2818	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2819	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2820	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2821	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2822	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2823	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2824	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2825	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2826	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2827	pHlp->pfnPrintf(pHlp, "\n");
2828	}
2829	else
2830	{
2831	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2832
2833	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2834	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2835	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2836	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2837
2838	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2839	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2840	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2841	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2842	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2843	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2844	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2845	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2846	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2847	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2848	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2849	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2850	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2851	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2852	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2853	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2854	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2855	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2856	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2857	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2858	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2859	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2860	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2861	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2862	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2863	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2864	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2865	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2866	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2867	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2868	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2869	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2870	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2871
2872	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2873	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2874	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2875	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2876	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2877	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2878	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2879	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2880	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2881	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2882	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2883	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2884	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2885	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2886	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2887	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2888	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2889	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2890	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2891	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2892	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2893	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2894	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2895	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2896	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2897	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2898	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2899	}
2900	}
2901	if (cStdMax >= 2 && iVerbosity)
2902	{
2903	/** @todo */
2904	}
2905
2906	/*
2907	* Extended.
2908	* Implemented after AMD specs.
2909	*/
2910	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2911
2912	pHlp->pfnPrintf(pHlp,
2913	"\n"
2914	" RAW Extended CPUIDs\n"
2915	" Function eax ebx ecx edx\n");
2916	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2917	{
2918	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2919	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2920
2921	pHlp->pfnPrintf(pHlp,
2922	"Gst: %08x %08x %08x %08x %08x%s\n"
2923	"Hst: %08x %08x %08x %08x\n",
2924	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2925	i <= cExtMax ? "" : "*",
2926	Host.eax, Host.ebx, Host.ecx, Host.edx);
2927	}
2928
2929	/*
2930	* Understandable output
2931	*/
2932	if (iVerbosity)
2933	{
2934	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2935	pHlp->pfnPrintf(pHlp,
2936	"Ext Name: %.4s%.4s%.4s\n"
2937	"Ext Supports: 0x80000000-%#010x\n",
2938	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2939	}
2940
2941	if (iVerbosity && cExtMax >= 1)
2942	{
2943	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2944	uint32_t uEAX = Guest.eax;
2945	pHlp->pfnPrintf(pHlp,
2946	"Family: %d \tExtended: %d \tEffective: %d\n"
2947	"Model: %d \tExtended: %d \tEffective: %d\n"
2948	"Stepping: %d\n"
2949	"Brand ID: %#05x\n",
2950	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2951	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2952	ASMGetCpuStepping(uEAX),
2953	Guest.ebx & 0xfff);
2954
2955	if (iVerbosity == 1)
2956	{
2957	uint32_t uEDX = Guest.edx;
2958	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2959	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2960	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2961	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2962	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2963	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2964	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2965	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2966	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2967	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2968	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2969	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2970	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2971	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2972	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2973	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2974	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2975	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2976	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2977	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2978	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2979	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2980	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2981	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2982	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2983	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2984	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2985	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2986	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2987	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2988	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2989	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2990	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2991	pHlp->pfnPrintf(pHlp, "\n");
2992
2993	uint32_t uECX = Guest.ecx;
2994	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2995	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2996	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2997	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2998	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2999	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3000	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3001	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3002	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3003	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3004	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3005	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3006	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3007	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3008	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3009	for (unsigned iBit = 5; iBit < 32; iBit++)
3010	if (uECX & RT_BIT(iBit))
3011	pHlp->pfnPrintf(pHlp, " %d", iBit);
3012	pHlp->pfnPrintf(pHlp, "\n");
3013	}
3014	else
3015	{
3016	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3017
3018	uint32_t uEdxGst = Guest.edx;
3019	uint32_t uEdxHst = Host.edx;
3020	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3021	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3022	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3023	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3024	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3025	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3026	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3027	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3028	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3029	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3030	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3031	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3032	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3033	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3034	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3035	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3036	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3037	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3038	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3039	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3040	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3041	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3042	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3043	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3044	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3045	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3046	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3047	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3048	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3049	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3050	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3051	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3052	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3053
3054	uint32_t uEcxGst = Guest.ecx;
3055	uint32_t uEcxHst = Host.ecx;
3056	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3057	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3058	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3059	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3060	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3061	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3062	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3063	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3064	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3065	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3066	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3067	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3068	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3069	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3070	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3071	}
3072	}
3073
3074	if (iVerbosity && cExtMax >= 2)
3075	{
3076	char szString[443+1] = {0};
3077	uint32_t pu32 = (uint32_t )szString;
3078	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3079	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3080	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3081	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3082	if (cExtMax >= 3)
3083	{
3084	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3085	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3086	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3087	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3088	}
3089	if (cExtMax >= 4)
3090	{
3091	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3092	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3093	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3094	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3095	}
3096	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3097	}
3098
3099	if (iVerbosity && cExtMax >= 5)
3100	{
3101	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3102	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3103	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3104	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3105	char sz1[32];
3106	char sz2[32];
3107
3108	pHlp->pfnPrintf(pHlp,
3109	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3110	"TLB 2/4M Data: %s %3d entries\n",
3111	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3112	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3113	pHlp->pfnPrintf(pHlp,
3114	"TLB 4K Instr/Uni: %s %3d entries\n"
3115	"TLB 4K Data: %s %3d entries\n",
3116	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3117	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3118	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3119	"L1 Instr Cache Lines Per Tag: %d\n"
3120	"L1 Instr Cache Associativity: %s\n"
3121	"L1 Instr Cache Size: %d KB\n",
3122	(uEDX >> 0) & 0xff,
3123	(uEDX >> 8) & 0xff,
3124	getCacheAss((uEDX >> 16) & 0xff, sz1),
3125	(uEDX >> 24) & 0xff);
3126	pHlp->pfnPrintf(pHlp,
3127	"L1 Data Cache Line Size: %d bytes\n"
3128	"L1 Data Cache Lines Per Tag: %d\n"
3129	"L1 Data Cache Associativity: %s\n"
3130	"L1 Data Cache Size: %d KB\n",
3131	(uECX >> 0) & 0xff,
3132	(uECX >> 8) & 0xff,
3133	getCacheAss((uECX >> 16) & 0xff, sz1),
3134	(uECX >> 24) & 0xff);
3135	}
3136
3137	if (iVerbosity && cExtMax >= 6)
3138	{
3139	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3140	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3141	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3142
3143	pHlp->pfnPrintf(pHlp,
3144	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3145	"L2 TLB 2/4M Data: %s %4d entries\n",
3146	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3147	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3148	pHlp->pfnPrintf(pHlp,
3149	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3150	"L2 TLB 4K Data: %s %4d entries\n",
3151	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3152	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3153	pHlp->pfnPrintf(pHlp,
3154	"L2 Cache Line Size: %d bytes\n"
3155	"L2 Cache Lines Per Tag: %d\n"
3156	"L2 Cache Associativity: %s\n"
3157	"L2 Cache Size: %d KB\n",
3158	(uEDX >> 0) & 0xff,
3159	(uEDX >> 8) & 0xf,
3160	getL2CacheAss((uEDX >> 12) & 0xf),
3161	(uEDX >> 16) & 0xffff);
3162	}
3163
3164	if (iVerbosity && cExtMax >= 7)
3165	{
3166	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3167
3168	pHlp->pfnPrintf(pHlp, "APM Features: ");
3169	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3170	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3171	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3172	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3173	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3174	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3175	for (unsigned iBit = 6; iBit < 32; iBit++)
3176	if (uEDX & RT_BIT(iBit))
3177	pHlp->pfnPrintf(pHlp, " %d", iBit);
3178	pHlp->pfnPrintf(pHlp, "\n");
3179	}
3180
3181	if (iVerbosity && cExtMax >= 8)
3182	{
3183	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3184	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3185
3186	pHlp->pfnPrintf(pHlp,
3187	"Physical Address Width: %d bits\n"
3188	"Virtual Address Width: %d bits\n",
3189	(uEAX >> 0) & 0xff,
3190	(uEAX >> 8) & 0xff);
3191	pHlp->pfnPrintf(pHlp,
3192	"Physical Core Count: %d\n",
3193	(uECX >> 0) & 0xff);
3194	}
3195
3196
3197	/*
3198	* Centaur.
3199	*/
3200	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3201
3202	pHlp->pfnPrintf(pHlp,
3203	"\n"
3204	" RAW Centaur CPUIDs\n"
3205	" Function eax ebx ecx edx\n");
3206	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3207	{
3208	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3209	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3210
3211	pHlp->pfnPrintf(pHlp,
3212	"Gst: %08x %08x %08x %08x %08x%s\n"
3213	"Hst: %08x %08x %08x %08x\n",
3214	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3215	i <= cCentaurMax ? "" : "*",
3216	Host.eax, Host.ebx, Host.ecx, Host.edx);
3217	}
3218
3219	/*
3220	* Understandable output
3221	*/
3222	if (iVerbosity)
3223	{
3224	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3225	pHlp->pfnPrintf(pHlp,
3226	"Centaur Supports: 0xc0000000-%#010x\n",
3227	Guest.eax);
3228	}
3229
3230	if (iVerbosity && cCentaurMax >= 1)
3231	{
3232	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3233	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3234	uint32_t uEdxHst = Host.edx;
3235
3236	if (iVerbosity == 1)
3237	{
3238	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3239	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3240	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3241	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3242	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3243	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3244	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3245	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3246	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3247	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3248	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3249	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3250	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3251	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3252	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3253	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3254	for (unsigned iBit = 14; iBit < 32; iBit++)
3255	if (uEdxGst & RT_BIT(iBit))
3256	pHlp->pfnPrintf(pHlp, " %d", iBit);
3257	pHlp->pfnPrintf(pHlp, "\n");
3258	}
3259	else
3260	{
3261	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3262	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3263	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3264	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3265	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3266	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3267	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3268	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3269	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3270	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3271	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3272	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3273	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3274	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3275	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3276	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3277	for (unsigned iBit = 14; iBit < 32; iBit++)
3278	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3279	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3280	pHlp->pfnPrintf(pHlp, "\n");
3281	}
3282	}
3283	}
3284
3285
3286	/**
3287	* Structure used when disassembling and instructions in DBGF.
3288	* This is used so the reader function can get the stuff it needs.
3289	*/
3290	typedef struct CPUMDISASSTATE
3291	{
3292	/** Pointer to the CPU structure. */
3293	PDISCPUSTATE pCpu;
3294	/** The VM handle. */
3295	PVM pVM;
3296	/** The VMCPU handle. */
3297	PVMCPU pVCpu;
3298	/** Pointer to the first byte in the segemnt. */
3299	RTGCUINTPTR GCPtrSegBase;
3300	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3301	RTGCUINTPTR GCPtrSegEnd;
3302	/** The size of the segment minus 1. */
3303	RTGCUINTPTR cbSegLimit;
3304	/** Pointer to the current page - R3 Ptr. */
3305	void const *pvPageR3;
3306	/** Pointer to the current page - GC Ptr. */
3307	RTGCPTR pvPageGC;
3308	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3309	PGMPAGEMAPLOCK PageMapLock;
3310	/** Whether the PageMapLock is valid or not. */
3311	bool fLocked;
3312	/** 64 bits mode or not. */
3313	bool f64Bits;
3314	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3315
3316
3317	/**
3318	* Instruction reader.
3319	*
3320	* @returns VBox status code.
3321	* @param PtrSrc Address to read from.
3322	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3323	* @param pu8Dst Where to store the bytes.
3324	* @param cbRead Number of bytes to read.
3325	* @param uDisCpu Pointer to the disassembler cpu state.
3326	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3327	*/
3328	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3329	{
3330	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3331	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3332	Assert(cbRead > 0);
3333	for (;;)
3334	{
3335	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3336
3337	/* Need to update the page translation? */
3338	if ( !pState->pvPageR3
3339	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3340	{
3341	int rc = VINF_SUCCESS;
3342
3343	/* translate the address */
3344	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3345	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3346	&& !HWACCMIsEnabled(pState->pVM))
3347	{
3348	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3349	if (!pState->pvPageR3)
3350	rc = VERR_INVALID_POINTER;
3351	}
3352	else
3353	{
3354	/* Release mapping lock previously acquired. */
3355	if (pState->fLocked)
3356	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3357	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3358	pState->fLocked = RT_SUCCESS_NP(rc);
3359	}
3360	if (RT_FAILURE(rc))
3361	{
3362	pState->pvPageR3 = NULL;
3363	return rc;
3364	}
3365	}
3366
3367	/* check the segemnt limit */
3368	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3369	return VERR_OUT_OF_SELECTOR_BOUNDS;
3370
3371	/* calc how much we can read */
3372	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3373	if (!pState->f64Bits)
3374	{
3375	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3376	if (cb > cbSeg && cbSeg)
3377	cb = cbSeg;
3378	}
3379	if (cb > cbRead)
3380	cb = cbRead;
3381
3382	/* read and advance */
3383	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3384	cbRead -= cb;
3385	if (!cbRead)
3386	return VINF_SUCCESS;
3387	pu8Dst += cb;
3388	PtrSrc += cb;
3389	}
3390	}
3391
3392
3393	/**
3394	* Disassemble an instruction and return the information in the provided structure.
3395	*
3396	* @returns VBox status code.
3397	* @param pVM VM Handle
3398	* @param pVCpu VMCPU Handle
3399	* @param pCtx CPU context
3400	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3401	* @param pCpu Disassembly state
3402	* @param pszPrefix String prefix for logging (debug only)
3403	*
3404	*/
3405	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3406	{
3407	CPUMDISASSTATE State;
3408	int rc;
3409
3410	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3411	State.pCpu = pCpu;
3412	State.pvPageGC = 0;
3413	State.pvPageR3 = NULL;
3414	State.pVM = pVM;
3415	State.pVCpu = pVCpu;
3416	State.fLocked = false;
3417	State.f64Bits = false;
3418
3419	/*
3420	* Get selector information.
3421	*/
3422	if ( (pCtx->cr0 & X86_CR0_PE)
3423	&& pCtx->eflags.Bits.u1VM == 0)
3424	{
3425	if (CPUMAreHiddenSelRegsValid(pVM))
3426	{
3427	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3428	State.GCPtrSegBase = pCtx->csHid.u64Base;
3429	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3430	State.cbSegLimit = pCtx->csHid.u32Limit;
3431	pCpu->mode = (State.f64Bits)
3432	? CPUMODE_64BIT
3433	: pCtx->csHid.Attr.n.u1DefBig
3434	? CPUMODE_32BIT
3435	: CPUMODE_16BIT;
3436	}
3437	else
3438	{
3439	DBGFSELINFO SelInfo;
3440
3441	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3442	if (RT_FAILURE(rc))
3443	{
3444	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3445	return rc;
3446	}
3447
3448	/*
3449	* Validate the selector.
3450	*/
3451	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3452	if (RT_FAILURE(rc))
3453	{
3454	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3455	return rc;
3456	}
3457	State.GCPtrSegBase = SelInfo.GCPtrBase;
3458	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3459	State.cbSegLimit = SelInfo.cbLimit;
3460	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3461	}
3462	}
3463	else
3464	{
3465	/* real or V86 mode */
3466	pCpu->mode = CPUMODE_16BIT;
3467	State.GCPtrSegBase = pCtx->cs * 16;
3468	State.GCPtrSegEnd = 0xFFFFFFFF;
3469	State.cbSegLimit = 0xFFFFFFFF;
3470	}
3471
3472	/*
3473	* Disassemble the instruction.
3474	*/
3475	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3476	pCpu->apvUserData[0] = &State;
3477
3478	uint32_t cbInstr;
3479	#ifndef LOG_ENABLED
3480	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3481	if (RT_SUCCESS(rc))
3482	{
3483	#else
3484	char szOutput[160];
3485	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3486	if (RT_SUCCESS(rc))
3487	{
3488	/* log it */
3489	if (pszPrefix)
3490	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3491	else
3492	Log(("%s", szOutput));
3493	#endif
3494	rc = VINF_SUCCESS;
3495	}
3496	else
3497	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3498
3499	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3500	if (State.fLocked)
3501	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3502
3503	return rc;
3504	}
3505
3506	#ifdef DEBUG
3507
3508	/**
3509	* Disassemble an instruction and dump it to the log
3510	*
3511	* @returns VBox status code.
3512	* @param pVM VM Handle
3513	* @param pVCpu VMCPU Handle
3514	* @param pCtx CPU context
3515	* @param pc GC instruction pointer
3516	* @param pszPrefix String prefix for logging
3517	*
3518	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3519	*/
3520	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3521	{
3522	DISCPUSTATE Cpu;
3523	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3524	}
3525
3526
3527	/**
3528	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3529	*
3530	* @internal
3531	*/
3532	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3533	{
3534	/** @todo SMP support!! */
3535	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3536	}
3537
3538	#endif /* DEBUG */
3539
3540	/**
3541	* API for controlling a few of the CPU features found in CR4.
3542	*
3543	* Currently only X86_CR4_TSD is accepted as input.
3544	*
3545	* @returns VBox status code.
3546	*
3547	* @param pVM The VM handle.
3548	* @param fOr The CR4 OR mask.
3549	* @param fAnd The CR4 AND mask.
3550	*/
3551	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3552	{
3553	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3554	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3555
3556	pVM->cpum.s.CR4.OrMask &= fAnd;
3557	pVM->cpum.s.CR4.OrMask \|= fOr;
3558
3559	return VINF_SUCCESS;
3560	}
3561
3562
3563	/**
3564	* Gets a pointer to the array of standard CPUID leaves.
3565	*
3566	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3567	*
3568	* @returns Pointer to the standard CPUID leaves (read-only).
3569	* @param pVM The VM handle.
3570	* @remark Intended for PATM.
3571	*/
3572	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3573	{
3574	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3575	}
3576
3577
3578	/**
3579	* Gets a pointer to the array of extended CPUID leaves.
3580	*
3581	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3582	*
3583	* @returns Pointer to the extended CPUID leaves (read-only).
3584	* @param pVM The VM handle.
3585	* @remark Intended for PATM.
3586	*/
3587	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3588	{
3589	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3590	}
3591
3592
3593	/**
3594	* Gets a pointer to the array of centaur CPUID leaves.
3595	*
3596	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3597	*
3598	* @returns Pointer to the centaur CPUID leaves (read-only).
3599	* @param pVM The VM handle.
3600	* @remark Intended for PATM.
3601	*/
3602	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3603	{
3604	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3605	}
3606
3607
3608	/**
3609	* Gets a pointer to the default CPUID leaf.
3610	*
3611	* @returns Pointer to the default CPUID leaf (read-only).
3612	* @param pVM The VM handle.
3613	* @remark Intended for PATM.
3614	*/
3615	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3616	{
3617	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3618	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 26871

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