CPUM.cpp@ 32963

Last change on this file since 32963 was 32356, checked in by vboxsync, 14 years ago
VMM: Avoid 700 unnecessary fflush(VBox.log) calls.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 188.0 KB

Line
1	/* $Id: CPUM.cpp 32356 2010-09-09 13:43:45Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers accross world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/cpum.h>
39	#include <VBox/cpumdis.h>
40	#include <VBox/pgm.h>
41	#include <VBox/mm.h>
42	#include <VBox/selm.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/patm.h>
45	#include <VBox/hwaccm.h>
46	#include <VBox/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include <include/internal/pgm.h>
60
61	/*******************************************************************************
62	* Defined Constants And Macros *
63	*******************************************************************************/
64	/** The current saved state version. */
65	#define CPUM_SAVED_STATE_VERSION 12
66	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
67	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
68	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
69	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
70	* changes. */
71	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
72	/** The saved state version for the 2.1 trunk before the MSR changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
74	/** The saved state version of 2.0, used for backwards compatibility. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
76	/** The saved state version of 1.6, used for backwards compatability. */
77	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
78
79
80	/*******************************************************************************
81	* Structures and Typedefs *
82	*******************************************************************************/
83
84	/**
85	* What kind of cpu info dump to perform.
86	*/
87	typedef enum CPUMDUMPTYPE
88	{
89	CPUMDUMPTYPE_TERSE,
90	CPUMDUMPTYPE_DEFAULT,
91	CPUMDUMPTYPE_VERBOSE
92	} CPUMDUMPTYPE;
93	/** Pointer to a cpu info dump type. */
94	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
101	static int cpumR3CpuIdInit(PVM pVM);
102	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
103	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
104	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
106	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113
114
115	/**
116	* Initializes the CPUM.
117	*
118	* @returns VBox status code.
119	* @param pVM The VM to operate on.
120	*/
121	VMMR3DECL(int) CPUMR3Init(PVM pVM)
122	{
123	LogFlow(("CPUMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	*/
128	AssertCompileMemberAlignment(VM, cpum.s, 32);
129	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
130	AssertCompileSizeAlignment(CPUMCTX, 64);
131	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
132	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
133	AssertCompileMemberAlignment(VM, cpum, 64);
134	AssertCompileMemberAlignment(VM, aCpus, 64);
135	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
136	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
137
138	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
139	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
140	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
141
142	/* Calculate the offset from CPUMCPU to CPUM. */
143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
144	{
145	PVMCPU pVCpu = &pVM->aCpus[i];
146
147	/*
148	* Setup any fixed pointers and offsets.
149	*/
150	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
151	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
152
153	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
154	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
155	}
156
157	/*
158	* Check that the CPU supports the minimum features we require.
159	*/
160	if (!ASMHasCpuId())
161	{
162	Log(("The CPU doesn't support CPUID!\n"));
163	return VERR_UNSUPPORTED_CPU;
164	}
165	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
166	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
167
168	/* Setup the CR4 AND and OR masks used in the switcher */
169	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
170	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
171	{
172	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
173	/* No FXSAVE implies no SSE */
174	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
175	pVM->cpum.s.CR4.OrMask = 0;
176	}
177	else
178	{
179	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
181	}
182
183	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
184	{
185	Log(("The CPU doesn't support MMX!\n"));
186	return VERR_UNSUPPORTED_CPU;
187	}
188	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
189	{
190	Log(("The CPU doesn't support TSC!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	/* Bogus on AMD? */
194	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
195	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
196
197	/*
198	* Detech the host CPU vendor.
199	* (The guest CPU vendor is re-detected later on.)
200	*/
201	uint32_t uEAX, uEBX, uECX, uEDX;
202	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
204	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
205
206	/*
207	* Setup hypervisor startup values.
208	*/
209
210	/*
211	* Register saved state data item.
212	*/
213	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
214	NULL, cpumR3LiveExec, NULL,
215	NULL, cpumR3SaveExec, NULL,
216	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	/*
221	* Register info handlers.
222	*/
223	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
224	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
225	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
227	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
228	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
229
230	/*
231	* Initialize the Guest CPUID state.
232	*/
233	rc = cpumR3CpuIdInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236	CPUMR3Reset(pVM);
237	return VINF_SUCCESS;
238	}
239
240
241	/**
242	* Initializes the per-VCPU CPUM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("CPUMR3InitCPU\n"));
250	return VINF_SUCCESS;
251	}
252
253
254	/**
255	* Detect the CPU vendor give n the
256	*
257	* @returns The vendor.
258	* @param uEAX EAX from CPUID(0).
259	* @param uEBX EBX from CPUID(0).
260	* @param uECX ECX from CPUID(0).
261	* @param uEDX EDX from CPUID(0).
262	*/
263	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
264	{
265	if ( uEAX >= 1
266	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
267	&& uECX == X86_CPUID_VENDOR_AMD_ECX
268	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
269	return CPUMCPUVENDOR_AMD;
270
271	if ( uEAX >= 1
272	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
273	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
274	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
275	return CPUMCPUVENDOR_INTEL;
276
277	/** @todo detect the other buggers... */
278	return CPUMCPUVENDOR_UNKNOWN;
279	}
280
281
282	/**
283	* Fetches overrides for a CPUID leaf.
284	*
285	* @returns VBox status code.
286	* @param pLeaf The leaf to load the overrides into.
287	* @param pCfgNode The CFGM node containing the overrides
288	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
289	* @param iLeaf The CPUID leaf number.
290	*/
291	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
292	{
293	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
294	if (pLeafNode)
295	{
296	uint32_t u32;
297	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->eax = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->ebx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
310	if (RT_SUCCESS(rc))
311	pLeaf->ecx = u32;
312	else
313	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
314
315	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
316	if (RT_SUCCESS(rc))
317	pLeaf->edx = u32;
318	else
319	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
320
321	}
322	return VINF_SUCCESS;
323	}
324
325
326	/**
327	* Load the overrides for a set of CPUID leaves.
328	*
329	* @returns VBox status code.
330	* @param paLeaves The leaf array.
331	* @param cLeaves The number of leaves.
332	* @param uStart The start leaf number.
333	* @param pCfgNode The CFGM node containing the overrides
334	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
335	*/
336	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
337	{
338	for (uint32_t i = 0; i < cLeaves; i++)
339	{
340	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
341	if (RT_FAILURE(rc))
342	return rc;
343	}
344
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Init a set of host CPUID leaves.
350	*
351	* @returns VBox status code.
352	* @param paLeaves The leaf array.
353	* @param cLeaves The number of leaves.
354	* @param uStart The start leaf number.
355	* @param pCfgNode The /CPUM/HostCPUID/ node.
356	*/
357	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
358	{
359	/* Using the ECX variant for all of them can't hurt... */
360	for (uint32_t i = 0; i < cLeaves; i++)
361	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
362
363	/* Load CPUID leaf override; we currently don't care if the user
364	specifies features the host CPU doesn't support. */
365	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
366	}
367
368
369	/**
370	* Initializes the emulated CPU's cpuid information.
371	*
372	* @returns VBox status code.
373	* @param pVM The VM to operate on.
374	*/
375	static int cpumR3CpuIdInit(PVM pVM)
376	{
377	PCPUM pCPUM = &pVM->cpum.s;
378	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
379	uint32_t i;
380	int rc;
381
382	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
383	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
384	{ \
385	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
386	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
387	}
388	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
389	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
390	{ \
391	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
392	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
393	}
394
395	/*
396	* Read the configuration.
397	*/
398	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
399	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
400	* completely overridden by VirtualBox custom strings. Some
401	* CPUID information is withheld, like the cache info. */
402	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
406	* When non-zero CPUID features that could cause portability issues will be
407	* stripped. The higher the value the more features gets stripped. Higher
408	* values should only be used when older CPUs are involved since it may
409	* harm performance and maybe also cause problems with specific guests. */
410	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
411	AssertRCReturn(rc, rc);
412
413	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
414
415	/*
416	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
417	* been overridden).
418	*/
419	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
420	* Overrides the host CPUID leaf values used for calculating the guest CPUID
421	* leaves. This can be used to preserve the CPUID values when moving a VM
422	* to a different machine. Another use is restricting (or extending) the
423	* feature set exposed to the guest. */
424	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
425	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
426	AssertRCReturn(rc, rc);
427	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
428	AssertRCReturn(rc, rc);
429	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
430	AssertRCReturn(rc, rc);
431
432	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
433	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
434
435	/*
436	* Determine the default leaf.
437	*
438	* Intel returns values of the highest standard function, while AMD
439	* returns zeros. VIA on the other hand seems to returning nothing or
440	* perhaps some random garbage, we don't try to duplicate this behavior.
441	*/
442	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
443	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
444	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
445
446
447	/* Cpuid 1 & 0x80000001:
448	* Only report features we can support.
449	*
450	* Note! When enabling new features the Synthetic CPU and Portable CPUID
451	* options may require adjusting (i.e. stripping what was enabled).
452	*/
453	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
454	\| X86_CPUID_FEATURE_EDX_VME
455	\| X86_CPUID_FEATURE_EDX_DE
456	\| X86_CPUID_FEATURE_EDX_PSE
457	\| X86_CPUID_FEATURE_EDX_TSC
458	\| X86_CPUID_FEATURE_EDX_MSR
459	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
460	\| X86_CPUID_FEATURE_EDX_MCE
461	\| X86_CPUID_FEATURE_EDX_CX8
462	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
463	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
464	//\| X86_CPUID_FEATURE_EDX_SEP
465	\| X86_CPUID_FEATURE_EDX_MTRR
466	\| X86_CPUID_FEATURE_EDX_PGE
467	\| X86_CPUID_FEATURE_EDX_MCA
468	\| X86_CPUID_FEATURE_EDX_CMOV
469	\| X86_CPUID_FEATURE_EDX_PAT
470	\| X86_CPUID_FEATURE_EDX_PSE36
471	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
472	\| X86_CPUID_FEATURE_EDX_CLFSH
473	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
474	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
475	\| X86_CPUID_FEATURE_EDX_MMX
476	\| X86_CPUID_FEATURE_EDX_FXSR
477	\| X86_CPUID_FEATURE_EDX_SSE
478	\| X86_CPUID_FEATURE_EDX_SSE2
479	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
480	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
481	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
482	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
483	\| 0;
484	pCPUM->aGuestCpuIdStd[1].ecx &= 0
485	\| X86_CPUID_FEATURE_ECX_SSE3
486	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
487	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
488	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
489	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
490	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
491	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
492	\| X86_CPUID_FEATURE_ECX_SSSE3
493	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
494	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
495	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
496	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
497	/* ECX Bit 21 - x2APIC support - not yet. */
498	// \| X86_CPUID_FEATURE_ECX_X2APIC
499	/* ECX Bit 23 - POPCNT instruction. */
500	//\| X86_CPUID_FEATURE_ECX_POPCNT
501	\| 0;
502	if (pCPUM->u8PortableCpuIdLevel > 0)
503	{
504	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
505	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
506	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
507	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
508	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
509	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
510	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
511
512	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
513	\| X86_CPUID_FEATURE_EDX_PSN
514	\| X86_CPUID_FEATURE_EDX_DS
515	\| X86_CPUID_FEATURE_EDX_ACPI
516	\| X86_CPUID_FEATURE_EDX_SS
517	\| X86_CPUID_FEATURE_EDX_TM
518	\| X86_CPUID_FEATURE_EDX_PBE
519	)));
520	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
521	\| X86_CPUID_FEATURE_ECX_DTES64
522	\| X86_CPUID_FEATURE_ECX_CPLDS
523	\| X86_CPUID_FEATURE_ECX_VMX
524	\| X86_CPUID_FEATURE_ECX_SMX
525	\| X86_CPUID_FEATURE_ECX_EST
526	\| X86_CPUID_FEATURE_ECX_TM2
527	\| X86_CPUID_FEATURE_ECX_CNTXID
528	\| X86_CPUID_FEATURE_ECX_FMA
529	\| X86_CPUID_FEATURE_ECX_CX16
530	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
531	\| X86_CPUID_FEATURE_ECX_PDCM
532	\| X86_CPUID_FEATURE_ECX_DCA
533	\| X86_CPUID_FEATURE_ECX_MOVBE
534	\| X86_CPUID_FEATURE_ECX_AES
535	\| X86_CPUID_FEATURE_ECX_POPCNT
536	\| X86_CPUID_FEATURE_ECX_XSAVE
537	\| X86_CPUID_FEATURE_ECX_OSXSAVE
538	\| X86_CPUID_FEATURE_ECX_AVX
539	)));
540	}
541
542	/* Cpuid 0x80000001:
543	* Only report features we can support.
544	*
545	* Note! When enabling new features the Synthetic CPU and Portable CPUID
546	* options may require adjusting (i.e. stripping what was enabled).
547	*
548	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
549	*/
550	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
551	\| X86_CPUID_AMD_FEATURE_EDX_VME
552	\| X86_CPUID_AMD_FEATURE_EDX_DE
553	\| X86_CPUID_AMD_FEATURE_EDX_PSE
554	\| X86_CPUID_AMD_FEATURE_EDX_TSC
555	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
556	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
557	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
558	\| X86_CPUID_AMD_FEATURE_EDX_CX8
559	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
560	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
561	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
562	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
563	\| X86_CPUID_AMD_FEATURE_EDX_PGE
564	\| X86_CPUID_AMD_FEATURE_EDX_MCA
565	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
566	\| X86_CPUID_AMD_FEATURE_EDX_PAT
567	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
568	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
569	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
570	\| X86_CPUID_AMD_FEATURE_EDX_MMX
571	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
572	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
573	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
574	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
575	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
576	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
577	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
578	\| 0;
579	pCPUM->aGuestCpuIdExt[1].ecx &= 0
580	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
581	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
582	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
583	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
584	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
585	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
586	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
587	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
588	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
589	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
590	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
591	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
592	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
593	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
594	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
595	\| 0;
596	if (pCPUM->u8PortableCpuIdLevel > 0)
597	{
598	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
599	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
600	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
601	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
602	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
603	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
604	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
605
606	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
607	\| X86_CPUID_AMD_FEATURE_ECX_SVM
608	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
609	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
610	\| X86_CPUID_AMD_FEATURE_ECX_ABM
611	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
612	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
613	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
614	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
615	\| X86_CPUID_AMD_FEATURE_ECX_IBS
616	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
617	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
618	\| X86_CPUID_AMD_FEATURE_ECX_WDT
619	\| UINT32_C(0xffffc000)
620	)));
621	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
622	\| X86_CPUID_AMD_FEATURE_EDX_SEP
623	\| RT_BIT(18)
624	\| RT_BIT(19)
625	\| RT_BIT(21)
626	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
627	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
628	\| RT_BIT(28)
629	)));
630	}
631
632	/*
633	* Apply the Synthetic CPU modifications. (TODO: move this up)
634	*/
635	if (pCPUM->fSyntheticCpu)
636	{
637	static const char s_szVendor[13] = "VirtualBox ";
638	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
639
640	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
641
642	/* Limit the nr of standard leaves; 5 for monitor/mwait */
643	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
644
645	/* 0: Vendor */
646	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
647	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
648	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
649
650	/* 1.eax: Version information. family : model : stepping */
651	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
652
653	/* Leaves 2 - 4 are Intel only - zero them out */
654	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
655	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
656	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
657
658	/* Leaf 5 = monitor/mwait */
659
660	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
661	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
662	/* AMD only - set to zero. */
663	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
664
665	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
666	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
667
668	/* 0x800000002-4: Processor Name String Identifier. */
669	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
670	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
671	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
672	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
673	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
674	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
675	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
676	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
677	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
678	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
679	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
680	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
681
682	/* 0x800000005-7 - reserved -> zero */
683	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
684	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
685	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
686
687	/* 0x800000008: only the max virtual and physical address size. */
688	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
689	}
690
691	/*
692	* Hide HTT, multicode, SMP, whatever.
693	* (APIC-ID := 0 and #LogCpus := 0)
694	*/
695	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
696	#ifdef VBOX_WITH_MULTI_CORE
697	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
698	&& pVM->cCpus > 1)
699	{
700	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
701	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
702	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
703	}
704	#endif
705
706	/* Cpuid 2:
707	* Intel: Cache and TLB information
708	* AMD: Reserved
709	* Safe to expose; restrict the number of calls to 1 for the portable case.
710	*/
711	if ( pCPUM->u8PortableCpuIdLevel > 0
712	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
713	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
714	{
715	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
716	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
717	}
718
719	/* Cpuid 3:
720	* Intel: EAX, EBX - reserved (transmeta uses these)
721	* ECX, EDX - Processor Serial Number if available, otherwise reserved
722	* AMD: Reserved
723	* Safe to expose
724	*/
725	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
726	{
727	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
728	if (pCPUM->u8PortableCpuIdLevel > 0)
729	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
730	}
731
732	/* Cpuid 4:
733	* Intel: Deterministic Cache Parameters Leaf
734	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
735	* AMD: Reserved
736	* Safe to expose, except for EAX:
737	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
738	* Bits 31-26: Maximum number of processor cores in this physical package**
739	* Note: These SMP values are constant regardless of ECX
740	*/
741	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
742	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
743	#ifdef VBOX_WITH_MULTI_CORE
744	if ( pVM->cCpus > 1
745	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
746	{
747	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
748	/* One logical processor with possibly multiple cores. */
749	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
750	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
751	}
752	#endif
753
754	/* Cpuid 5: Monitor/mwait Leaf
755	* Intel: ECX, EDX - reserved
756	* EAX, EBX - Smallest and largest monitor line size
757	* AMD: EDX - reserved
758	* EAX, EBX - Smallest and largest monitor line size
759	* ECX - extensions (ignored for now)
760	* Safe to expose
761	*/
762	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
763	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
764
765	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
766	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
767	* Expose MWAIT extended features to the guest. For now we expose
768	* just MWAIT break on interrupt feature (bit 1).
769	*/
770	bool fMWaitExtensions;
771	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
772	if (fMWaitExtensions)
773	{
774	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
775	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
776	it shall be part of our power management virtualization model */
777	#if 0
778	/* MWAIT sub C-states */
779	pCPUM->aGuestCpuIdStd[5].edx =
780	(0 << 0) /* 0 in C0 */ \|
781	(2 << 4) /* 2 in C1 */ \|
782	(2 << 8) /* 2 in C2 */ \|
783	(2 << 12) /* 2 in C3 */ \|
784	(0 << 16) /* 0 in C4 */
785	;
786	#endif
787	}
788	else
789	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
790
791	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
792	* Safe to pass on to the guest.
793	*
794	* Intel: 0x800000005 reserved
795	* 0x800000006 L2 cache information
796	* AMD: 0x800000005 L1 cache information
797	* 0x800000006 L2/L3 cache information
798	*/
799
800	/* Cpuid 0x800000007:
801	* AMD: EAX, EBX, ECX - reserved
802	* EDX: Advanced Power Management Information
803	* Intel: Reserved
804	*/
805	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
806	{
807	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
808
809	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
810
811	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
812	{
813	/* Only expose the TSC invariant capability bit to the guest. */
814	pCPUM->aGuestCpuIdExt[7].edx &= 0
815	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
816	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
817	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
818	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
819	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
820	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
821	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
822	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
823	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
824	* Linux kernels blindly assume that the AMD performance counters work
825	* if this is set for 64 bits guests. (Can't really find a CPUID feature
826	* bit for them though.) */
827	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
828	#endif
829	\| 0;
830	}
831	else
832	pCPUM->aGuestCpuIdExt[7].edx = 0;
833	}
834
835	/* Cpuid 0x800000008:
836	* AMD: EBX, EDX - reserved
837	* EAX: Virtual/Physical/Guest address Size
838	* ECX: Number of cores + APICIdCoreIdSize
839	* Intel: EAX: Virtual/Physical address Size
840	* EBX, ECX, EDX - reserved
841	*/
842	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
843	{
844	/* Only expose the virtual and physical address sizes to the guest. */
845	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
846	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
847	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
848	* NC (0-7) Number of cores; 0 equals 1 core */
849	pCPUM->aGuestCpuIdExt[8].ecx = 0;
850	#ifdef VBOX_WITH_MULTI_CORE
851	if ( pVM->cCpus > 1
852	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
853	{
854	/* Legacy method to determine the number of cores. */
855	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
856	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
857	}
858	#endif
859	}
860
861	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
862	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
863	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
864	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
865	*/
866	bool fNt4LeafLimit;
867	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
868	if (fNt4LeafLimit)
869	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
870
871	/*
872	* Limit it the number of entries and fill the remaining with the defaults.
873	*
874	* The limits are masking off stuff about power saving and similar, this
875	* is perhaps a bit crudely done as there is probably some relatively harmless
876	* info too in these leaves (like words about having a constant TSC).
877	*/
878	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
879	pCPUM->aGuestCpuIdStd[0].eax = 5;
880	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
881	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
882
883	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
884	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
885	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
886	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
887	: 0;
888	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
889	i++)
890	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
891
892	/*
893	* Centaur stuff (VIA).
894	*
895	* The important part here (we think) is to make sure the 0xc0000000
896	* function returns 0xc0000001. As for the features, we don't currently
897	* let on about any of those... 0xc0000002 seems to be some
898	* temperature/hz/++ stuff, include it as well (static).
899	*/
900	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
901	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
902	{
903	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
904	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
905	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
906	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
907	i++)
908	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
909	}
910	else
911	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
912	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
913
914
915	/*
916	* Load CPUID overrides from configuration.
917	* Note: Kind of redundant now, but allows unchanged overrides
918	*/
919	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
920	* Overrides the CPUID leaf values. */
921	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
922	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
923	AssertRCReturn(rc, rc);
924	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
925	AssertRCReturn(rc, rc);
926	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
927	AssertRCReturn(rc, rc);
928
929	/*
930	* Check if PAE was explicitely enabled by the user.
931	*/
932	bool fEnable;
933	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
934	if (fEnable)
935	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
936
937	/*
938	* We don't normally enable NX for raw-mode, so give the user a chance to
939	* force it on.
940	*/
941	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
942	if (fEnable)
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
944
945	/*
946	* Log the cpuid and we're good.
947	*/
948	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
949	RTCPUSET OnlineSet;
950	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
951	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
952	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
953	LogRel(("*********************** CPUID dump **********************\n"));
954	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
955	LogRel(("\n"));
956	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
957	RTLogRelSetBuffering(fOldBuffered);
958	LogRel(("****************** End of CPUID dump ********************\n"));
959
960	#undef PORTABLE_DISABLE_FEATURE_BIT
961	#undef PORTABLE_CLEAR_BITS_WHEN
962
963	return VINF_SUCCESS;
964	}
965
966
967	/**
968	* Applies relocations to data and code managed by this
969	* component. This function will be called at init and
970	* whenever the VMM need to relocate it self inside the GC.
971	*
972	* The CPUM will update the addresses used by the switcher.
973	*
974	* @param pVM The VM.
975	*/
976	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
977	{
978	LogFlow(("CPUMR3Relocate\n"));
979	for (VMCPUID i = 0; i < pVM->cCpus; i++)
980	{
981	/*
982	* Switcher pointers.
983	*/
984	PVMCPU pVCpu = &pVM->aCpus[i];
985	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
986	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
987
988	}
989	}
990
991
992	/**
993	* Apply late CPUM property changes based on the fHWVirtEx setting
994	*
995	* @param pVM The VM to operate on.
996	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
997	*/
998	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
999	{
1000	/*
1001	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1002	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1003	* of processors from (cpuid(4).eax >> 26) + 1.
1004	*
1005	* Note: this code is obsolete, but let's keep it here for reference.
1006	* Purpose is valid when we artifically cap the max std id to less than 4.
1007	*/
1008	if (!fHWVirtExEnabled)
1009	{
1010	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
1011	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1012	}
1013	}
1014
1015	/**
1016	* Terminates the CPUM.
1017	*
1018	* Termination means cleaning up and freeing all resources,
1019	* the VM it self is at this point powered off or suspended.
1020	*
1021	* @returns VBox status code.
1022	* @param pVM The VM to operate on.
1023	*/
1024	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1025	{
1026	CPUMR3TermCPU(pVM);
1027	return 0;
1028	}
1029
1030
1031	/**
1032	* Terminates the per-VCPU CPUM.
1033	*
1034	* Termination means cleaning up and freeing all resources,
1035	* the VM it self is at this point powered off or suspended.
1036	*
1037	* @returns VBox status code.
1038	* @param pVM The VM to operate on.
1039	*/
1040	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
1041	{
1042	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1043	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1044	{
1045	PVMCPU pVCpu = &pVM->aCpus[i];
1046	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1047
1048	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1049	pVCpu->cpum.s.uMagic = 0;
1050	pCtx->dr[5] = 0;
1051	}
1052	#endif
1053	return 0;
1054	}
1055
1056
1057	/**
1058	* Resets a virtual CPU.
1059	*
1060	* Used by CPUMR3Reset and CPU hot plugging.
1061	*
1062	* @param pVCpu The virtual CPU handle.
1063	*/
1064	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1065	{
1066	/** @todo anything different for VCPU > 0? */
1067	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1068
1069	/*
1070	* Initialize everything to ZERO first.
1071	*/
1072	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1073	memset(pCtx, 0, sizeof(*pCtx));
1074	pVCpu->cpum.s.fUseFlags = fUseFlags;
1075
1076	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1077	pCtx->eip = 0x0000fff0;
1078	pCtx->edx = 0x00000600; /* P6 processor */
1079	pCtx->eflags.Bits.u1Reserved0 = 1;
1080
1081	pCtx->cs = 0xf000;
1082	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1083	pCtx->csHid.u32Limit = 0x0000ffff;
1084	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1085	pCtx->csHid.Attr.n.u1Present = 1;
1086	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1087
1088	pCtx->dsHid.u32Limit = 0x0000ffff;
1089	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1090	pCtx->dsHid.Attr.n.u1Present = 1;
1091	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1092
1093	pCtx->esHid.u32Limit = 0x0000ffff;
1094	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1095	pCtx->esHid.Attr.n.u1Present = 1;
1096	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1097
1098	pCtx->fsHid.u32Limit = 0x0000ffff;
1099	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1100	pCtx->fsHid.Attr.n.u1Present = 1;
1101	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1102
1103	pCtx->gsHid.u32Limit = 0x0000ffff;
1104	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1105	pCtx->gsHid.Attr.n.u1Present = 1;
1106	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1107
1108	pCtx->ssHid.u32Limit = 0x0000ffff;
1109	pCtx->ssHid.Attr.n.u1Present = 1;
1110	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1111	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1112
1113	pCtx->idtr.cbIdt = 0xffff;
1114	pCtx->gdtr.cbGdt = 0xffff;
1115
1116	pCtx->ldtrHid.u32Limit = 0xffff;
1117	pCtx->ldtrHid.Attr.n.u1Present = 1;
1118	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1119
1120	pCtx->trHid.u32Limit = 0xffff;
1121	pCtx->trHid.Attr.n.u1Present = 1;
1122	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1123
1124	pCtx->dr[6] = X86_DR6_INIT_VAL;
1125	pCtx->dr[7] = X86_DR7_INIT_VAL;
1126
1127	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
1128	pCtx->fpu.FCW = 0x37f;
1129
1130	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1131	pCtx->fpu.MXCSR = 0x1F80;
1132
1133	/* Init PAT MSR */
1134	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1135
1136	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1137	* The Intel docs don't mention it.
1138	*/
1139	pCtx->msrEFER = 0;
1140	}
1141
1142
1143	/**
1144	* Resets the CPU.
1145	*
1146	* @returns VINF_SUCCESS.
1147	* @param pVM The VM handle.
1148	*/
1149	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1150	{
1151	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1152	{
1153	CPUMR3ResetCpu(&pVM->aCpus[i]);
1154
1155	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1156	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1157
1158	/* Magic marker for searching in crash dumps. */
1159	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1160	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1161	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1162	#endif
1163	}
1164	}
1165
1166
1167	/**
1168	* Called both in pass 0 and the final pass.
1169	*
1170	* @param pVM The VM handle.
1171	* @param pSSM The saved state handle.
1172	*/
1173	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1174	{
1175	/*
1176	* Save all the CPU ID leaves here so we can check them for compatability
1177	* upon loading.
1178	*/
1179	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1180	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1181
1182	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1183	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1184
1185	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1186	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1187
1188	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1189
1190	/*
1191	* Save a good portion of the raw CPU IDs as well as they may come in
1192	* handy when validating features for raw mode.
1193	*/
1194	CPUMCPUID aRawStd[16];
1195	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1196	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1197	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1198	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1199
1200	CPUMCPUID aRawExt[32];
1201	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1202	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1203	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1204	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1205	}
1206
1207
1208	/**
1209	* Loads the CPU ID leaves saved by pass 0.
1210	*
1211	* @returns VBox status code.
1212	* @param pVM The VM handle.
1213	* @param pSSM The saved state handle.
1214	* @param uVersion The format version.
1215	*/
1216	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1217	{
1218	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1219
1220	/*
1221	* Define a bunch of macros for simplifying the code.
1222	*/
1223	/* Generic expression + failure message. */
1224	#define CPUID_CHECK_RET(expr, fmt) \
1225	do { \
1226	if (!(expr)) \
1227	{ \
1228	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1229	if (fStrictCpuIdChecks) \
1230	{ \
1231	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1232	RTStrFree(pszMsg); \
1233	return rcCpuid; \
1234	} \
1235	LogRel(("CPUM: %s\n", pszMsg)); \
1236	RTStrFree(pszMsg); \
1237	} \
1238	} while (0)
1239	#define CPUID_CHECK_WRN(expr, fmt) \
1240	do { \
1241	if (!(expr)) \
1242	LogRel(fmt); \
1243	} while (0)
1244
1245	/* For comparing two values and bitch if they differs. */
1246	#define CPUID_CHECK2_RET(what, host, saved) \
1247	do { \
1248	if ((host) != (saved)) \
1249	{ \
1250	if (fStrictCpuIdChecks) \
1251	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1252	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1253	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1254	} \
1255	} while (0)
1256	#define CPUID_CHECK2_WRN(what, host, saved) \
1257	do { \
1258	if ((host) != (saved)) \
1259	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1260	} while (0)
1261
1262	/* For checking raw cpu features (raw mode). */
1263	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1264	do { \
1265	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1266	{ \
1267	if (fStrictCpuIdChecks) \
1268	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1269	N_(#bit " mismatch: host=%d saved=%d"), \
1270	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1271	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1272	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1273	} \
1274	} while (0)
1275	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1276	do { \
1277	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1278	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1279	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1280	} while (0)
1281	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1282
1283	/* For checking guest features. */
1284	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1285	do { \
1286	if ( (aGuestCpuId##set [1].reg & bit) \
1287	&& !(aHostRaw##set [1].reg & bit) \
1288	&& !(aHostOverride##set [1].reg & bit) \
1289	&& !(aGuestOverride##set [1].reg & bit) \
1290	) \
1291	{ \
1292	if (fStrictCpuIdChecks) \
1293	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1294	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1295	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1296	} \
1297	} while (0)
1298	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1299	do { \
1300	if ( (aGuestCpuId##set [1].reg & bit) \
1301	&& !(aHostRaw##set [1].reg & bit) \
1302	&& !(aHostOverride##set [1].reg & bit) \
1303	&& !(aGuestOverride##set [1].reg & bit) \
1304	) \
1305	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1306	} while (0)
1307	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1308	do { \
1309	if ( (aGuestCpuId##set [1].reg & bit) \
1310	&& !(aHostRaw##set [1].reg & bit) \
1311	&& !(aHostOverride##set [1].reg & bit) \
1312	&& !(aGuestOverride##set [1].reg & bit) \
1313	) \
1314	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1315	} while (0)
1316	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1317
1318	/* For checking guest features if AMD guest CPU. */
1319	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1320	do { \
1321	if ( (aGuestCpuId##set [1].reg & bit) \
1322	&& fGuestAmd \
1323	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1324	&& !(aHostOverride##set [1].reg & bit) \
1325	&& !(aGuestOverride##set [1].reg & bit) \
1326	) \
1327	{ \
1328	if (fStrictCpuIdChecks) \
1329	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1330	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1331	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1332	} \
1333	} while (0)
1334	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1335	do { \
1336	if ( (aGuestCpuId##set [1].reg & bit) \
1337	&& fGuestAmd \
1338	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1339	&& !(aHostOverride##set [1].reg & bit) \
1340	&& !(aGuestOverride##set [1].reg & bit) \
1341	) \
1342	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1343	} while (0)
1344	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1345	do { \
1346	if ( (aGuestCpuId##set [1].reg & bit) \
1347	&& fGuestAmd \
1348	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1349	&& !(aHostOverride##set [1].reg & bit) \
1350	&& !(aGuestOverride##set [1].reg & bit) \
1351	) \
1352	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1353	} while (0)
1354	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1355
1356	/* For checking AMD features which have a corresponding bit in the standard
1357	range. (Intel defines very few bits in the extended feature sets.) */
1358	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1359	do { \
1360	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1361	&& !(fHostAmd \
1362	? aHostRawExt[1].reg & (ExtBit) \
1363	: aHostRawStd[1].reg & (StdBit)) \
1364	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1365	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1366	) \
1367	{ \
1368	if (fStrictCpuIdChecks) \
1369	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1370	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1371	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1372	} \
1373	} while (0)
1374	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1375	do { \
1376	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1377	&& !(fHostAmd \
1378	? aHostRawExt[1].reg & (ExtBit) \
1379	: aHostRawStd[1].reg & (StdBit)) \
1380	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1381	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1382	) \
1383	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1384	} while (0)
1385	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1386	do { \
1387	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1388	&& !(fHostAmd \
1389	? aHostRawExt[1].reg & (ExtBit) \
1390	: aHostRawStd[1].reg & (StdBit)) \
1391	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1392	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1393	) \
1394	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1395	} while (0)
1396	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1397
1398	/*
1399	* Load them into stack buffers first.
1400	*/
1401	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1402	uint32_t cGuestCpuIdStd;
1403	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1404	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1405	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1406	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1407
1408	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1409	uint32_t cGuestCpuIdExt;
1410	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1411	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1412	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1413	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1414
1415	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1416	uint32_t cGuestCpuIdCentaur;
1417	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1418	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1419	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1420	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1421
1422	CPUMCPUID GuestCpuIdDef;
1423	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1424	AssertRCReturn(rc, rc);
1425
1426	CPUMCPUID aRawStd[16];
1427	uint32_t cRawStd;
1428	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1429	if (cRawStd > RT_ELEMENTS(aRawStd))
1430	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1431	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1432
1433	CPUMCPUID aRawExt[32];
1434	uint32_t cRawExt;
1435	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1436	if (cRawExt > RT_ELEMENTS(aRawExt))
1437	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1438	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1439	AssertRCReturn(rc, rc);
1440
1441	/*
1442	* Note that we support restoring less than the current amount of standard
1443	* leaves because we've been allowed more is newer version of VBox.
1444	*
1445	* So, pad new entries with the default.
1446	*/
1447	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1448	aGuestCpuIdStd[i] = GuestCpuIdDef;
1449
1450	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1451	aGuestCpuIdExt[i] = GuestCpuIdDef;
1452
1453	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1454	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1455
1456	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1457	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1458
1459	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1460	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1461
1462	/*
1463	* Get the raw CPU IDs for the current host.
1464	*/
1465	CPUMCPUID aHostRawStd[16];
1466	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1467	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1468
1469	CPUMCPUID aHostRawExt[32];
1470	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1471	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1472
1473	/*
1474	* Get the host and guest overrides so we don't reject the state because
1475	* some feature was enabled thru these interfaces.
1476	* Note! We currently only need the feature leaves, so skip rest.
1477	*/
1478	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1479	CPUMCPUID aGuestOverrideStd[2];
1480	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1481	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1482
1483	CPUMCPUID aGuestOverrideExt[2];
1484	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1485	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1486
1487	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1488	CPUMCPUID aHostOverrideStd[2];
1489	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1490	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1491
1492	CPUMCPUID aHostOverrideExt[2];
1493	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1494	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1495
1496	/*
1497	* This can be skipped.
1498	*/
1499	bool fStrictCpuIdChecks;
1500	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1501
1502
1503
1504	/*
1505	* For raw-mode we'll require that the CPUs are very similar since we don't
1506	* intercept CPUID instructions for user mode applications.
1507	*/
1508	if (!HWACCMIsEnabled(pVM))
1509	{
1510	/* CPUID(0) */
1511	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1512	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1513	&& aHostRawStd[0].edx == aRawStd[0].edx,
1514	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1515	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1516	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1517	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1518	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1519	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1520
1521	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1522
1523	/* CPUID(1).eax */
1524	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1525	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1526	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1527
1528	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1529	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1530	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1531
1532	/* CPUID(1).ecx */
1533	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1535	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1536	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1537	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1538	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1539	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1540	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1541	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1543	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1545	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1547	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1548	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1549	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1551	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1552	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1553	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1554	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1555	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1556	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1557	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1558	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1559	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1560	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1561	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1562	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1563	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1564	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1565
1566	/* CPUID(1).edx */
1567	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1568	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1569	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1571	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1572	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1573	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1575	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1576	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1577	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1578	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1579	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1580	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1581	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1582	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1583	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1584	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1585	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1586	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1587	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1588	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1589	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1590	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1591	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1592	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1593	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1594	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1595	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1596	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1597	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1598	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1599
1600	/* CPUID(2) - config, mostly about caches. ignore. */
1601	/* CPUID(3) - processor serial number. ignore. */
1602	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1603	/* CPUID(5) - mwait/monitor config. ignore. */
1604	/* CPUID(6) - power management. ignore. */
1605	/* CPUID(7) - ???. ignore. */
1606	/* CPUID(8) - ???. ignore. */
1607	/* CPUID(9) - DCA. ignore for now. */
1608	/* CPUID(a) - PeMo info. ignore for now. */
1609	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1610
1611	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1612	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1613	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1614	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1615	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1616	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1617	{
1618	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1619	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1620	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1621	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1622	}
1623
1624	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1625	Note! Intel have/is marking many of the fields here as reserved. We
1626	will verify them as if it's an AMD CPU. */
1627	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1628	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1629	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1630	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1631	{
1632	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1633	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1634	&& aHostRawExt[0].edx == aRawExt[0].edx,
1635	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1636	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1637	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1638	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1639
1640	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1641	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1642	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1643	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1644	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1645	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1646
1647	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1648	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1649	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1650	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1651
1652	/* CPUID(0x80000001).ecx */
1653	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1654	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1655	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1656	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1657	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1663	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1665	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1666	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1671	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1672	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1673	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1674	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1675	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1676	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1677	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1678	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1679	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1680	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1681	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1682	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1683	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1684	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1685
1686	/* CPUID(0x80000001).edx */
1687	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1688	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1689	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1690	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1691	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1692	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1693	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1695	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1696	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1700	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1701	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1702	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1703	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1704	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1705	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1706	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1707	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1708	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1709	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1710	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1711	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1712	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1713	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1714	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1715	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1716	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1717	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1718	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1719
1720	/** @todo verify the rest as well. */
1721	}
1722	}
1723
1724
1725
1726	/*
1727	* Verify that we can support the features already exposed to the guest on
1728	* this host.
1729	*
1730	* Most of the features we're emulating requires intercepting instruction
1731	* and doing it the slow way, so there is no need to warn when they aren't
1732	* present in the host CPU. Thus we use IGN instead of EMU on these.
1733	*
1734	* Trailing comments:
1735	* "EMU" - Possible to emulate, could be lots of work and very slow.
1736	* "EMU?" - Can this be emulated?
1737	*/
1738	/* CPUID(1).ecx */
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1740	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1741	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1742	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1744	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1745	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1746	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1747	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1749	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1750	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1752	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1753	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1754	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1755	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1756	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1757	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1758	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1759	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1760	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1761	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1762	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1763	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1764	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1765	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1766	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1767	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1768	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1769	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1770	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1771
1772	/* CPUID(1).edx */
1773	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1774	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1775	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1776	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1777	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1778	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1779	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1780	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1781	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1782	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1783	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1784	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1785	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1786	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1787	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1789	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1790	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1791	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1792	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1793	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1794	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1795	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1796	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1797	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1798	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1799	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1800	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1801	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1802	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1803	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1804	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1805
1806	/* CPUID(0x80000000). */
1807	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1808	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1809	{
1810	/** @todo deal with no 0x80000001 on the host. */
1811	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1812	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1813
1814	/* CPUID(0x80000001).ecx */
1815	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1817	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1818	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1819	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1820	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1821	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1822	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1823	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1824	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1825	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1826	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1827	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1828	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1833	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1834	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1835	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1836	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1837	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1838	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1839	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1840	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1841	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1842	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1843	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1844	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1845	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1846	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1847
1848	/* CPUID(0x80000001).edx */
1849	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1850	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1851	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1852	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1853	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1854	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1855	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1856	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1857	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1858	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1859	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1860	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1861	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1862	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1863	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1864	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1865	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1866	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1867	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1868	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1869	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1870	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1871	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1872	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1873	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1874	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1875	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1876	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1877	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1878	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1879	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1880	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1881	}
1882
1883	/*
1884	* We're good, commit the CPU ID leaves.
1885	*/
1886	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1887	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1888	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1889	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1890
1891	#undef CPUID_CHECK_RET
1892	#undef CPUID_CHECK_WRN
1893	#undef CPUID_CHECK2_RET
1894	#undef CPUID_CHECK2_WRN
1895	#undef CPUID_RAW_FEATURE_RET
1896	#undef CPUID_RAW_FEATURE_WRN
1897	#undef CPUID_RAW_FEATURE_IGN
1898	#undef CPUID_GST_FEATURE_RET
1899	#undef CPUID_GST_FEATURE_WRN
1900	#undef CPUID_GST_FEATURE_EMU
1901	#undef CPUID_GST_FEATURE_IGN
1902	#undef CPUID_GST_FEATURE2_RET
1903	#undef CPUID_GST_FEATURE2_WRN
1904	#undef CPUID_GST_FEATURE2_EMU
1905	#undef CPUID_GST_FEATURE2_IGN
1906	#undef CPUID_GST_AMD_FEATURE_RET
1907	#undef CPUID_GST_AMD_FEATURE_WRN
1908	#undef CPUID_GST_AMD_FEATURE_EMU
1909	#undef CPUID_GST_AMD_FEATURE_IGN
1910
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	/**
1916	* Pass 0 live exec callback.
1917	*
1918	* @returns VINF_SSM_DONT_CALL_AGAIN.
1919	* @param pVM The VM handle.
1920	* @param pSSM The saved state handle.
1921	* @param uPass The pass (0).
1922	*/
1923	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1924	{
1925	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1926	cpumR3SaveCpuId(pVM, pSSM);
1927	return VINF_SSM_DONT_CALL_AGAIN;
1928	}
1929
1930
1931	/**
1932	* Execute state save operation.
1933	*
1934	* @returns VBox status code.
1935	* @param pVM VM Handle.
1936	* @param pSSM SSM operation handle.
1937	*/
1938	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1939	{
1940	/*
1941	* Save.
1942	*/
1943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1944	{
1945	PVMCPU pVCpu = &pVM->aCpus[i];
1946
1947	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1948	}
1949
1950	SSMR3PutU32(pSSM, pVM->cCpus);
1951	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1952	{
1953	PVMCPU pVCpu = &pVM->aCpus[i];
1954
1955	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1956	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1957	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1958	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1959	}
1960
1961	cpumR3SaveCpuId(pVM, pSSM);
1962	return VINF_SUCCESS;
1963	}
1964
1965
1966	/**
1967	* Load a version 1.6 CPUMCTX structure.
1968	*
1969	* @returns VBox status code.
1970	* @param pVM VM Handle.
1971	* @param pCpumctx16 Version 1.6 CPUMCTX
1972	*/
1973	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1974	{
1975	#define CPUMCTX16_LOADREG(RegName) \
1976	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1977
1978	#define CPUMCTX16_LOADDRXREG(RegName) \
1979	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1980
1981	#define CPUMCTX16_LOADHIDREG(RegName) \
1982	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1983	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1984	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1985
1986	#define CPUMCTX16_LOADSEGREG(RegName) \
1987	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1988	CPUMCTX16_LOADHIDREG(RegName);
1989
1990	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1991
1992	CPUMCTX16_LOADREG(rax);
1993	CPUMCTX16_LOADREG(rbx);
1994	CPUMCTX16_LOADREG(rcx);
1995	CPUMCTX16_LOADREG(rdx);
1996	CPUMCTX16_LOADREG(rdi);
1997	CPUMCTX16_LOADREG(rsi);
1998	CPUMCTX16_LOADREG(rbp);
1999	CPUMCTX16_LOADREG(esp);
2000	CPUMCTX16_LOADREG(rip);
2001	CPUMCTX16_LOADREG(rflags);
2002
2003	CPUMCTX16_LOADSEGREG(cs);
2004	CPUMCTX16_LOADSEGREG(ds);
2005	CPUMCTX16_LOADSEGREG(es);
2006	CPUMCTX16_LOADSEGREG(fs);
2007	CPUMCTX16_LOADSEGREG(gs);
2008	CPUMCTX16_LOADSEGREG(ss);
2009
2010	CPUMCTX16_LOADREG(r8);
2011	CPUMCTX16_LOADREG(r9);
2012	CPUMCTX16_LOADREG(r10);
2013	CPUMCTX16_LOADREG(r11);
2014	CPUMCTX16_LOADREG(r12);
2015	CPUMCTX16_LOADREG(r13);
2016	CPUMCTX16_LOADREG(r14);
2017	CPUMCTX16_LOADREG(r15);
2018
2019	CPUMCTX16_LOADREG(cr0);
2020	CPUMCTX16_LOADREG(cr2);
2021	CPUMCTX16_LOADREG(cr3);
2022	CPUMCTX16_LOADREG(cr4);
2023
2024	CPUMCTX16_LOADDRXREG(0);
2025	CPUMCTX16_LOADDRXREG(1);
2026	CPUMCTX16_LOADDRXREG(2);
2027	CPUMCTX16_LOADDRXREG(3);
2028	CPUMCTX16_LOADDRXREG(4);
2029	CPUMCTX16_LOADDRXREG(5);
2030	CPUMCTX16_LOADDRXREG(6);
2031	CPUMCTX16_LOADDRXREG(7);
2032
2033	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2034	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2035	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2036	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2037
2038	CPUMCTX16_LOADREG(ldtr);
2039	CPUMCTX16_LOADREG(tr);
2040
2041	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2042
2043	CPUMCTX16_LOADREG(msrEFER);
2044	CPUMCTX16_LOADREG(msrSTAR);
2045	CPUMCTX16_LOADREG(msrPAT);
2046	CPUMCTX16_LOADREG(msrLSTAR);
2047	CPUMCTX16_LOADREG(msrCSTAR);
2048	CPUMCTX16_LOADREG(msrSFMASK);
2049	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2050
2051	CPUMCTX16_LOADHIDREG(ldtr);
2052	CPUMCTX16_LOADHIDREG(tr);
2053
2054	#undef CPUMCTX16_LOADSEGREG
2055	#undef CPUMCTX16_LOADHIDREG
2056	#undef CPUMCTX16_LOADDRXREG
2057	#undef CPUMCTX16_LOADREG
2058	}
2059
2060
2061	/**
2062	* @copydoc FNSSMINTLOADPREP
2063	*/
2064	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2065	{
2066	pVM->cpum.s.fPendingRestore = true;
2067	return VINF_SUCCESS;
2068	}
2069
2070
2071	/**
2072	* @copydoc FNSSMINTLOADEXEC
2073	*/
2074	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2075	{
2076	/*
2077	* Validate version.
2078	*/
2079	if ( uVersion != CPUM_SAVED_STATE_VERSION
2080	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2081	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2082	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2083	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2084	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2085	{
2086	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2087	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2088	}
2089
2090	if (uPass == SSM_PASS_FINAL)
2091	{
2092	/*
2093	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2094	* really old SSM file versions.)
2095	*/
2096	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2097	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2098	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2099	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2100
2101	/*
2102	* Restore.
2103	*/
2104	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2105	{
2106	PVMCPU pVCpu = &pVM->aCpus[i];
2107	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2108	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2109
2110	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2111	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2112	pVCpu->cpum.s.Hyper.esp = uESP;
2113	}
2114
2115	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2116	{
2117	CPUMCTX_VER1_6 cpumctx16;
2118	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2119	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2120
2121	/* Save the old cpumctx state into the new one. */
2122	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2123
2124	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2125	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2126	}
2127	else
2128	{
2129	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2130	{
2131	uint32_t cCpus;
2132	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2133	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2134	VERR_SSM_UNEXPECTED_DATA);
2135	}
2136	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2137	\|\| pVM->cCpus == 1,
2138	("cCpus=%u\n", pVM->cCpus),
2139	VERR_SSM_UNEXPECTED_DATA);
2140
2141	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2142	{
2143	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2144	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2145	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2146	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2147	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2148	}
2149	}
2150
2151	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2152	raw-mode guest, so we have to do it ourselves. */
2153	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2154	&& !HWACCMIsEnabled(pVM))
2155	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2156	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2157	}
2158
2159	pVM->cpum.s.fPendingRestore = false;
2160
2161	/*
2162	* Guest CPUIDs.
2163	*/
2164	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2165	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2166
2167	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2168	* actually required. */
2169
2170	/*
2171	* Restore the CPUID leaves.
2172	*
2173	* Note that we support restoring less than the current amount of standard
2174	* leaves because we've been allowed more is newer version of VBox.
2175	*/
2176	uint32_t cElements;
2177	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2178	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2179	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2180	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2181
2182	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2183	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2184	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2185	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2186
2187	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2188	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2189	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2190	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2191
2192	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2193
2194	/*
2195	* Check that the basic cpuid id information is unchanged.
2196	*/
2197	/** @todo we should check the 64 bits capabilities too! */
2198	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2199	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2200	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2201	uint32_t au32CpuIdSaved[8];
2202	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2203	if (RT_SUCCESS(rc))
2204	{
2205	/* Ignore CPU stepping. */
2206	au32CpuId[4] &= 0xfffffff0;
2207	au32CpuIdSaved[4] &= 0xfffffff0;
2208
2209	/* Ignore APIC ID (AMD specs). */
2210	au32CpuId[5] &= ~0xff000000;
2211	au32CpuIdSaved[5] &= ~0xff000000;
2212
2213	/* Ignore the number of Logical CPUs (AMD specs). */
2214	au32CpuId[5] &= ~0x00ff0000;
2215	au32CpuIdSaved[5] &= ~0x00ff0000;
2216
2217	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2218	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2219	\| X86_CPUID_FEATURE_ECX_VMX
2220	\| X86_CPUID_FEATURE_ECX_SMX
2221	\| X86_CPUID_FEATURE_ECX_EST
2222	\| X86_CPUID_FEATURE_ECX_TM2
2223	\| X86_CPUID_FEATURE_ECX_CNTXID
2224	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2225	\| X86_CPUID_FEATURE_ECX_PDCM
2226	\| X86_CPUID_FEATURE_ECX_DCA
2227	\| X86_CPUID_FEATURE_ECX_X2APIC
2228	);
2229	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2230	\| X86_CPUID_FEATURE_ECX_VMX
2231	\| X86_CPUID_FEATURE_ECX_SMX
2232	\| X86_CPUID_FEATURE_ECX_EST
2233	\| X86_CPUID_FEATURE_ECX_TM2
2234	\| X86_CPUID_FEATURE_ECX_CNTXID
2235	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2236	\| X86_CPUID_FEATURE_ECX_PDCM
2237	\| X86_CPUID_FEATURE_ECX_DCA
2238	\| X86_CPUID_FEATURE_ECX_X2APIC
2239	);
2240
2241	/* Make sure we don't forget to update the masks when enabling
2242	* features in the future.
2243	*/
2244	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2245	( X86_CPUID_FEATURE_ECX_DTES64
2246	\| X86_CPUID_FEATURE_ECX_VMX
2247	\| X86_CPUID_FEATURE_ECX_SMX
2248	\| X86_CPUID_FEATURE_ECX_EST
2249	\| X86_CPUID_FEATURE_ECX_TM2
2250	\| X86_CPUID_FEATURE_ECX_CNTXID
2251	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2252	\| X86_CPUID_FEATURE_ECX_PDCM
2253	\| X86_CPUID_FEATURE_ECX_DCA
2254	\| X86_CPUID_FEATURE_ECX_X2APIC
2255	)));
2256	/* do the compare */
2257	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2258	{
2259	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2260	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2261	"Saved=%.*Rhxs\n"
2262	"Real =%.*Rhxs\n",
2263	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2264	sizeof(au32CpuId), au32CpuId));
2265	else
2266	{
2267	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2268	"Saved=%.*Rhxs\n"
2269	"Real =%.*Rhxs\n",
2270	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2271	sizeof(au32CpuId), au32CpuId));
2272	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2273	}
2274	}
2275	}
2276
2277	return rc;
2278	}
2279
2280
2281	/**
2282	* @copydoc FNSSMINTLOADPREP
2283	*/
2284	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2285	{
2286	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2287	return VINF_SUCCESS;
2288
2289	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2290	if (pVM->cpum.s.fPendingRestore)
2291	{
2292	LogRel(("CPUM: Missing state!\n"));
2293	return VERR_INTERNAL_ERROR_2;
2294	}
2295
2296	/* Notify PGM of the NXE states in case they've changed. */
2297	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2298	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2299	return VINF_SUCCESS;
2300	}
2301
2302
2303	/**
2304	* Checks if the CPUM state restore is still pending.
2305	*
2306	* @returns true / false.
2307	* @param pVM The VM handle.
2308	*/
2309	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2310	{
2311	return pVM->cpum.s.fPendingRestore;
2312	}
2313
2314
2315	/**
2316	* Formats the EFLAGS value into mnemonics.
2317	*
2318	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2319	* @param efl The EFLAGS value.
2320	*/
2321	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2322	{
2323	/*
2324	* Format the flags.
2325	*/
2326	static const struct
2327	{
2328	const char pszSet; const char pszClear; uint32_t fFlag;
2329	} s_aFlags[] =
2330	{
2331	{ "vip",NULL, X86_EFL_VIP },
2332	{ "vif",NULL, X86_EFL_VIF },
2333	{ "ac", NULL, X86_EFL_AC },
2334	{ "vm", NULL, X86_EFL_VM },
2335	{ "rf", NULL, X86_EFL_RF },
2336	{ "nt", NULL, X86_EFL_NT },
2337	{ "ov", "nv", X86_EFL_OF },
2338	{ "dn", "up", X86_EFL_DF },
2339	{ "ei", "di", X86_EFL_IF },
2340	{ "tf", NULL, X86_EFL_TF },
2341	{ "nt", "pl", X86_EFL_SF },
2342	{ "nz", "zr", X86_EFL_ZF },
2343	{ "ac", "na", X86_EFL_AF },
2344	{ "po", "pe", X86_EFL_PF },
2345	{ "cy", "nc", X86_EFL_CF },
2346	};
2347	char *psz = pszEFlags;
2348	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2349	{
2350	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2351	if (pszAdd)
2352	{
2353	strcpy(psz, pszAdd);
2354	psz += strlen(pszAdd);
2355	*psz++ = ' ';
2356	}
2357	}
2358	psz[-1] = '\0';
2359	}
2360
2361
2362	/**
2363	* Formats a full register dump.
2364	*
2365	* @param pVM VM Handle.
2366	* @param pCtx The context to format.
2367	* @param pCtxCore The context core to format.
2368	* @param pHlp Output functions.
2369	* @param enmType The dump type.
2370	* @param pszPrefix Register name prefix.
2371	*/
2372	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2373	{
2374	/*
2375	* Format the EFLAGS.
2376	*/
2377	uint32_t efl = pCtxCore->eflags.u32;
2378	char szEFlags[80];
2379	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2380
2381	/*
2382	* Format the registers.
2383	*/
2384	switch (enmType)
2385	{
2386	case CPUMDUMPTYPE_TERSE:
2387	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2388	pHlp->pfnPrintf(pHlp,
2389	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2390	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2391	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2392	"%sr14=%016RX64 %sr15=%016RX64\n"
2393	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2394	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2395	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2396	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2397	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2398	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2399	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2400	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2401	else
2402	pHlp->pfnPrintf(pHlp,
2403	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2404	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2405	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2406	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2407	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2408	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2409	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2410	break;
2411
2412	case CPUMDUMPTYPE_DEFAULT:
2413	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2414	pHlp->pfnPrintf(pHlp,
2415	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2416	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2417	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2418	"%sr14=%016RX64 %sr15=%016RX64\n"
2419	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2420	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2421	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2422	,
2423	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2424	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2425	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2426	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2427	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2428	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2429	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2430	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2431	else
2432	pHlp->pfnPrintf(pHlp,
2433	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2434	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2435	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2436	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2437	,
2438	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2439	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2440	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2441	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2442	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2443	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2444	break;
2445
2446	case CPUMDUMPTYPE_VERBOSE:
2447	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2448	pHlp->pfnPrintf(pHlp,
2449	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2450	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2451	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2452	"%sr14=%016RX64 %sr15=%016RX64\n"
2453	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2454	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2455	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2456	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2457	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2458	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2459	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2460	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2461	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2462	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2463	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2464	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2465	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2466	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2467	,
2468	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2469	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2470	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2471	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2472	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2473	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2474	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2475	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2476	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2477	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2478	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2479	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2480	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2481	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2482	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2483	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2484	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2485	else
2486	pHlp->pfnPrintf(pHlp,
2487	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2488	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2489	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2490	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2491	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2492	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2493	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2494	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2495	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2496	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2497	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2498	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2499	,
2500	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2501	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2502	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2503	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2504	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2505	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2506	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2507	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2508	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2509	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2510	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2511	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2512
2513	pHlp->pfnPrintf(pHlp,
2514	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2515	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2516	,
2517	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2518	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2519	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2520	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2521	);
2522	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2523	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2524	{
2525	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2526	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2527	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2528	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2529	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2530	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2531	/** @todo This isn't entirenly correct and needs more work! */
2532	pHlp->pfnPrintf(pHlp,
2533	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2534	pszPrefix, iST, pszPrefix, iFPR,
2535	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2536	uTag, chSign, iInteger, u64Fraction, uExponent);
2537	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2538	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2539	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2540	else
2541	pHlp->pfnPrintf(pHlp, "\n");
2542	}
2543	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2544	pHlp->pfnPrintf(pHlp,
2545	iXMM & 1
2546	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2547	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2548	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2549	pCtx->fpu.aXMM[iXMM].au32[3],
2550	pCtx->fpu.aXMM[iXMM].au32[2],
2551	pCtx->fpu.aXMM[iXMM].au32[1],
2552	pCtx->fpu.aXMM[iXMM].au32[0]);
2553	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2554	if (pCtx->fpu.au32RsrvdRest[i])
2555	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2556	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2557
2558	pHlp->pfnPrintf(pHlp,
2559	"%sEFER =%016RX64\n"
2560	"%sPAT =%016RX64\n"
2561	"%sSTAR =%016RX64\n"
2562	"%sCSTAR =%016RX64\n"
2563	"%sLSTAR =%016RX64\n"
2564	"%sSFMASK =%016RX64\n"
2565	"%sKERNELGSBASE =%016RX64\n",
2566	pszPrefix, pCtx->msrEFER,
2567	pszPrefix, pCtx->msrPAT,
2568	pszPrefix, pCtx->msrSTAR,
2569	pszPrefix, pCtx->msrCSTAR,
2570	pszPrefix, pCtx->msrLSTAR,
2571	pszPrefix, pCtx->msrSFMASK,
2572	pszPrefix, pCtx->msrKERNELGSBASE);
2573	break;
2574	}
2575	}
2576
2577
2578	/**
2579	* Display all cpu states and any other cpum info.
2580	*
2581	* @param pVM VM Handle.
2582	* @param pHlp The info helper functions.
2583	* @param pszArgs Arguments, ignored.
2584	*/
2585	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2586	{
2587	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2588	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2589	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2590	cpumR3InfoHost(pVM, pHlp, pszArgs);
2591	}
2592
2593
2594	/**
2595	* Parses the info argument.
2596	*
2597	* The argument starts with 'verbose', 'terse' or 'default' and then
2598	* continues with the comment string.
2599	*
2600	* @param pszArgs The pointer to the argument string.
2601	* @param penmType Where to store the dump type request.
2602	* @param ppszComment Where to store the pointer to the comment string.
2603	*/
2604	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2605	{
2606	if (!pszArgs)
2607	{
2608	*penmType = CPUMDUMPTYPE_DEFAULT;
2609	*ppszComment = "";
2610	}
2611	else
2612	{
2613	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2614	{
2615	pszArgs += 5;
2616	*penmType = CPUMDUMPTYPE_VERBOSE;
2617	}
2618	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2619	{
2620	pszArgs += 5;
2621	*penmType = CPUMDUMPTYPE_TERSE;
2622	}
2623	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2624	{
2625	pszArgs += 7;
2626	*penmType = CPUMDUMPTYPE_DEFAULT;
2627	}
2628	else
2629	*penmType = CPUMDUMPTYPE_DEFAULT;
2630	*ppszComment = RTStrStripL(pszArgs);
2631	}
2632	}
2633
2634
2635	/**
2636	* Display the guest cpu state.
2637	*
2638	* @param pVM VM Handle.
2639	* @param pHlp The info helper functions.
2640	* @param pszArgs Arguments, ignored.
2641	*/
2642	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2643	{
2644	CPUMDUMPTYPE enmType;
2645	const char *pszComment;
2646	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2647
2648	/* @todo SMP support! */
2649	PVMCPU pVCpu = VMMGetCpu(pVM);
2650	if (!pVCpu)
2651	pVCpu = &pVM->aCpus[0];
2652
2653	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2654
2655	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2656	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2657	}
2658
2659
2660	/**
2661	* Display the current guest instruction
2662	*
2663	* @param pVM VM Handle.
2664	* @param pHlp The info helper functions.
2665	* @param pszArgs Arguments, ignored.
2666	*/
2667	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2668	{
2669	char szInstruction[256];
2670	/* @todo SMP support! */
2671	PVMCPU pVCpu = VMMGetCpu(pVM);
2672	if (!pVCpu)
2673	pVCpu = &pVM->aCpus[0];
2674
2675	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2676	if (RT_SUCCESS(rc))
2677	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2678	}
2679
2680
2681	/**
2682	* Display the hypervisor cpu state.
2683	*
2684	* @param pVM VM Handle.
2685	* @param pHlp The info helper functions.
2686	* @param pszArgs Arguments, ignored.
2687	*/
2688	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2689	{
2690	CPUMDUMPTYPE enmType;
2691	const char *pszComment;
2692	/* @todo SMP */
2693	PVMCPU pVCpu = &pVM->aCpus[0];
2694
2695	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2696	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2697	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2698	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2699	}
2700
2701
2702	/**
2703	* Display the host cpu state.
2704	*
2705	* @param pVM VM Handle.
2706	* @param pHlp The info helper functions.
2707	* @param pszArgs Arguments, ignored.
2708	*/
2709	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2710	{
2711	CPUMDUMPTYPE enmType;
2712	const char *pszComment;
2713	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2714	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2715
2716	/*
2717	* Format the EFLAGS.
2718	*/
2719	/* @todo SMP */
2720	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2721	#if HC_ARCH_BITS == 32
2722	uint32_t efl = pCtx->eflags.u32;
2723	#else
2724	uint64_t efl = pCtx->rflags;
2725	#endif
2726	char szEFlags[80];
2727	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2728
2729	/*
2730	* Format the registers.
2731	*/
2732	#if HC_ARCH_BITS == 32
2733	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2734	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2735	# endif
2736	{
2737	pHlp->pfnPrintf(pHlp,
2738	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2739	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2740	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2741	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2742	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2743	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2744	,
2745	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2746	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2747	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2748	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2749	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2750	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2751	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2752	}
2753	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2754	else
2755	# endif
2756	#endif
2757	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2758	{
2759	pHlp->pfnPrintf(pHlp,
2760	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2761	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2762	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2763	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2764	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2765	"r14=%016RX64 r15=%016RX64\n"
2766	"iopl=%d %31s\n"
2767	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2768	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2769	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2770	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2771	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2772	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2773	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2774	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2775	,
2776	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2777	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2778	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2779	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2780	pCtx->r11, pCtx->r12, pCtx->r13,
2781	pCtx->r14, pCtx->r15,
2782	X86_EFL_GET_IOPL(efl), szEFlags,
2783	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2784	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2785	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2786	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2787	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2788	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2789	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2790	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2791	}
2792	#endif
2793	}
2794
2795
2796	/**
2797	* Get L1 cache / TLS associativity.
2798	*/
2799	static const char getCacheAss(unsigned u, char pszBuf)
2800	{
2801	if (u == 0)
2802	return "res0 ";
2803	if (u == 1)
2804	return "direct";
2805	if (u == 255)
2806	return "fully";
2807	if (u >= 256)
2808	return "???";
2809
2810	RTStrPrintf(pszBuf, 16, "%d way", u);
2811	return pszBuf;
2812	}
2813
2814
2815	/**
2816	* Get L2 cache soociativity.
2817	*/
2818	const char *getL2CacheAss(unsigned u)
2819	{
2820	switch (u)
2821	{
2822	case 0: return "off ";
2823	case 1: return "direct";
2824	case 2: return "2 way ";
2825	case 3: return "res3 ";
2826	case 4: return "4 way ";
2827	case 5: return "res5 ";
2828	case 6: return "8 way ";
2829	case 7: return "res7 ";
2830	case 8: return "16 way";
2831	case 9: return "res9 ";
2832	case 10: return "res10 ";
2833	case 11: return "res11 ";
2834	case 12: return "res12 ";
2835	case 13: return "res13 ";
2836	case 14: return "res14 ";
2837	case 15: return "fully ";
2838	default: return "????";
2839	}
2840	}
2841
2842
2843	/**
2844	* Display the guest CpuId leaves.
2845	*
2846	* @param pVM VM Handle.
2847	* @param pHlp The info helper functions.
2848	* @param pszArgs "terse", "default" or "verbose".
2849	*/
2850	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2851	{
2852	/*
2853	* Parse the argument.
2854	*/
2855	unsigned iVerbosity = 1;
2856	if (pszArgs)
2857	{
2858	pszArgs = RTStrStripL(pszArgs);
2859	if (!strcmp(pszArgs, "terse"))
2860	iVerbosity--;
2861	else if (!strcmp(pszArgs, "verbose"))
2862	iVerbosity++;
2863	}
2864
2865	/*
2866	* Start cracking.
2867	*/
2868	CPUMCPUID Host;
2869	CPUMCPUID Guest;
2870	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2871
2872	pHlp->pfnPrintf(pHlp,
2873	" RAW Standard CPUIDs\n"
2874	" Function eax ebx ecx edx\n");
2875	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2876	{
2877	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2878	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2879
2880	pHlp->pfnPrintf(pHlp,
2881	"Gst: %08x %08x %08x %08x %08x%s\n"
2882	"Hst: %08x %08x %08x %08x\n",
2883	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2884	i <= cStdMax ? "" : "*",
2885	Host.eax, Host.ebx, Host.ecx, Host.edx);
2886	}
2887
2888	/*
2889	* If verbose, decode it.
2890	*/
2891	if (iVerbosity)
2892	{
2893	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2894	pHlp->pfnPrintf(pHlp,
2895	"Name: %.04s%.04s%.04s\n"
2896	"Supports: 0-%x\n",
2897	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2898	}
2899
2900	/*
2901	* Get Features.
2902	*/
2903	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2904	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2905	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2906	if (cStdMax >= 1 && iVerbosity)
2907	{
2908	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2909
2910	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2911	uint32_t uEAX = Guest.eax;
2912
2913	pHlp->pfnPrintf(pHlp,
2914	"Family: %d \tExtended: %d \tEffective: %d\n"
2915	"Model: %d \tExtended: %d \tEffective: %d\n"
2916	"Stepping: %d\n"
2917	"Type: %d (%s)\n"
2918	"APIC ID: %#04x\n"
2919	"Logical CPUs: %d\n"
2920	"CLFLUSH Size: %d\n"
2921	"Brand ID: %#04x\n",
2922	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2923	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2924	ASMGetCpuStepping(uEAX),
2925	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2926	(Guest.ebx >> 24) & 0xff,
2927	(Guest.ebx >> 16) & 0xff,
2928	(Guest.ebx >> 8) & 0xff,
2929	(Guest.ebx >> 0) & 0xff);
2930	if (iVerbosity == 1)
2931	{
2932	uint32_t uEDX = Guest.edx;
2933	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2934	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2935	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2936	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2937	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2938	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2939	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2940	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2941	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2942	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2943	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2944	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2945	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2946	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2947	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2948	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2949	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2950	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2951	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2952	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2953	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2954	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2955	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2956	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2957	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2958	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2959	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2960	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2961	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2962	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2963	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2964	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2965	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2966	pHlp->pfnPrintf(pHlp, "\n");
2967
2968	uint32_t uECX = Guest.ecx;
2969	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2970	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2971	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2972	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2973	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2974	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2975	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2976	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2977	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2978	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2979	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2980	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2981	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2982	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2983	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2984	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2985	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2986	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2987	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2988	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2989	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2990	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2991	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2992	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2993	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2994	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2995	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2996	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2997	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2998	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2999	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3000	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3001	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3002	pHlp->pfnPrintf(pHlp, "\n");
3003	}
3004	else
3005	{
3006	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3007
3008	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3009	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3010	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3011	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3012
3013	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3014	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3015	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3016	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3017	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3018	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3019	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3020	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3021	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3022	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3023	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3024	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3025	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3026	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3027	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3028	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3029	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3030	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3031	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3032	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3033	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3034	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3035	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3036	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3037	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3038	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3039	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3040	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3041	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3042	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3043	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3044	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3045	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3046
3047	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3048	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3049	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3050	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3051	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3052	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3053	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3054	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3055	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3056	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3057	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3058	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3059	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3060	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3061	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3062	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3063	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3064	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3065	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3066	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3067	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3068	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3069	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3070	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
3071	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3072	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3073	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
3074	}
3075	}
3076	if (cStdMax >= 2 && iVerbosity)
3077	{
3078	/** @todo */
3079	}
3080
3081	/*
3082	* Extended.
3083	* Implemented after AMD specs.
3084	*/
3085	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3086
3087	pHlp->pfnPrintf(pHlp,
3088	"\n"
3089	" RAW Extended CPUIDs\n"
3090	" Function eax ebx ecx edx\n");
3091	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3092	{
3093	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3094	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3095
3096	pHlp->pfnPrintf(pHlp,
3097	"Gst: %08x %08x %08x %08x %08x%s\n"
3098	"Hst: %08x %08x %08x %08x\n",
3099	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3100	i <= cExtMax ? "" : "*",
3101	Host.eax, Host.ebx, Host.ecx, Host.edx);
3102	}
3103
3104	/*
3105	* Understandable output
3106	*/
3107	if (iVerbosity)
3108	{
3109	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3110	pHlp->pfnPrintf(pHlp,
3111	"Ext Name: %.4s%.4s%.4s\n"
3112	"Ext Supports: 0x80000000-%#010x\n",
3113	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3114	}
3115
3116	if (iVerbosity && cExtMax >= 1)
3117	{
3118	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3119	uint32_t uEAX = Guest.eax;
3120	pHlp->pfnPrintf(pHlp,
3121	"Family: %d \tExtended: %d \tEffective: %d\n"
3122	"Model: %d \tExtended: %d \tEffective: %d\n"
3123	"Stepping: %d\n"
3124	"Brand ID: %#05x\n",
3125	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3126	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3127	ASMGetCpuStepping(uEAX),
3128	Guest.ebx & 0xfff);
3129
3130	if (iVerbosity == 1)
3131	{
3132	uint32_t uEDX = Guest.edx;
3133	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3134	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3135	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3136	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3137	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3138	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3139	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3140	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3141	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3142	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3143	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3144	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3145	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3146	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3147	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3148	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3149	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3150	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3151	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3152	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3153	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3154	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3155	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3156	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3157	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3158	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3159	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3160	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3161	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3162	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3163	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3164	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3165	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3166	pHlp->pfnPrintf(pHlp, "\n");
3167
3168	uint32_t uECX = Guest.ecx;
3169	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3170	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3171	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3172	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3173	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3174	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3175	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3176	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3177	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3178	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3179	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3180	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3181	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3182	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3183	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3184	for (unsigned iBit = 5; iBit < 32; iBit++)
3185	if (uECX & RT_BIT(iBit))
3186	pHlp->pfnPrintf(pHlp, " %d", iBit);
3187	pHlp->pfnPrintf(pHlp, "\n");
3188	}
3189	else
3190	{
3191	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3192
3193	uint32_t uEdxGst = Guest.edx;
3194	uint32_t uEdxHst = Host.edx;
3195	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3196	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3197	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3198	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3199	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3200	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3201	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3202	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3203	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3204	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3205	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3206	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3207	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3208	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3209	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3210	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3211	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3212	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3213	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3214	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3215	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3216	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3217	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3218	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3219	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3220	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3221	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3222	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3223	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3224	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3225	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3226	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3227	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3228
3229	uint32_t uEcxGst = Guest.ecx;
3230	uint32_t uEcxHst = Host.ecx;
3231	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3232	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3233	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3234	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3235	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3236	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3237	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3238	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3239	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3240	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3241	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3242	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3243	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3244	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3245	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3246	}
3247	}
3248
3249	if (iVerbosity && cExtMax >= 2)
3250	{
3251	char szString[443+1] = {0};
3252	uint32_t pu32 = (uint32_t )szString;
3253	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3254	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3255	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3256	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3257	if (cExtMax >= 3)
3258	{
3259	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3260	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3261	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3262	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3263	}
3264	if (cExtMax >= 4)
3265	{
3266	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3267	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3268	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3269	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3270	}
3271	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3272	}
3273
3274	if (iVerbosity && cExtMax >= 5)
3275	{
3276	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3277	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3278	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3279	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3280	char sz1[32];
3281	char sz2[32];
3282
3283	pHlp->pfnPrintf(pHlp,
3284	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3285	"TLB 2/4M Data: %s %3d entries\n",
3286	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3287	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3288	pHlp->pfnPrintf(pHlp,
3289	"TLB 4K Instr/Uni: %s %3d entries\n"
3290	"TLB 4K Data: %s %3d entries\n",
3291	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3292	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3293	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3294	"L1 Instr Cache Lines Per Tag: %d\n"
3295	"L1 Instr Cache Associativity: %s\n"
3296	"L1 Instr Cache Size: %d KB\n",
3297	(uEDX >> 0) & 0xff,
3298	(uEDX >> 8) & 0xff,
3299	getCacheAss((uEDX >> 16) & 0xff, sz1),
3300	(uEDX >> 24) & 0xff);
3301	pHlp->pfnPrintf(pHlp,
3302	"L1 Data Cache Line Size: %d bytes\n"
3303	"L1 Data Cache Lines Per Tag: %d\n"
3304	"L1 Data Cache Associativity: %s\n"
3305	"L1 Data Cache Size: %d KB\n",
3306	(uECX >> 0) & 0xff,
3307	(uECX >> 8) & 0xff,
3308	getCacheAss((uECX >> 16) & 0xff, sz1),
3309	(uECX >> 24) & 0xff);
3310	}
3311
3312	if (iVerbosity && cExtMax >= 6)
3313	{
3314	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3315	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3316	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3317
3318	pHlp->pfnPrintf(pHlp,
3319	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3320	"L2 TLB 2/4M Data: %s %4d entries\n",
3321	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3322	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3323	pHlp->pfnPrintf(pHlp,
3324	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3325	"L2 TLB 4K Data: %s %4d entries\n",
3326	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3327	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3328	pHlp->pfnPrintf(pHlp,
3329	"L2 Cache Line Size: %d bytes\n"
3330	"L2 Cache Lines Per Tag: %d\n"
3331	"L2 Cache Associativity: %s\n"
3332	"L2 Cache Size: %d KB\n",
3333	(uEDX >> 0) & 0xff,
3334	(uEDX >> 8) & 0xf,
3335	getL2CacheAss((uEDX >> 12) & 0xf),
3336	(uEDX >> 16) & 0xffff);
3337	}
3338
3339	if (iVerbosity && cExtMax >= 7)
3340	{
3341	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3342
3343	pHlp->pfnPrintf(pHlp, "APM Features: ");
3344	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3345	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3346	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3347	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3348	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3349	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3350	for (unsigned iBit = 6; iBit < 32; iBit++)
3351	if (uEDX & RT_BIT(iBit))
3352	pHlp->pfnPrintf(pHlp, " %d", iBit);
3353	pHlp->pfnPrintf(pHlp, "\n");
3354	}
3355
3356	if (iVerbosity && cExtMax >= 8)
3357	{
3358	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3359	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3360
3361	pHlp->pfnPrintf(pHlp,
3362	"Physical Address Width: %d bits\n"
3363	"Virtual Address Width: %d bits\n"
3364	"Guest Physical Address Width: %d bits\n",
3365	(uEAX >> 0) & 0xff,
3366	(uEAX >> 8) & 0xff,
3367	(uEAX >> 16) & 0xff);
3368	pHlp->pfnPrintf(pHlp,
3369	"Physical Core Count: %d\n",
3370	(uECX >> 0) & 0xff);
3371	}
3372
3373
3374	/*
3375	* Centaur.
3376	*/
3377	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3378
3379	pHlp->pfnPrintf(pHlp,
3380	"\n"
3381	" RAW Centaur CPUIDs\n"
3382	" Function eax ebx ecx edx\n");
3383	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3384	{
3385	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3386	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3387
3388	pHlp->pfnPrintf(pHlp,
3389	"Gst: %08x %08x %08x %08x %08x%s\n"
3390	"Hst: %08x %08x %08x %08x\n",
3391	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3392	i <= cCentaurMax ? "" : "*",
3393	Host.eax, Host.ebx, Host.ecx, Host.edx);
3394	}
3395
3396	/*
3397	* Understandable output
3398	*/
3399	if (iVerbosity)
3400	{
3401	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3402	pHlp->pfnPrintf(pHlp,
3403	"Centaur Supports: 0xc0000000-%#010x\n",
3404	Guest.eax);
3405	}
3406
3407	if (iVerbosity && cCentaurMax >= 1)
3408	{
3409	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3410	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3411	uint32_t uEdxHst = Host.edx;
3412
3413	if (iVerbosity == 1)
3414	{
3415	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3416	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3417	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3418	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3419	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3420	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3421	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3422	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3423	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3424	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3425	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3426	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3427	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3428	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3429	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3430	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3431	for (unsigned iBit = 14; iBit < 32; iBit++)
3432	if (uEdxGst & RT_BIT(iBit))
3433	pHlp->pfnPrintf(pHlp, " %d", iBit);
3434	pHlp->pfnPrintf(pHlp, "\n");
3435	}
3436	else
3437	{
3438	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3439	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3440	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3441	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3442	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3443	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3444	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3445	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3446	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3447	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3448	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3449	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3450	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3451	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3452	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3453	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3454	for (unsigned iBit = 14; iBit < 32; iBit++)
3455	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3456	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3457	pHlp->pfnPrintf(pHlp, "\n");
3458	}
3459	}
3460	}
3461
3462
3463	/**
3464	* Structure used when disassembling and instructions in DBGF.
3465	* This is used so the reader function can get the stuff it needs.
3466	*/
3467	typedef struct CPUMDISASSTATE
3468	{
3469	/** Pointer to the CPU structure. */
3470	PDISCPUSTATE pCpu;
3471	/** The VM handle. */
3472	PVM pVM;
3473	/** The VMCPU handle. */
3474	PVMCPU pVCpu;
3475	/** Pointer to the first byte in the segemnt. */
3476	RTGCUINTPTR GCPtrSegBase;
3477	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3478	RTGCUINTPTR GCPtrSegEnd;
3479	/** The size of the segment minus 1. */
3480	RTGCUINTPTR cbSegLimit;
3481	/** Pointer to the current page - R3 Ptr. */
3482	void const *pvPageR3;
3483	/** Pointer to the current page - GC Ptr. */
3484	RTGCPTR pvPageGC;
3485	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3486	PGMPAGEMAPLOCK PageMapLock;
3487	/** Whether the PageMapLock is valid or not. */
3488	bool fLocked;
3489	/** 64 bits mode or not. */
3490	bool f64Bits;
3491	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3492
3493
3494	/**
3495	* Instruction reader.
3496	*
3497	* @returns VBox status code.
3498	* @param PtrSrc Address to read from.
3499	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3500	* @param pu8Dst Where to store the bytes.
3501	* @param cbRead Number of bytes to read.
3502	* @param uDisCpu Pointer to the disassembler cpu state.
3503	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3504	*/
3505	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3506	{
3507	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3508	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3509	Assert(cbRead > 0);
3510	for (;;)
3511	{
3512	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3513
3514	/* Need to update the page translation? */
3515	if ( !pState->pvPageR3
3516	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3517	{
3518	int rc = VINF_SUCCESS;
3519
3520	/* translate the address */
3521	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3522	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3523	&& !HWACCMIsEnabled(pState->pVM))
3524	{
3525	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3526	if (!pState->pvPageR3)
3527	rc = VERR_INVALID_POINTER;
3528	}
3529	else
3530	{
3531	/* Release mapping lock previously acquired. */
3532	if (pState->fLocked)
3533	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3534	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3535	pState->fLocked = RT_SUCCESS_NP(rc);
3536	}
3537	if (RT_FAILURE(rc))
3538	{
3539	pState->pvPageR3 = NULL;
3540	return rc;
3541	}
3542	}
3543
3544	/* check the segemnt limit */
3545	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3546	return VERR_OUT_OF_SELECTOR_BOUNDS;
3547
3548	/* calc how much we can read */
3549	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3550	if (!pState->f64Bits)
3551	{
3552	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3553	if (cb > cbSeg && cbSeg)
3554	cb = cbSeg;
3555	}
3556	if (cb > cbRead)
3557	cb = cbRead;
3558
3559	/* read and advance */
3560	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3561	cbRead -= cb;
3562	if (!cbRead)
3563	return VINF_SUCCESS;
3564	pu8Dst += cb;
3565	PtrSrc += cb;
3566	}
3567	}
3568
3569
3570	/**
3571	* Disassemble an instruction and return the information in the provided structure.
3572	*
3573	* @returns VBox status code.
3574	* @param pVM VM Handle
3575	* @param pVCpu VMCPU Handle
3576	* @param pCtx CPU context
3577	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3578	* @param pCpu Disassembly state
3579	* @param pszPrefix String prefix for logging (debug only)
3580	*
3581	*/
3582	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3583	{
3584	CPUMDISASSTATE State;
3585	int rc;
3586
3587	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3588	State.pCpu = pCpu;
3589	State.pvPageGC = 0;
3590	State.pvPageR3 = NULL;
3591	State.pVM = pVM;
3592	State.pVCpu = pVCpu;
3593	State.fLocked = false;
3594	State.f64Bits = false;
3595
3596	/*
3597	* Get selector information.
3598	*/
3599	if ( (pCtx->cr0 & X86_CR0_PE)
3600	&& pCtx->eflags.Bits.u1VM == 0)
3601	{
3602	if (CPUMAreHiddenSelRegsValid(pVCpu))
3603	{
3604	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3605	State.GCPtrSegBase = pCtx->csHid.u64Base;
3606	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3607	State.cbSegLimit = pCtx->csHid.u32Limit;
3608	pCpu->mode = (State.f64Bits)
3609	? CPUMODE_64BIT
3610	: pCtx->csHid.Attr.n.u1DefBig
3611	? CPUMODE_32BIT
3612	: CPUMODE_16BIT;
3613	}
3614	else
3615	{
3616	DBGFSELINFO SelInfo;
3617
3618	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3619	if (RT_FAILURE(rc))
3620	{
3621	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3622	return rc;
3623	}
3624
3625	/*
3626	* Validate the selector.
3627	*/
3628	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3629	if (RT_FAILURE(rc))
3630	{
3631	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3632	return rc;
3633	}
3634	State.GCPtrSegBase = SelInfo.GCPtrBase;
3635	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3636	State.cbSegLimit = SelInfo.cbLimit;
3637	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3638	}
3639	}
3640	else
3641	{
3642	/* real or V86 mode */
3643	pCpu->mode = CPUMODE_16BIT;
3644	State.GCPtrSegBase = pCtx->cs * 16;
3645	State.GCPtrSegEnd = 0xFFFFFFFF;
3646	State.cbSegLimit = 0xFFFFFFFF;
3647	}
3648
3649	/*
3650	* Disassemble the instruction.
3651	*/
3652	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3653	pCpu->apvUserData[0] = &State;
3654
3655	uint32_t cbInstr;
3656	#ifndef LOG_ENABLED
3657	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3658	if (RT_SUCCESS(rc))
3659	{
3660	#else
3661	char szOutput[160];
3662	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3663	if (RT_SUCCESS(rc))
3664	{
3665	/* log it */
3666	if (pszPrefix)
3667	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3668	else
3669	Log(("%s", szOutput));
3670	#endif
3671	rc = VINF_SUCCESS;
3672	}
3673	else
3674	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3675
3676	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3677	if (State.fLocked)
3678	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3679
3680	return rc;
3681	}
3682
3683	#ifdef DEBUG
3684
3685	/**
3686	* Disassemble an instruction and dump it to the log
3687	*
3688	* @returns VBox status code.
3689	* @param pVM VM Handle
3690	* @param pVCpu VMCPU Handle
3691	* @param pCtx CPU context
3692	* @param pc GC instruction pointer
3693	* @param pszPrefix String prefix for logging
3694	*
3695	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3696	*/
3697	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3698	{
3699	DISCPUSTATE Cpu;
3700	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3701	}
3702
3703
3704	/**
3705	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3706	*
3707	* @internal
3708	*/
3709	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3710	{
3711	/** @todo SMP support!! */
3712	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3713	}
3714
3715	#endif /* DEBUG */
3716
3717	/**
3718	* API for controlling a few of the CPU features found in CR4.
3719	*
3720	* Currently only X86_CR4_TSD is accepted as input.
3721	*
3722	* @returns VBox status code.
3723	*
3724	* @param pVM The VM handle.
3725	* @param fOr The CR4 OR mask.
3726	* @param fAnd The CR4 AND mask.
3727	*/
3728	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3729	{
3730	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3731	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3732
3733	pVM->cpum.s.CR4.OrMask &= fAnd;
3734	pVM->cpum.s.CR4.OrMask \|= fOr;
3735
3736	return VINF_SUCCESS;
3737	}
3738
3739
3740	/**
3741	* Gets a pointer to the array of standard CPUID leaves.
3742	*
3743	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3744	*
3745	* @returns Pointer to the standard CPUID leaves (read-only).
3746	* @param pVM The VM handle.
3747	* @remark Intended for PATM.
3748	*/
3749	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3750	{
3751	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3752	}
3753
3754
3755	/**
3756	* Gets a pointer to the array of extended CPUID leaves.
3757	*
3758	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3759	*
3760	* @returns Pointer to the extended CPUID leaves (read-only).
3761	* @param pVM The VM handle.
3762	* @remark Intended for PATM.
3763	*/
3764	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3765	{
3766	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3767	}
3768
3769
3770	/**
3771	* Gets a pointer to the array of centaur CPUID leaves.
3772	*
3773	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3774	*
3775	* @returns Pointer to the centaur CPUID leaves (read-only).
3776	* @param pVM The VM handle.
3777	* @remark Intended for PATM.
3778	*/
3779	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3780	{
3781	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3782	}
3783
3784
3785	/**
3786	* Gets a pointer to the default CPUID leaf.
3787	*
3788	* @returns Pointer to the default CPUID leaf (read-only).
3789	* @param pVM The VM handle.
3790	* @remark Intended for PATM.
3791	*/
3792	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3793	{
3794	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3795	}
3796
3797
3798	/**
3799	* Transforms the guest CPU state to raw-ring mode.
3800	*
3801	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3802	*
3803	* @returns VBox status. (recompiler failure)
3804	* @param pVCpu The VMCPU handle.
3805	* @param pCtxCore The context core (for trap usage).
3806	* @see @ref pg_raw
3807	*/
3808	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3809	{
3810	PVM pVM = pVCpu->CTX_SUFF(pVM);
3811
3812	Assert(!pVCpu->cpum.s.fRawEntered);
3813	Assert(!pVCpu->cpum.s.fRemEntered);
3814	if (!pCtxCore)
3815	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3816
3817	/*
3818	* Are we in Ring-0?
3819	*/
3820	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3821	&& !pCtxCore->eflags.Bits.u1VM)
3822	{
3823	/*
3824	* Enter execution mode.
3825	*/
3826	PATMRawEnter(pVM, pCtxCore);
3827
3828	/*
3829	* Set CPL to Ring-1.
3830	*/
3831	pCtxCore->ss \|= 1;
3832	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3833	pCtxCore->cs \|= 1;
3834	}
3835	else
3836	{
3837	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3838	("ring-1 code not supported\n"));
3839	/*
3840	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3841	*/
3842	PATMRawEnter(pVM, pCtxCore);
3843	}
3844
3845	/*
3846	* Invalidate the hidden registers.
3847	*/
3848	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3849
3850	/*
3851	* Assert sanity.
3852	*/
3853	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3854	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3855	\|\| pCtxCore->eflags.Bits.u1VM,
3856	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3857	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3858
3859	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3860
3861	pVCpu->cpum.s.fRawEntered = true;
3862	return VINF_SUCCESS;
3863	}
3864
3865
3866	/**
3867	* Transforms the guest CPU state from raw-ring mode to correct values.
3868	*
3869	* This function will change any selector registers with DPL=1 to DPL=0.
3870	*
3871	* @returns Adjusted rc.
3872	* @param pVCpu The VMCPU handle.
3873	* @param rc Raw mode return code
3874	* @param pCtxCore The context core (for trap usage).
3875	* @see @ref pg_raw
3876	*/
3877	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3878	{
3879	PVM pVM = pVCpu->CTX_SUFF(pVM);
3880
3881	/*
3882	* Don't leave if we've already left (in GC).
3883	*/
3884	Assert(pVCpu->cpum.s.fRawEntered);
3885	Assert(!pVCpu->cpum.s.fRemEntered);
3886	if (!pVCpu->cpum.s.fRawEntered)
3887	return rc;
3888	pVCpu->cpum.s.fRawEntered = false;
3889
3890	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3891	if (!pCtxCore)
3892	pCtxCore = CPUMCTX2CORE(pCtx);
3893	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3894	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3895	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3896
3897	/*
3898	* Are we executing in raw ring-1?
3899	*/
3900	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3901	&& !pCtxCore->eflags.Bits.u1VM)
3902	{
3903	/*
3904	* Leave execution mode.
3905	*/
3906	PATMRawLeave(pVM, pCtxCore, rc);
3907	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3908	/** @todo See what happens if we remove this. */
3909	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3910	pCtxCore->ds &= ~X86_SEL_RPL;
3911	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3912	pCtxCore->es &= ~X86_SEL_RPL;
3913	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3914	pCtxCore->fs &= ~X86_SEL_RPL;
3915	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3916	pCtxCore->gs &= ~X86_SEL_RPL;
3917
3918	/*
3919	* Ring-1 selector => Ring-0.
3920	*/
3921	pCtxCore->ss &= ~X86_SEL_RPL;
3922	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3923	pCtxCore->cs &= ~X86_SEL_RPL;
3924	}
3925	else
3926	{
3927	/*
3928	* PATM is taking care of the IOPL and IF flags for us.
3929	*/
3930	PATMRawLeave(pVM, pCtxCore, rc);
3931	if (!pCtxCore->eflags.Bits.u1VM)
3932	{
3933	/** @todo See what happens if we remove this. */
3934	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3935	pCtxCore->ds &= ~X86_SEL_RPL;
3936	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3937	pCtxCore->es &= ~X86_SEL_RPL;
3938	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3939	pCtxCore->fs &= ~X86_SEL_RPL;
3940	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3941	pCtxCore->gs &= ~X86_SEL_RPL;
3942	}
3943	}
3944
3945	return rc;
3946	}
3947
3948
3949	/**
3950	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3951	*
3952	* Only REM should ever call this function!
3953	*
3954	* @returns The changed flags.
3955	* @param pVCpu The VMCPU handle.
3956	* @param puCpl Where to return the current privilege level (CPL).
3957	*/
3958	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3959	{
3960	Assert(!pVCpu->cpum.s.fRawEntered);
3961	Assert(!pVCpu->cpum.s.fRemEntered);
3962
3963	/*
3964	* Get the CPL first.
3965	*/
3966	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3967
3968	/*
3969	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3970	*/
3971	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3972	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3973
3974	/** @todo change the switcher to use the fChanged flags. */
3975	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3976	{
3977	fFlags \|= CPUM_CHANGED_FPU_REM;
3978	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3979	}
3980
3981	pVCpu->cpum.s.fRemEntered = true;
3982	return fFlags;
3983	}
3984
3985
3986	/**
3987	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3988	*
3989	* @param pVCpu The virtual CPU handle.
3990	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3991	* registers.
3992	*/
3993	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3994	{
3995	Assert(!pVCpu->cpum.s.fRawEntered);
3996	Assert(pVCpu->cpum.s.fRemEntered);
3997
3998	if (fNoOutOfSyncSels)
3999	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4000	else
4001	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4002
4003	pVCpu->cpum.s.fRemEntered = false;
4004	}
4005

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 32963

Download in other formats: