VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 768

Last change on this file since 768 was 768, checked in by vboxsync, 18 years ago

Forgot another X86_CPUID_FEATURE_EDX_SEP flag.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 73.2 KB
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1/* $Id: CPUM.cpp 768 2007-02-08 10:31:13Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46#include "x86context.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 3
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107 /* Hidden selector registers are invalid by default. */
108 pVM->cpum.s.fValidHiddenSelRegs = false;
109
110 /*
111 * Check that the CPU supports the minimum features we require.
112 */
113 /** @todo check the contract! */
114 if (!ASMHasCpuId())
115 {
116 Log(("The CPU doesn't support CPUID!\n"));
117 return VERR_UNSUPPORTED_CPU;
118 }
119 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121 /* Setup the CR4 AND and OR masks used in the switcher */
122 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124 {
125 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126 /* No FXSAVE implies no SSE */
127 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
128 pVM->cpum.s.CR4.OrMask = 0;
129 }
130 else
131 {
132 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
133 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
134 }
135
136#ifdef CPUM_TRAP_RDTSC
137 pVM->cpum.s.CR4.OrMask |= X86_CR4_TSD;
138#endif
139
140 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
141 {
142 Log(("The CPU doesn't support MMX!\n"));
143 return VERR_UNSUPPORTED_CPU;
144 }
145 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
146 {
147 Log(("The CPU doesn't support TSC!\n"));
148 return VERR_UNSUPPORTED_CPU;
149 }
150 /* Bogus on AMD? */
151 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
152 {
153 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
154 }
155
156 /*
157 * Setup hypervisor startup values.
158 */
159
160 /*
161 * Register saved state data item.
162 */
163 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
164 NULL, cpumR3Save, NULL,
165 NULL, cpumR3Load, NULL);
166 if (VBOX_FAILURE(rc))
167 return rc;
168
169 /*
170 * Register info handlers.
171 */
172 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
173 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
174 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
175 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
176 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
177
178 /*
179 * Initialize the Guest CPU state.
180 */
181 rc = cpumR3CpuIdInit(pVM);
182 if (VBOX_FAILURE(rc))
183 return rc;
184 CPUMR3Reset(pVM);
185 return VINF_SUCCESS;
186}
187
188
189/**
190 * Initializes the emulated CPU's cpuid information.
191 *
192 * @returns VBox status code.
193 * @param pVM The VM to operate on.
194 */
195static int cpumR3CpuIdInit(PVM pVM)
196{
197 PCPUM pCPUM = &pVM->cpum.s;
198 uint32_t i;
199
200 /*
201 * Get the host CPUIDs.
202 */
203 for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
204 ASMCpuId(i,
205 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
206 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
207 for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
208 ASMCpuId(0x80000000 + i,
209 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
210 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
211
212 /*
213 * Only report features we can support.
214 */
215 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
216 //| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
217 | X86_CPUID_FEATURE_EDX_DE
218 | X86_CPUID_FEATURE_EDX_PSE
219 | X86_CPUID_FEATURE_EDX_TSC
220 | X86_CPUID_FEATURE_EDX_MSR
221 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
222 | X86_CPUID_FEATURE_EDX_MCE
223 | X86_CPUID_FEATURE_EDX_CX8
224 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
225 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
226 /** @todo this doesn't apply to hwaccm -> we find out much later whether it's enabled or not */
227 //| X86_CPUID_FEATURE_EDX_SEP
228 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
229 | X86_CPUID_FEATURE_EDX_PGE
230 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
231 | X86_CPUID_FEATURE_EDX_CMOV
232 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
233 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
234 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
235 //| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
236 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
237 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
238 | X86_CPUID_FEATURE_EDX_MMX
239 | X86_CPUID_FEATURE_EDX_FXSR
240 | X86_CPUID_FEATURE_EDX_SSE
241 | X86_CPUID_FEATURE_EDX_SSE2
242 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
243 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
244 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
245 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
246 | 0;
247 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
248 | X86_CPUID_FEATURE_ECX_MONITOR
249 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
250 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
251 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
252 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
253 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
254 | 0;
255
256#if 1 /* we didn't used to do this, but I guess we should */
257 /* ASSUMES that this is ALLWAYS the AMD define feature set if present. */
258 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
259 //| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
260 | X86_CPUID_AMD_FEATURE_EDX_DE
261 | X86_CPUID_AMD_FEATURE_EDX_PSE
262 | X86_CPUID_AMD_FEATURE_EDX_TSC
263 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
264 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
265 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
266 | X86_CPUID_AMD_FEATURE_EDX_CX8
267 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
268 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
269 /** @todo this doesn't apply to hwaccm -> we find out much later whether it's enabled or not */
270 //| X86_CPUID_AMD_FEATURE_EDX_SEP
271 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
272 | X86_CPUID_AMD_FEATURE_EDX_PGE
273 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
274 | X86_CPUID_AMD_FEATURE_EDX_CMOV
275 | X86_CPUID_AMD_FEATURE_EDX_PAT
276 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
277 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
278 | X86_CPUID_AMD_FEATURE_EDX_MMX
279 | X86_CPUID_AMD_FEATURE_EDX_FXSR
280 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
281 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
282 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
283 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
284 | 0;
285 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
286 | 0;
287#endif
288
289#if 0 /* this is what we used to do. */
290 /*
291 * Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
292 */
293 pCPUM->aGuestCpuIdStd[1].ebx = 0;
294
295 /*
296 * Set the max standard index to 2.
297 */
298 pCPUM->aGuestCpuIdStd[0].eax = 2;
299 pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
300
301#else /* this is what we probably should do */
302 /*
303 * Hide HTT, multicode, SMP, whatever.
304 * (APIC-ID := 0 and #LogCpus := 0)
305 */
306 pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
307
308 /*
309 * Determin the default value and limit it the number of entries.
310 * Intel returns values of the highest standard function, while AMD returns zeros.
311 */
312 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
313 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
314 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
315
316 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
317 pCPUM->aGuestCpuIdStd[0].eax = 2;
318
319 if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
320 pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
321
322#endif
323
324 /*
325 * Assign defaults to the entries we chopped off.
326 */
327 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
328 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
329 for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
330 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
331
332 /*
333 * Load CPUID overrides from configuration.
334 */
335 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
336 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
337 for (;;)
338 {
339 while (cElements-- < 0)
340 {
341 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
342 if (pNode)
343 {
344 uint32_t u32;
345 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
346 if (VBOX_SUCCESS(rc))
347 pCpuId->eax = u32;
348 else
349 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
350
351 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
352 if (VBOX_SUCCESS(rc))
353 pCpuId->ebx = u32;
354 else
355 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
356
357 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
358 if (VBOX_SUCCESS(rc))
359 pCpuId->ecx = u32;
360 else
361 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
362
363 rc = CFGMR3QueryU32(pNode, "edx", &u32);
364 if (VBOX_SUCCESS(rc))
365 pCpuId->edx = u32;
366 else
367 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
368 }
369 }
370
371 /* next */
372 if (i & 0x80000000)
373 break;
374 pCpuId = &pCPUM->aGuestCpuIdExt[0];
375 cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
376 i = 0x80000000;
377 }
378
379 /*
380 * Log the cpuid and we're good.
381 */
382 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
383 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
384 LogRel(("************************* CPUID dump ************************\n"));
385 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
386 LogRel(("\n"));
387 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
388 LogRel(("******************** End of CPUID dump **********************\n"));
389 return VINF_SUCCESS;
390}
391
392
393
394
395/**
396 * Applies relocations to data and code managed by this
397 * component. This function will be called at init and
398 * whenever the VMM need to relocate it self inside the GC.
399 *
400 * The CPUM will update the addresses used by the switcher.
401 *
402 * @param pVM The VM.
403 */
404CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
405{
406 LogFlow(("CPUMR3Relocate\n"));
407 /*
408 * Switcher pointers.
409 */
410 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
411 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
412}
413
414
415/**
416 * Queries the pointer to the internal CPUMCTX structure
417 *
418 * @returns VBox status code.
419 * @param pVM Handle to the virtual machine.
420 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
421 */
422CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
423{
424 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
425 /*
426 * Store the address. (Later we might check how's calling, thus the RC.)
427 */
428 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
429 return VINF_SUCCESS;
430}
431
432
433/**
434 * Terminates the CPUM.
435 *
436 * Termination means cleaning up and freeing all resources,
437 * the VM it self is at this point powered off or suspended.
438 *
439 * @returns VBox status code.
440 * @param pVM The VM to operate on.
441 */
442CPUMR3DECL(int) CPUMR3Term(PVM pVM)
443{
444 /** @todo */
445 return 0;
446}
447
448
449/**
450 * Resets the CPU.
451 *
452 * @returns VINF_SUCCESS.
453 * @param pVM The VM handle.
454 */
455CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
456{
457 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
458
459 /*
460 * Initialize everything to ZERO first.
461 */
462 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
463 memset(pCtx, 0, sizeof(*pCtx));
464 pVM->cpum.s.fUseFlags = fUseFlags;
465
466 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
467 pCtx->eip = 0x0000fff0;
468 pCtx->edx = 0x00000600; /* P6 processor */
469 pCtx->eflags.Bits.u1Reserved0 = 1;
470
471 pCtx->cs = 0xf000;
472 pCtx->csHid.u32Base = 0xffff0000;
473 pCtx->csHid.u32Limit = 0x0000ffff;
474 pCtx->dsHid.u32Limit = 0x0000ffff;
475 pCtx->esHid.u32Limit = 0x0000ffff;
476 pCtx->fsHid.u32Limit = 0x0000ffff;
477 pCtx->gsHid.u32Limit = 0x0000ffff;
478 pCtx->ssHid.u32Limit = 0x0000ffff;
479 pCtx->idtr.cbIdt = 0xffff;
480 pCtx->gdtr.cbGdt = 0xffff;
481 pCtx->ldtrHid.u32Limit = 0xffff;
482 pCtx->ldtrHid.Attr.u = X86_DESC_P;
483 pCtx->trHid.u32Limit = 0xffff;
484 pCtx->trHid.Attr.u = X86_DESC_P;
485
486 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
487 pCtx->fpu.FCW = 0x37f;
488}
489
490
491
492/**
493 * Execute state save operation.
494 *
495 * @returns VBox status code.
496 * @param pVM VM Handle.
497 * @param pSSM SSM operation handle.
498 */
499static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
500{
501 /*
502 * Save.
503 */
504 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
505 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
506 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
507 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
508
509 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
510 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
511
512 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
513 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
514
515 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
516
517 /* Add the cpuid for checking that the cpu is unchanged. */
518 uint32_t au32CpuId[8] = {0};
519 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
520 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
521 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
522}
523
524
525/**
526 * Execute state load operation.
527 *
528 * @returns VBox status code.
529 * @param pVM VM Handle.
530 * @param pSSM SSM operation handle.
531 * @param u32Version Data layout version.
532 */
533static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
534{
535 /*
536 * Validate version.
537 */
538 if (u32Version != CPUM_SAVED_STATE_VERSION)
539 {
540 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
541 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
542 }
543
544 /*
545 * Restore.
546 */
547 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
548 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
549 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
550 pVM->cpum.s.Hyper.cr3 = uCR3;
551 pVM->cpum.s.Hyper.esp = uESP;
552 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
553 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
554 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
555
556 uint32_t cElements;
557 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
558 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
559 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
560 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
561
562 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
563 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
564 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
565 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
566
567 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
568
569 /*
570 * Check that the basic cpuid id information is unchanged.
571 */
572 uint32_t au32CpuId[8] = {0};
573 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
574 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
575 uint32_t au32CpuIdSaved[8];
576 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
577 if (VBOX_SUCCESS(rc))
578 {
579 /* Ignore APIC ID (AMD specs). */
580 au32CpuId[5] &= ~0xff000000;
581 au32CpuIdSaved[5] &= ~0xff000000;
582 /* Ignore the number of Logical CPUs (AMD specs). */
583 au32CpuId[5] &= ~0x00ff0000;
584 au32CpuIdSaved[5] &= ~0x00ff0000;
585
586 /* do the compare */
587 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
588 {
589 Log(("cpumR3Load: CpuId mismatch!\n"
590 "Saved=%.*Vhxs\n"
591 "Real =%.*Vhxs\n",
592 sizeof(au32CpuIdSaved), au32CpuIdSaved,
593 sizeof(au32CpuId), au32CpuId));
594 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
595 }
596 }
597
598 return rc;
599}
600
601
602/**
603 * Formats the EFLAGS value into mnemonics.
604 *
605 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
606 * @param efl The EFLAGS value.
607 */
608static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
609{
610 /*
611 * Format the flags.
612 */
613 static struct
614 {
615 const char *pszSet; const char *pszClear; uint32_t fFlag;
616 } s_aFlags[] =
617 {
618 { "vip",NULL, X86_EFL_VIP },
619 { "vif",NULL, X86_EFL_VIF },
620 { "ac", NULL, X86_EFL_AC },
621 { "vm", NULL, X86_EFL_VM },
622 { "rf", NULL, X86_EFL_RF },
623 { "nt", NULL, X86_EFL_NT },
624 { "ov", "nv", X86_EFL_OF },
625 { "dn", "up", X86_EFL_DF },
626 { "ei", "di", X86_EFL_IF },
627 { "tf", NULL, X86_EFL_TF },
628 { "nt", "pl", X86_EFL_SF },
629 { "nz", "zr", X86_EFL_ZF },
630 { "ac", "na", X86_EFL_AF },
631 { "po", "pe", X86_EFL_PF },
632 { "cy", "nc", X86_EFL_CF },
633 };
634 char *psz = pszEFlags;
635 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
636 {
637 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
638 if (pszAdd)
639 {
640 strcpy(psz, pszAdd);
641 psz += strlen(pszAdd);
642 *psz++ = ' ';
643 }
644 }
645 psz[-1] = '\0';
646}
647
648
649/**
650 * Formats a full register dump.
651 *
652 * @param pCtx The context to format.
653 * @param pCtxCore The context core to format.
654 * @param pHlp Output functions.
655 * @param enmType The dump type.
656 * @param pszPrefix Register name prefix.
657 */
658static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
659{
660 /*
661 * Format the EFLAGS.
662 */
663 uint32_t efl = pCtxCore->eflags.u32;
664 char szEFlags[80];
665 cpumR3InfoFormatFlags(&szEFlags[0], efl);
666
667 /*
668 * Format the registers.
669 */
670 switch (enmType)
671 {
672 case CPUMDUMPTYPE_TERSE:
673 pHlp->pfnPrintf(pHlp,
674 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
675 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
676 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
677 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
678 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
679 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
680 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
681 break;
682
683 case CPUMDUMPTYPE_DEFAULT:
684 pHlp->pfnPrintf(pHlp,
685 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
686 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
687 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
688 "%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
689 ,
690 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
691 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
692 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
693 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl,
694 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
695 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
696 break;
697
698 case CPUMDUMPTYPE_VERBOSE:
699 pHlp->pfnPrintf(pHlp,
700 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
701 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
702 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
703 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
704 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
705 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
706 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
707 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
708 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
709 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
710 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
711 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
712 "%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
713 ,
714 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
715 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
716 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
717 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
718 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
719 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
720 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
721 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
722 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
723 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
724 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
725 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
726 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
727 break;
728 }
729}
730
731
732/**
733 * Display all cpu states and any other cpum info.
734 *
735 * @param pVM VM Handle.
736 * @param pHlp The info helper functions.
737 * @param pszArgs Arguments, ignored.
738 */
739static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
740{
741 cpumR3InfoGuest(pVM, pHlp, pszArgs);
742 cpumR3InfoHyper(pVM, pHlp, pszArgs);
743 cpumR3InfoHost(pVM, pHlp, pszArgs);
744}
745
746
747/**
748 * Parses the info argument.
749 *
750 * The argument starts with 'verbose', 'terse' or 'default' and then
751 * continues with the comment string.
752 *
753 * @param pszArgs The pointer to the argument string.
754 * @param penmType Where to store the dump type request.
755 * @param ppszComment Where to store the pointer to the comment string.
756 */
757static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
758{
759 if (!pszArgs)
760 {
761 *penmType = CPUMDUMPTYPE_DEFAULT;
762 *ppszComment = "";
763 }
764 else
765 {
766 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
767 {
768 pszArgs += 5;
769 *penmType = CPUMDUMPTYPE_VERBOSE;
770 }
771 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
772 {
773 pszArgs += 5;
774 *penmType = CPUMDUMPTYPE_TERSE;
775 }
776 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
777 {
778 pszArgs += 7;
779 *penmType = CPUMDUMPTYPE_DEFAULT;
780 }
781 else
782 *penmType = CPUMDUMPTYPE_DEFAULT;
783 *ppszComment = RTStrStripL(pszArgs);
784 }
785}
786
787
788/**
789 * Display the guest cpu state.
790 *
791 * @param pVM VM Handle.
792 * @param pHlp The info helper functions.
793 * @param pszArgs Arguments, ignored.
794 */
795static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
796{
797 CPUMDUMPTYPE enmType;
798 const char *pszComment;
799 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
800 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
801 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
802}
803
804
805/**
806 * Display the hypervisor cpu state.
807 *
808 * @param pVM VM Handle.
809 * @param pHlp The info helper functions.
810 * @param pszArgs Arguments, ignored.
811 */
812static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
813{
814 CPUMDUMPTYPE enmType;
815 const char *pszComment;
816 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
817 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
818 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
819}
820
821
822/**
823 * Display the host cpu state.
824 *
825 * @param pVM VM Handle.
826 * @param pHlp The info helper functions.
827 * @param pszArgs Arguments, ignored.
828 */
829static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
830{
831 CPUMDUMPTYPE enmType;
832 const char *pszComment;
833 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
834 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
835
836 /*
837 * Format the EFLAGS.
838 */
839 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
840#if HC_ARCH_BITS == 32
841 uint32_t efl = pCtx->eflags.u32;
842#else
843 uint64_t efl = pCtx->rflags;
844#endif
845 char szEFlags[80];
846 cpumR3InfoFormatFlags(&szEFlags[0], efl);
847
848 /*
849 * Format the registers.
850 */
851#if HC_ARCH_BITS == 32
852 pHlp->pfnPrintf(pHlp,
853 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
854 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
855 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
856 "cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
857 "dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
858 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
859 ,
860 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
861 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
862 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
863 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
864 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
865 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, (RTSEL)pCtx->ldtr,
866 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
867#else /* 64-bit */
868 pHlp->pfnPrintf(pHlp,
869 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
870 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
871 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
872 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
873 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
874 "r14=%016RX64 r15=%016RX64\n"
875 "iopl=%d %31s\n"
876 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
877 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
878 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
879 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
880 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
881 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
882 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
883 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
884 ,
885 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
886 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
887 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
888 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
889 pCtx->r11, pCtx->r12, pCtx->r13,
890 pCtx->r14, pCtx->r15,
891 X86_EFL_GET_IOPL(efl), szEFlags,
892 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
893 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
894 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
895 pCtx->dr0, pCtx->dr1, pCtx->dr2,
896 pCtx->dr3, pCtx->dr6, pCtx->dr7,
897 *(uint64_t *)&pCtx->gdtr[2], *(uint16_t *)&pCtx->gdtr[0], *(uint64_t *)&pCtx->idtr[2], *(uint16_t *)&pCtx->idtr[0],
898 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
899 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
900#endif
901}
902
903/**
904 * Get L1 cache / TLS associativity.
905 */
906static const char *getCacheAss(unsigned u, char *pszBuf)
907{
908 if (u == 0)
909 return "res0 ";
910 if (u == 1)
911 return "direct";
912 if (u >= 256)
913 return "???";
914
915 RTStrPrintf(pszBuf, 16, "%d way", u);
916 return pszBuf;
917}
918
919
920/**
921 * Get L2 cache soociativity.
922 */
923const char *getL2CacheAss(unsigned u)
924{
925 switch (u)
926 {
927 case 0: return "off ";
928 case 1: return "direct";
929 case 2: return "2 way ";
930 case 3: return "res3 ";
931 case 4: return "4 way ";
932 case 5: return "res5 ";
933 case 6: return "8 way ";
934 case 7: return "res7 ";
935 case 8: return "16 way";
936 case 9: return "res9 ";
937 case 10: return "res10 ";
938 case 11: return "res11 ";
939 case 12: return "res12 ";
940 case 13: return "res13 ";
941 case 14: return "res14 ";
942 case 15: return "fully ";
943 default:
944 return "????";
945 }
946}
947
948
949/**
950 * Display the guest CpuId leafs.
951 *
952 * @param pVM VM Handle.
953 * @param pHlp The info helper functions.
954 * @param pszArgs "terse", "default" or "verbose".
955 */
956static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
957{
958 /*
959 * Parse the argument.
960 */
961 unsigned iVerbosity = 1;
962 if (pszArgs)
963 {
964 pszArgs = RTStrStripL(pszArgs);
965 if (!strcmp(pszArgs, "terse"))
966 iVerbosity--;
967 else if (!strcmp(pszArgs, "verbose"))
968 iVerbosity++;
969 }
970
971 /*
972 * Start cracking.
973 */
974 CPUMCPUID Host;
975 CPUMCPUID Guest;
976 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
977
978 pHlp->pfnPrintf(pHlp,
979 " RAW Standard CPUIDs\n"
980 " Function eax ebx ecx edx\n");
981 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
982 {
983 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
984 ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
985
986 pHlp->pfnPrintf(pHlp,
987 "Gst: %08x %08x %08x %08x %08x%s\n"
988 "Hst: %08x %08x %08x %08x\n",
989 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
990 i <= cStdMax ? "" : "*",
991 Host.eax, Host.ebx, Host.ecx, Host.edx);
992 }
993
994 /*
995 * If verbose, decode it.
996 */
997 if (iVerbosity)
998 {
999 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1000 pHlp->pfnPrintf(pHlp,
1001 "Name: %.04s%.04s%.04s\n"
1002 "Supports: 0-%x\n",
1003 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1004 }
1005
1006 /*
1007 * Get Features.
1008 */
1009 if (cStdMax >= 1 && iVerbosity)
1010 {
1011 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1012 uint32_t uEAX = Guest.eax;
1013
1014 pHlp->pfnPrintf(pHlp,
1015 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1016 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1017 "Stepping: %d\n"
1018 "APIC ID: %#04x\n"
1019 "Logical CPUs: %d\n"
1020 "CLFLUSH Size: %d\n"
1021 "Brand ID: %#04x\n",
1022 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1023 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1024 (uEAX >> 0) & 0xf,
1025 (Guest.ebx >> 24) & 0xff,
1026 (Guest.ebx >> 16) & 0xff,
1027 (Guest.ebx >> 8) & 0xff,
1028 (Guest.ebx >> 0) & 0xff);
1029 if (iVerbosity == 1)
1030 {
1031 uint32_t uEDX = Guest.edx;
1032 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1033 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1034 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1035 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1036 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1037 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1038 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1039 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1040 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1041 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1042 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1043 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1044 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1045 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1046 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1047 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1048 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1049 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1050 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1051 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1052 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1053 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1054 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1055 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1056 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1057 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1058 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1059 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1060 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1061 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1062 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1063 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1064 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1065 pHlp->pfnPrintf(pHlp, "\n");
1066
1067 uint32_t uECX = Guest.ecx;
1068 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1069 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1070 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1071 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1072 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1073 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1074 if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1075 if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1076 if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1077 if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1078 if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1079 if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1080 if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1081 if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1082 if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1083 for (unsigned iBit = 14; iBit < 32; iBit++)
1084 if (uECX & BIT(iBit))
1085 pHlp->pfnPrintf(pHlp, " %d", iBit);
1086 pHlp->pfnPrintf(pHlp, "\n");
1087 }
1088 else
1089 {
1090 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1091
1092 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1093 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1094 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1095 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1096
1097 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1098 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1099 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1100 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1101 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1102 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1103 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1104 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1105 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1106 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1107 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1108 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1109 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1110 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1111 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1112 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1113 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1114 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1115 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1116 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1117 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1118 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1119 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1120 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1121 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1122 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1123 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1124 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1125 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1126 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1127 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1128 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1129 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1130
1131 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1132 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1133 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1134 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1135 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1136 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1137 pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1138 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1139 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1140 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1141 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1142 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1143 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1144 }
1145 }
1146 if (cStdMax >= 2 && iVerbosity)
1147 {
1148 /** @todo */
1149 }
1150
1151 /*
1152 * Extended.
1153 * Implemented after AMD specs.
1154 */
1155 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1156
1157 pHlp->pfnPrintf(pHlp,
1158 "\n"
1159 " RAW Extended CPUIDs\n"
1160 " Function eax ebx ecx edx\n");
1161 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1162 {
1163 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1164 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1165
1166 pHlp->pfnPrintf(pHlp,
1167 "Gst: %08x %08x %08x %08x %08x%s\n"
1168 "Hst: %08x %08x %08x %08x\n",
1169 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1170 i <= cExtMax ? "" : "*",
1171 Host.eax, Host.ebx, Host.ecx, Host.edx);
1172 }
1173
1174 /*
1175 * Understandable output
1176 */
1177 if (iVerbosity && cExtMax >= 0)
1178 {
1179 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1180 pHlp->pfnPrintf(pHlp,
1181 "Ext Name: %.4s%.4s%.4s\n"
1182 "Ext Supports: 0x80000000-%#010x\n",
1183 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1184 }
1185
1186 if (iVerbosity && cExtMax >= 1)
1187 {
1188 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1189 uint32_t uEAX = Guest.eax;
1190 pHlp->pfnPrintf(pHlp,
1191 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1192 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1193 "Stepping: %d\n"
1194 "Brand ID: %#05x\n",
1195 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1196 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1197 (uEAX >> 0) & 0xf,
1198 Guest.ebx & 0xfff);
1199
1200 if (iVerbosity == 1)
1201 {
1202 uint32_t uEDX = Guest.edx;
1203 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1204 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1205 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1206 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1207 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1208 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1209 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1210 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1211 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1212 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1213 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1214 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1215 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1216 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1217 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1218 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1219 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1220 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1221 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1222 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1223 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1224 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1225 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1226 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1227 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1228 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1229 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1230 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1231 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1232 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1233 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1234 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1235 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1236 pHlp->pfnPrintf(pHlp, "\n");
1237
1238 uint32_t uECX = Guest.ecx;
1239 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1240 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1241 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1242 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1243 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1244 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1245 for (unsigned iBit = 5; iBit < 32; iBit++)
1246 if (uECX & BIT(iBit))
1247 pHlp->pfnPrintf(pHlp, " %d", iBit);
1248 pHlp->pfnPrintf(pHlp, "\n");
1249 }
1250 else
1251 {
1252 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1253
1254 uint32_t uEdxGst = Guest.edx;
1255 uint32_t uEdxHst = Host.edx;
1256 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1257 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1258 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1259 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1260 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1261 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1262 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1263 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1264 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1265 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1266 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1267 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1268 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1269 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1270 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1271 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1272 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1273 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1274 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1275 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1276 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1277 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1278 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1279 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1280 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1281 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1282 pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1283 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1284 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1285 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1286 pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1287 pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1288 pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1289
1290 uint32_t uEcxGst = Guest.ecx;
1291 uint32_t uEcxHst = Host.ecx;
1292 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1293 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1294 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1295 pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1296 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1297 pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1298 }
1299 }
1300
1301 if (iVerbosity && cExtMax >= 2)
1302 {
1303 char szString[4*4*3+1] = {0};
1304 uint32_t *pu32 = (uint32_t *)szString;
1305 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1306 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1307 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1308 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1309 if (cExtMax >= 3)
1310 {
1311 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1312 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1313 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1314 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1315 }
1316 if (cExtMax >= 4)
1317 {
1318 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1319 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1320 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1321 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1322 }
1323 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1324 }
1325
1326 if (iVerbosity && cExtMax >= 5)
1327 {
1328 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1329 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1330 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1331 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1332 char sz1[32];
1333 char sz2[32];
1334
1335 pHlp->pfnPrintf(pHlp,
1336 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1337 "TLB 2/4M Data: %s %3d entries\n",
1338 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1339 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1340 pHlp->pfnPrintf(pHlp,
1341 "TLB 4K Instr/Uni: %s %3d entries\n"
1342 "TLB 4K Data: %s %3d entries\n",
1343 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1344 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1345 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1346 "L1 Instr Cache Lines Per Tag: %d\n"
1347 "L1 Instr Cache Associativity: %s\n"
1348 "L1 Instr Cache Size: %d KB\n",
1349 (uEDX >> 0) & 0xff,
1350 (uEDX >> 8) & 0xff,
1351 getCacheAss((uEDX >> 16) & 0xff, sz1),
1352 (uEDX >> 24) & 0xff);
1353 pHlp->pfnPrintf(pHlp,
1354 "L1 Data Cache Line Size: %d bytes\n"
1355 "L1 Data Cache Lines Per Tag: %d\n"
1356 "L1 Data Cache Associativity: %s\n"
1357 "L1 Data Cache Size: %d KB\n",
1358 (uECX >> 0) & 0xff,
1359 (uECX >> 8) & 0xff,
1360 getCacheAss((uECX >> 16) & 0xff, sz1),
1361 (uECX >> 24) & 0xff);
1362 }
1363
1364 if (iVerbosity && cExtMax >= 6)
1365 {
1366 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1367 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1368 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1369
1370 pHlp->pfnPrintf(pHlp,
1371 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1372 "L2 TLB 2/4M Data: %s %4d entries\n",
1373 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1374 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1375 pHlp->pfnPrintf(pHlp,
1376 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1377 "L2 TLB 4K Data: %s %4d entries\n",
1378 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1379 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1380 pHlp->pfnPrintf(pHlp,
1381 "L2 Cache Line Size: %d bytes\n"
1382 "L2 Cache Lines Per Tag: %d\n"
1383 "L2 Cache Associativity: %s\n"
1384 "L2 Cache Size: %d KB\n",
1385 (uEDX >> 0) & 0xff,
1386 (uEDX >> 8) & 0xf,
1387 getL2CacheAss((uEDX >> 12) & 0xf),
1388 (uEDX >> 16) & 0xffff);
1389 }
1390
1391 if (iVerbosity && cExtMax >= 7)
1392 {
1393 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1394
1395 pHlp->pfnPrintf(pHlp, "APM Features: ");
1396 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1397 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1398 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1399 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1400 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1401 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1402 for (unsigned iBit = 6; iBit < 32; iBit++)
1403 if (uEDX & BIT(iBit))
1404 pHlp->pfnPrintf(pHlp, " %d", iBit);
1405 pHlp->pfnPrintf(pHlp, "\n");
1406 }
1407
1408 if (iVerbosity && cExtMax >= 8)
1409 {
1410 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1411 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1412
1413 pHlp->pfnPrintf(pHlp,
1414 "Physical Address Width: %d bits\n"
1415 "Virtual Address Width: %d bits\n",
1416 (uEAX >> 0) & 0xff,
1417 (uEAX >> 8) & 0xff);
1418 pHlp->pfnPrintf(pHlp,
1419 "Physical Core Count: %d\n",
1420 (uECX >> 0) & 0xff);
1421 }
1422}
1423
1424
1425/**
1426 * Structure used when disassembling and instructions in DBGF.
1427 * This is used so the reader function can get the stuff it needs.
1428 */
1429typedef struct CPUMDISASSTATE
1430{
1431 /** Pointer to the CPU structure. */
1432 PDISCPUSTATE pCpu;
1433 /** The VM handle. */
1434 PVM pVM;
1435 /** Pointer to the first byte in the segemnt. */
1436 RTGCUINTPTR GCPtrSegBase;
1437 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1438 RTGCUINTPTR GCPtrSegEnd;
1439 /** The size of the segment minus 1. */
1440 RTGCUINTPTR cbSegLimit;
1441 /** Pointer to the current page - HC Ptr. */
1442 void *pvPageHC;
1443 /** Pointer to the current page - GC Ptr. */
1444 RTGCPTR pvPageGC;
1445 /** The rc of the operation.
1446 *
1447 * @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1448 * When we've got time we should adjust the disassembler to use VBox status codes and not
1449 * boolean returns.
1450 */
1451 int rc;
1452} CPUMDISASSTATE, *PCPUMDISASSTATE;
1453
1454
1455/**
1456 * Instruction reader.
1457 *
1458 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1459 * @param PtrSrc Address to read from.
1460 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1461 * @param pu8Dst Where to store the bytes.
1462 * @param cbRead Number of bytes to read.
1463 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1464 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1465 * @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
1466 * declared as what it actually is a PDISCPUSTATE.
1467 */
1468static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1469{
1470 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1471 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1472 Assert(cbRead > 0);
1473 for (;;)
1474 {
1475 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1476
1477 /* Need to update the page translation? */
1478 if ( !pState->pvPageHC
1479 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1480 {
1481 /* translate the address */
1482 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1483 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1484 {
1485 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1486 if (!pState->pvPageHC)
1487 pState->rc = VERR_INVALID_POINTER;
1488 }
1489 else
1490 pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1491 if (VBOX_FAILURE(pState->rc))
1492 {
1493 pState->pvPageHC = NULL;
1494 return pState->rc;
1495 }
1496 }
1497
1498 /* check the segemnt limit */
1499 if (PtrSrc > pState->cbSegLimit)
1500 return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1501
1502 /* calc how much we can read */
1503 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1504 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1505 if (cb > cbSeg && !cbSeg)
1506 cb = cbSeg;
1507 if (cb > cbRead)
1508 cb = cbRead;
1509
1510 /* read and advance */
1511 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1512 cbRead -= cb;
1513 if (!cbRead)
1514 return VINF_SUCCESS;
1515 pu8Dst += cb;
1516 PtrSrc += cb;
1517 }
1518}
1519
1520
1521/**
1522 * Disassemble an instruction and return the information in the provided structure.
1523 *
1524 * @returns VBox status code.
1525 * @param pVM VM Handle
1526 * @param pCtx CPU context
1527 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1528 * @param pCpu Disassembly state
1529 * @param pszPrefix String prefix for logging (debug only)
1530 *
1531 */
1532CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1533{
1534 CPUMDISASSTATE State;
1535 int rc;
1536
1537 State.pCpu = pCpu;
1538 State.pvPageGC = 0;
1539 State.pvPageHC = NULL;
1540 State.rc = VINF_SUCCESS;
1541 State.pVM = pVM;
1542 /*
1543 * Get selector information.
1544 */
1545 if (pCtx->eflags.Bits.u1VM == 0)
1546 {
1547 if (CPUMAreHiddenSelRegsValid(pVM))
1548 {
1549 State.GCPtrSegBase = pCtx->csHid.u32Base;
1550 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1551 State.cbSegLimit = pCtx->csHid.u32Limit;
1552 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1553 }
1554 else
1555 {
1556 SELMSELINFO SelInfo;
1557
1558 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1559 if (!VBOX_SUCCESS(rc))
1560 {
1561 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1562 return rc;
1563 }
1564
1565 /*
1566 * Validate the selector.
1567 */
1568 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1569 if (!VBOX_SUCCESS(rc))
1570 {
1571 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1572 return rc;
1573 }
1574 State.GCPtrSegBase = SelInfo.GCPtrBase;
1575 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1576 State.cbSegLimit = SelInfo.cbLimit;
1577 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1578 }
1579 }
1580 else
1581 {
1582 /* V86 mode */
1583 pCpu->mode = CPUMODE_16BIT; /* @todo */
1584 State.GCPtrSegBase = pCtx->cs * 16;
1585 State.GCPtrSegEnd = 0xFFFFFFFF;
1586 State.cbSegLimit = 0xFFFFFFFF;
1587 }
1588
1589 /*
1590 * Disassemble the instruction.
1591 */
1592 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1593 pCpu->dwUserData[0] = (uintptr_t)&State;
1594
1595 uint32_t cbInstr;
1596#ifdef LOG_ENABLED
1597 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1598 {
1599#else
1600 char szOutput[160];
1601 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1602 {
1603 /* log it */
1604 if (pszPrefix)
1605 Log(("%s: %s", pszPrefix, szOutput));
1606 else
1607 Log(("%s", szOutput));
1608#endif
1609 return VINF_SUCCESS;
1610 }
1611
1612 /* DISInstr failure */
1613 if (VBOX_FAILURE(State.rc))
1614 {
1615 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1616 return State.rc;
1617 }
1618 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1619 rc = VERR_GENERAL_FAILURE;
1620 return rc;
1621}
1622
1623
1624#ifdef DEBUG
1625/**
1626 * Disassemble an instruction and dump it to the log
1627 *
1628 * @returns VBox status code.
1629 * @param pVM VM Handle
1630 * @param pCtx CPU context
1631 * @param pc GC instruction pointer
1632 * @param prefix String prefix for logging
1633 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1634 *
1635 */
1636CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1637{
1638 DISCPUSTATE cpu;
1639
1640 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1641}
1642
1643/**
1644 * Disassemble an instruction and dump it to the log
1645 *
1646 * @returns VBox status code.
1647 * @param pVM VM Handle
1648 * @param pCtx CPU context
1649 * @param pc GC instruction pointer
1650 * @param prefix String prefix for logging
1651 * @param nrInstructions
1652 *
1653 */
1654CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1655{
1656 for(int i=0;i<nrInstructions;i++)
1657 {
1658 DISCPUSTATE cpu;
1659
1660 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1661 pc += cpu.opsize;
1662 }
1663}
1664
1665#endif
1666
1667#ifdef DEBUG
1668/**
1669 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1670 *
1671 * @internal
1672 */
1673CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1674{
1675 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1676}
1677#endif
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