VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 10208

Last change on this file since 10208 was 10208, checked in by vboxsync, 16 years ago

Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers. Safe to pass on to the guest.
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1/* $Id: CPUM.cpp 10208 2008-07-04 09:17:59Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/mm.h>
43#include <VBox/selm.h>
44#include <VBox/dbgf.h>
45#include <VBox/patm.h>
46#include <VBox/ssm.h>
47#include "CPUMInternal.h"
48#include <VBox/vm.h>
49
50#include <VBox/param.h>
51#include <VBox/dis.h>
52#include <VBox/err.h>
53#include <VBox/log.h>
54#include <iprt/assert.h>
55#include <iprt/asm.h>
56#include <iprt/string.h>
57#include <iprt/system.h>
58
59
60/*******************************************************************************
61* Defined Constants And Macros *
62*******************************************************************************/
63/** The saved state version. */
64#define CPUM_SAVED_STATE_VERSION 8
65
66
67/*******************************************************************************
68* Structures and Typedefs *
69*******************************************************************************/
70
71/**
72 * What kind of cpu info dump to perform.
73 */
74typedef enum CPUMDUMPTYPE
75{
76 CPUMDUMPTYPE_TERSE,
77 CPUMDUMPTYPE_DEFAULT,
78 CPUMDUMPTYPE_VERBOSE
79
80} CPUMDUMPTYPE;
81/** Pointer to a cpu info dump type. */
82typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
83
84
85/*******************************************************************************
86* Internal Functions *
87*******************************************************************************/
88static int cpumR3CpuIdInit(PVM pVM);
89static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
91static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
92static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97
98
99/**
100 * Initializes the CPUM.
101 *
102 * @returns VBox status code.
103 * @param pVM The VM to operate on.
104 */
105CPUMR3DECL(int) CPUMR3Init(PVM pVM)
106{
107 LogFlow(("CPUMR3Init\n"));
108
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
113 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
114
115 /*
116 * Setup any fixed pointers and offsets.
117 */
118 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
119 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
120 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
121 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
122
123 /* Hidden selector registers are invalid by default. */
124 pVM->cpum.s.fValidHiddenSelRegs = false;
125
126 /*
127 * Check that the CPU supports the minimum features we require.
128 */
129 /** @todo check the contract! */
130 if (!ASMHasCpuId())
131 {
132 Log(("The CPU doesn't support CPUID!\n"));
133 return VERR_UNSUPPORTED_CPU;
134 }
135 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
136
137 /* Setup the CR4 AND and OR masks used in the switcher */
138 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
139 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
140 {
141 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
142 /* No FXSAVE implies no SSE */
143 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
144 pVM->cpum.s.CR4.OrMask = 0;
145 }
146 else
147 {
148 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
149 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
150 }
151
152 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
153 {
154 Log(("The CPU doesn't support MMX!\n"));
155 return VERR_UNSUPPORTED_CPU;
156 }
157 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
158 {
159 Log(("The CPU doesn't support TSC!\n"));
160 return VERR_UNSUPPORTED_CPU;
161 }
162 /* Bogus on AMD? */
163 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
164 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
165
166 /*
167 * Setup hypervisor startup values.
168 */
169
170 /*
171 * Register saved state data item.
172 */
173 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
174 NULL, cpumR3Save, NULL,
175 NULL, cpumR3Load, NULL);
176 if (VBOX_FAILURE(rc))
177 return rc;
178
179 /* Query the CPU manufacturer. */
180 uint32_t uEAX, uEBX, uECX, uEDX;
181 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
182 if ( uEAX >= 1
183 && uEBX == X86_CPUID_VENDOR_AMD_EBX
184 && uECX == X86_CPUID_VENDOR_AMD_ECX
185 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
186 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
187 else if ( uEAX >= 1
188 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
189 && uECX == X86_CPUID_VENDOR_INTEL_ECX
190 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
191 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
192 else /** @todo Via */
193 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
194
195 /*
196 * Register info handlers.
197 */
198 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
199 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
200 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
201 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
202 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
203 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
204
205 /*
206 * Initialize the Guest CPU state.
207 */
208 rc = cpumR3CpuIdInit(pVM);
209 if (VBOX_FAILURE(rc))
210 return rc;
211 CPUMR3Reset(pVM);
212 return VINF_SUCCESS;
213}
214
215
216/**
217 * Initializes the emulated CPU's cpuid information.
218 *
219 * @returns VBox status code.
220 * @param pVM The VM to operate on.
221 */
222static int cpumR3CpuIdInit(PVM pVM)
223{
224 PCPUM pCPUM = &pVM->cpum.s;
225 uint32_t i;
226
227 /*
228 * Get the host CPUIDs.
229 */
230 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
231 ASMCpuId_Idx_ECX(i, 0,
232 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
233 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
234 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
235 ASMCpuId(0x80000000 + i,
236 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
237 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
238 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
239 ASMCpuId(0xc0000000 + i,
240 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
241 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
242
243
244 /*
245 * Only report features we can support.
246 */
247 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
248 | X86_CPUID_FEATURE_EDX_VME
249 | X86_CPUID_FEATURE_EDX_DE
250 | X86_CPUID_FEATURE_EDX_PSE
251 | X86_CPUID_FEATURE_EDX_TSC
252 | X86_CPUID_FEATURE_EDX_MSR
253 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
254 | X86_CPUID_FEATURE_EDX_MCE
255 | X86_CPUID_FEATURE_EDX_CX8
256 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
257 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
258 //| X86_CPUID_FEATURE_EDX_SEP
259 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
260 | X86_CPUID_FEATURE_EDX_PGE
261 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
262 | X86_CPUID_FEATURE_EDX_CMOV
263 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
264 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
265 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
266 | X86_CPUID_FEATURE_EDX_CLFSH
267 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
268 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
269 | X86_CPUID_FEATURE_EDX_MMX
270 | X86_CPUID_FEATURE_EDX_FXSR
271 | X86_CPUID_FEATURE_EDX_SSE
272 | X86_CPUID_FEATURE_EDX_SSE2
273 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
274 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
275 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
276 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
277 | 0;
278 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
279 | X86_CPUID_FEATURE_ECX_MONITOR
280 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
281 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
282 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
283 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
284 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
285 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
286 //| X86_CPUID_FEATURE_ECX_CX16
287 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
288 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
289 /* ECX Bit 23 - POPCOUNT instruction. */
290 //| X86_CPUID_FEATURE_ECX_POPCOUNT
291 | 0;
292
293 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
294 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
295 | X86_CPUID_AMD_FEATURE_EDX_VME
296 | X86_CPUID_AMD_FEATURE_EDX_DE
297 | X86_CPUID_AMD_FEATURE_EDX_PSE
298 | X86_CPUID_AMD_FEATURE_EDX_TSC
299 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
300 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
301 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
302 | X86_CPUID_AMD_FEATURE_EDX_CX8
303 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
304 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
305 //| X86_CPUID_AMD_FEATURE_EDX_SEP
306 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
307 | X86_CPUID_AMD_FEATURE_EDX_PGE
308 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
309 | X86_CPUID_AMD_FEATURE_EDX_CMOV
310 | X86_CPUID_AMD_FEATURE_EDX_PAT
311 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
312 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
313 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
314 | X86_CPUID_AMD_FEATURE_EDX_MMX
315 | X86_CPUID_AMD_FEATURE_EDX_FXSR
316 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
317 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
318 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
319 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
320 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
321 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
322 | 0;
323 pCPUM->aGuestCpuIdExt[1].ecx &= 0
324 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
325 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
326 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
327 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
328 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
329 //| X86_CPUID_AMD_FEATURE_ECX_ABM
330 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
331 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
332 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
333 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
334 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
335 //| X86_CPUID_AMD_FEATURE_ECX_WDT
336 | 0;
337
338 /*
339 * Hide HTT, multicode, SMP, whatever.
340 * (APIC-ID := 0 and #LogCpus := 0)
341 */
342 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
343
344 /*
345 * Determine the default.
346 *
347 * Intel returns values of the highest standard function, while AMD
348 * returns zeros. VIA on the other hand seems to returning nothing or
349 * perhaps some random garbage, we don't try duplicate this behavior.
350 */
351 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
352 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
353 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
354
355 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
356 * Safe to pass on to the guest.
357 *
358 * Intel: 0x800000005 reserved
359 * 0x800000006 L2 cache information
360 * AMD: 0x800000005 L1 cache information
361 * 0x800000006 L2/L3 cache information
362 */
363
364 /*
365 * Limit it the number of entries and fill the remaining with the defaults.
366 *
367 * The limits are masking off stuff about power saving and similar, this
368 * is perhaps a bit crudely done as there is probably some relatively harmless
369 * info too in these leaves (like words about having a constant TSC).
370 */
371 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
372 pCPUM->aGuestCpuIdStd[0].eax = 2;
373 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
374 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
375
376 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000006))
377 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000006);
378 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
379 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
380 : 0;
381 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
382 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
383
384 /*
385 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
386 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
387 * We currently don't support more than 1 processor.
388 */
389 pCPUM->aGuestCpuIdStd[4].eax = 0;
390
391 /*
392 * Centaur stuff (VIA).
393 *
394 * The important part here (we think) is to make sure the 0xc0000000
395 * function returns 0xc0000001. As for the features, we don't currently
396 * let on about any of those... 0xc0000002 seems to be some
397 * temperature/hz/++ stuff, include it as well (static).
398 */
399 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
400 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
401 {
402 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
403 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
404 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
405 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
406 i++)
407 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
408 }
409 else
410 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
411 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
412
413
414 /*
415 * Load CPUID overrides from configuration.
416 */
417 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
418 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
419 for (i=0;; )
420 {
421 while (cElements-- > 0)
422 {
423 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
424 if (pNode)
425 {
426 uint32_t u32;
427 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
428 if (VBOX_SUCCESS(rc))
429 pCpuId->eax = u32;
430 else
431 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
432
433 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
434 if (VBOX_SUCCESS(rc))
435 pCpuId->ebx = u32;
436 else
437 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
438
439 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
440 if (VBOX_SUCCESS(rc))
441 pCpuId->ecx = u32;
442 else
443 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
444
445 rc = CFGMR3QueryU32(pNode, "edx", &u32);
446 if (VBOX_SUCCESS(rc))
447 pCpuId->edx = u32;
448 else
449 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
450 }
451 pCpuId++;
452 i++;
453 }
454
455 /* next */
456 if ((i & UINT32_C(0xc0000000)) == 0)
457 {
458 pCpuId = &pCPUM->aGuestCpuIdExt[0];
459 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
460 i = UINT32_C(0x80000000);
461 }
462 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
463 {
464 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
465 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
466 i = UINT32_C(0xc0000000);
467 }
468 else
469 break;
470 }
471
472 /* Check if PAE was explicitely enabled by the user. */
473 bool fEnable = false;
474 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
475 if (VBOX_SUCCESS(rc) && fEnable)
476 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
477
478 /*
479 * Log the cpuid and we're good.
480 */
481 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
482 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
483 LogRel(("************************* CPUID dump ************************\n"));
484 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
485 LogRel(("\n"));
486 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
487 LogRel(("******************** End of CPUID dump **********************\n"));
488 return VINF_SUCCESS;
489}
490
491
492
493
494/**
495 * Applies relocations to data and code managed by this
496 * component. This function will be called at init and
497 * whenever the VMM need to relocate it self inside the GC.
498 *
499 * The CPUM will update the addresses used by the switcher.
500 *
501 * @param pVM The VM.
502 */
503CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
504{
505 LogFlow(("CPUMR3Relocate\n"));
506 /*
507 * Switcher pointers.
508 */
509 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
510 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
511 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
512}
513
514
515/**
516 * Queries the pointer to the internal CPUMCTX structure
517 *
518 * @returns VBox status code.
519 * @param pVM Handle to the virtual machine.
520 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
521 */
522CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
523{
524 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
525 /*
526 * Store the address. (Later we might check how's calling, thus the RC.)
527 */
528 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
529 return VINF_SUCCESS;
530}
531
532
533/**
534 * Terminates the CPUM.
535 *
536 * Termination means cleaning up and freeing all resources,
537 * the VM it self is at this point powered off or suspended.
538 *
539 * @returns VBox status code.
540 * @param pVM The VM to operate on.
541 */
542CPUMR3DECL(int) CPUMR3Term(PVM pVM)
543{
544 /** @todo ? */
545 return 0;
546}
547
548
549/**
550 * Resets the CPU.
551 *
552 * @returns VINF_SUCCESS.
553 * @param pVM The VM handle.
554 */
555CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
556{
557 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
558
559 /*
560 * Initialize everything to ZERO first.
561 */
562 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
563 memset(pCtx, 0, sizeof(*pCtx));
564 pVM->cpum.s.fUseFlags = fUseFlags;
565
566 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
567 pCtx->eip = 0x0000fff0;
568 pCtx->edx = 0x00000600; /* P6 processor */
569 pCtx->eflags.Bits.u1Reserved0 = 1;
570
571 pCtx->cs = 0xf000;
572 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
573 pCtx->csHid.u32Limit = 0x0000ffff;
574 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
575 pCtx->csHid.Attr.n.u1Present = 1;
576 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
577
578 pCtx->dsHid.u32Limit = 0x0000ffff;
579 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
580 pCtx->dsHid.Attr.n.u1Present = 1;
581 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
582
583 pCtx->esHid.u32Limit = 0x0000ffff;
584 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
585 pCtx->esHid.Attr.n.u1Present = 1;
586 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
587
588 pCtx->fsHid.u32Limit = 0x0000ffff;
589 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
590 pCtx->fsHid.Attr.n.u1Present = 1;
591 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
592
593 pCtx->gsHid.u32Limit = 0x0000ffff;
594 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
595 pCtx->gsHid.Attr.n.u1Present = 1;
596 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
597
598 pCtx->ssHid.u32Limit = 0x0000ffff;
599 pCtx->ssHid.Attr.n.u1Present = 1;
600 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
601 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
602
603 pCtx->idtr.cbIdt = 0xffff;
604 pCtx->gdtr.cbGdt = 0xffff;
605
606 pCtx->ldtrHid.u32Limit = 0xffff;
607 pCtx->ldtrHid.Attr.n.u1Present = 1;
608 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
609
610 pCtx->trHid.u32Limit = 0xffff;
611 pCtx->trHid.Attr.n.u1Present = 1;
612 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
613
614 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
615 pCtx->dr7 = 0x400;
616
617 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
618 pCtx->fpu.FCW = 0x37f;
619
620 /* Init PAT MSR */
621 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
622}
623
624
625/**
626 * Execute state save operation.
627 *
628 * @returns VBox status code.
629 * @param pVM VM Handle.
630 * @param pSSM SSM operation handle.
631 */
632static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
633{
634 /*
635 * Save.
636 */
637 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
638 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
639 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
640 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
641
642 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
643 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
644
645 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
646 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
647
648 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
649 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
650
651 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
652
653 /* Add the cpuid for checking that the cpu is unchanged. */
654 uint32_t au32CpuId[8] = {0};
655 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
656 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
657 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
658}
659
660
661/**
662 * Execute state load operation.
663 *
664 * @returns VBox status code.
665 * @param pVM VM Handle.
666 * @param pSSM SSM operation handle.
667 * @param u32Version Data layout version.
668 */
669static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
670{
671 /*
672 * Validate version.
673 */
674 if (u32Version != CPUM_SAVED_STATE_VERSION)
675 {
676 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
677 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
678 }
679
680 /*
681 * Restore.
682 */
683 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
684 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
685 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
686 pVM->cpum.s.Hyper.cr3 = uCR3;
687 pVM->cpum.s.Hyper.esp = uESP;
688 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
689 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
690 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
691
692 uint32_t cElements;
693 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
694 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
695 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
696 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
697
698 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
699 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
700 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
701 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
702
703 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
704 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
705 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
706 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
707
708 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
709
710 /*
711 * Check that the basic cpuid id information is unchanged.
712 */
713 uint32_t au32CpuId[8] = {0};
714 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
715 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
716 uint32_t au32CpuIdSaved[8];
717 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
718 if (VBOX_SUCCESS(rc))
719 {
720 /* Ignore APIC ID (AMD specs). */
721 au32CpuId[5] &= ~0xff000000;
722 au32CpuIdSaved[5] &= ~0xff000000;
723 /* Ignore the number of Logical CPUs (AMD specs). */
724 au32CpuId[5] &= ~0x00ff0000;
725 au32CpuIdSaved[5] &= ~0x00ff0000;
726
727 /* do the compare */
728 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
729 {
730 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
731 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
732 "Saved=%.*Vhxs\n"
733 "Real =%.*Vhxs\n",
734 sizeof(au32CpuIdSaved), au32CpuIdSaved,
735 sizeof(au32CpuId), au32CpuId));
736 else
737 {
738 LogRel(("cpumR3Load: CpuId mismatch!\n"
739 "Saved=%.*Vhxs\n"
740 "Real =%.*Vhxs\n",
741 sizeof(au32CpuIdSaved), au32CpuIdSaved,
742 sizeof(au32CpuId), au32CpuId));
743 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
744 }
745 }
746 }
747
748 return rc;
749}
750
751
752/**
753 * Formats the EFLAGS value into mnemonics.
754 *
755 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
756 * @param efl The EFLAGS value.
757 */
758static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
759{
760 /*
761 * Format the flags.
762 */
763 static struct
764 {
765 const char *pszSet; const char *pszClear; uint32_t fFlag;
766 } s_aFlags[] =
767 {
768 { "vip",NULL, X86_EFL_VIP },
769 { "vif",NULL, X86_EFL_VIF },
770 { "ac", NULL, X86_EFL_AC },
771 { "vm", NULL, X86_EFL_VM },
772 { "rf", NULL, X86_EFL_RF },
773 { "nt", NULL, X86_EFL_NT },
774 { "ov", "nv", X86_EFL_OF },
775 { "dn", "up", X86_EFL_DF },
776 { "ei", "di", X86_EFL_IF },
777 { "tf", NULL, X86_EFL_TF },
778 { "nt", "pl", X86_EFL_SF },
779 { "nz", "zr", X86_EFL_ZF },
780 { "ac", "na", X86_EFL_AF },
781 { "po", "pe", X86_EFL_PF },
782 { "cy", "nc", X86_EFL_CF },
783 };
784 char *psz = pszEFlags;
785 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
786 {
787 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
788 if (pszAdd)
789 {
790 strcpy(psz, pszAdd);
791 psz += strlen(pszAdd);
792 *psz++ = ' ';
793 }
794 }
795 psz[-1] = '\0';
796}
797
798
799/**
800 * Formats a full register dump.
801 *
802 * @param pVM VM Handle.
803 * @param pCtx The context to format.
804 * @param pCtxCore The context core to format.
805 * @param pHlp Output functions.
806 * @param enmType The dump type.
807 * @param pszPrefix Register name prefix.
808 */
809static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
810{
811 /*
812 * Format the EFLAGS.
813 */
814 uint32_t efl = pCtxCore->eflags.u32;
815 char szEFlags[80];
816 cpumR3InfoFormatFlags(&szEFlags[0], efl);
817
818 /*
819 * Format the registers.
820 */
821 switch (enmType)
822 {
823 case CPUMDUMPTYPE_TERSE:
824 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
825 {
826 pHlp->pfnPrintf(pHlp,
827 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
828 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
829 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
830 "%sr14=%016RX64 %sr15=%016RX64\n"
831 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
832 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
833 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
834 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
835 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
836 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
837 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
838 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
839 }
840 else
841 pHlp->pfnPrintf(pHlp,
842 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
843 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
844 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
845 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
846 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
847 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
848 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
849 break;
850
851 case CPUMDUMPTYPE_DEFAULT:
852 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
853 {
854 pHlp->pfnPrintf(pHlp,
855 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
856 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
857 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
858 "%sr14=%016RX64 %sr15=%016RX64\n"
859 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
860 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
861 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
862 ,
863 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
864 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
865 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
866 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
867 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
868 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
869 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
870 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
871 }
872 else
873 pHlp->pfnPrintf(pHlp,
874 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
875 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
876 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
877 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
878 ,
879 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
880 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
881 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
882 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
883 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
884 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
885 break;
886
887 case CPUMDUMPTYPE_VERBOSE:
888 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
889 {
890 pHlp->pfnPrintf(pHlp,
891 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
892 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
893 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
894 "%sr14=%016RX64 %sr15=%016RX64\n"
895 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
896 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
897 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
898 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
899 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
900 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
901 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
902 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
903 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
904 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
905 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
906 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
907 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
908 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
909 ,
910 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
911 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
912 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
913 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
914 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
915 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
916 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
917 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
918 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
919 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
920 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
921 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
922 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
923 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
924 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
925 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
926 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
927 }
928 else
929 pHlp->pfnPrintf(pHlp,
930 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
931 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
932 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
933 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
934 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
935 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
936 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
937 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
938 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
939 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
940 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
941 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
942 ,
943 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
944 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
945 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
946 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
947 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
948 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
949 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
950 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
951 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
952 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
953 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
954 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
955
956 pHlp->pfnPrintf(pHlp,
957 "FPU:\n"
958 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
959 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
960 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
961 ,
962 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
963 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
964 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
965 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
966
967
968 pHlp->pfnPrintf(pHlp,
969 "MSR:\n"
970 "%sEFER =%016RX64\n"
971 "%sPAT =%016RX64\n"
972 "%sSTAR =%016RX64\n"
973 "%sCSTAR =%016RX64\n"
974 "%sLSTAR =%016RX64\n"
975 "%sSFMASK =%016RX64\n"
976 "%sKERNELGSBASE =%016RX64\n",
977 pszPrefix, pCtx->msrEFER,
978 pszPrefix, pCtx->msrPAT,
979 pszPrefix, pCtx->msrSTAR,
980 pszPrefix, pCtx->msrCSTAR,
981 pszPrefix, pCtx->msrLSTAR,
982 pszPrefix, pCtx->msrSFMASK,
983 pszPrefix, pCtx->msrKERNELGSBASE);
984
985 break;
986 }
987}
988
989
990/**
991 * Display all cpu states and any other cpum info.
992 *
993 * @param pVM VM Handle.
994 * @param pHlp The info helper functions.
995 * @param pszArgs Arguments, ignored.
996 */
997static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
998{
999 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1000 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1001 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1002 cpumR3InfoHost(pVM, pHlp, pszArgs);
1003}
1004
1005
1006/**
1007 * Parses the info argument.
1008 *
1009 * The argument starts with 'verbose', 'terse' or 'default' and then
1010 * continues with the comment string.
1011 *
1012 * @param pszArgs The pointer to the argument string.
1013 * @param penmType Where to store the dump type request.
1014 * @param ppszComment Where to store the pointer to the comment string.
1015 */
1016static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1017{
1018 if (!pszArgs)
1019 {
1020 *penmType = CPUMDUMPTYPE_DEFAULT;
1021 *ppszComment = "";
1022 }
1023 else
1024 {
1025 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1026 {
1027 pszArgs += 5;
1028 *penmType = CPUMDUMPTYPE_VERBOSE;
1029 }
1030 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1031 {
1032 pszArgs += 5;
1033 *penmType = CPUMDUMPTYPE_TERSE;
1034 }
1035 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1036 {
1037 pszArgs += 7;
1038 *penmType = CPUMDUMPTYPE_DEFAULT;
1039 }
1040 else
1041 *penmType = CPUMDUMPTYPE_DEFAULT;
1042 *ppszComment = RTStrStripL(pszArgs);
1043 }
1044}
1045
1046
1047/**
1048 * Display the guest cpu state.
1049 *
1050 * @param pVM VM Handle.
1051 * @param pHlp The info helper functions.
1052 * @param pszArgs Arguments, ignored.
1053 */
1054static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1055{
1056 CPUMDUMPTYPE enmType;
1057 const char *pszComment;
1058 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1059 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1060 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1061}
1062
1063/**
1064 * Display the current guest instruction
1065 *
1066 * @param pVM VM Handle.
1067 * @param pHlp The info helper functions.
1068 * @param pszArgs Arguments, ignored.
1069 */
1070static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1071{
1072 char szInstruction[256];
1073 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1074 if (VBOX_SUCCESS(rc))
1075 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1076}
1077
1078
1079/**
1080 * Display the hypervisor cpu state.
1081 *
1082 * @param pVM VM Handle.
1083 * @param pHlp The info helper functions.
1084 * @param pszArgs Arguments, ignored.
1085 */
1086static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1087{
1088 CPUMDUMPTYPE enmType;
1089 const char *pszComment;
1090 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1091 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1092 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1093 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1094}
1095
1096
1097/**
1098 * Display the host cpu state.
1099 *
1100 * @param pVM VM Handle.
1101 * @param pHlp The info helper functions.
1102 * @param pszArgs Arguments, ignored.
1103 */
1104static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1105{
1106 CPUMDUMPTYPE enmType;
1107 const char *pszComment;
1108 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1109 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1110
1111 /*
1112 * Format the EFLAGS.
1113 */
1114 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1115#if HC_ARCH_BITS == 32
1116 uint32_t efl = pCtx->eflags.u32;
1117#else
1118 uint64_t efl = pCtx->rflags;
1119#endif
1120 char szEFlags[80];
1121 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1122
1123 /*
1124 * Format the registers.
1125 */
1126#if HC_ARCH_BITS == 32
1127# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1128 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1129# endif
1130 {
1131 pHlp->pfnPrintf(pHlp,
1132 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1133 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1134 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1135 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1136 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1137 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1138 ,
1139 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1140 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1141 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1142 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1143 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1144 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1145 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1146 }
1147# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1148 else
1149# endif
1150#endif
1151#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1152 {
1153 pHlp->pfnPrintf(pHlp,
1154 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1155 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1156 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1157 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1158 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1159 "r14=%016RX64 r15=%016RX64\n"
1160 "iopl=%d %31s\n"
1161 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1162 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1163 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
1164 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1165 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1166 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1167 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1168 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1169 ,
1170 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1171 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1172 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1173 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1174 pCtx->r11, pCtx->r12, pCtx->r13,
1175 pCtx->r14, pCtx->r15,
1176 X86_EFL_GET_IOPL(efl), szEFlags,
1177 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1178 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1179 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1180 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1181 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1182 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1183 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1184 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1185 }
1186#endif
1187}
1188
1189
1190/**
1191 * Get L1 cache / TLS associativity.
1192 */
1193static const char *getCacheAss(unsigned u, char *pszBuf)
1194{
1195 if (u == 0)
1196 return "res0 ";
1197 if (u == 1)
1198 return "direct";
1199 if (u >= 256)
1200 return "???";
1201
1202 RTStrPrintf(pszBuf, 16, "%d way", u);
1203 return pszBuf;
1204}
1205
1206
1207/**
1208 * Get L2 cache soociativity.
1209 */
1210const char *getL2CacheAss(unsigned u)
1211{
1212 switch (u)
1213 {
1214 case 0: return "off ";
1215 case 1: return "direct";
1216 case 2: return "2 way ";
1217 case 3: return "res3 ";
1218 case 4: return "4 way ";
1219 case 5: return "res5 ";
1220 case 6: return "8 way "; case 7: return "res7 ";
1221 case 8: return "16 way";
1222 case 9: return "res9 ";
1223 case 10: return "res10 ";
1224 case 11: return "res11 ";
1225 case 12: return "res12 ";
1226 case 13: return "res13 ";
1227 case 14: return "res14 ";
1228 case 15: return "fully ";
1229 default:
1230 return "????";
1231 }
1232}
1233
1234
1235/**
1236 * Display the guest CpuId leaves.
1237 *
1238 * @param pVM VM Handle.
1239 * @param pHlp The info helper functions.
1240 * @param pszArgs "terse", "default" or "verbose".
1241 */
1242static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1243{
1244 /*
1245 * Parse the argument.
1246 */
1247 unsigned iVerbosity = 1;
1248 if (pszArgs)
1249 {
1250 pszArgs = RTStrStripL(pszArgs);
1251 if (!strcmp(pszArgs, "terse"))
1252 iVerbosity--;
1253 else if (!strcmp(pszArgs, "verbose"))
1254 iVerbosity++;
1255 }
1256
1257 /*
1258 * Start cracking.
1259 */
1260 CPUMCPUID Host;
1261 CPUMCPUID Guest;
1262 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1263
1264 pHlp->pfnPrintf(pHlp,
1265 " RAW Standard CPUIDs\n"
1266 " Function eax ebx ecx edx\n");
1267 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1268 {
1269 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1270 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1271
1272 pHlp->pfnPrintf(pHlp,
1273 "Gst: %08x %08x %08x %08x %08x%s\n"
1274 "Hst: %08x %08x %08x %08x\n",
1275 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1276 i <= cStdMax ? "" : "*",
1277 Host.eax, Host.ebx, Host.ecx, Host.edx);
1278 }
1279
1280 /*
1281 * If verbose, decode it.
1282 */
1283 if (iVerbosity)
1284 {
1285 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1286 pHlp->pfnPrintf(pHlp,
1287 "Name: %.04s%.04s%.04s\n"
1288 "Supports: 0-%x\n",
1289 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1290 }
1291
1292 /*
1293 * Get Features.
1294 */
1295 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1296 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1297 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1298 if (cStdMax >= 1 && iVerbosity)
1299 {
1300 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1301 uint32_t uEAX = Guest.eax;
1302
1303 pHlp->pfnPrintf(pHlp,
1304 "Family: %d \tExtended: %d \tEffective: %d\n"
1305 "Model: %d \tExtended: %d \tEffective: %d\n"
1306 "Stepping: %d\n"
1307 "APIC ID: %#04x\n"
1308 "Logical CPUs: %d\n"
1309 "CLFLUSH Size: %d\n"
1310 "Brand ID: %#04x\n",
1311 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1312 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1313 ASMGetCpuStepping(uEAX),
1314 (Guest.ebx >> 24) & 0xff,
1315 (Guest.ebx >> 16) & 0xff,
1316 (Guest.ebx >> 8) & 0xff,
1317 (Guest.ebx >> 0) & 0xff);
1318 if (iVerbosity == 1)
1319 {
1320 uint32_t uEDX = Guest.edx;
1321 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1322 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1323 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1324 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1325 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1326 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1327 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1328 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1329 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1330 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1331 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1332 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1333 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1334 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1335 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1336 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1337 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1338 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1339 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1340 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1341 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1342 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1343 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1344 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1345 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1346 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1347 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1348 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1349 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1350 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1351 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1352 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1353 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1354 pHlp->pfnPrintf(pHlp, "\n");
1355
1356 uint32_t uECX = Guest.ecx;
1357 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1358 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1359 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1360 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1361 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1362 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1363 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1364 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1365 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1366 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1367 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1368 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1369 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1370 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1371 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1372 for (unsigned iBit = 14; iBit < 32; iBit++)
1373 if (uECX & RT_BIT(iBit))
1374 pHlp->pfnPrintf(pHlp, " %d", iBit);
1375 pHlp->pfnPrintf(pHlp, "\n");
1376 }
1377 else
1378 {
1379 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1380
1381 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1382 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1383 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1384 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1385
1386 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1387 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1388 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1389 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1390 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1391 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1392 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1393 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1394 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1395 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1396 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1397 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1398 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1399 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1400 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1401 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1402 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1403 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1404 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1405 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1406 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1407 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1408 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1409 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1410 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1411 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1412 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1413 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1414 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1415 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1416 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1417 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1418 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1419
1420 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1421 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1422 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1423 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1424 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1425 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1426 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1427 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1428 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1429 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1430 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1431 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1432 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1433 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1434 }
1435 }
1436 if (cStdMax >= 2 && iVerbosity)
1437 {
1438 /** @todo */
1439 }
1440
1441 /*
1442 * Extended.
1443 * Implemented after AMD specs.
1444 */
1445 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1446
1447 pHlp->pfnPrintf(pHlp,
1448 "\n"
1449 " RAW Extended CPUIDs\n"
1450 " Function eax ebx ecx edx\n");
1451 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1452 {
1453 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1454 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1455
1456 pHlp->pfnPrintf(pHlp,
1457 "Gst: %08x %08x %08x %08x %08x%s\n"
1458 "Hst: %08x %08x %08x %08x\n",
1459 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1460 i <= cExtMax ? "" : "*",
1461 Host.eax, Host.ebx, Host.ecx, Host.edx);
1462 }
1463
1464 /*
1465 * Understandable output
1466 */
1467 if (iVerbosity && cExtMax >= 0)
1468 {
1469 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1470 pHlp->pfnPrintf(pHlp,
1471 "Ext Name: %.4s%.4s%.4s\n"
1472 "Ext Supports: 0x80000000-%#010x\n",
1473 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1474 }
1475
1476 if (iVerbosity && cExtMax >= 1)
1477 {
1478 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1479 uint32_t uEAX = Guest.eax;
1480 pHlp->pfnPrintf(pHlp,
1481 "Family: %d \tExtended: %d \tEffective: %d\n"
1482 "Model: %d \tExtended: %d \tEffective: %d\n"
1483 "Stepping: %d\n"
1484 "Brand ID: %#05x\n",
1485 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1486 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1487 ASMGetCpuStepping(uEAX),
1488 Guest.ebx & 0xfff);
1489
1490 if (iVerbosity == 1)
1491 {
1492 uint32_t uEDX = Guest.edx;
1493 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1494 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1495 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1496 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1497 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1498 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1499 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1500 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1501 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1502 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1503 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1504 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1505 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1506 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1507 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1508 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1509 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1510 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1511 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1512 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1513 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1514 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1515 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1516 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1517 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1518 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1519 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1520 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1521 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1522 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1523 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1524 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1525 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1526 pHlp->pfnPrintf(pHlp, "\n");
1527
1528 uint32_t uECX = Guest.ecx;
1529 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1530 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1531 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1532 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1533 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1534 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1535 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1536 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1537 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1538 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1539 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1540 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1541 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1542 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1543 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1544 for (unsigned iBit = 5; iBit < 32; iBit++)
1545 if (uECX & RT_BIT(iBit))
1546 pHlp->pfnPrintf(pHlp, " %d", iBit);
1547 pHlp->pfnPrintf(pHlp, "\n");
1548 }
1549 else
1550 {
1551 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1552
1553 uint32_t uEdxGst = Guest.edx;
1554 uint32_t uEdxHst = Host.edx;
1555 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1556 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1557 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1558 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1559 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1560 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1561 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1562 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1563 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1564 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1565 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1566 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1567 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1568 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1569 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1570 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1571 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1572 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1573 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1574 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1575 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1576 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1577 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1578 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1579 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1580 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1581 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1582 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1583 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1584 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1585 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1586 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1587 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1588
1589 uint32_t uEcxGst = Guest.ecx;
1590 uint32_t uEcxHst = Host.ecx;
1591 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1592 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1593 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1594 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1595 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1596 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1597 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1598 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1599 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1600 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1601 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1602 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1603 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1604 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1605 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1606 }
1607 }
1608
1609 if (iVerbosity && cExtMax >= 2)
1610 {
1611 char szString[4*4*3+1] = {0};
1612 uint32_t *pu32 = (uint32_t *)szString;
1613 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1614 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1615 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1616 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1617 if (cExtMax >= 3)
1618 {
1619 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1620 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1621 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1622 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1623 }
1624 if (cExtMax >= 4)
1625 {
1626 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1627 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1628 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1629 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1630 }
1631 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1632 }
1633
1634 if (iVerbosity && cExtMax >= 5)
1635 {
1636 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1637 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1638 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1639 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1640 char sz1[32];
1641 char sz2[32];
1642
1643 pHlp->pfnPrintf(pHlp,
1644 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1645 "TLB 2/4M Data: %s %3d entries\n",
1646 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1647 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1648 pHlp->pfnPrintf(pHlp,
1649 "TLB 4K Instr/Uni: %s %3d entries\n"
1650 "TLB 4K Data: %s %3d entries\n",
1651 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1652 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1653 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1654 "L1 Instr Cache Lines Per Tag: %d\n"
1655 "L1 Instr Cache Associativity: %s\n"
1656 "L1 Instr Cache Size: %d KB\n",
1657 (uEDX >> 0) & 0xff,
1658 (uEDX >> 8) & 0xff,
1659 getCacheAss((uEDX >> 16) & 0xff, sz1),
1660 (uEDX >> 24) & 0xff);
1661 pHlp->pfnPrintf(pHlp,
1662 "L1 Data Cache Line Size: %d bytes\n"
1663 "L1 Data Cache Lines Per Tag: %d\n"
1664 "L1 Data Cache Associativity: %s\n"
1665 "L1 Data Cache Size: %d KB\n",
1666 (uECX >> 0) & 0xff,
1667 (uECX >> 8) & 0xff,
1668 getCacheAss((uECX >> 16) & 0xff, sz1),
1669 (uECX >> 24) & 0xff);
1670 }
1671
1672 if (iVerbosity && cExtMax >= 6)
1673 {
1674 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1675 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1676 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1677
1678 pHlp->pfnPrintf(pHlp,
1679 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1680 "L2 TLB 2/4M Data: %s %4d entries\n",
1681 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1682 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1683 pHlp->pfnPrintf(pHlp,
1684 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1685 "L2 TLB 4K Data: %s %4d entries\n",
1686 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1687 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1688 pHlp->pfnPrintf(pHlp,
1689 "L2 Cache Line Size: %d bytes\n"
1690 "L2 Cache Lines Per Tag: %d\n"
1691 "L2 Cache Associativity: %s\n"
1692 "L2 Cache Size: %d KB\n",
1693 (uEDX >> 0) & 0xff,
1694 (uEDX >> 8) & 0xf,
1695 getL2CacheAss((uEDX >> 12) & 0xf),
1696 (uEDX >> 16) & 0xffff);
1697 }
1698
1699 if (iVerbosity && cExtMax >= 7)
1700 {
1701 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1702
1703 pHlp->pfnPrintf(pHlp, "APM Features: ");
1704 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1705 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1706 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1707 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1708 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1709 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1710 for (unsigned iBit = 6; iBit < 32; iBit++)
1711 if (uEDX & RT_BIT(iBit))
1712 pHlp->pfnPrintf(pHlp, " %d", iBit);
1713 pHlp->pfnPrintf(pHlp, "\n");
1714 }
1715
1716 if (iVerbosity && cExtMax >= 8)
1717 {
1718 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1719 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1720
1721 pHlp->pfnPrintf(pHlp,
1722 "Physical Address Width: %d bits\n"
1723 "Virtual Address Width: %d bits\n",
1724 (uEAX >> 0) & 0xff,
1725 (uEAX >> 8) & 0xff);
1726 pHlp->pfnPrintf(pHlp,
1727 "Physical Core Count: %d\n",
1728 (uECX >> 0) & 0xff);
1729 }
1730
1731
1732 /*
1733 * Centaur.
1734 */
1735 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1736
1737 pHlp->pfnPrintf(pHlp,
1738 "\n"
1739 " RAW Centaur CPUIDs\n"
1740 " Function eax ebx ecx edx\n");
1741 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1742 {
1743 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1744 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1745
1746 pHlp->pfnPrintf(pHlp,
1747 "Gst: %08x %08x %08x %08x %08x%s\n"
1748 "Hst: %08x %08x %08x %08x\n",
1749 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1750 i <= cCentaurMax ? "" : "*",
1751 Host.eax, Host.ebx, Host.ecx, Host.edx);
1752 }
1753
1754 /*
1755 * Understandable output
1756 */
1757 if (iVerbosity && cCentaurMax >= 0)
1758 {
1759 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1760 pHlp->pfnPrintf(pHlp,
1761 "Centaur Supports: 0xc0000000-%#010x\n",
1762 Guest.eax);
1763 }
1764
1765 if (iVerbosity && cCentaurMax >= 1)
1766 {
1767 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1768 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1769 uint32_t uEdxHst = Host.edx;
1770
1771 if (iVerbosity == 1)
1772 {
1773 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1774 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1775 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1776 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1777 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1778 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1779 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1780 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1781 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1782 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1783 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1784 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1785 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1786 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1787 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1788 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1789 for (unsigned iBit = 14; iBit < 32; iBit++)
1790 if (uEdxGst & RT_BIT(iBit))
1791 pHlp->pfnPrintf(pHlp, " %d", iBit);
1792 pHlp->pfnPrintf(pHlp, "\n");
1793 }
1794 else
1795 {
1796 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1797 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1798 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1799 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1800 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1801 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1802 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1803 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1804 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1805 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1806 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1807 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1808 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1809 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1810 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1811 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1812 for (unsigned iBit = 14; iBit < 32; iBit++)
1813 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1814 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1815 pHlp->pfnPrintf(pHlp, "\n");
1816 }
1817 }
1818}
1819
1820
1821/**
1822 * Structure used when disassembling and instructions in DBGF.
1823 * This is used so the reader function can get the stuff it needs.
1824 */
1825typedef struct CPUMDISASSTATE
1826{
1827 /** Pointer to the CPU structure. */
1828 PDISCPUSTATE pCpu;
1829 /** The VM handle. */
1830 PVM pVM;
1831 /** Pointer to the first byte in the segemnt. */
1832 RTGCUINTPTR GCPtrSegBase;
1833 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1834 RTGCUINTPTR GCPtrSegEnd;
1835 /** The size of the segment minus 1. */
1836 RTGCUINTPTR cbSegLimit;
1837 /** Pointer to the current page - HC Ptr. */
1838 void const *pvPageHC;
1839 /** Pointer to the current page - GC Ptr. */
1840 RTGCPTR pvPageGC;
1841 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1842 PGMPAGEMAPLOCK PageMapLock;
1843 /** Whether the PageMapLock is valid or not. */
1844 bool fLocked;
1845 /** 64 bits mode or not. */
1846 bool f64Bits;
1847} CPUMDISASSTATE, *PCPUMDISASSTATE;
1848
1849
1850/**
1851 * Instruction reader.
1852 *
1853 * @returns VBox status code.
1854 * @param PtrSrc Address to read from.
1855 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1856 * @param pu8Dst Where to store the bytes.
1857 * @param cbRead Number of bytes to read.
1858 * @param uDisCpu Pointer to the disassembler cpu state.
1859 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1860 */
1861static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1862{
1863 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1864 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1865 Assert(cbRead > 0);
1866 for (;;)
1867 {
1868 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1869
1870 /* Need to update the page translation? */
1871 if ( !pState->pvPageHC
1872 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1873 {
1874 int rc = VINF_SUCCESS;
1875
1876 /* translate the address */
1877 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1878 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1879 {
1880 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1881 if (!pState->pvPageHC)
1882 rc = VERR_INVALID_POINTER;
1883 }
1884 else
1885 {
1886 /* Release mapping lock previously acquired. */
1887 if (pState->fLocked)
1888 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1889 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1890 pState->fLocked = RT_SUCCESS_NP(rc);
1891 }
1892 if (VBOX_FAILURE(rc))
1893 {
1894 pState->pvPageHC = NULL;
1895 return rc;
1896 }
1897 }
1898
1899 /* check the segemnt limit */
1900 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
1901 return VERR_OUT_OF_SELECTOR_BOUNDS;
1902
1903 /* calc how much we can read */
1904 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1905 if (!pState->f64Bits)
1906 {
1907 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1908 if (cb > cbSeg && cbSeg)
1909 cb = cbSeg;
1910 }
1911 if (cb > cbRead)
1912 cb = cbRead;
1913
1914 /* read and advance */
1915 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1916 cbRead -= cb;
1917 if (!cbRead)
1918 return VINF_SUCCESS;
1919 pu8Dst += cb;
1920 PtrSrc += cb;
1921 }
1922}
1923
1924
1925/**
1926 * Disassemble an instruction and return the information in the provided structure.
1927 *
1928 * @returns VBox status code.
1929 * @param pVM VM Handle
1930 * @param pCtx CPU context
1931 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1932 * @param pCpu Disassembly state
1933 * @param pszPrefix String prefix for logging (debug only)
1934 *
1935 */
1936CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1937{
1938 CPUMDISASSTATE State;
1939 int rc;
1940
1941 const PGMMODE enmMode = PGMGetGuestMode(pVM);
1942 State.pCpu = pCpu;
1943 State.pvPageGC = 0;
1944 State.pvPageHC = NULL;
1945 State.pVM = pVM;
1946 State.fLocked = false;
1947 State.f64Bits = false;
1948
1949 /*
1950 * Get selector information.
1951 */
1952 if ( (pCtx->cr0 & X86_CR0_PE)
1953 && pCtx->eflags.Bits.u1VM == 0)
1954 {
1955 if (CPUMAreHiddenSelRegsValid(pVM))
1956 {
1957 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
1958 State.GCPtrSegBase = pCtx->csHid.u64Base;
1959 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
1960 State.cbSegLimit = pCtx->csHid.u32Limit;
1961 pCpu->mode = (State.f64Bits)
1962 ? CPUMODE_64BIT
1963 : pCtx->csHid.Attr.n.u1DefBig
1964 ? CPUMODE_32BIT
1965 : CPUMODE_16BIT;
1966 }
1967 else
1968 {
1969 SELMSELINFO SelInfo;
1970
1971 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1972 if (!VBOX_SUCCESS(rc))
1973 {
1974 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1975 return rc;
1976 }
1977
1978 /*
1979 * Validate the selector.
1980 */
1981 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1982 if (!VBOX_SUCCESS(rc))
1983 {
1984 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1985 return rc;
1986 }
1987 State.GCPtrSegBase = SelInfo.GCPtrBase;
1988 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1989 State.cbSegLimit = SelInfo.cbLimit;
1990 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1991 }
1992 }
1993 else
1994 {
1995 /* real or V86 mode */
1996 pCpu->mode = CPUMODE_16BIT;
1997 State.GCPtrSegBase = pCtx->cs * 16;
1998 State.GCPtrSegEnd = 0xFFFFFFFF;
1999 State.cbSegLimit = 0xFFFFFFFF;
2000 }
2001
2002 /*
2003 * Disassemble the instruction.
2004 */
2005 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2006 pCpu->apvUserData[0] = &State;
2007
2008 uint32_t cbInstr;
2009#ifndef LOG_ENABLED
2010 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2011 if (VBOX_SUCCESS(rc))
2012 {
2013#else
2014 char szOutput[160];
2015 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2016 if (VBOX_SUCCESS(rc))
2017 {
2018 /* log it */
2019 if (pszPrefix)
2020 Log(("%s: %s", pszPrefix, szOutput));
2021 else
2022 Log(("%s", szOutput));
2023#endif
2024 rc = VINF_SUCCESS;
2025 }
2026 else
2027 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2028
2029 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2030 if (State.fLocked)
2031 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2032
2033 return rc;
2034}
2035
2036#ifdef DEBUG
2037
2038/**
2039 * Disassemble an instruction and dump it to the log
2040 *
2041 * @returns VBox status code.
2042 * @param pVM VM Handle
2043 * @param pCtx CPU context
2044 * @param pc GC instruction pointer
2045 * @param prefix String prefix for logging
2046 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2047 *
2048 */
2049CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2050{
2051 DISCPUSTATE cpu;
2052
2053 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2054}
2055
2056/**
2057 * Disassemble an instruction and dump it to the log
2058 *
2059 * @returns VBox status code.
2060 * @param pVM VM Handle
2061 * @param pCtx CPU context
2062 * @param pc GC instruction pointer
2063 * @param prefix String prefix for logging
2064 * @param nrInstructions
2065 *
2066 */
2067CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2068{
2069 for(int i=0;i<nrInstructions;i++)
2070 {
2071 DISCPUSTATE cpu;
2072
2073 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2074 pc += cpu.opsize;
2075 }
2076}
2077
2078#endif /* DEBUG */
2079
2080#ifdef DEBUG
2081/**
2082 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2083 *
2084 * @internal
2085 */
2086CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2087{
2088 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2089}
2090#endif /* DEBUG */
2091
2092
2093/**
2094 * API for controlling a few of the CPU features found in CR4.
2095 *
2096 * Currently only X86_CR4_TSD is accepted as input.
2097 *
2098 * @returns VBox status code.
2099 *
2100 * @param pVM The VM handle.
2101 * @param fOr The CR4 OR mask.
2102 * @param fAnd The CR4 AND mask.
2103 */
2104CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2105{
2106 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2107 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2108
2109 pVM->cpum.s.CR4.OrMask &= fAnd;
2110 pVM->cpum.s.CR4.OrMask |= fOr;
2111
2112 return VINF_SUCCESS;
2113}
2114
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