VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 10569

Last change on this file since 10569 was 10569, checked in by vboxsync, 16 years ago

Expose cpuid 2-5 minus dangerous bits.
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File size: 102.2 KB
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1/* $Id: CPUM.cpp 10569 2008-07-12 15:59:27Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/pdm.h>
43#include <VBox/mm.h>
44#include <VBox/selm.h>
45#include <VBox/dbgf.h>
46#include <VBox/patm.h>
47#include <VBox/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm.h>
57#include <iprt/string.h>
58#include <iprt/system.h>
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** The saved state version. */
65#define CPUM_SAVED_STATE_VERSION 8
66
67
68/*******************************************************************************
69* Structures and Typedefs *
70*******************************************************************************/
71
72/**
73 * What kind of cpu info dump to perform.
74 */
75typedef enum CPUMDUMPTYPE
76{
77 CPUMDUMPTYPE_TERSE,
78 CPUMDUMPTYPE_DEFAULT,
79 CPUMDUMPTYPE_VERBOSE
80
81} CPUMDUMPTYPE;
82/** Pointer to a cpu info dump type. */
83typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static int cpumR3CpuIdInit(PVM pVM);
90static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
91static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
92static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98
99
100/**
101 * Initializes the CPUM.
102 *
103 * @returns VBox status code.
104 * @param pVM The VM to operate on.
105 */
106CPUMR3DECL(int) CPUMR3Init(PVM pVM)
107{
108 LogFlow(("CPUMR3Init\n"));
109
110 /*
111 * Assert alignment and sizes.
112 */
113 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
114 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
115
116 /*
117 * Setup any fixed pointers and offsets.
118 */
119 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
120 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
121 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
122 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
123
124 /* Hidden selector registers are invalid by default. */
125 pVM->cpum.s.fValidHiddenSelRegs = false;
126
127 /*
128 * Check that the CPU supports the minimum features we require.
129 */
130 /** @todo check the contract! */
131 if (!ASMHasCpuId())
132 {
133 Log(("The CPU doesn't support CPUID!\n"));
134 return VERR_UNSUPPORTED_CPU;
135 }
136 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
137
138 /* Setup the CR4 AND and OR masks used in the switcher */
139 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
140 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
141 {
142 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
143 /* No FXSAVE implies no SSE */
144 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
145 pVM->cpum.s.CR4.OrMask = 0;
146 }
147 else
148 {
149 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
150 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
151 }
152
153 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
154 {
155 Log(("The CPU doesn't support MMX!\n"));
156 return VERR_UNSUPPORTED_CPU;
157 }
158 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
159 {
160 Log(("The CPU doesn't support TSC!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 /* Bogus on AMD? */
164 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
165 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
166
167 /*
168 * Setup hypervisor startup values.
169 */
170
171 /*
172 * Register saved state data item.
173 */
174 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
175 NULL, cpumR3Save, NULL,
176 NULL, cpumR3Load, NULL);
177 if (VBOX_FAILURE(rc))
178 return rc;
179
180 /* Query the CPU manufacturer. */
181 uint32_t uEAX, uEBX, uECX, uEDX;
182 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
183 if ( uEAX >= 1
184 && uEBX == X86_CPUID_VENDOR_AMD_EBX
185 && uECX == X86_CPUID_VENDOR_AMD_ECX
186 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
187 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
188 else if ( uEAX >= 1
189 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
190 && uECX == X86_CPUID_VENDOR_INTEL_ECX
191 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
193 else /** @todo Via */
194 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
195
196 /*
197 * Register info handlers.
198 */
199 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
200 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
201 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
202 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
203 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
204 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
205
206 /*
207 * Initialize the Guest CPU state.
208 */
209 rc = cpumR3CpuIdInit(pVM);
210 if (VBOX_FAILURE(rc))
211 return rc;
212 CPUMR3Reset(pVM);
213 return VINF_SUCCESS;
214}
215
216
217/**
218 * Initializes the emulated CPU's cpuid information.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223static int cpumR3CpuIdInit(PVM pVM)
224{
225 PCPUM pCPUM = &pVM->cpum.s;
226 uint32_t i;
227
228 /*
229 * Get the host CPUIDs.
230 */
231 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
232 ASMCpuId_Idx_ECX(i, 0,
233 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
234 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
235 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
236 ASMCpuId(0x80000000 + i,
237 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
238 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
239 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
240 ASMCpuId(0xc0000000 + i,
241 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
242 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
243
244
245 /*
246 * Only report features we can support.
247 */
248 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
249 | X86_CPUID_FEATURE_EDX_VME
250 | X86_CPUID_FEATURE_EDX_DE
251 | X86_CPUID_FEATURE_EDX_PSE
252 | X86_CPUID_FEATURE_EDX_TSC
253 | X86_CPUID_FEATURE_EDX_MSR
254 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
255 | X86_CPUID_FEATURE_EDX_MCE
256 | X86_CPUID_FEATURE_EDX_CX8
257 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
258 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
259 //| X86_CPUID_FEATURE_EDX_SEP
260 | X86_CPUID_FEATURE_EDX_MTRR
261 | X86_CPUID_FEATURE_EDX_PGE
262 | X86_CPUID_FEATURE_EDX_MCA
263 | X86_CPUID_FEATURE_EDX_CMOV
264 | X86_CPUID_FEATURE_EDX_PAT
265 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
266 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
267 | X86_CPUID_FEATURE_EDX_CLFSH
268 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
269 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
270 | X86_CPUID_FEATURE_EDX_MMX
271 | X86_CPUID_FEATURE_EDX_FXSR
272 | X86_CPUID_FEATURE_EDX_SSE
273 | X86_CPUID_FEATURE_EDX_SSE2
274 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
275 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
276 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
277 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
278 | 0;
279 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
280 | X86_CPUID_FEATURE_ECX_MONITOR
281 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
282 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
283 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
284 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
285 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
286 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
287 //| X86_CPUID_FEATURE_ECX_CX16
288 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
289 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
290 /* ECX Bit 23 - POPCOUNT instruction. */
291 //| X86_CPUID_FEATURE_ECX_POPCOUNT
292 | 0;
293
294 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
295 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
296 | X86_CPUID_AMD_FEATURE_EDX_VME
297 | X86_CPUID_AMD_FEATURE_EDX_DE
298 | X86_CPUID_AMD_FEATURE_EDX_PSE
299 | X86_CPUID_AMD_FEATURE_EDX_TSC
300 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
301 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
302 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
303 | X86_CPUID_AMD_FEATURE_EDX_CX8
304 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
305 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
306 //| X86_CPUID_AMD_FEATURE_EDX_SEP
307 | X86_CPUID_AMD_FEATURE_EDX_MTRR
308 | X86_CPUID_AMD_FEATURE_EDX_PGE
309 | X86_CPUID_AMD_FEATURE_EDX_MCA
310 | X86_CPUID_AMD_FEATURE_EDX_CMOV
311 | X86_CPUID_AMD_FEATURE_EDX_PAT
312 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
313 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
314 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
315 | X86_CPUID_AMD_FEATURE_EDX_MMX
316 | X86_CPUID_AMD_FEATURE_EDX_FXSR
317 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
318 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
319 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
320 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
321 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
322 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
323 | 0;
324 pCPUM->aGuestCpuIdExt[1].ecx &= 0
325 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
326 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
327 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
328 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
329 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
330 //| X86_CPUID_AMD_FEATURE_ECX_ABM
331 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
332 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
333 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
334 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
335 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
336 //| X86_CPUID_AMD_FEATURE_ECX_WDT
337 | 0;
338
339 /*
340 * Hide HTT, multicode, SMP, whatever.
341 * (APIC-ID := 0 and #LogCpus := 0)
342 */
343 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
344
345 /* Cpuid 2:
346 * Intel: Cache and TLB information
347 * AMD: Reserved
348 * Safe to expose
349 */
350
351 /* Cpuid 3:
352 * Intel: EAX, EBX - reserved
353 * ECX, EDX - Processor Serial Number if available, otherwise reserved
354 * AMD: Reserved
355 * Safe to expose
356 */
357 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
358 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
359
360 /* Cpuid 4:
361 * Intel: Deterministic Cache Parameters Leaf
362 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
363 * AMD: Reserved
364 * Safe to expose, except for EAX:
365 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
366 * Bits 31-26: Maximum number of processor cores in this physical package**
367 */
368 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
369 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
370
371 /* Cpuid 5: Monitor/mwait Leaf
372 * Intel: ECX, EDX - reserved
373 * EAX, EBX - Smallest and largest monitor line size
374 * AMD: EDX - reserved
375 * EAX, EBX - Smallest and largest monitor line size
376 * ECX - extensions (ignored for now)
377 * Safe to expose
378 */
379 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
380
381 /*
382 * Determine the default.
383 *
384 * Intel returns values of the highest standard function, while AMD
385 * returns zeros. VIA on the other hand seems to returning nothing or
386 * perhaps some random garbage, we don't try to duplicate this behavior.
387 */
388 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
389 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
390 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
391
392 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
393 * Safe to pass on to the guest.
394 *
395 * Intel: 0x800000005 reserved
396 * 0x800000006 L2 cache information
397 * AMD: 0x800000005 L1 cache information
398 * 0x800000006 L2/L3 cache information
399 */
400
401 /* Cpuid 0x800000007:
402 * AMD: EAX, EBX, ECX - reserved
403 * EDX: Advanced Power Management Information
404 * Intel: Reserved
405 */
406 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
407 {
408 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
409
410 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
411
412 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
413 {
414 /* Only expose the TSC invariant capability bit to the guest. */
415 pCPUM->aGuestCpuIdExt[7].edx &= 0
416 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
417 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
418 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
419 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
420 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
421 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
422 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
423 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
424 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
425 | 0;
426 }
427 else
428 pCPUM->aGuestCpuIdExt[7].edx = 0;
429 }
430
431 /* Cpuid 0x800000008:
432 * AMD: EBX, EDX - reserved
433 * EAX: Virtual/Physical address Size
434 * ECX: Number of cores + APICIdCoreIdSize
435 * Intel: EAX: Virtual/Physical address Size
436 * EBX, ECX, EDX - reserved
437 */
438 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
439 {
440 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
441 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
442 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
443 * NC (0-7) Number of cores; 0 equals 1 core */
444 pCPUM->aGuestCpuIdExt[8].ecx = 0;
445 }
446
447 /*
448 * Limit it the number of entries and fill the remaining with the defaults.
449 *
450 * The limits are masking off stuff about power saving and similar, this
451 * is perhaps a bit crudely done as there is probably some relatively harmless
452 * info too in these leaves (like words about having a constant TSC).
453 */
454 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
455 pCPUM->aGuestCpuIdStd[0].eax = 2;
456 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
457 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
458
459 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
460 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
461 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
462 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
463 : 0;
464 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
465 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
466
467 /*
468 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
469 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
470 * We currently don't support more than 1 processor.
471 */
472 pCPUM->aGuestCpuIdStd[4].eax = 0;
473
474 /*
475 * Centaur stuff (VIA).
476 *
477 * The important part here (we think) is to make sure the 0xc0000000
478 * function returns 0xc0000001. As for the features, we don't currently
479 * let on about any of those... 0xc0000002 seems to be some
480 * temperature/hz/++ stuff, include it as well (static).
481 */
482 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
483 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
484 {
485 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
486 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
487 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
488 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
489 i++)
490 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
491 }
492 else
493 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
494 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
495
496
497 /*
498 * Load CPUID overrides from configuration.
499 */
500 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
501 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
502 for (i=0;; )
503 {
504 while (cElements-- > 0)
505 {
506 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
507 if (pNode)
508 {
509 uint32_t u32;
510 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
511 if (VBOX_SUCCESS(rc))
512 pCpuId->eax = u32;
513 else
514 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
515
516 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
517 if (VBOX_SUCCESS(rc))
518 pCpuId->ebx = u32;
519 else
520 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
521
522 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
523 if (VBOX_SUCCESS(rc))
524 pCpuId->ecx = u32;
525 else
526 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
527
528 rc = CFGMR3QueryU32(pNode, "edx", &u32);
529 if (VBOX_SUCCESS(rc))
530 pCpuId->edx = u32;
531 else
532 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
533 }
534 pCpuId++;
535 i++;
536 }
537
538 /* next */
539 if ((i & UINT32_C(0xc0000000)) == 0)
540 {
541 pCpuId = &pCPUM->aGuestCpuIdExt[0];
542 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
543 i = UINT32_C(0x80000000);
544 }
545 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
546 {
547 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
548 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
549 i = UINT32_C(0xc0000000);
550 }
551 else
552 break;
553 }
554
555 /* Check if PAE was explicitely enabled by the user. */
556 bool fEnable = false;
557 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
558 if (VBOX_SUCCESS(rc) && fEnable)
559 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
560
561 /*
562 * Log the cpuid and we're good.
563 */
564 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
565 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
566 LogRel(("************************* CPUID dump ************************\n"));
567 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
568 LogRel(("\n"));
569 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
570 LogRel(("******************** End of CPUID dump **********************\n"));
571 return VINF_SUCCESS;
572}
573
574
575
576
577/**
578 * Applies relocations to data and code managed by this
579 * component. This function will be called at init and
580 * whenever the VMM need to relocate it self inside the GC.
581 *
582 * The CPUM will update the addresses used by the switcher.
583 *
584 * @param pVM The VM.
585 */
586CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
587{
588 LogFlow(("CPUMR3Relocate\n"));
589 /*
590 * Switcher pointers.
591 */
592 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
593 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
594 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
595}
596
597
598/**
599 * Queries the pointer to the internal CPUMCTX structure
600 *
601 * @returns VBox status code.
602 * @param pVM Handle to the virtual machine.
603 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
604 */
605CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
606{
607 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
608 /*
609 * Store the address. (Later we might check how's calling, thus the RC.)
610 */
611 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
612 return VINF_SUCCESS;
613}
614
615
616/**
617 * Terminates the CPUM.
618 *
619 * Termination means cleaning up and freeing all resources,
620 * the VM it self is at this point powered off or suspended.
621 *
622 * @returns VBox status code.
623 * @param pVM The VM to operate on.
624 */
625CPUMR3DECL(int) CPUMR3Term(PVM pVM)
626{
627 /** @todo ? */
628 return 0;
629}
630
631
632/**
633 * Resets the CPU.
634 *
635 * @returns VINF_SUCCESS.
636 * @param pVM The VM handle.
637 */
638CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
639{
640 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
641
642 /*
643 * Initialize everything to ZERO first.
644 */
645 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
646 memset(pCtx, 0, sizeof(*pCtx));
647 pVM->cpum.s.fUseFlags = fUseFlags;
648
649 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
650 pCtx->eip = 0x0000fff0;
651 pCtx->edx = 0x00000600; /* P6 processor */
652 pCtx->eflags.Bits.u1Reserved0 = 1;
653
654 pCtx->cs = 0xf000;
655 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
656 pCtx->csHid.u32Limit = 0x0000ffff;
657 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
658 pCtx->csHid.Attr.n.u1Present = 1;
659 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
660
661 pCtx->dsHid.u32Limit = 0x0000ffff;
662 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
663 pCtx->dsHid.Attr.n.u1Present = 1;
664 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
665
666 pCtx->esHid.u32Limit = 0x0000ffff;
667 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
668 pCtx->esHid.Attr.n.u1Present = 1;
669 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
670
671 pCtx->fsHid.u32Limit = 0x0000ffff;
672 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
673 pCtx->fsHid.Attr.n.u1Present = 1;
674 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
675
676 pCtx->gsHid.u32Limit = 0x0000ffff;
677 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
678 pCtx->gsHid.Attr.n.u1Present = 1;
679 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
680
681 pCtx->ssHid.u32Limit = 0x0000ffff;
682 pCtx->ssHid.Attr.n.u1Present = 1;
683 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
684 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
685
686 pCtx->idtr.cbIdt = 0xffff;
687 pCtx->gdtr.cbGdt = 0xffff;
688
689 pCtx->ldtrHid.u32Limit = 0xffff;
690 pCtx->ldtrHid.Attr.n.u1Present = 1;
691 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
692
693 pCtx->trHid.u32Limit = 0xffff;
694 pCtx->trHid.Attr.n.u1Present = 1;
695 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
696
697 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
698 pCtx->dr7 = 0x400;
699
700 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
701 pCtx->fpu.FCW = 0x37f;
702
703 /* Init PAT MSR */
704 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
705}
706
707
708/**
709 * Execute state save operation.
710 *
711 * @returns VBox status code.
712 * @param pVM VM Handle.
713 * @param pSSM SSM operation handle.
714 */
715static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
716{
717 /*
718 * Save.
719 */
720 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
721 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
722 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
723 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
724
725 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
726 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
727
728 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
729 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
730
731 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
732 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
733
734 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
735
736 /* Add the cpuid for checking that the cpu is unchanged. */
737 uint32_t au32CpuId[8] = {0};
738 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
739 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
740 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
741}
742
743
744/**
745 * Execute state load operation.
746 *
747 * @returns VBox status code.
748 * @param pVM VM Handle.
749 * @param pSSM SSM operation handle.
750 * @param u32Version Data layout version.
751 */
752static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
753{
754 /*
755 * Validate version.
756 */
757 if (u32Version != CPUM_SAVED_STATE_VERSION)
758 {
759 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
760 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
761 }
762
763 /*
764 * Restore.
765 */
766 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
767 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
768 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
769 pVM->cpum.s.Hyper.cr3 = uCR3;
770 pVM->cpum.s.Hyper.esp = uESP;
771 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
772 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
773 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
774
775 uint32_t cElements;
776 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
777 /* Support old saved states with a smaller standard cpuid array. */
778 if (cElements > ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
779 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
780 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
781
782 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
783 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
784 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
785 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
786
787 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
788 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
789 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
790 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
791
792 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
793
794 /*
795 * Check that the basic cpuid id information is unchanged.
796 */
797 uint32_t au32CpuId[8] = {0};
798 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
799 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
800 uint32_t au32CpuIdSaved[8];
801 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
802 if (VBOX_SUCCESS(rc))
803 {
804 /* Ignore APIC ID (AMD specs). */
805 au32CpuId[5] &= ~0xff000000;
806 au32CpuIdSaved[5] &= ~0xff000000;
807 /* Ignore the number of Logical CPUs (AMD specs). */
808 au32CpuId[5] &= ~0x00ff0000;
809 au32CpuIdSaved[5] &= ~0x00ff0000;
810
811 /* do the compare */
812 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
813 {
814 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
815 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
816 "Saved=%.*Vhxs\n"
817 "Real =%.*Vhxs\n",
818 sizeof(au32CpuIdSaved), au32CpuIdSaved,
819 sizeof(au32CpuId), au32CpuId));
820 else
821 {
822 LogRel(("cpumR3Load: CpuId mismatch!\n"
823 "Saved=%.*Vhxs\n"
824 "Real =%.*Vhxs\n",
825 sizeof(au32CpuIdSaved), au32CpuIdSaved,
826 sizeof(au32CpuId), au32CpuId));
827 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
828 }
829 }
830 }
831
832 return rc;
833}
834
835
836/**
837 * Formats the EFLAGS value into mnemonics.
838 *
839 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
840 * @param efl The EFLAGS value.
841 */
842static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
843{
844 /*
845 * Format the flags.
846 */
847 static struct
848 {
849 const char *pszSet; const char *pszClear; uint32_t fFlag;
850 } s_aFlags[] =
851 {
852 { "vip",NULL, X86_EFL_VIP },
853 { "vif",NULL, X86_EFL_VIF },
854 { "ac", NULL, X86_EFL_AC },
855 { "vm", NULL, X86_EFL_VM },
856 { "rf", NULL, X86_EFL_RF },
857 { "nt", NULL, X86_EFL_NT },
858 { "ov", "nv", X86_EFL_OF },
859 { "dn", "up", X86_EFL_DF },
860 { "ei", "di", X86_EFL_IF },
861 { "tf", NULL, X86_EFL_TF },
862 { "nt", "pl", X86_EFL_SF },
863 { "nz", "zr", X86_EFL_ZF },
864 { "ac", "na", X86_EFL_AF },
865 { "po", "pe", X86_EFL_PF },
866 { "cy", "nc", X86_EFL_CF },
867 };
868 char *psz = pszEFlags;
869 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
870 {
871 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
872 if (pszAdd)
873 {
874 strcpy(psz, pszAdd);
875 psz += strlen(pszAdd);
876 *psz++ = ' ';
877 }
878 }
879 psz[-1] = '\0';
880}
881
882
883/**
884 * Formats a full register dump.
885 *
886 * @param pVM VM Handle.
887 * @param pCtx The context to format.
888 * @param pCtxCore The context core to format.
889 * @param pHlp Output functions.
890 * @param enmType The dump type.
891 * @param pszPrefix Register name prefix.
892 */
893static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
894{
895 /*
896 * Format the EFLAGS.
897 */
898 uint32_t efl = pCtxCore->eflags.u32;
899 char szEFlags[80];
900 cpumR3InfoFormatFlags(&szEFlags[0], efl);
901
902 /*
903 * Format the registers.
904 */
905 switch (enmType)
906 {
907 case CPUMDUMPTYPE_TERSE:
908 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
909 {
910 pHlp->pfnPrintf(pHlp,
911 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
912 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
913 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
914 "%sr14=%016RX64 %sr15=%016RX64\n"
915 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
916 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
917 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
918 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
919 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
920 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
921 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
922 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
923 }
924 else
925 pHlp->pfnPrintf(pHlp,
926 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
927 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
928 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
929 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
930 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
931 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
932 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
933 break;
934
935 case CPUMDUMPTYPE_DEFAULT:
936 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
937 {
938 pHlp->pfnPrintf(pHlp,
939 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
940 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
941 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
942 "%sr14=%016RX64 %sr15=%016RX64\n"
943 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
944 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
945 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
946 ,
947 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
948 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
949 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
950 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
951 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
952 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
953 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
954 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
955 }
956 else
957 pHlp->pfnPrintf(pHlp,
958 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
959 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
960 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
961 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
962 ,
963 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
964 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
965 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
966 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
967 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
968 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
969 break;
970
971 case CPUMDUMPTYPE_VERBOSE:
972 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
973 {
974 pHlp->pfnPrintf(pHlp,
975 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
976 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
977 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
978 "%sr14=%016RX64 %sr15=%016RX64\n"
979 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
980 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
981 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
982 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
983 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
984 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
985 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
986 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
987 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
988 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
989 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
990 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
991 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
992 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
993 ,
994 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
995 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
996 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
997 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
998 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
999 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1000 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1001 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1002 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1003 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1004 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1005 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1006 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1007 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1008 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1009 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1010 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1011 }
1012 else
1013 pHlp->pfnPrintf(pHlp,
1014 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1015 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1016 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1017 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1018 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1019 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1020 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1021 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1022 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1023 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1024 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1025 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1026 ,
1027 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1028 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1029 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
1030 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1031 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
1032 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1033 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1034 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1035 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1036 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1037 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1038 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1039
1040 pHlp->pfnPrintf(pHlp,
1041 "FPU:\n"
1042 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1043 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1044 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1045 ,
1046 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1047 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1048 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1049 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1050
1051
1052 pHlp->pfnPrintf(pHlp,
1053 "MSR:\n"
1054 "%sEFER =%016RX64\n"
1055 "%sPAT =%016RX64\n"
1056 "%sSTAR =%016RX64\n"
1057 "%sCSTAR =%016RX64\n"
1058 "%sLSTAR =%016RX64\n"
1059 "%sSFMASK =%016RX64\n"
1060 "%sKERNELGSBASE =%016RX64\n",
1061 pszPrefix, pCtx->msrEFER,
1062 pszPrefix, pCtx->msrPAT,
1063 pszPrefix, pCtx->msrSTAR,
1064 pszPrefix, pCtx->msrCSTAR,
1065 pszPrefix, pCtx->msrLSTAR,
1066 pszPrefix, pCtx->msrSFMASK,
1067 pszPrefix, pCtx->msrKERNELGSBASE);
1068
1069 break;
1070 }
1071}
1072
1073
1074/**
1075 * Display all cpu states and any other cpum info.
1076 *
1077 * @param pVM VM Handle.
1078 * @param pHlp The info helper functions.
1079 * @param pszArgs Arguments, ignored.
1080 */
1081static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1082{
1083 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1084 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1085 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1086 cpumR3InfoHost(pVM, pHlp, pszArgs);
1087}
1088
1089
1090/**
1091 * Parses the info argument.
1092 *
1093 * The argument starts with 'verbose', 'terse' or 'default' and then
1094 * continues with the comment string.
1095 *
1096 * @param pszArgs The pointer to the argument string.
1097 * @param penmType Where to store the dump type request.
1098 * @param ppszComment Where to store the pointer to the comment string.
1099 */
1100static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1101{
1102 if (!pszArgs)
1103 {
1104 *penmType = CPUMDUMPTYPE_DEFAULT;
1105 *ppszComment = "";
1106 }
1107 else
1108 {
1109 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1110 {
1111 pszArgs += 5;
1112 *penmType = CPUMDUMPTYPE_VERBOSE;
1113 }
1114 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1115 {
1116 pszArgs += 5;
1117 *penmType = CPUMDUMPTYPE_TERSE;
1118 }
1119 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1120 {
1121 pszArgs += 7;
1122 *penmType = CPUMDUMPTYPE_DEFAULT;
1123 }
1124 else
1125 *penmType = CPUMDUMPTYPE_DEFAULT;
1126 *ppszComment = RTStrStripL(pszArgs);
1127 }
1128}
1129
1130
1131/**
1132 * Display the guest cpu state.
1133 *
1134 * @param pVM VM Handle.
1135 * @param pHlp The info helper functions.
1136 * @param pszArgs Arguments, ignored.
1137 */
1138static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1139{
1140 CPUMDUMPTYPE enmType;
1141 const char *pszComment;
1142 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1143 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1144 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1145}
1146
1147/**
1148 * Display the current guest instruction
1149 *
1150 * @param pVM VM Handle.
1151 * @param pHlp The info helper functions.
1152 * @param pszArgs Arguments, ignored.
1153 */
1154static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1155{
1156 char szInstruction[256];
1157 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1158 if (VBOX_SUCCESS(rc))
1159 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1160}
1161
1162
1163/**
1164 * Display the hypervisor cpu state.
1165 *
1166 * @param pVM VM Handle.
1167 * @param pHlp The info helper functions.
1168 * @param pszArgs Arguments, ignored.
1169 */
1170static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1171{
1172 CPUMDUMPTYPE enmType;
1173 const char *pszComment;
1174 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1175 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1176 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1177 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1178}
1179
1180
1181/**
1182 * Display the host cpu state.
1183 *
1184 * @param pVM VM Handle.
1185 * @param pHlp The info helper functions.
1186 * @param pszArgs Arguments, ignored.
1187 */
1188static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1189{
1190 CPUMDUMPTYPE enmType;
1191 const char *pszComment;
1192 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1193 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1194
1195 /*
1196 * Format the EFLAGS.
1197 */
1198 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1199#if HC_ARCH_BITS == 32
1200 uint32_t efl = pCtx->eflags.u32;
1201#else
1202 uint64_t efl = pCtx->rflags;
1203#endif
1204 char szEFlags[80];
1205 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1206
1207 /*
1208 * Format the registers.
1209 */
1210#if HC_ARCH_BITS == 32
1211# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1212 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1213# endif
1214 {
1215 pHlp->pfnPrintf(pHlp,
1216 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1217 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1218 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1219 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1220 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1221 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1222 ,
1223 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1224 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1225 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1226 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1227 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1228 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1229 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1230 }
1231# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1232 else
1233# endif
1234#endif
1235#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1236 {
1237 pHlp->pfnPrintf(pHlp,
1238 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1239 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1240 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1241 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1242 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1243 "r14=%016RX64 r15=%016RX64\n"
1244 "iopl=%d %31s\n"
1245 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1246 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1247 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1248 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1249 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1250 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1251 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1252 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1253 ,
1254 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1255 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1256 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1257 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1258 pCtx->r11, pCtx->r12, pCtx->r13,
1259 pCtx->r14, pCtx->r15,
1260 X86_EFL_GET_IOPL(efl), szEFlags,
1261 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1262 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1263 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1264 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1265 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1266 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1267 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1268 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1269 }
1270#endif
1271}
1272
1273
1274/**
1275 * Get L1 cache / TLS associativity.
1276 */
1277static const char *getCacheAss(unsigned u, char *pszBuf)
1278{
1279 if (u == 0)
1280 return "res0 ";
1281 if (u == 1)
1282 return "direct";
1283 if (u >= 256)
1284 return "???";
1285
1286 RTStrPrintf(pszBuf, 16, "%d way", u);
1287 return pszBuf;
1288}
1289
1290
1291/**
1292 * Get L2 cache soociativity.
1293 */
1294const char *getL2CacheAss(unsigned u)
1295{
1296 switch (u)
1297 {
1298 case 0: return "off ";
1299 case 1: return "direct";
1300 case 2: return "2 way ";
1301 case 3: return "res3 ";
1302 case 4: return "4 way ";
1303 case 5: return "res5 ";
1304 case 6: return "8 way "; case 7: return "res7 ";
1305 case 8: return "16 way";
1306 case 9: return "res9 ";
1307 case 10: return "res10 ";
1308 case 11: return "res11 ";
1309 case 12: return "res12 ";
1310 case 13: return "res13 ";
1311 case 14: return "res14 ";
1312 case 15: return "fully ";
1313 default:
1314 return "????";
1315 }
1316}
1317
1318
1319/**
1320 * Display the guest CpuId leaves.
1321 *
1322 * @param pVM VM Handle.
1323 * @param pHlp The info helper functions.
1324 * @param pszArgs "terse", "default" or "verbose".
1325 */
1326static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1327{
1328 /*
1329 * Parse the argument.
1330 */
1331 unsigned iVerbosity = 1;
1332 if (pszArgs)
1333 {
1334 pszArgs = RTStrStripL(pszArgs);
1335 if (!strcmp(pszArgs, "terse"))
1336 iVerbosity--;
1337 else if (!strcmp(pszArgs, "verbose"))
1338 iVerbosity++;
1339 }
1340
1341 /*
1342 * Start cracking.
1343 */
1344 CPUMCPUID Host;
1345 CPUMCPUID Guest;
1346 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1347
1348 pHlp->pfnPrintf(pHlp,
1349 " RAW Standard CPUIDs\n"
1350 " Function eax ebx ecx edx\n");
1351 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1352 {
1353 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1354 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1355
1356 pHlp->pfnPrintf(pHlp,
1357 "Gst: %08x %08x %08x %08x %08x%s\n"
1358 "Hst: %08x %08x %08x %08x\n",
1359 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1360 i <= cStdMax ? "" : "*",
1361 Host.eax, Host.ebx, Host.ecx, Host.edx);
1362 }
1363
1364 /*
1365 * If verbose, decode it.
1366 */
1367 if (iVerbosity)
1368 {
1369 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1370 pHlp->pfnPrintf(pHlp,
1371 "Name: %.04s%.04s%.04s\n"
1372 "Supports: 0-%x\n",
1373 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1374 }
1375
1376 /*
1377 * Get Features.
1378 */
1379 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1380 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1381 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1382 if (cStdMax >= 1 && iVerbosity)
1383 {
1384 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1385 uint32_t uEAX = Guest.eax;
1386
1387 pHlp->pfnPrintf(pHlp,
1388 "Family: %d \tExtended: %d \tEffective: %d\n"
1389 "Model: %d \tExtended: %d \tEffective: %d\n"
1390 "Stepping: %d\n"
1391 "APIC ID: %#04x\n"
1392 "Logical CPUs: %d\n"
1393 "CLFLUSH Size: %d\n"
1394 "Brand ID: %#04x\n",
1395 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1396 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1397 ASMGetCpuStepping(uEAX),
1398 (Guest.ebx >> 24) & 0xff,
1399 (Guest.ebx >> 16) & 0xff,
1400 (Guest.ebx >> 8) & 0xff,
1401 (Guest.ebx >> 0) & 0xff);
1402 if (iVerbosity == 1)
1403 {
1404 uint32_t uEDX = Guest.edx;
1405 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1406 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1407 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1408 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1409 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1410 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1411 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1412 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1413 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1414 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1415 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1416 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1417 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1418 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1419 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1420 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1421 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1422 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1423 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1424 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1425 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1426 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1427 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1428 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1429 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1430 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1431 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1432 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1433 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1434 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1435 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1436 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1437 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1438 pHlp->pfnPrintf(pHlp, "\n");
1439
1440 uint32_t uECX = Guest.ecx;
1441 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1442 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1443 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1444 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1445 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1446 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1447 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1448 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1449 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1450 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1451 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1452 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1453 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1454 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1455 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1456 for (unsigned iBit = 14; iBit < 32; iBit++)
1457 if (uECX & RT_BIT(iBit))
1458 pHlp->pfnPrintf(pHlp, " %d", iBit);
1459 pHlp->pfnPrintf(pHlp, "\n");
1460 }
1461 else
1462 {
1463 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1464
1465 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1466 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1467 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1468 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1469
1470 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1471 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1472 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1473 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1474 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1475 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1476 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1477 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1478 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1479 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1480 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1481 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1482 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1483 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1484 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1485 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1486 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1487 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1488 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1489 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1490 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1491 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1492 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1493 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1494 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1495 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1496 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1497 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1498 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1499 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1500 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1501 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1502 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1503
1504 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1505 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1506 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1507 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1508 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1509 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1510 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1511 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1512 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1513 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1514 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1515 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1516 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1517 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1518 }
1519 }
1520 if (cStdMax >= 2 && iVerbosity)
1521 {
1522 /** @todo */
1523 }
1524
1525 /*
1526 * Extended.
1527 * Implemented after AMD specs.
1528 */
1529 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1530
1531 pHlp->pfnPrintf(pHlp,
1532 "\n"
1533 " RAW Extended CPUIDs\n"
1534 " Function eax ebx ecx edx\n");
1535 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1536 {
1537 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1538 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1539
1540 pHlp->pfnPrintf(pHlp,
1541 "Gst: %08x %08x %08x %08x %08x%s\n"
1542 "Hst: %08x %08x %08x %08x\n",
1543 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1544 i <= cExtMax ? "" : "*",
1545 Host.eax, Host.ebx, Host.ecx, Host.edx);
1546 }
1547
1548 /*
1549 * Understandable output
1550 */
1551 if (iVerbosity && cExtMax >= 0)
1552 {
1553 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1554 pHlp->pfnPrintf(pHlp,
1555 "Ext Name: %.4s%.4s%.4s\n"
1556 "Ext Supports: 0x80000000-%#010x\n",
1557 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1558 }
1559
1560 if (iVerbosity && cExtMax >= 1)
1561 {
1562 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1563 uint32_t uEAX = Guest.eax;
1564 pHlp->pfnPrintf(pHlp,
1565 "Family: %d \tExtended: %d \tEffective: %d\n"
1566 "Model: %d \tExtended: %d \tEffective: %d\n"
1567 "Stepping: %d\n"
1568 "Brand ID: %#05x\n",
1569 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1570 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1571 ASMGetCpuStepping(uEAX),
1572 Guest.ebx & 0xfff);
1573
1574 if (iVerbosity == 1)
1575 {
1576 uint32_t uEDX = Guest.edx;
1577 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1578 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1579 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1580 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1581 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1582 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1583 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1584 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1585 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1586 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1587 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1588 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1589 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1590 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1591 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1592 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1593 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1594 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1595 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1596 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1597 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1598 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1599 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1600 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1601 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1602 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1603 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1604 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1605 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1606 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1607 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1608 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1609 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1610 pHlp->pfnPrintf(pHlp, "\n");
1611
1612 uint32_t uECX = Guest.ecx;
1613 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1614 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1615 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1616 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1617 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1618 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1619 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1620 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1621 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1622 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1623 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1624 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1625 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1626 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1627 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1628 for (unsigned iBit = 5; iBit < 32; iBit++)
1629 if (uECX & RT_BIT(iBit))
1630 pHlp->pfnPrintf(pHlp, " %d", iBit);
1631 pHlp->pfnPrintf(pHlp, "\n");
1632 }
1633 else
1634 {
1635 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1636
1637 uint32_t uEdxGst = Guest.edx;
1638 uint32_t uEdxHst = Host.edx;
1639 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1640 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1641 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1642 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1643 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1644 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1645 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1646 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1647 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1648 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1649 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1650 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1651 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1652 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1653 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1654 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1655 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1656 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1657 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1658 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1659 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1660 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1661 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1662 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1663 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1664 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1665 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1666 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1667 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1668 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1669 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1670 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1671 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1672
1673 uint32_t uEcxGst = Guest.ecx;
1674 uint32_t uEcxHst = Host.ecx;
1675 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1676 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1677 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1678 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1679 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1680 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1681 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1682 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1683 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1684 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1685 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1686 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1687 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1688 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1689 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1690 }
1691 }
1692
1693 if (iVerbosity && cExtMax >= 2)
1694 {
1695 char szString[4*4*3+1] = {0};
1696 uint32_t *pu32 = (uint32_t *)szString;
1697 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1698 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1699 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1700 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1701 if (cExtMax >= 3)
1702 {
1703 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1704 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1705 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1706 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1707 }
1708 if (cExtMax >= 4)
1709 {
1710 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1711 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1712 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1713 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1714 }
1715 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1716 }
1717
1718 if (iVerbosity && cExtMax >= 5)
1719 {
1720 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1721 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1722 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1723 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1724 char sz1[32];
1725 char sz2[32];
1726
1727 pHlp->pfnPrintf(pHlp,
1728 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1729 "TLB 2/4M Data: %s %3d entries\n",
1730 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1731 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1732 pHlp->pfnPrintf(pHlp,
1733 "TLB 4K Instr/Uni: %s %3d entries\n"
1734 "TLB 4K Data: %s %3d entries\n",
1735 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1736 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1737 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1738 "L1 Instr Cache Lines Per Tag: %d\n"
1739 "L1 Instr Cache Associativity: %s\n"
1740 "L1 Instr Cache Size: %d KB\n",
1741 (uEDX >> 0) & 0xff,
1742 (uEDX >> 8) & 0xff,
1743 getCacheAss((uEDX >> 16) & 0xff, sz1),
1744 (uEDX >> 24) & 0xff);
1745 pHlp->pfnPrintf(pHlp,
1746 "L1 Data Cache Line Size: %d bytes\n"
1747 "L1 Data Cache Lines Per Tag: %d\n"
1748 "L1 Data Cache Associativity: %s\n"
1749 "L1 Data Cache Size: %d KB\n",
1750 (uECX >> 0) & 0xff,
1751 (uECX >> 8) & 0xff,
1752 getCacheAss((uECX >> 16) & 0xff, sz1),
1753 (uECX >> 24) & 0xff);
1754 }
1755
1756 if (iVerbosity && cExtMax >= 6)
1757 {
1758 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1759 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1760 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1761
1762 pHlp->pfnPrintf(pHlp,
1763 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1764 "L2 TLB 2/4M Data: %s %4d entries\n",
1765 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1766 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1767 pHlp->pfnPrintf(pHlp,
1768 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1769 "L2 TLB 4K Data: %s %4d entries\n",
1770 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1771 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1772 pHlp->pfnPrintf(pHlp,
1773 "L2 Cache Line Size: %d bytes\n"
1774 "L2 Cache Lines Per Tag: %d\n"
1775 "L2 Cache Associativity: %s\n"
1776 "L2 Cache Size: %d KB\n",
1777 (uEDX >> 0) & 0xff,
1778 (uEDX >> 8) & 0xf,
1779 getL2CacheAss((uEDX >> 12) & 0xf),
1780 (uEDX >> 16) & 0xffff);
1781 }
1782
1783 if (iVerbosity && cExtMax >= 7)
1784 {
1785 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1786
1787 pHlp->pfnPrintf(pHlp, "APM Features: ");
1788 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1789 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1790 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1791 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1792 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1793 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1794 for (unsigned iBit = 6; iBit < 32; iBit++)
1795 if (uEDX & RT_BIT(iBit))
1796 pHlp->pfnPrintf(pHlp, " %d", iBit);
1797 pHlp->pfnPrintf(pHlp, "\n");
1798 }
1799
1800 if (iVerbosity && cExtMax >= 8)
1801 {
1802 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1803 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1804
1805 pHlp->pfnPrintf(pHlp,
1806 "Physical Address Width: %d bits\n"
1807 "Virtual Address Width: %d bits\n",
1808 (uEAX >> 0) & 0xff,
1809 (uEAX >> 8) & 0xff);
1810 pHlp->pfnPrintf(pHlp,
1811 "Physical Core Count: %d\n",
1812 (uECX >> 0) & 0xff);
1813 }
1814
1815
1816 /*
1817 * Centaur.
1818 */
1819 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1820
1821 pHlp->pfnPrintf(pHlp,
1822 "\n"
1823 " RAW Centaur CPUIDs\n"
1824 " Function eax ebx ecx edx\n");
1825 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1826 {
1827 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1828 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1829
1830 pHlp->pfnPrintf(pHlp,
1831 "Gst: %08x %08x %08x %08x %08x%s\n"
1832 "Hst: %08x %08x %08x %08x\n",
1833 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1834 i <= cCentaurMax ? "" : "*",
1835 Host.eax, Host.ebx, Host.ecx, Host.edx);
1836 }
1837
1838 /*
1839 * Understandable output
1840 */
1841 if (iVerbosity && cCentaurMax >= 0)
1842 {
1843 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1844 pHlp->pfnPrintf(pHlp,
1845 "Centaur Supports: 0xc0000000-%#010x\n",
1846 Guest.eax);
1847 }
1848
1849 if (iVerbosity && cCentaurMax >= 1)
1850 {
1851 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1852 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1853 uint32_t uEdxHst = Host.edx;
1854
1855 if (iVerbosity == 1)
1856 {
1857 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1858 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1859 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1860 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1861 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1862 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1863 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1864 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1865 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1866 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1867 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1868 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1869 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1870 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1871 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1872 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1873 for (unsigned iBit = 14; iBit < 32; iBit++)
1874 if (uEdxGst & RT_BIT(iBit))
1875 pHlp->pfnPrintf(pHlp, " %d", iBit);
1876 pHlp->pfnPrintf(pHlp, "\n");
1877 }
1878 else
1879 {
1880 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1881 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1882 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1883 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1884 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1885 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1886 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1887 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1888 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1889 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1890 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1891 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1892 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1893 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1894 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1895 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1896 for (unsigned iBit = 14; iBit < 32; iBit++)
1897 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1898 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1899 pHlp->pfnPrintf(pHlp, "\n");
1900 }
1901 }
1902}
1903
1904
1905/**
1906 * Structure used when disassembling and instructions in DBGF.
1907 * This is used so the reader function can get the stuff it needs.
1908 */
1909typedef struct CPUMDISASSTATE
1910{
1911 /** Pointer to the CPU structure. */
1912 PDISCPUSTATE pCpu;
1913 /** The VM handle. */
1914 PVM pVM;
1915 /** Pointer to the first byte in the segemnt. */
1916 RTGCUINTPTR GCPtrSegBase;
1917 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1918 RTGCUINTPTR GCPtrSegEnd;
1919 /** The size of the segment minus 1. */
1920 RTGCUINTPTR cbSegLimit;
1921 /** Pointer to the current page - HC Ptr. */
1922 void const *pvPageHC;
1923 /** Pointer to the current page - GC Ptr. */
1924 RTGCPTR pvPageGC;
1925 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1926 PGMPAGEMAPLOCK PageMapLock;
1927 /** Whether the PageMapLock is valid or not. */
1928 bool fLocked;
1929 /** 64 bits mode or not. */
1930 bool f64Bits;
1931} CPUMDISASSTATE, *PCPUMDISASSTATE;
1932
1933
1934/**
1935 * Instruction reader.
1936 *
1937 * @returns VBox status code.
1938 * @param PtrSrc Address to read from.
1939 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1940 * @param pu8Dst Where to store the bytes.
1941 * @param cbRead Number of bytes to read.
1942 * @param uDisCpu Pointer to the disassembler cpu state.
1943 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1944 */
1945static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1946{
1947 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1948 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1949 Assert(cbRead > 0);
1950 for (;;)
1951 {
1952 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1953
1954 /* Need to update the page translation? */
1955 if ( !pState->pvPageHC
1956 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1957 {
1958 int rc = VINF_SUCCESS;
1959
1960 /* translate the address */
1961 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1962 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1963 {
1964 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1965 if (!pState->pvPageHC)
1966 rc = VERR_INVALID_POINTER;
1967 }
1968 else
1969 {
1970 /* Release mapping lock previously acquired. */
1971 if (pState->fLocked)
1972 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1973 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1974 pState->fLocked = RT_SUCCESS_NP(rc);
1975 }
1976 if (VBOX_FAILURE(rc))
1977 {
1978 pState->pvPageHC = NULL;
1979 return rc;
1980 }
1981 }
1982
1983 /* check the segemnt limit */
1984 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
1985 return VERR_OUT_OF_SELECTOR_BOUNDS;
1986
1987 /* calc how much we can read */
1988 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1989 if (!pState->f64Bits)
1990 {
1991 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1992 if (cb > cbSeg && cbSeg)
1993 cb = cbSeg;
1994 }
1995 if (cb > cbRead)
1996 cb = cbRead;
1997
1998 /* read and advance */
1999 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2000 cbRead -= cb;
2001 if (!cbRead)
2002 return VINF_SUCCESS;
2003 pu8Dst += cb;
2004 PtrSrc += cb;
2005 }
2006}
2007
2008
2009/**
2010 * Disassemble an instruction and return the information in the provided structure.
2011 *
2012 * @returns VBox status code.
2013 * @param pVM VM Handle
2014 * @param pCtx CPU context
2015 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2016 * @param pCpu Disassembly state
2017 * @param pszPrefix String prefix for logging (debug only)
2018 *
2019 */
2020CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2021{
2022 CPUMDISASSTATE State;
2023 int rc;
2024
2025 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2026 State.pCpu = pCpu;
2027 State.pvPageGC = 0;
2028 State.pvPageHC = NULL;
2029 State.pVM = pVM;
2030 State.fLocked = false;
2031 State.f64Bits = false;
2032
2033 /*
2034 * Get selector information.
2035 */
2036 if ( (pCtx->cr0 & X86_CR0_PE)
2037 && pCtx->eflags.Bits.u1VM == 0)
2038 {
2039 if (CPUMAreHiddenSelRegsValid(pVM))
2040 {
2041 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2042 State.GCPtrSegBase = pCtx->csHid.u64Base;
2043 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2044 State.cbSegLimit = pCtx->csHid.u32Limit;
2045 pCpu->mode = (State.f64Bits)
2046 ? CPUMODE_64BIT
2047 : pCtx->csHid.Attr.n.u1DefBig
2048 ? CPUMODE_32BIT
2049 : CPUMODE_16BIT;
2050 }
2051 else
2052 {
2053 SELMSELINFO SelInfo;
2054
2055 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2056 if (!VBOX_SUCCESS(rc))
2057 {
2058 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2059 return rc;
2060 }
2061
2062 /*
2063 * Validate the selector.
2064 */
2065 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2066 if (!VBOX_SUCCESS(rc))
2067 {
2068 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2069 return rc;
2070 }
2071 State.GCPtrSegBase = SelInfo.GCPtrBase;
2072 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2073 State.cbSegLimit = SelInfo.cbLimit;
2074 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2075 }
2076 }
2077 else
2078 {
2079 /* real or V86 mode */
2080 pCpu->mode = CPUMODE_16BIT;
2081 State.GCPtrSegBase = pCtx->cs * 16;
2082 State.GCPtrSegEnd = 0xFFFFFFFF;
2083 State.cbSegLimit = 0xFFFFFFFF;
2084 }
2085
2086 /*
2087 * Disassemble the instruction.
2088 */
2089 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2090 pCpu->apvUserData[0] = &State;
2091
2092 uint32_t cbInstr;
2093#ifndef LOG_ENABLED
2094 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2095 if (VBOX_SUCCESS(rc))
2096 {
2097#else
2098 char szOutput[160];
2099 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2100 if (VBOX_SUCCESS(rc))
2101 {
2102 /* log it */
2103 if (pszPrefix)
2104 Log(("%s: %s", pszPrefix, szOutput));
2105 else
2106 Log(("%s", szOutput));
2107#endif
2108 rc = VINF_SUCCESS;
2109 }
2110 else
2111 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2112
2113 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2114 if (State.fLocked)
2115 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2116
2117 return rc;
2118}
2119
2120#ifdef DEBUG
2121
2122/**
2123 * Disassemble an instruction and dump it to the log
2124 *
2125 * @returns VBox status code.
2126 * @param pVM VM Handle
2127 * @param pCtx CPU context
2128 * @param pc GC instruction pointer
2129 * @param prefix String prefix for logging
2130 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2131 *
2132 */
2133CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2134{
2135 DISCPUSTATE cpu;
2136
2137 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2138}
2139
2140/**
2141 * Disassemble an instruction and dump it to the log
2142 *
2143 * @returns VBox status code.
2144 * @param pVM VM Handle
2145 * @param pCtx CPU context
2146 * @param pc GC instruction pointer
2147 * @param prefix String prefix for logging
2148 * @param nrInstructions
2149 *
2150 */
2151CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2152{
2153 for(int i=0;i<nrInstructions;i++)
2154 {
2155 DISCPUSTATE cpu;
2156
2157 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2158 pc += cpu.opsize;
2159 }
2160}
2161
2162#endif /* DEBUG */
2163
2164#ifdef DEBUG
2165/**
2166 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2167 *
2168 * @internal
2169 */
2170CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2171{
2172 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2173}
2174#endif /* DEBUG */
2175
2176
2177/**
2178 * API for controlling a few of the CPU features found in CR4.
2179 *
2180 * Currently only X86_CR4_TSD is accepted as input.
2181 *
2182 * @returns VBox status code.
2183 *
2184 * @param pVM The VM handle.
2185 * @param fOr The CR4 OR mask.
2186 * @param fAnd The CR4 AND mask.
2187 */
2188CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2189{
2190 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2191 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2192
2193 pVM->cpum.s.CR4.OrMask &= fAnd;
2194 pVM->cpum.s.CR4.OrMask |= fOr;
2195
2196 return VINF_SUCCESS;
2197}
2198
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