VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 10821

Last change on this file since 10821 was 10821, checked in by vboxsync, 16 years ago

Backed out 33264 - NT4 installation regression (investigate)
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1/* $Id: CPUM.cpp 10821 2008-07-23 08:03:39Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/pdm.h>
43#include <VBox/mm.h>
44#include <VBox/selm.h>
45#include <VBox/dbgf.h>
46#include <VBox/patm.h>
47#include <VBox/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm.h>
57#include <iprt/string.h>
58#include <iprt/system.h>
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** The saved state version. */
65#define CPUM_SAVED_STATE_VERSION 8
66
67
68/*******************************************************************************
69* Structures and Typedefs *
70*******************************************************************************/
71
72/**
73 * What kind of cpu info dump to perform.
74 */
75typedef enum CPUMDUMPTYPE
76{
77 CPUMDUMPTYPE_TERSE,
78 CPUMDUMPTYPE_DEFAULT,
79 CPUMDUMPTYPE_VERBOSE
80
81} CPUMDUMPTYPE;
82/** Pointer to a cpu info dump type. */
83typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
84
85/*******************************************************************************
86* Internal Functions *
87*******************************************************************************/
88static int cpumR3CpuIdInit(PVM pVM);
89static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
91static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
92static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97
98
99/**
100 * Initializes the CPUM.
101 *
102 * @returns VBox status code.
103 * @param pVM The VM to operate on.
104 */
105CPUMR3DECL(int) CPUMR3Init(PVM pVM)
106{
107 LogFlow(("CPUMR3Init\n"));
108
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
113 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
114
115 /*
116 * Setup any fixed pointers and offsets.
117 */
118 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
119 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
120 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
121 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
122
123 /* Hidden selector registers are invalid by default. */
124 pVM->cpum.s.fValidHiddenSelRegs = false;
125
126 /*
127 * Check that the CPU supports the minimum features we require.
128 */
129 /** @todo check the contract! */
130 if (!ASMHasCpuId())
131 {
132 Log(("The CPU doesn't support CPUID!\n"));
133 return VERR_UNSUPPORTED_CPU;
134 }
135 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
136 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
137
138 /* Setup the CR4 AND and OR masks used in the switcher */
139 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
140 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
141 {
142 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
143 /* No FXSAVE implies no SSE */
144 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
145 pVM->cpum.s.CR4.OrMask = 0;
146 }
147 else
148 {
149 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
150 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
151 }
152
153 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
154 {
155 Log(("The CPU doesn't support MMX!\n"));
156 return VERR_UNSUPPORTED_CPU;
157 }
158 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
159 {
160 Log(("The CPU doesn't support TSC!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 /* Bogus on AMD? */
164 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
165 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
166
167 /*
168 * Setup hypervisor startup values.
169 */
170
171 /*
172 * Register saved state data item.
173 */
174 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
175 NULL, cpumR3Save, NULL,
176 NULL, cpumR3Load, NULL);
177 if (VBOX_FAILURE(rc))
178 return rc;
179
180 /* Query the CPU manufacturer. */
181 uint32_t uEAX, uEBX, uECX, uEDX;
182 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
183 if ( uEAX >= 1
184 && uEBX == X86_CPUID_VENDOR_AMD_EBX
185 && uECX == X86_CPUID_VENDOR_AMD_ECX
186 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
187 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
188 else if ( uEAX >= 1
189 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
190 && uECX == X86_CPUID_VENDOR_INTEL_ECX
191 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
193 else /** @todo Via */
194 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
195
196 /*
197 * Register info handlers.
198 */
199 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
200 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
201 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
202 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
203 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
204 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
205
206 /*
207 * Initialize the Guest CPU state.
208 */
209 rc = cpumR3CpuIdInit(pVM);
210 if (VBOX_FAILURE(rc))
211 return rc;
212 CPUMR3Reset(pVM);
213 return VINF_SUCCESS;
214}
215
216
217/**
218 * Initializes the emulated CPU's cpuid information.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223static int cpumR3CpuIdInit(PVM pVM)
224{
225 PCPUM pCPUM = &pVM->cpum.s;
226 uint32_t i;
227
228 /*
229 * Get the host CPUIDs.
230 */
231 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
232 ASMCpuId_Idx_ECX(i, 0,
233 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
234 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
235 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
236 ASMCpuId(0x80000000 + i,
237 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
238 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
239 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
240 ASMCpuId(0xc0000000 + i,
241 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
242 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
243
244
245 /*
246 * Only report features we can support.
247 */
248 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
249 | X86_CPUID_FEATURE_EDX_VME
250 | X86_CPUID_FEATURE_EDX_DE
251 | X86_CPUID_FEATURE_EDX_PSE
252 | X86_CPUID_FEATURE_EDX_TSC
253 | X86_CPUID_FEATURE_EDX_MSR
254 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
255 | X86_CPUID_FEATURE_EDX_MCE
256 | X86_CPUID_FEATURE_EDX_CX8
257 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
258 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
259 //| X86_CPUID_FEATURE_EDX_SEP
260 | X86_CPUID_FEATURE_EDX_MTRR
261 | X86_CPUID_FEATURE_EDX_PGE
262 | X86_CPUID_FEATURE_EDX_MCA
263 | X86_CPUID_FEATURE_EDX_CMOV
264 | X86_CPUID_FEATURE_EDX_PAT
265 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
266 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
267 | X86_CPUID_FEATURE_EDX_CLFSH
268 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
269 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
270 | X86_CPUID_FEATURE_EDX_MMX
271 | X86_CPUID_FEATURE_EDX_FXSR
272 | X86_CPUID_FEATURE_EDX_SSE
273 | X86_CPUID_FEATURE_EDX_SSE2
274 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
275 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
276 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
277 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
278 | 0;
279 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
280 | X86_CPUID_FEATURE_ECX_MONITOR
281 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
282 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
283 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
284 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
285 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
286 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
287 //| X86_CPUID_FEATURE_ECX_CX16
288 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
289 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
290 /* ECX Bit 23 - POPCOUNT instruction. */
291 //| X86_CPUID_FEATURE_ECX_POPCOUNT
292 | 0;
293
294 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
295 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
296 | X86_CPUID_AMD_FEATURE_EDX_VME
297 | X86_CPUID_AMD_FEATURE_EDX_DE
298 | X86_CPUID_AMD_FEATURE_EDX_PSE
299 | X86_CPUID_AMD_FEATURE_EDX_TSC
300 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
301 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
302 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
303 | X86_CPUID_AMD_FEATURE_EDX_CX8
304 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
305 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
306 //| X86_CPUID_AMD_FEATURE_EDX_SEP
307 | X86_CPUID_AMD_FEATURE_EDX_MTRR
308 | X86_CPUID_AMD_FEATURE_EDX_PGE
309 | X86_CPUID_AMD_FEATURE_EDX_MCA
310 | X86_CPUID_AMD_FEATURE_EDX_CMOV
311 | X86_CPUID_AMD_FEATURE_EDX_PAT
312 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
313 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
314 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
315 | X86_CPUID_AMD_FEATURE_EDX_MMX
316 | X86_CPUID_AMD_FEATURE_EDX_FXSR
317 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
318 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
319 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
320 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
321 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
322 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
323 | 0;
324 pCPUM->aGuestCpuIdExt[1].ecx &= 0
325 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
326 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
327 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
328 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
329 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
330 //| X86_CPUID_AMD_FEATURE_ECX_ABM
331 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
332 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
333 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
334 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
335 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
336 //| X86_CPUID_AMD_FEATURE_ECX_WDT
337 | 0;
338
339 /*
340 * Hide HTT, multicode, SMP, whatever.
341 * (APIC-ID := 0 and #LogCpus := 0)
342 */
343 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
344
345 /* Cpuid 2:
346 * Intel: Cache and TLB information
347 * AMD: Reserved
348 * Safe to expose
349 */
350
351 /* Cpuid 3:
352 * Intel: EAX, EBX - reserved
353 * ECX, EDX - Processor Serial Number if available, otherwise reserved
354 * AMD: Reserved
355 * Safe to expose
356 */
357 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
358 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
359
360 /* Cpuid 4:
361 * Intel: Deterministic Cache Parameters Leaf
362 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
363 * AMD: Reserved
364 * Safe to expose, except for EAX:
365 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
366 * Bits 31-26: Maximum number of processor cores in this physical package**
367 */
368 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
369 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
370
371 /* Cpuid 5: Monitor/mwait Leaf
372 * Intel: ECX, EDX - reserved
373 * EAX, EBX - Smallest and largest monitor line size
374 * AMD: EDX - reserved
375 * EAX, EBX - Smallest and largest monitor line size
376 * ECX - extensions (ignored for now)
377 * Safe to expose
378 */
379 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
380 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
381
382 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
383
384 /*
385 * Determine the default.
386 *
387 * Intel returns values of the highest standard function, while AMD
388 * returns zeros. VIA on the other hand seems to returning nothing or
389 * perhaps some random garbage, we don't try to duplicate this behavior.
390 */
391 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
392 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
393 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
394
395 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
396 * Safe to pass on to the guest.
397 *
398 * Intel: 0x800000005 reserved
399 * 0x800000006 L2 cache information
400 * AMD: 0x800000005 L1 cache information
401 * 0x800000006 L2/L3 cache information
402 */
403
404 /* Cpuid 0x800000007:
405 * AMD: EAX, EBX, ECX - reserved
406 * EDX: Advanced Power Management Information
407 * Intel: Reserved
408 */
409 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
410 {
411 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
412
413 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
414
415 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
416 {
417 /* Only expose the TSC invariant capability bit to the guest. */
418 pCPUM->aGuestCpuIdExt[7].edx &= 0
419 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
420 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
421 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
422 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
423 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
424 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
425 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
426 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
427 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
428 | 0;
429 }
430 else
431 pCPUM->aGuestCpuIdExt[7].edx = 0;
432 }
433
434 /* Cpuid 0x800000008:
435 * AMD: EBX, EDX - reserved
436 * EAX: Virtual/Physical address Size
437 * ECX: Number of cores + APICIdCoreIdSize
438 * Intel: EAX: Virtual/Physical address Size
439 * EBX, ECX, EDX - reserved
440 */
441 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
442 {
443 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
444 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
445 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
446 * NC (0-7) Number of cores; 0 equals 1 core */
447 pCPUM->aGuestCpuIdExt[8].ecx = 0;
448 }
449
450 /*
451 * Limit it the number of entries and fill the remaining with the defaults.
452 *
453 * The limits are masking off stuff about power saving and similar, this
454 * is perhaps a bit crudely done as there is probably some relatively harmless
455 * info too in these leaves (like words about having a constant TSC).
456 */
457#if 0
458 /** @todo NT4 installation regression - investigate */
459 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
460 pCPUM->aGuestCpuIdStd[0].eax = 5;
461#else
462 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
463 pCPUM->aGuestCpuIdStd[0].eax = 2;
464#endif
465 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
466 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
467
468 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
469 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
470 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
471 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
472 : 0;
473 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
474 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
475
476 /*
477 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
478 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
479 * We currently don't support more than 1 processor.
480 */
481 pCPUM->aGuestCpuIdStd[4].eax = 0;
482
483 /*
484 * Centaur stuff (VIA).
485 *
486 * The important part here (we think) is to make sure the 0xc0000000
487 * function returns 0xc0000001. As for the features, we don't currently
488 * let on about any of those... 0xc0000002 seems to be some
489 * temperature/hz/++ stuff, include it as well (static).
490 */
491 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
492 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
493 {
494 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
495 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
496 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
497 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
498 i++)
499 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
500 }
501 else
502 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
503 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
504
505
506 /*
507 * Load CPUID overrides from configuration.
508 */
509 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
510 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
511 for (i=0;; )
512 {
513 while (cElements-- > 0)
514 {
515 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
516 if (pNode)
517 {
518 uint32_t u32;
519 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
520 if (VBOX_SUCCESS(rc))
521 pCpuId->eax = u32;
522 else
523 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
524
525 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
526 if (VBOX_SUCCESS(rc))
527 pCpuId->ebx = u32;
528 else
529 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
530
531 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
532 if (VBOX_SUCCESS(rc))
533 pCpuId->ecx = u32;
534 else
535 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
536
537 rc = CFGMR3QueryU32(pNode, "edx", &u32);
538 if (VBOX_SUCCESS(rc))
539 pCpuId->edx = u32;
540 else
541 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
542 }
543 pCpuId++;
544 i++;
545 }
546
547 /* next */
548 if ((i & UINT32_C(0xc0000000)) == 0)
549 {
550 pCpuId = &pCPUM->aGuestCpuIdExt[0];
551 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
552 i = UINT32_C(0x80000000);
553 }
554 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
555 {
556 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
557 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
558 i = UINT32_C(0xc0000000);
559 }
560 else
561 break;
562 }
563
564 /* Check if PAE was explicitely enabled by the user. */
565 bool fEnable = false;
566 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
567 if (VBOX_SUCCESS(rc) && fEnable)
568 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
569
570 /*
571 * Log the cpuid and we're good.
572 */
573 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
574 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
575 LogRel(("************************* CPUID dump ************************\n"));
576 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
577 LogRel(("\n"));
578 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
579 LogRel(("******************** End of CPUID dump **********************\n"));
580 return VINF_SUCCESS;
581}
582
583
584
585
586/**
587 * Applies relocations to data and code managed by this
588 * component. This function will be called at init and
589 * whenever the VMM need to relocate it self inside the GC.
590 *
591 * The CPUM will update the addresses used by the switcher.
592 *
593 * @param pVM The VM.
594 */
595CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
596{
597 LogFlow(("CPUMR3Relocate\n"));
598 /*
599 * Switcher pointers.
600 */
601 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
602 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
603 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
604}
605
606
607/**
608 * Queries the pointer to the internal CPUMCTX structure
609 *
610 * @returns VBox status code.
611 * @param pVM Handle to the virtual machine.
612 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
613 */
614CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
615{
616 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
617 /*
618 * Store the address. (Later we might check how's calling, thus the RC.)
619 */
620 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
621 return VINF_SUCCESS;
622}
623
624
625/**
626 * Terminates the CPUM.
627 *
628 * Termination means cleaning up and freeing all resources,
629 * the VM it self is at this point powered off or suspended.
630 *
631 * @returns VBox status code.
632 * @param pVM The VM to operate on.
633 */
634CPUMR3DECL(int) CPUMR3Term(PVM pVM)
635{
636 /** @todo ? */
637 return 0;
638}
639
640
641/**
642 * Resets the CPU.
643 *
644 * @returns VINF_SUCCESS.
645 * @param pVM The VM handle.
646 */
647CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
648{
649 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
650
651 /*
652 * Initialize everything to ZERO first.
653 */
654 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
655 memset(pCtx, 0, sizeof(*pCtx));
656 pVM->cpum.s.fUseFlags = fUseFlags;
657
658 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
659 pCtx->eip = 0x0000fff0;
660 pCtx->edx = 0x00000600; /* P6 processor */
661 pCtx->eflags.Bits.u1Reserved0 = 1;
662
663 pCtx->cs = 0xf000;
664 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
665 pCtx->csHid.u32Limit = 0x0000ffff;
666 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
667 pCtx->csHid.Attr.n.u1Present = 1;
668 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
669
670 pCtx->dsHid.u32Limit = 0x0000ffff;
671 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
672 pCtx->dsHid.Attr.n.u1Present = 1;
673 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
674
675 pCtx->esHid.u32Limit = 0x0000ffff;
676 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
677 pCtx->esHid.Attr.n.u1Present = 1;
678 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
679
680 pCtx->fsHid.u32Limit = 0x0000ffff;
681 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
682 pCtx->fsHid.Attr.n.u1Present = 1;
683 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
684
685 pCtx->gsHid.u32Limit = 0x0000ffff;
686 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
687 pCtx->gsHid.Attr.n.u1Present = 1;
688 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
689
690 pCtx->ssHid.u32Limit = 0x0000ffff;
691 pCtx->ssHid.Attr.n.u1Present = 1;
692 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
693 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
694
695 pCtx->idtr.cbIdt = 0xffff;
696 pCtx->gdtr.cbGdt = 0xffff;
697
698 pCtx->ldtrHid.u32Limit = 0xffff;
699 pCtx->ldtrHid.Attr.n.u1Present = 1;
700 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
701
702 pCtx->trHid.u32Limit = 0xffff;
703 pCtx->trHid.Attr.n.u1Present = 1;
704 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
705
706 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
707 pCtx->dr7 = 0x400;
708
709 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
710 pCtx->fpu.FCW = 0x37f;
711
712 /* Init PAT MSR */
713 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
714}
715
716
717/**
718 * Execute state save operation.
719 *
720 * @returns VBox status code.
721 * @param pVM VM Handle.
722 * @param pSSM SSM operation handle.
723 */
724static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
725{
726 /*
727 * Save.
728 */
729 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
730 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
731 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
732 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
733
734 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
735 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
736
737 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
738 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
739
740 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
741 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
742
743 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
744
745 /* Add the cpuid for checking that the cpu is unchanged. */
746 uint32_t au32CpuId[8] = {0};
747 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
748 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
749 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
750}
751
752
753/**
754 * Execute state load operation.
755 *
756 * @returns VBox status code.
757 * @param pVM VM Handle.
758 * @param pSSM SSM operation handle.
759 * @param u32Version Data layout version.
760 */
761static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
762{
763 /*
764 * Validate version.
765 */
766 if (u32Version != CPUM_SAVED_STATE_VERSION)
767 {
768 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
769 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
770 }
771
772 /*
773 * Restore.
774 */
775 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
776 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
777 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
778 pVM->cpum.s.Hyper.cr3 = uCR3;
779 pVM->cpum.s.Hyper.esp = uESP;
780 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
781 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
782 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
783
784 uint32_t cElements;
785 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
786 /* Support old saved states with a smaller standard cpuid array. */
787 if (cElements > ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
788 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
789 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
790
791 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
792 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
793 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
794 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
795
796 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
797 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
798 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
799 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
800
801 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
802
803 /*
804 * Check that the basic cpuid id information is unchanged.
805 */
806 uint32_t au32CpuId[8] = {0};
807 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
808 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
809 uint32_t au32CpuIdSaved[8];
810 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
811 if (VBOX_SUCCESS(rc))
812 {
813 /* Ignore APIC ID (AMD specs). */
814 au32CpuId[5] &= ~0xff000000;
815 au32CpuIdSaved[5] &= ~0xff000000;
816 /* Ignore the number of Logical CPUs (AMD specs). */
817 au32CpuId[5] &= ~0x00ff0000;
818 au32CpuIdSaved[5] &= ~0x00ff0000;
819
820 /* do the compare */
821 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
822 {
823 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
824 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
825 "Saved=%.*Vhxs\n"
826 "Real =%.*Vhxs\n",
827 sizeof(au32CpuIdSaved), au32CpuIdSaved,
828 sizeof(au32CpuId), au32CpuId));
829 else
830 {
831 LogRel(("cpumR3Load: CpuId mismatch!\n"
832 "Saved=%.*Vhxs\n"
833 "Real =%.*Vhxs\n",
834 sizeof(au32CpuIdSaved), au32CpuIdSaved,
835 sizeof(au32CpuId), au32CpuId));
836 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
837 }
838 }
839 }
840
841 return rc;
842}
843
844
845/**
846 * Formats the EFLAGS value into mnemonics.
847 *
848 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
849 * @param efl The EFLAGS value.
850 */
851static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
852{
853 /*
854 * Format the flags.
855 */
856 static struct
857 {
858 const char *pszSet; const char *pszClear; uint32_t fFlag;
859 } s_aFlags[] =
860 {
861 { "vip",NULL, X86_EFL_VIP },
862 { "vif",NULL, X86_EFL_VIF },
863 { "ac", NULL, X86_EFL_AC },
864 { "vm", NULL, X86_EFL_VM },
865 { "rf", NULL, X86_EFL_RF },
866 { "nt", NULL, X86_EFL_NT },
867 { "ov", "nv", X86_EFL_OF },
868 { "dn", "up", X86_EFL_DF },
869 { "ei", "di", X86_EFL_IF },
870 { "tf", NULL, X86_EFL_TF },
871 { "nt", "pl", X86_EFL_SF },
872 { "nz", "zr", X86_EFL_ZF },
873 { "ac", "na", X86_EFL_AF },
874 { "po", "pe", X86_EFL_PF },
875 { "cy", "nc", X86_EFL_CF },
876 };
877 char *psz = pszEFlags;
878 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
879 {
880 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
881 if (pszAdd)
882 {
883 strcpy(psz, pszAdd);
884 psz += strlen(pszAdd);
885 *psz++ = ' ';
886 }
887 }
888 psz[-1] = '\0';
889}
890
891
892/**
893 * Formats a full register dump.
894 *
895 * @param pVM VM Handle.
896 * @param pCtx The context to format.
897 * @param pCtxCore The context core to format.
898 * @param pHlp Output functions.
899 * @param enmType The dump type.
900 * @param pszPrefix Register name prefix.
901 */
902static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
903{
904 /*
905 * Format the EFLAGS.
906 */
907 uint32_t efl = pCtxCore->eflags.u32;
908 char szEFlags[80];
909 cpumR3InfoFormatFlags(&szEFlags[0], efl);
910
911 /*
912 * Format the registers.
913 */
914 switch (enmType)
915 {
916 case CPUMDUMPTYPE_TERSE:
917 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
918 {
919 pHlp->pfnPrintf(pHlp,
920 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
921 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
922 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
923 "%sr14=%016RX64 %sr15=%016RX64\n"
924 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
925 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
926 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
927 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
928 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
929 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
930 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
931 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
932 }
933 else
934 pHlp->pfnPrintf(pHlp,
935 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
936 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
937 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
938 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
939 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
940 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
941 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
942 break;
943
944 case CPUMDUMPTYPE_DEFAULT:
945 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
946 {
947 pHlp->pfnPrintf(pHlp,
948 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
949 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
950 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
951 "%sr14=%016RX64 %sr15=%016RX64\n"
952 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
953 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
954 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
955 ,
956 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
957 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
958 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
959 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
960 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
961 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
962 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
963 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
964 }
965 else
966 pHlp->pfnPrintf(pHlp,
967 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
968 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
969 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
970 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
971 ,
972 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
973 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
974 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
975 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
976 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
977 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
978 break;
979
980 case CPUMDUMPTYPE_VERBOSE:
981 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
982 {
983 pHlp->pfnPrintf(pHlp,
984 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
985 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
986 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
987 "%sr14=%016RX64 %sr15=%016RX64\n"
988 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
989 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
990 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
991 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
992 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
993 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
994 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
995 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
996 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
997 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
998 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
999 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1000 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1001 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1002 ,
1003 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1004 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1005 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1006 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1007 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1008 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1009 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1010 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1011 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1012 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1013 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1014 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1015 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1016 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1017 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1018 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1019 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1020 }
1021 else
1022 pHlp->pfnPrintf(pHlp,
1023 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1024 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1025 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1026 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1027 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1028 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1029 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1030 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1031 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1032 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1033 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1034 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1035 ,
1036 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1037 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1038 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
1039 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1040 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
1041 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1042 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1043 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1044 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1045 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1046 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1047 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1048
1049 pHlp->pfnPrintf(pHlp,
1050 "FPU:\n"
1051 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1052 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1053 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1054 ,
1055 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1056 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1057 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1058 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1059
1060
1061 pHlp->pfnPrintf(pHlp,
1062 "MSR:\n"
1063 "%sEFER =%016RX64\n"
1064 "%sPAT =%016RX64\n"
1065 "%sSTAR =%016RX64\n"
1066 "%sCSTAR =%016RX64\n"
1067 "%sLSTAR =%016RX64\n"
1068 "%sSFMASK =%016RX64\n"
1069 "%sKERNELGSBASE =%016RX64\n",
1070 pszPrefix, pCtx->msrEFER,
1071 pszPrefix, pCtx->msrPAT,
1072 pszPrefix, pCtx->msrSTAR,
1073 pszPrefix, pCtx->msrCSTAR,
1074 pszPrefix, pCtx->msrLSTAR,
1075 pszPrefix, pCtx->msrSFMASK,
1076 pszPrefix, pCtx->msrKERNELGSBASE);
1077
1078 break;
1079 }
1080}
1081
1082
1083/**
1084 * Display all cpu states and any other cpum info.
1085 *
1086 * @param pVM VM Handle.
1087 * @param pHlp The info helper functions.
1088 * @param pszArgs Arguments, ignored.
1089 */
1090static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1091{
1092 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1093 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1094 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1095 cpumR3InfoHost(pVM, pHlp, pszArgs);
1096}
1097
1098
1099/**
1100 * Parses the info argument.
1101 *
1102 * The argument starts with 'verbose', 'terse' or 'default' and then
1103 * continues with the comment string.
1104 *
1105 * @param pszArgs The pointer to the argument string.
1106 * @param penmType Where to store the dump type request.
1107 * @param ppszComment Where to store the pointer to the comment string.
1108 */
1109static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1110{
1111 if (!pszArgs)
1112 {
1113 *penmType = CPUMDUMPTYPE_DEFAULT;
1114 *ppszComment = "";
1115 }
1116 else
1117 {
1118 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1119 {
1120 pszArgs += 5;
1121 *penmType = CPUMDUMPTYPE_VERBOSE;
1122 }
1123 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1124 {
1125 pszArgs += 5;
1126 *penmType = CPUMDUMPTYPE_TERSE;
1127 }
1128 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1129 {
1130 pszArgs += 7;
1131 *penmType = CPUMDUMPTYPE_DEFAULT;
1132 }
1133 else
1134 *penmType = CPUMDUMPTYPE_DEFAULT;
1135 *ppszComment = RTStrStripL(pszArgs);
1136 }
1137}
1138
1139
1140/**
1141 * Display the guest cpu state.
1142 *
1143 * @param pVM VM Handle.
1144 * @param pHlp The info helper functions.
1145 * @param pszArgs Arguments, ignored.
1146 */
1147static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1148{
1149 CPUMDUMPTYPE enmType;
1150 const char *pszComment;
1151 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1152 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1153 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1154}
1155
1156/**
1157 * Display the current guest instruction
1158 *
1159 * @param pVM VM Handle.
1160 * @param pHlp The info helper functions.
1161 * @param pszArgs Arguments, ignored.
1162 */
1163static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1164{
1165 char szInstruction[256];
1166 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1167 if (VBOX_SUCCESS(rc))
1168 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1169}
1170
1171
1172/**
1173 * Display the hypervisor cpu state.
1174 *
1175 * @param pVM VM Handle.
1176 * @param pHlp The info helper functions.
1177 * @param pszArgs Arguments, ignored.
1178 */
1179static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1180{
1181 CPUMDUMPTYPE enmType;
1182 const char *pszComment;
1183 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1184 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1185 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1186 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1187}
1188
1189
1190/**
1191 * Display the host cpu state.
1192 *
1193 * @param pVM VM Handle.
1194 * @param pHlp The info helper functions.
1195 * @param pszArgs Arguments, ignored.
1196 */
1197static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1198{
1199 CPUMDUMPTYPE enmType;
1200 const char *pszComment;
1201 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1202 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1203
1204 /*
1205 * Format the EFLAGS.
1206 */
1207 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1208#if HC_ARCH_BITS == 32
1209 uint32_t efl = pCtx->eflags.u32;
1210#else
1211 uint64_t efl = pCtx->rflags;
1212#endif
1213 char szEFlags[80];
1214 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1215
1216 /*
1217 * Format the registers.
1218 */
1219#if HC_ARCH_BITS == 32
1220# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1221 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1222# endif
1223 {
1224 pHlp->pfnPrintf(pHlp,
1225 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1226 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1227 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1228 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1229 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1230 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1231 ,
1232 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1233 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1234 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1235 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1236 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1237 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1238 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1239 }
1240# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1241 else
1242# endif
1243#endif
1244#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1245 {
1246 pHlp->pfnPrintf(pHlp,
1247 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1248 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1249 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1250 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1251 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1252 "r14=%016RX64 r15=%016RX64\n"
1253 "iopl=%d %31s\n"
1254 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1255 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1256 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1257 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1258 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1259 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1260 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1261 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1262 ,
1263 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1264 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1265 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1266 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1267 pCtx->r11, pCtx->r12, pCtx->r13,
1268 pCtx->r14, pCtx->r15,
1269 X86_EFL_GET_IOPL(efl), szEFlags,
1270 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1271 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1272 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1273 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1274 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1275 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1276 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1277 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1278 }
1279#endif
1280}
1281
1282
1283/**
1284 * Get L1 cache / TLS associativity.
1285 */
1286static const char *getCacheAss(unsigned u, char *pszBuf)
1287{
1288 if (u == 0)
1289 return "res0 ";
1290 if (u == 1)
1291 return "direct";
1292 if (u >= 256)
1293 return "???";
1294
1295 RTStrPrintf(pszBuf, 16, "%d way", u);
1296 return pszBuf;
1297}
1298
1299
1300/**
1301 * Get L2 cache soociativity.
1302 */
1303const char *getL2CacheAss(unsigned u)
1304{
1305 switch (u)
1306 {
1307 case 0: return "off ";
1308 case 1: return "direct";
1309 case 2: return "2 way ";
1310 case 3: return "res3 ";
1311 case 4: return "4 way ";
1312 case 5: return "res5 ";
1313 case 6: return "8 way "; case 7: return "res7 ";
1314 case 8: return "16 way";
1315 case 9: return "res9 ";
1316 case 10: return "res10 ";
1317 case 11: return "res11 ";
1318 case 12: return "res12 ";
1319 case 13: return "res13 ";
1320 case 14: return "res14 ";
1321 case 15: return "fully ";
1322 default:
1323 return "????";
1324 }
1325}
1326
1327
1328/**
1329 * Display the guest CpuId leaves.
1330 *
1331 * @param pVM VM Handle.
1332 * @param pHlp The info helper functions.
1333 * @param pszArgs "terse", "default" or "verbose".
1334 */
1335static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1336{
1337 /*
1338 * Parse the argument.
1339 */
1340 unsigned iVerbosity = 1;
1341 if (pszArgs)
1342 {
1343 pszArgs = RTStrStripL(pszArgs);
1344 if (!strcmp(pszArgs, "terse"))
1345 iVerbosity--;
1346 else if (!strcmp(pszArgs, "verbose"))
1347 iVerbosity++;
1348 }
1349
1350 /*
1351 * Start cracking.
1352 */
1353 CPUMCPUID Host;
1354 CPUMCPUID Guest;
1355 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1356
1357 pHlp->pfnPrintf(pHlp,
1358 " RAW Standard CPUIDs\n"
1359 " Function eax ebx ecx edx\n");
1360 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1361 {
1362 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1363 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1364
1365 pHlp->pfnPrintf(pHlp,
1366 "Gst: %08x %08x %08x %08x %08x%s\n"
1367 "Hst: %08x %08x %08x %08x\n",
1368 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1369 i <= cStdMax ? "" : "*",
1370 Host.eax, Host.ebx, Host.ecx, Host.edx);
1371 }
1372
1373 /*
1374 * If verbose, decode it.
1375 */
1376 if (iVerbosity)
1377 {
1378 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1379 pHlp->pfnPrintf(pHlp,
1380 "Name: %.04s%.04s%.04s\n"
1381 "Supports: 0-%x\n",
1382 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1383 }
1384
1385 /*
1386 * Get Features.
1387 */
1388 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1389 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1390 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1391 if (cStdMax >= 1 && iVerbosity)
1392 {
1393 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1394 uint32_t uEAX = Guest.eax;
1395
1396 pHlp->pfnPrintf(pHlp,
1397 "Family: %d \tExtended: %d \tEffective: %d\n"
1398 "Model: %d \tExtended: %d \tEffective: %d\n"
1399 "Stepping: %d\n"
1400 "APIC ID: %#04x\n"
1401 "Logical CPUs: %d\n"
1402 "CLFLUSH Size: %d\n"
1403 "Brand ID: %#04x\n",
1404 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1405 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1406 ASMGetCpuStepping(uEAX),
1407 (Guest.ebx >> 24) & 0xff,
1408 (Guest.ebx >> 16) & 0xff,
1409 (Guest.ebx >> 8) & 0xff,
1410 (Guest.ebx >> 0) & 0xff);
1411 if (iVerbosity == 1)
1412 {
1413 uint32_t uEDX = Guest.edx;
1414 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1415 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1416 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1417 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1418 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1419 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1420 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1421 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1422 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1423 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1424 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1425 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1426 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1427 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1428 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1429 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1430 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1431 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1432 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1433 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1434 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1435 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1436 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1437 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1438 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1439 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1440 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1441 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1442 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1443 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1444 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1445 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1446 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1447 pHlp->pfnPrintf(pHlp, "\n");
1448
1449 uint32_t uECX = Guest.ecx;
1450 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1451 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1452 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1453 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1454 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1455 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1456 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1457 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1458 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1459 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1460 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1461 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1462 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1463 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1464 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1465 for (unsigned iBit = 14; iBit < 32; iBit++)
1466 if (uECX & RT_BIT(iBit))
1467 pHlp->pfnPrintf(pHlp, " %d", iBit);
1468 pHlp->pfnPrintf(pHlp, "\n");
1469 }
1470 else
1471 {
1472 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1473
1474 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1475 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1476 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1477 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1478
1479 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1480 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1481 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1482 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1483 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1484 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1485 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1486 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1487 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1488 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1489 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1490 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1491 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1492 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1493 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1494 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1495 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1496 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1497 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1498 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1499 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1500 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1501 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1502 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1503 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1504 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1505 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1506 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1507 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1508 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1509 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1510 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1511 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1512
1513 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1514 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1515 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1516 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1517 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1518 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1519 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1520 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1521 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1522 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1523 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1524 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1525 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1526 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1527 }
1528 }
1529 if (cStdMax >= 2 && iVerbosity)
1530 {
1531 /** @todo */
1532 }
1533
1534 /*
1535 * Extended.
1536 * Implemented after AMD specs.
1537 */
1538 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1539
1540 pHlp->pfnPrintf(pHlp,
1541 "\n"
1542 " RAW Extended CPUIDs\n"
1543 " Function eax ebx ecx edx\n");
1544 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1545 {
1546 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1547 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1548
1549 pHlp->pfnPrintf(pHlp,
1550 "Gst: %08x %08x %08x %08x %08x%s\n"
1551 "Hst: %08x %08x %08x %08x\n",
1552 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1553 i <= cExtMax ? "" : "*",
1554 Host.eax, Host.ebx, Host.ecx, Host.edx);
1555 }
1556
1557 /*
1558 * Understandable output
1559 */
1560 if (iVerbosity && cExtMax >= 0)
1561 {
1562 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1563 pHlp->pfnPrintf(pHlp,
1564 "Ext Name: %.4s%.4s%.4s\n"
1565 "Ext Supports: 0x80000000-%#010x\n",
1566 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1567 }
1568
1569 if (iVerbosity && cExtMax >= 1)
1570 {
1571 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1572 uint32_t uEAX = Guest.eax;
1573 pHlp->pfnPrintf(pHlp,
1574 "Family: %d \tExtended: %d \tEffective: %d\n"
1575 "Model: %d \tExtended: %d \tEffective: %d\n"
1576 "Stepping: %d\n"
1577 "Brand ID: %#05x\n",
1578 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1579 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1580 ASMGetCpuStepping(uEAX),
1581 Guest.ebx & 0xfff);
1582
1583 if (iVerbosity == 1)
1584 {
1585 uint32_t uEDX = Guest.edx;
1586 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1587 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1588 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1589 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1590 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1591 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1592 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1593 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1594 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1595 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1596 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1597 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1598 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1599 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1600 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1601 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1602 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1603 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1604 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1605 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1606 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1607 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1608 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1609 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1610 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1611 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1612 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1613 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1614 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1615 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1616 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1617 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1618 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1619 pHlp->pfnPrintf(pHlp, "\n");
1620
1621 uint32_t uECX = Guest.ecx;
1622 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1623 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1624 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1625 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1626 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1627 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1628 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1629 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1630 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1631 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1632 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1633 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1634 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1635 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1636 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1637 for (unsigned iBit = 5; iBit < 32; iBit++)
1638 if (uECX & RT_BIT(iBit))
1639 pHlp->pfnPrintf(pHlp, " %d", iBit);
1640 pHlp->pfnPrintf(pHlp, "\n");
1641 }
1642 else
1643 {
1644 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1645
1646 uint32_t uEdxGst = Guest.edx;
1647 uint32_t uEdxHst = Host.edx;
1648 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1649 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1650 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1651 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1652 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1653 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1654 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1655 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1656 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1657 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1658 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1659 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1660 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1661 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1662 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1663 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1664 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1665 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1666 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1667 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1668 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1669 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1670 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1671 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1672 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1673 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1674 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1675 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1676 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1677 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1678 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1679 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1680 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1681
1682 uint32_t uEcxGst = Guest.ecx;
1683 uint32_t uEcxHst = Host.ecx;
1684 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1685 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1686 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1687 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1688 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1689 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1690 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1691 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1692 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1693 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1694 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1695 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1696 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1697 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1698 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1699 }
1700 }
1701
1702 if (iVerbosity && cExtMax >= 2)
1703 {
1704 char szString[4*4*3+1] = {0};
1705 uint32_t *pu32 = (uint32_t *)szString;
1706 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1707 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1708 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1709 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1710 if (cExtMax >= 3)
1711 {
1712 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1713 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1714 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1715 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1716 }
1717 if (cExtMax >= 4)
1718 {
1719 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1720 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1721 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1722 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1723 }
1724 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1725 }
1726
1727 if (iVerbosity && cExtMax >= 5)
1728 {
1729 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1730 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1731 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1732 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1733 char sz1[32];
1734 char sz2[32];
1735
1736 pHlp->pfnPrintf(pHlp,
1737 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1738 "TLB 2/4M Data: %s %3d entries\n",
1739 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1740 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1741 pHlp->pfnPrintf(pHlp,
1742 "TLB 4K Instr/Uni: %s %3d entries\n"
1743 "TLB 4K Data: %s %3d entries\n",
1744 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1745 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1746 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1747 "L1 Instr Cache Lines Per Tag: %d\n"
1748 "L1 Instr Cache Associativity: %s\n"
1749 "L1 Instr Cache Size: %d KB\n",
1750 (uEDX >> 0) & 0xff,
1751 (uEDX >> 8) & 0xff,
1752 getCacheAss((uEDX >> 16) & 0xff, sz1),
1753 (uEDX >> 24) & 0xff);
1754 pHlp->pfnPrintf(pHlp,
1755 "L1 Data Cache Line Size: %d bytes\n"
1756 "L1 Data Cache Lines Per Tag: %d\n"
1757 "L1 Data Cache Associativity: %s\n"
1758 "L1 Data Cache Size: %d KB\n",
1759 (uECX >> 0) & 0xff,
1760 (uECX >> 8) & 0xff,
1761 getCacheAss((uECX >> 16) & 0xff, sz1),
1762 (uECX >> 24) & 0xff);
1763 }
1764
1765 if (iVerbosity && cExtMax >= 6)
1766 {
1767 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1768 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1769 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1770
1771 pHlp->pfnPrintf(pHlp,
1772 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1773 "L2 TLB 2/4M Data: %s %4d entries\n",
1774 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1775 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1776 pHlp->pfnPrintf(pHlp,
1777 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1778 "L2 TLB 4K Data: %s %4d entries\n",
1779 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1780 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1781 pHlp->pfnPrintf(pHlp,
1782 "L2 Cache Line Size: %d bytes\n"
1783 "L2 Cache Lines Per Tag: %d\n"
1784 "L2 Cache Associativity: %s\n"
1785 "L2 Cache Size: %d KB\n",
1786 (uEDX >> 0) & 0xff,
1787 (uEDX >> 8) & 0xf,
1788 getL2CacheAss((uEDX >> 12) & 0xf),
1789 (uEDX >> 16) & 0xffff);
1790 }
1791
1792 if (iVerbosity && cExtMax >= 7)
1793 {
1794 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1795
1796 pHlp->pfnPrintf(pHlp, "APM Features: ");
1797 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1798 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1799 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1800 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1801 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1802 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1803 for (unsigned iBit = 6; iBit < 32; iBit++)
1804 if (uEDX & RT_BIT(iBit))
1805 pHlp->pfnPrintf(pHlp, " %d", iBit);
1806 pHlp->pfnPrintf(pHlp, "\n");
1807 }
1808
1809 if (iVerbosity && cExtMax >= 8)
1810 {
1811 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1812 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1813
1814 pHlp->pfnPrintf(pHlp,
1815 "Physical Address Width: %d bits\n"
1816 "Virtual Address Width: %d bits\n",
1817 (uEAX >> 0) & 0xff,
1818 (uEAX >> 8) & 0xff);
1819 pHlp->pfnPrintf(pHlp,
1820 "Physical Core Count: %d\n",
1821 (uECX >> 0) & 0xff);
1822 }
1823
1824
1825 /*
1826 * Centaur.
1827 */
1828 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1829
1830 pHlp->pfnPrintf(pHlp,
1831 "\n"
1832 " RAW Centaur CPUIDs\n"
1833 " Function eax ebx ecx edx\n");
1834 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1835 {
1836 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1837 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1838
1839 pHlp->pfnPrintf(pHlp,
1840 "Gst: %08x %08x %08x %08x %08x%s\n"
1841 "Hst: %08x %08x %08x %08x\n",
1842 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1843 i <= cCentaurMax ? "" : "*",
1844 Host.eax, Host.ebx, Host.ecx, Host.edx);
1845 }
1846
1847 /*
1848 * Understandable output
1849 */
1850 if (iVerbosity && cCentaurMax >= 0)
1851 {
1852 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1853 pHlp->pfnPrintf(pHlp,
1854 "Centaur Supports: 0xc0000000-%#010x\n",
1855 Guest.eax);
1856 }
1857
1858 if (iVerbosity && cCentaurMax >= 1)
1859 {
1860 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1861 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1862 uint32_t uEdxHst = Host.edx;
1863
1864 if (iVerbosity == 1)
1865 {
1866 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1867 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1868 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1869 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1870 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1871 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1872 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1873 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1874 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1875 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1876 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1877 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1878 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1879 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1880 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1881 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1882 for (unsigned iBit = 14; iBit < 32; iBit++)
1883 if (uEdxGst & RT_BIT(iBit))
1884 pHlp->pfnPrintf(pHlp, " %d", iBit);
1885 pHlp->pfnPrintf(pHlp, "\n");
1886 }
1887 else
1888 {
1889 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1890 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1891 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1892 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1893 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1894 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1895 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1896 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1897 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1898 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1899 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1900 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1901 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1902 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1903 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1904 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1905 for (unsigned iBit = 14; iBit < 32; iBit++)
1906 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1907 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1908 pHlp->pfnPrintf(pHlp, "\n");
1909 }
1910 }
1911}
1912
1913
1914/**
1915 * Structure used when disassembling and instructions in DBGF.
1916 * This is used so the reader function can get the stuff it needs.
1917 */
1918typedef struct CPUMDISASSTATE
1919{
1920 /** Pointer to the CPU structure. */
1921 PDISCPUSTATE pCpu;
1922 /** The VM handle. */
1923 PVM pVM;
1924 /** Pointer to the first byte in the segemnt. */
1925 RTGCUINTPTR GCPtrSegBase;
1926 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1927 RTGCUINTPTR GCPtrSegEnd;
1928 /** The size of the segment minus 1. */
1929 RTGCUINTPTR cbSegLimit;
1930 /** Pointer to the current page - HC Ptr. */
1931 void const *pvPageHC;
1932 /** Pointer to the current page - GC Ptr. */
1933 RTGCPTR pvPageGC;
1934 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1935 PGMPAGEMAPLOCK PageMapLock;
1936 /** Whether the PageMapLock is valid or not. */
1937 bool fLocked;
1938 /** 64 bits mode or not. */
1939 bool f64Bits;
1940} CPUMDISASSTATE, *PCPUMDISASSTATE;
1941
1942
1943/**
1944 * Instruction reader.
1945 *
1946 * @returns VBox status code.
1947 * @param PtrSrc Address to read from.
1948 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1949 * @param pu8Dst Where to store the bytes.
1950 * @param cbRead Number of bytes to read.
1951 * @param uDisCpu Pointer to the disassembler cpu state.
1952 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1953 */
1954static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1955{
1956 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1957 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1958 Assert(cbRead > 0);
1959 for (;;)
1960 {
1961 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1962
1963 /* Need to update the page translation? */
1964 if ( !pState->pvPageHC
1965 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1966 {
1967 int rc = VINF_SUCCESS;
1968
1969 /* translate the address */
1970 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1971 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1972 {
1973 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1974 if (!pState->pvPageHC)
1975 rc = VERR_INVALID_POINTER;
1976 }
1977 else
1978 {
1979 /* Release mapping lock previously acquired. */
1980 if (pState->fLocked)
1981 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1982 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1983 pState->fLocked = RT_SUCCESS_NP(rc);
1984 }
1985 if (VBOX_FAILURE(rc))
1986 {
1987 pState->pvPageHC = NULL;
1988 return rc;
1989 }
1990 }
1991
1992 /* check the segemnt limit */
1993 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
1994 return VERR_OUT_OF_SELECTOR_BOUNDS;
1995
1996 /* calc how much we can read */
1997 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1998 if (!pState->f64Bits)
1999 {
2000 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2001 if (cb > cbSeg && cbSeg)
2002 cb = cbSeg;
2003 }
2004 if (cb > cbRead)
2005 cb = cbRead;
2006
2007 /* read and advance */
2008 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2009 cbRead -= cb;
2010 if (!cbRead)
2011 return VINF_SUCCESS;
2012 pu8Dst += cb;
2013 PtrSrc += cb;
2014 }
2015}
2016
2017
2018/**
2019 * Disassemble an instruction and return the information in the provided structure.
2020 *
2021 * @returns VBox status code.
2022 * @param pVM VM Handle
2023 * @param pCtx CPU context
2024 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2025 * @param pCpu Disassembly state
2026 * @param pszPrefix String prefix for logging (debug only)
2027 *
2028 */
2029CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2030{
2031 CPUMDISASSTATE State;
2032 int rc;
2033
2034 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2035 State.pCpu = pCpu;
2036 State.pvPageGC = 0;
2037 State.pvPageHC = NULL;
2038 State.pVM = pVM;
2039 State.fLocked = false;
2040 State.f64Bits = false;
2041
2042 /*
2043 * Get selector information.
2044 */
2045 if ( (pCtx->cr0 & X86_CR0_PE)
2046 && pCtx->eflags.Bits.u1VM == 0)
2047 {
2048 if (CPUMAreHiddenSelRegsValid(pVM))
2049 {
2050 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2051 State.GCPtrSegBase = pCtx->csHid.u64Base;
2052 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2053 State.cbSegLimit = pCtx->csHid.u32Limit;
2054 pCpu->mode = (State.f64Bits)
2055 ? CPUMODE_64BIT
2056 : pCtx->csHid.Attr.n.u1DefBig
2057 ? CPUMODE_32BIT
2058 : CPUMODE_16BIT;
2059 }
2060 else
2061 {
2062 SELMSELINFO SelInfo;
2063
2064 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2065 if (!VBOX_SUCCESS(rc))
2066 {
2067 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2068 return rc;
2069 }
2070
2071 /*
2072 * Validate the selector.
2073 */
2074 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2075 if (!VBOX_SUCCESS(rc))
2076 {
2077 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2078 return rc;
2079 }
2080 State.GCPtrSegBase = SelInfo.GCPtrBase;
2081 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2082 State.cbSegLimit = SelInfo.cbLimit;
2083 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2084 }
2085 }
2086 else
2087 {
2088 /* real or V86 mode */
2089 pCpu->mode = CPUMODE_16BIT;
2090 State.GCPtrSegBase = pCtx->cs * 16;
2091 State.GCPtrSegEnd = 0xFFFFFFFF;
2092 State.cbSegLimit = 0xFFFFFFFF;
2093 }
2094
2095 /*
2096 * Disassemble the instruction.
2097 */
2098 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2099 pCpu->apvUserData[0] = &State;
2100
2101 uint32_t cbInstr;
2102#ifndef LOG_ENABLED
2103 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2104 if (VBOX_SUCCESS(rc))
2105 {
2106#else
2107 char szOutput[160];
2108 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2109 if (VBOX_SUCCESS(rc))
2110 {
2111 /* log it */
2112 if (pszPrefix)
2113 Log(("%s: %s", pszPrefix, szOutput));
2114 else
2115 Log(("%s", szOutput));
2116#endif
2117 rc = VINF_SUCCESS;
2118 }
2119 else
2120 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2121
2122 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2123 if (State.fLocked)
2124 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2125
2126 return rc;
2127}
2128
2129#ifdef DEBUG
2130
2131/**
2132 * Disassemble an instruction and dump it to the log
2133 *
2134 * @returns VBox status code.
2135 * @param pVM VM Handle
2136 * @param pCtx CPU context
2137 * @param pc GC instruction pointer
2138 * @param prefix String prefix for logging
2139 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2140 *
2141 */
2142CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2143{
2144 DISCPUSTATE cpu;
2145
2146 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2147}
2148
2149/**
2150 * Disassemble an instruction and dump it to the log
2151 *
2152 * @returns VBox status code.
2153 * @param pVM VM Handle
2154 * @param pCtx CPU context
2155 * @param pc GC instruction pointer
2156 * @param prefix String prefix for logging
2157 * @param nrInstructions
2158 *
2159 */
2160CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2161{
2162 for(int i=0;i<nrInstructions;i++)
2163 {
2164 DISCPUSTATE cpu;
2165
2166 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2167 pc += cpu.opsize;
2168 }
2169}
2170
2171#endif /* DEBUG */
2172
2173#ifdef DEBUG
2174/**
2175 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2176 *
2177 * @internal
2178 */
2179CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2180{
2181 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2182}
2183#endif /* DEBUG */
2184
2185
2186/**
2187 * API for controlling a few of the CPU features found in CR4.
2188 *
2189 * Currently only X86_CR4_TSD is accepted as input.
2190 *
2191 * @returns VBox status code.
2192 *
2193 * @param pVM The VM handle.
2194 * @param fOr The CR4 OR mask.
2195 * @param fAnd The CR4 AND mask.
2196 */
2197CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2198{
2199 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2200 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2201
2202 pVM->cpum.s.CR4.OrMask &= fAnd;
2203 pVM->cpum.s.CR4.OrMask |= fOr;
2204
2205 return VINF_SUCCESS;
2206}
2207
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