VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 11705

Last change on this file since 11705 was 11705, checked in by vboxsync, 16 years ago

Moved #3026 'fix'.
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1/* $Id: CPUM.cpp 11705 2008-08-27 14:53:58Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/pdm.h>
43#include <VBox/mm.h>
44#include <VBox/selm.h>
45#include <VBox/dbgf.h>
46#include <VBox/patm.h>
47#include <VBox/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm.h>
57#include <iprt/string.h>
58#include <iprt/mp.h>
59#include <iprt/cpuset.h>
60
61
62/*******************************************************************************
63* Defined Constants And Macros *
64*******************************************************************************/
65/** The saved state version. */
66#define CPUM_SAVED_STATE_VERSION 8
67
68
69/*******************************************************************************
70* Structures and Typedefs *
71*******************************************************************************/
72
73/**
74 * What kind of cpu info dump to perform.
75 */
76typedef enum CPUMDUMPTYPE
77{
78 CPUMDUMPTYPE_TERSE,
79 CPUMDUMPTYPE_DEFAULT,
80 CPUMDUMPTYPE_VERBOSE
81
82} CPUMDUMPTYPE;
83/** Pointer to a cpu info dump type. */
84typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static int cpumR3CpuIdInit(PVM pVM);
90static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
91static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
92static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98
99
100/**
101 * Initializes the CPUM.
102 *
103 * @returns VBox status code.
104 * @param pVM The VM to operate on.
105 */
106CPUMR3DECL(int) CPUMR3Init(PVM pVM)
107{
108 LogFlow(("CPUMR3Init\n"));
109
110 /*
111 * Assert alignment and sizes.
112 */
113 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
114 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
115
116 /*
117 * Setup any fixed pointers and offsets.
118 */
119 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
120 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
121 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
122 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
123
124 /* Hidden selector registers are invalid by default. */
125 pVM->cpum.s.fValidHiddenSelRegs = false;
126
127 /*
128 * Check that the CPU supports the minimum features we require.
129 */
130 /** @todo check the contract! */
131 if (!ASMHasCpuId())
132 {
133 Log(("The CPU doesn't support CPUID!\n"));
134 return VERR_UNSUPPORTED_CPU;
135 }
136 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
137 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
138
139 /* Setup the CR4 AND and OR masks used in the switcher */
140 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
141 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
142 {
143 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
144 /* No FXSAVE implies no SSE */
145 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
146 pVM->cpum.s.CR4.OrMask = 0;
147 }
148 else
149 {
150 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
151 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
152 }
153
154 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
155 {
156 Log(("The CPU doesn't support MMX!\n"));
157 return VERR_UNSUPPORTED_CPU;
158 }
159 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
160 {
161 Log(("The CPU doesn't support TSC!\n"));
162 return VERR_UNSUPPORTED_CPU;
163 }
164 /* Bogus on AMD? */
165 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
166 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
167
168 /*
169 * Setup hypervisor startup values.
170 */
171
172 /*
173 * Register saved state data item.
174 */
175 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
176 NULL, cpumR3Save, NULL,
177 NULL, cpumR3Load, NULL);
178 if (VBOX_FAILURE(rc))
179 return rc;
180
181 /* Query the CPU manufacturer. */
182 uint32_t uEAX, uEBX, uECX, uEDX;
183 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
184 if ( uEAX >= 1
185 && uEBX == X86_CPUID_VENDOR_AMD_EBX
186 && uECX == X86_CPUID_VENDOR_AMD_ECX
187 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
188 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
189 else if ( uEAX >= 1
190 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
191 && uECX == X86_CPUID_VENDOR_INTEL_ECX
192 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
193 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
194 else /** @todo Via */
195 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
196
197 /*
198 * Register info handlers.
199 */
200 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
201 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
202 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
203 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
204 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
205 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
206
207 /*
208 * Initialize the Guest CPU state.
209 */
210 rc = cpumR3CpuIdInit(pVM);
211 if (VBOX_FAILURE(rc))
212 return rc;
213 CPUMR3Reset(pVM);
214 return VINF_SUCCESS;
215}
216
217
218/**
219 * Initializes the emulated CPU's cpuid information.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM to operate on.
223 */
224static int cpumR3CpuIdInit(PVM pVM)
225{
226 PCPUM pCPUM = &pVM->cpum.s;
227 uint32_t i;
228
229 /*
230 * Get the host CPUIDs.
231 */
232 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
233 ASMCpuId_Idx_ECX(i, 0,
234 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
235 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
236 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
237 ASMCpuId(0x80000000 + i,
238 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
239 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
240 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
241 ASMCpuId(0xc0000000 + i,
242 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
243 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
244
245
246 /*
247 * Only report features we can support.
248 */
249 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
250 | X86_CPUID_FEATURE_EDX_VME
251 | X86_CPUID_FEATURE_EDX_DE
252 | X86_CPUID_FEATURE_EDX_PSE
253 | X86_CPUID_FEATURE_EDX_TSC
254 | X86_CPUID_FEATURE_EDX_MSR
255 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
256 | X86_CPUID_FEATURE_EDX_MCE
257 | X86_CPUID_FEATURE_EDX_CX8
258 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
259 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
260 //| X86_CPUID_FEATURE_EDX_SEP
261 | X86_CPUID_FEATURE_EDX_MTRR
262 | X86_CPUID_FEATURE_EDX_PGE
263 | X86_CPUID_FEATURE_EDX_MCA
264 | X86_CPUID_FEATURE_EDX_CMOV
265 | X86_CPUID_FEATURE_EDX_PAT
266 | X86_CPUID_FEATURE_EDX_PSE36
267 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
268 | X86_CPUID_FEATURE_EDX_CLFSH
269 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
270 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
271 | X86_CPUID_FEATURE_EDX_MMX
272 | X86_CPUID_FEATURE_EDX_FXSR
273 | X86_CPUID_FEATURE_EDX_SSE
274 | X86_CPUID_FEATURE_EDX_SSE2
275 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
276 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
277 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
278 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
279 | 0;
280 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
281 | X86_CPUID_FEATURE_ECX_MONITOR
282 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
283 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
284 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
285 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
286 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
287 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
288 //| X86_CPUID_FEATURE_ECX_CX16
289 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
291 /* ECX Bit 23 - POPCOUNT instruction. */
292 //| X86_CPUID_FEATURE_ECX_POPCOUNT
293 | 0;
294
295 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
296 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
297 | X86_CPUID_AMD_FEATURE_EDX_VME
298 | X86_CPUID_AMD_FEATURE_EDX_DE
299 | X86_CPUID_AMD_FEATURE_EDX_PSE
300 | X86_CPUID_AMD_FEATURE_EDX_TSC
301 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
302 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
303 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
304 | X86_CPUID_AMD_FEATURE_EDX_CX8
305 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
306 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
307 //| X86_CPUID_AMD_FEATURE_EDX_SEP
308 | X86_CPUID_AMD_FEATURE_EDX_MTRR
309 | X86_CPUID_AMD_FEATURE_EDX_PGE
310 | X86_CPUID_AMD_FEATURE_EDX_MCA
311 | X86_CPUID_AMD_FEATURE_EDX_CMOV
312 | X86_CPUID_AMD_FEATURE_EDX_PAT
313 | X86_CPUID_AMD_FEATURE_EDX_PSE36
314 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
315 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
316 | X86_CPUID_AMD_FEATURE_EDX_MMX
317 | X86_CPUID_AMD_FEATURE_EDX_FXSR
318 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
319 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
320 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
321 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
322 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
323 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
324 | 0;
325 pCPUM->aGuestCpuIdExt[1].ecx &= 0
326 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
327 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
328 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
329 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
330 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
331 //| X86_CPUID_AMD_FEATURE_ECX_ABM
332 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
333 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
334 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
335 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
336 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
337 //| X86_CPUID_AMD_FEATURE_ECX_WDT
338 | 0;
339
340 /*
341 * Hide HTT, multicode, SMP, whatever.
342 * (APIC-ID := 0 and #LogCpus := 0)
343 */
344 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
345
346 /* Cpuid 2:
347 * Intel: Cache and TLB information
348 * AMD: Reserved
349 * Safe to expose
350 */
351
352 /* Cpuid 3:
353 * Intel: EAX, EBX - reserved
354 * ECX, EDX - Processor Serial Number if available, otherwise reserved
355 * AMD: Reserved
356 * Safe to expose
357 */
358 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
359 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
360
361 /* Cpuid 4:
362 * Intel: Deterministic Cache Parameters Leaf
363 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
364 * AMD: Reserved
365 * Safe to expose, except for EAX:
366 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
367 * Bits 31-26: Maximum number of processor cores in this physical package**
368 */
369 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
370 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
371
372 /* Cpuid 5: Monitor/mwait Leaf
373 * Intel: ECX, EDX - reserved
374 * EAX, EBX - Smallest and largest monitor line size
375 * AMD: EDX - reserved
376 * EAX, EBX - Smallest and largest monitor line size
377 * ECX - extensions (ignored for now)
378 * Safe to expose
379 */
380 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
381 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
382
383 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
384
385 /*
386 * Determine the default.
387 *
388 * Intel returns values of the highest standard function, while AMD
389 * returns zeros. VIA on the other hand seems to returning nothing or
390 * perhaps some random garbage, we don't try to duplicate this behavior.
391 */
392 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
393 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
394 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
395
396 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
397 * Safe to pass on to the guest.
398 *
399 * Intel: 0x800000005 reserved
400 * 0x800000006 L2 cache information
401 * AMD: 0x800000005 L1 cache information
402 * 0x800000006 L2/L3 cache information
403 */
404
405 /* Cpuid 0x800000007:
406 * AMD: EAX, EBX, ECX - reserved
407 * EDX: Advanced Power Management Information
408 * Intel: Reserved
409 */
410 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
411 {
412 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
413
414 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
415
416 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
417 {
418 /* Only expose the TSC invariant capability bit to the guest. */
419 pCPUM->aGuestCpuIdExt[7].edx &= 0
420 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
421 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
422 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
423 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
424 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
425 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
426 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
427 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
428 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
429 | 0;
430 }
431 else
432 pCPUM->aGuestCpuIdExt[7].edx = 0;
433 }
434
435 /* Cpuid 0x800000008:
436 * AMD: EBX, EDX - reserved
437 * EAX: Virtual/Physical address Size
438 * ECX: Number of cores + APICIdCoreIdSize
439 * Intel: EAX: Virtual/Physical address Size
440 * EBX, ECX, EDX - reserved
441 */
442 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
443 {
444 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
445 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
446 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
447 * NC (0-7) Number of cores; 0 equals 1 core */
448 pCPUM->aGuestCpuIdExt[8].ecx = 0;
449 }
450
451 /*
452 * Limit it the number of entries and fill the remaining with the defaults.
453 *
454 * The limits are masking off stuff about power saving and similar, this
455 * is perhaps a bit crudely done as there is probably some relatively harmless
456 * info too in these leaves (like words about having a constant TSC).
457 */
458#if 0
459 /** @todo NT4 installation regression - investigate */
460 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
461 pCPUM->aGuestCpuIdStd[0].eax = 5;
462#else
463 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
464 pCPUM->aGuestCpuIdStd[0].eax = 2;
465#endif
466 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
467 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
468
469 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
470 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
471 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
472 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
473 : 0;
474 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
475 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
476
477 /*
478 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
479 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
480 * We currently don't support more than 1 processor.
481 */
482 pCPUM->aGuestCpuIdStd[4].eax = 0;
483
484 /*
485 * Centaur stuff (VIA).
486 *
487 * The important part here (we think) is to make sure the 0xc0000000
488 * function returns 0xc0000001. As for the features, we don't currently
489 * let on about any of those... 0xc0000002 seems to be some
490 * temperature/hz/++ stuff, include it as well (static).
491 */
492 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
493 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
494 {
495 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
496 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
497 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
498 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
499 i++)
500 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
501 }
502 else
503 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
504 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
505
506
507 /*
508 * Load CPUID overrides from configuration.
509 */
510 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
511 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
512 for (i=0;; )
513 {
514 while (cElements-- > 0)
515 {
516 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
517 if (pNode)
518 {
519 uint32_t u32;
520 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
521 if (VBOX_SUCCESS(rc))
522 pCpuId->eax = u32;
523 else
524 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
525
526 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
527 if (VBOX_SUCCESS(rc))
528 pCpuId->ebx = u32;
529 else
530 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
531
532 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
533 if (VBOX_SUCCESS(rc))
534 pCpuId->ecx = u32;
535 else
536 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
537
538 rc = CFGMR3QueryU32(pNode, "edx", &u32);
539 if (VBOX_SUCCESS(rc))
540 pCpuId->edx = u32;
541 else
542 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
543 }
544 pCpuId++;
545 i++;
546 }
547
548 /* next */
549 if ((i & UINT32_C(0xc0000000)) == 0)
550 {
551 pCpuId = &pCPUM->aGuestCpuIdExt[0];
552 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
553 i = UINT32_C(0x80000000);
554 }
555 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
556 {
557 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
558 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
559 i = UINT32_C(0xc0000000);
560 }
561 else
562 break;
563 }
564
565 /* Check if PAE was explicitely enabled by the user. */
566 bool fEnable = false;
567 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
568 if (VBOX_SUCCESS(rc) && fEnable)
569 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
570
571 /*
572 * Log the cpuid and we're good.
573 */
574 RTCPUSET OnlineSet;
575 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
576 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
577 LogRel(("************************* CPUID dump ************************\n"));
578 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
579 LogRel(("\n"));
580 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
581 LogRel(("******************** End of CPUID dump **********************\n"));
582 return VINF_SUCCESS;
583}
584
585
586
587
588/**
589 * Applies relocations to data and code managed by this
590 * component. This function will be called at init and
591 * whenever the VMM need to relocate it self inside the GC.
592 *
593 * The CPUM will update the addresses used by the switcher.
594 *
595 * @param pVM The VM.
596 */
597CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
598{
599 LogFlow(("CPUMR3Relocate\n"));
600 /*
601 * Switcher pointers.
602 */
603 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
604 pVM->cpum.s.pHyperCoreGC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
605 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
606}
607
608
609/**
610 * Queries the pointer to the internal CPUMCTX structure
611 *
612 * @returns VBox status code.
613 * @param pVM Handle to the virtual machine.
614 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
615 */
616CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
617{
618 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
619 /*
620 * Store the address. (Later we might check how's calling, thus the RC.)
621 */
622 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
623 return VINF_SUCCESS;
624}
625
626
627/**
628 * Terminates the CPUM.
629 *
630 * Termination means cleaning up and freeing all resources,
631 * the VM it self is at this point powered off or suspended.
632 *
633 * @returns VBox status code.
634 * @param pVM The VM to operate on.
635 */
636CPUMR3DECL(int) CPUMR3Term(PVM pVM)
637{
638 /** @todo ? */
639 return 0;
640}
641
642
643/**
644 * Resets the CPU.
645 *
646 * @returns VINF_SUCCESS.
647 * @param pVM The VM handle.
648 */
649CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
650{
651 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
652
653 /*
654 * Initialize everything to ZERO first.
655 */
656 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
657 memset(pCtx, 0, sizeof(*pCtx));
658 pVM->cpum.s.fUseFlags = fUseFlags;
659
660 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
661 pCtx->eip = 0x0000fff0;
662 pCtx->edx = 0x00000600; /* P6 processor */
663 pCtx->eflags.Bits.u1Reserved0 = 1;
664
665 pCtx->cs = 0xf000;
666 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
667 pCtx->csHid.u32Limit = 0x0000ffff;
668 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
669 pCtx->csHid.Attr.n.u1Present = 1;
670 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
671
672 pCtx->dsHid.u32Limit = 0x0000ffff;
673 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
674 pCtx->dsHid.Attr.n.u1Present = 1;
675 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
676
677 pCtx->esHid.u32Limit = 0x0000ffff;
678 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
679 pCtx->esHid.Attr.n.u1Present = 1;
680 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
681
682 pCtx->fsHid.u32Limit = 0x0000ffff;
683 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
684 pCtx->fsHid.Attr.n.u1Present = 1;
685 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
686
687 pCtx->gsHid.u32Limit = 0x0000ffff;
688 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
689 pCtx->gsHid.Attr.n.u1Present = 1;
690 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
691
692 pCtx->ssHid.u32Limit = 0x0000ffff;
693 pCtx->ssHid.Attr.n.u1Present = 1;
694 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
695 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
696
697 pCtx->idtr.cbIdt = 0xffff;
698 pCtx->gdtr.cbGdt = 0xffff;
699
700 pCtx->ldtrHid.u32Limit = 0xffff;
701 pCtx->ldtrHid.Attr.n.u1Present = 1;
702 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
703
704 pCtx->trHid.u32Limit = 0xffff;
705 pCtx->trHid.Attr.n.u1Present = 1;
706 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
707
708 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
709 pCtx->dr7 = 0x400;
710
711 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
712 pCtx->fpu.FCW = 0x37f;
713
714 /* Init PAT MSR */
715 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
716}
717
718
719/**
720 * Execute state save operation.
721 *
722 * @returns VBox status code.
723 * @param pVM VM Handle.
724 * @param pSSM SSM operation handle.
725 */
726static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
727{
728 /*
729 * Save.
730 */
731 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
732 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
733 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
734 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
735
736 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
737 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
738
739 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
740 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
741
742 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
743 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
744
745 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
746
747 /* Add the cpuid for checking that the cpu is unchanged. */
748 uint32_t au32CpuId[8] = {0};
749 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
750 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
751 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
752}
753
754
755/**
756 * Execute state load operation.
757 *
758 * @returns VBox status code.
759 * @param pVM VM Handle.
760 * @param pSSM SSM operation handle.
761 * @param u32Version Data layout version.
762 */
763static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
764{
765 /*
766 * Validate version.
767 */
768 if (u32Version != CPUM_SAVED_STATE_VERSION)
769 {
770 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
771 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
772 }
773
774 /*
775 * Restore.
776 */
777 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
778 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
779 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
780 pVM->cpum.s.Hyper.cr3 = uCR3;
781 pVM->cpum.s.Hyper.esp = uESP;
782 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
783 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
784 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
785
786 uint32_t cElements;
787 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
788 /* Support old saved states with a smaller standard cpuid array. */
789 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
790 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
791 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
792
793 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
794 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
795 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
796 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
797
798 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
799 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
800 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
801 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
802
803 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
804
805 /*
806 * Check that the basic cpuid id information is unchanged.
807 */
808 uint32_t au32CpuId[8] = {0};
809 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
810 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
811 uint32_t au32CpuIdSaved[8];
812 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
813 if (VBOX_SUCCESS(rc))
814 {
815 /* Ignore APIC ID (AMD specs). */
816 au32CpuId[5] &= ~0xff000000;
817 au32CpuIdSaved[5] &= ~0xff000000;
818 /* Ignore the number of Logical CPUs (AMD specs). */
819 au32CpuId[5] &= ~0x00ff0000;
820 au32CpuIdSaved[5] &= ~0x00ff0000;
821
822 /* do the compare */
823 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
824 {
825 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
826 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
827 "Saved=%.*Vhxs\n"
828 "Real =%.*Vhxs\n",
829 sizeof(au32CpuIdSaved), au32CpuIdSaved,
830 sizeof(au32CpuId), au32CpuId));
831 else
832 {
833 LogRel(("cpumR3Load: CpuId mismatch!\n"
834 "Saved=%.*Vhxs\n"
835 "Real =%.*Vhxs\n",
836 sizeof(au32CpuIdSaved), au32CpuIdSaved,
837 sizeof(au32CpuId), au32CpuId));
838 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
839 }
840 }
841 }
842
843 return rc;
844}
845
846
847/**
848 * Formats the EFLAGS value into mnemonics.
849 *
850 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
851 * @param efl The EFLAGS value.
852 */
853static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
854{
855 /*
856 * Format the flags.
857 */
858 static struct
859 {
860 const char *pszSet; const char *pszClear; uint32_t fFlag;
861 } s_aFlags[] =
862 {
863 { "vip",NULL, X86_EFL_VIP },
864 { "vif",NULL, X86_EFL_VIF },
865 { "ac", NULL, X86_EFL_AC },
866 { "vm", NULL, X86_EFL_VM },
867 { "rf", NULL, X86_EFL_RF },
868 { "nt", NULL, X86_EFL_NT },
869 { "ov", "nv", X86_EFL_OF },
870 { "dn", "up", X86_EFL_DF },
871 { "ei", "di", X86_EFL_IF },
872 { "tf", NULL, X86_EFL_TF },
873 { "nt", "pl", X86_EFL_SF },
874 { "nz", "zr", X86_EFL_ZF },
875 { "ac", "na", X86_EFL_AF },
876 { "po", "pe", X86_EFL_PF },
877 { "cy", "nc", X86_EFL_CF },
878 };
879 char *psz = pszEFlags;
880 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
881 {
882 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
883 if (pszAdd)
884 {
885 strcpy(psz, pszAdd);
886 psz += strlen(pszAdd);
887 *psz++ = ' ';
888 }
889 }
890 psz[-1] = '\0';
891}
892
893
894/**
895 * Formats a full register dump.
896 *
897 * @param pVM VM Handle.
898 * @param pCtx The context to format.
899 * @param pCtxCore The context core to format.
900 * @param pHlp Output functions.
901 * @param enmType The dump type.
902 * @param pszPrefix Register name prefix.
903 */
904static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
905{
906 /*
907 * Format the EFLAGS.
908 */
909 uint32_t efl = pCtxCore->eflags.u32;
910 char szEFlags[80];
911 cpumR3InfoFormatFlags(&szEFlags[0], efl);
912
913 /*
914 * Format the registers.
915 */
916 switch (enmType)
917 {
918 case CPUMDUMPTYPE_TERSE:
919 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
920 {
921 pHlp->pfnPrintf(pHlp,
922 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
923 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
924 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
925 "%sr14=%016RX64 %sr15=%016RX64\n"
926 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
927 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
928 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
929 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
930 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
931 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
932 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
933 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
934 }
935 else
936 pHlp->pfnPrintf(pHlp,
937 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
938 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
939 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
940 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
941 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
942 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
943 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
944 break;
945
946 case CPUMDUMPTYPE_DEFAULT:
947 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
948 {
949 pHlp->pfnPrintf(pHlp,
950 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
951 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
952 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
953 "%sr14=%016RX64 %sr15=%016RX64\n"
954 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
955 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
956 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
957 ,
958 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
959 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
960 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
961 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
962 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
963 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
964 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
965 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
966 }
967 else
968 pHlp->pfnPrintf(pHlp,
969 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
970 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
971 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
972 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
973 ,
974 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
975 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
976 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
977 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
978 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
979 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
980 break;
981
982 case CPUMDUMPTYPE_VERBOSE:
983 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
984 {
985 pHlp->pfnPrintf(pHlp,
986 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
987 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
988 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
989 "%sr14=%016RX64 %sr15=%016RX64\n"
990 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
991 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
992 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
993 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
994 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
995 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
996 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
997 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
998 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
999 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1000 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1001 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1002 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1003 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1004 ,
1005 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1006 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1007 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1008 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1009 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1010 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1011 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1012 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1013 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1014 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1015 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1016 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1017 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1018 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1019 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1020 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1021 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1022 }
1023 else
1024 pHlp->pfnPrintf(pHlp,
1025 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1026 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1027 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1028 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1029 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1030 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1031 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1032 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1033 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1034 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1035 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1036 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1037 ,
1038 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1039 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1040 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
1041 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1042 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
1043 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1044 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1045 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1046 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1047 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1048 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1049 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1050
1051 pHlp->pfnPrintf(pHlp,
1052 "FPU:\n"
1053 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1054 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1055 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1056 ,
1057 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1058 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1059 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1060 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1061
1062
1063 pHlp->pfnPrintf(pHlp,
1064 "MSR:\n"
1065 "%sEFER =%016RX64\n"
1066 "%sPAT =%016RX64\n"
1067 "%sSTAR =%016RX64\n"
1068 "%sCSTAR =%016RX64\n"
1069 "%sLSTAR =%016RX64\n"
1070 "%sSFMASK =%016RX64\n"
1071 "%sKERNELGSBASE =%016RX64\n",
1072 pszPrefix, pCtx->msrEFER,
1073 pszPrefix, pCtx->msrPAT,
1074 pszPrefix, pCtx->msrSTAR,
1075 pszPrefix, pCtx->msrCSTAR,
1076 pszPrefix, pCtx->msrLSTAR,
1077 pszPrefix, pCtx->msrSFMASK,
1078 pszPrefix, pCtx->msrKERNELGSBASE);
1079
1080 break;
1081 }
1082}
1083
1084
1085/**
1086 * Display all cpu states and any other cpum info.
1087 *
1088 * @param pVM VM Handle.
1089 * @param pHlp The info helper functions.
1090 * @param pszArgs Arguments, ignored.
1091 */
1092static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1093{
1094 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1095 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1096 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1097 cpumR3InfoHost(pVM, pHlp, pszArgs);
1098}
1099
1100
1101/**
1102 * Parses the info argument.
1103 *
1104 * The argument starts with 'verbose', 'terse' or 'default' and then
1105 * continues with the comment string.
1106 *
1107 * @param pszArgs The pointer to the argument string.
1108 * @param penmType Where to store the dump type request.
1109 * @param ppszComment Where to store the pointer to the comment string.
1110 */
1111static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1112{
1113 if (!pszArgs)
1114 {
1115 *penmType = CPUMDUMPTYPE_DEFAULT;
1116 *ppszComment = "";
1117 }
1118 else
1119 {
1120 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1121 {
1122 pszArgs += 5;
1123 *penmType = CPUMDUMPTYPE_VERBOSE;
1124 }
1125 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1126 {
1127 pszArgs += 5;
1128 *penmType = CPUMDUMPTYPE_TERSE;
1129 }
1130 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1131 {
1132 pszArgs += 7;
1133 *penmType = CPUMDUMPTYPE_DEFAULT;
1134 }
1135 else
1136 *penmType = CPUMDUMPTYPE_DEFAULT;
1137 *ppszComment = RTStrStripL(pszArgs);
1138 }
1139}
1140
1141
1142/**
1143 * Display the guest cpu state.
1144 *
1145 * @param pVM VM Handle.
1146 * @param pHlp The info helper functions.
1147 * @param pszArgs Arguments, ignored.
1148 */
1149static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1150{
1151 CPUMDUMPTYPE enmType;
1152 const char *pszComment;
1153 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1154 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1155 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1156}
1157
1158/**
1159 * Display the current guest instruction
1160 *
1161 * @param pVM VM Handle.
1162 * @param pHlp The info helper functions.
1163 * @param pszArgs Arguments, ignored.
1164 */
1165static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1166{
1167 char szInstruction[256];
1168 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1169 if (VBOX_SUCCESS(rc))
1170 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1171}
1172
1173
1174/**
1175 * Display the hypervisor cpu state.
1176 *
1177 * @param pVM VM Handle.
1178 * @param pHlp The info helper functions.
1179 * @param pszArgs Arguments, ignored.
1180 */
1181static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1182{
1183 CPUMDUMPTYPE enmType;
1184 const char *pszComment;
1185 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1186 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1187 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1188 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1189}
1190
1191
1192/**
1193 * Display the host cpu state.
1194 *
1195 * @param pVM VM Handle.
1196 * @param pHlp The info helper functions.
1197 * @param pszArgs Arguments, ignored.
1198 */
1199static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1200{
1201 CPUMDUMPTYPE enmType;
1202 const char *pszComment;
1203 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1204 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1205
1206 /*
1207 * Format the EFLAGS.
1208 */
1209 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1210#if HC_ARCH_BITS == 32
1211 uint32_t efl = pCtx->eflags.u32;
1212#else
1213 uint64_t efl = pCtx->rflags;
1214#endif
1215 char szEFlags[80];
1216 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1217
1218 /*
1219 * Format the registers.
1220 */
1221#if HC_ARCH_BITS == 32
1222# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1223 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1224# endif
1225 {
1226 pHlp->pfnPrintf(pHlp,
1227 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1228 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1229 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1230 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1231 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1232 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1233 ,
1234 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1235 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1236 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1237 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1238 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1239 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1240 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1241 }
1242# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1243 else
1244# endif
1245#endif
1246#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1247 {
1248 pHlp->pfnPrintf(pHlp,
1249 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1250 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1251 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1252 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1253 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1254 "r14=%016RX64 r15=%016RX64\n"
1255 "iopl=%d %31s\n"
1256 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1257 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1258 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1259 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1260 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1261 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1262 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1263 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1264 ,
1265 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1266 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1267 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1268 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1269 pCtx->r11, pCtx->r12, pCtx->r13,
1270 pCtx->r14, pCtx->r15,
1271 X86_EFL_GET_IOPL(efl), szEFlags,
1272 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1273 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1274 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1275 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1276 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1277 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1278 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1279 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1280 }
1281#endif
1282}
1283
1284
1285/**
1286 * Get L1 cache / TLS associativity.
1287 */
1288static const char *getCacheAss(unsigned u, char *pszBuf)
1289{
1290 if (u == 0)
1291 return "res0 ";
1292 if (u == 1)
1293 return "direct";
1294 if (u >= 256)
1295 return "???";
1296
1297 RTStrPrintf(pszBuf, 16, "%d way", u);
1298 return pszBuf;
1299}
1300
1301
1302/**
1303 * Get L2 cache soociativity.
1304 */
1305const char *getL2CacheAss(unsigned u)
1306{
1307 switch (u)
1308 {
1309 case 0: return "off ";
1310 case 1: return "direct";
1311 case 2: return "2 way ";
1312 case 3: return "res3 ";
1313 case 4: return "4 way ";
1314 case 5: return "res5 ";
1315 case 6: return "8 way "; case 7: return "res7 ";
1316 case 8: return "16 way";
1317 case 9: return "res9 ";
1318 case 10: return "res10 ";
1319 case 11: return "res11 ";
1320 case 12: return "res12 ";
1321 case 13: return "res13 ";
1322 case 14: return "res14 ";
1323 case 15: return "fully ";
1324 default:
1325 return "????";
1326 }
1327}
1328
1329
1330/**
1331 * Display the guest CpuId leaves.
1332 *
1333 * @param pVM VM Handle.
1334 * @param pHlp The info helper functions.
1335 * @param pszArgs "terse", "default" or "verbose".
1336 */
1337static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1338{
1339 /*
1340 * Parse the argument.
1341 */
1342 unsigned iVerbosity = 1;
1343 if (pszArgs)
1344 {
1345 pszArgs = RTStrStripL(pszArgs);
1346 if (!strcmp(pszArgs, "terse"))
1347 iVerbosity--;
1348 else if (!strcmp(pszArgs, "verbose"))
1349 iVerbosity++;
1350 }
1351
1352 /*
1353 * Start cracking.
1354 */
1355 CPUMCPUID Host;
1356 CPUMCPUID Guest;
1357 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1358
1359 pHlp->pfnPrintf(pHlp,
1360 " RAW Standard CPUIDs\n"
1361 " Function eax ebx ecx edx\n");
1362 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1363 {
1364 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1365 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1366
1367 pHlp->pfnPrintf(pHlp,
1368 "Gst: %08x %08x %08x %08x %08x%s\n"
1369 "Hst: %08x %08x %08x %08x\n",
1370 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1371 i <= cStdMax ? "" : "*",
1372 Host.eax, Host.ebx, Host.ecx, Host.edx);
1373 }
1374
1375 /*
1376 * If verbose, decode it.
1377 */
1378 if (iVerbosity)
1379 {
1380 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1381 pHlp->pfnPrintf(pHlp,
1382 "Name: %.04s%.04s%.04s\n"
1383 "Supports: 0-%x\n",
1384 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1385 }
1386
1387 /*
1388 * Get Features.
1389 */
1390 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1391 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1392 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1393 if (cStdMax >= 1 && iVerbosity)
1394 {
1395 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1396 uint32_t uEAX = Guest.eax;
1397
1398 pHlp->pfnPrintf(pHlp,
1399 "Family: %d \tExtended: %d \tEffective: %d\n"
1400 "Model: %d \tExtended: %d \tEffective: %d\n"
1401 "Stepping: %d\n"
1402 "APIC ID: %#04x\n"
1403 "Logical CPUs: %d\n"
1404 "CLFLUSH Size: %d\n"
1405 "Brand ID: %#04x\n",
1406 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1407 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1408 ASMGetCpuStepping(uEAX),
1409 (Guest.ebx >> 24) & 0xff,
1410 (Guest.ebx >> 16) & 0xff,
1411 (Guest.ebx >> 8) & 0xff,
1412 (Guest.ebx >> 0) & 0xff);
1413 if (iVerbosity == 1)
1414 {
1415 uint32_t uEDX = Guest.edx;
1416 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1417 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1418 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1419 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1420 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1421 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1422 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1423 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1424 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1425 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1426 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1427 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1428 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1429 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1430 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1431 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1432 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1433 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1434 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1435 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1436 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1437 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1438 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1439 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1440 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1441 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1442 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1443 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1444 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1445 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1446 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1447 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1448 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1449 pHlp->pfnPrintf(pHlp, "\n");
1450
1451 uint32_t uECX = Guest.ecx;
1452 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1453 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1454 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1455 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1456 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1457 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1458 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1459 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1460 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1461 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1462 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1463 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1464 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1465 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1466 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1467 for (unsigned iBit = 14; iBit < 32; iBit++)
1468 if (uECX & RT_BIT(iBit))
1469 pHlp->pfnPrintf(pHlp, " %d", iBit);
1470 pHlp->pfnPrintf(pHlp, "\n");
1471 }
1472 else
1473 {
1474 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1475
1476 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1477 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1478 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1479 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1480
1481 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1482 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1483 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1484 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1485 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1486 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1487 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1488 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1489 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1490 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1491 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1492 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1493 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1494 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1495 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1496 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1497 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1498 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1499 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1500 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1501 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1502 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1503 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1504 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1505 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1506 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1507 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1508 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1509 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1510 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1511 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1512 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1513 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1514
1515 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1516 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1517 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1518 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1519 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1520 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1521 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1522 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1523 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1524 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1525 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1526 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1527 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1528 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1529 }
1530 }
1531 if (cStdMax >= 2 && iVerbosity)
1532 {
1533 /** @todo */
1534 }
1535
1536 /*
1537 * Extended.
1538 * Implemented after AMD specs.
1539 */
1540 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1541
1542 pHlp->pfnPrintf(pHlp,
1543 "\n"
1544 " RAW Extended CPUIDs\n"
1545 " Function eax ebx ecx edx\n");
1546 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1547 {
1548 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1549 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1550
1551 pHlp->pfnPrintf(pHlp,
1552 "Gst: %08x %08x %08x %08x %08x%s\n"
1553 "Hst: %08x %08x %08x %08x\n",
1554 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1555 i <= cExtMax ? "" : "*",
1556 Host.eax, Host.ebx, Host.ecx, Host.edx);
1557 }
1558
1559 /*
1560 * Understandable output
1561 */
1562 if (iVerbosity && cExtMax >= 0)
1563 {
1564 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1565 pHlp->pfnPrintf(pHlp,
1566 "Ext Name: %.4s%.4s%.4s\n"
1567 "Ext Supports: 0x80000000-%#010x\n",
1568 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1569 }
1570
1571 if (iVerbosity && cExtMax >= 1)
1572 {
1573 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1574 uint32_t uEAX = Guest.eax;
1575 pHlp->pfnPrintf(pHlp,
1576 "Family: %d \tExtended: %d \tEffective: %d\n"
1577 "Model: %d \tExtended: %d \tEffective: %d\n"
1578 "Stepping: %d\n"
1579 "Brand ID: %#05x\n",
1580 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1581 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1582 ASMGetCpuStepping(uEAX),
1583 Guest.ebx & 0xfff);
1584
1585 if (iVerbosity == 1)
1586 {
1587 uint32_t uEDX = Guest.edx;
1588 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1589 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1590 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1591 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1592 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1593 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1594 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1595 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1596 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1597 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1598 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1599 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1600 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1601 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1602 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1603 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1604 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1605 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1606 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1607 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1608 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1609 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1610 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1611 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1612 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1613 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1614 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1615 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1616 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1617 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1618 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1619 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1620 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1621 pHlp->pfnPrintf(pHlp, "\n");
1622
1623 uint32_t uECX = Guest.ecx;
1624 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1625 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1626 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1627 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1628 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1629 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1630 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1631 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1632 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1633 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1634 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1635 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1636 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1637 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1638 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1639 for (unsigned iBit = 5; iBit < 32; iBit++)
1640 if (uECX & RT_BIT(iBit))
1641 pHlp->pfnPrintf(pHlp, " %d", iBit);
1642 pHlp->pfnPrintf(pHlp, "\n");
1643 }
1644 else
1645 {
1646 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1647
1648 uint32_t uEdxGst = Guest.edx;
1649 uint32_t uEdxHst = Host.edx;
1650 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1651 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1652 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1653 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1654 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1655 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1656 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1657 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1658 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1659 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1660 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1661 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1662 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1663 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1664 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1665 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1666 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1667 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1668 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1669 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1670 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1671 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1672 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1673 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1674 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1675 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1676 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1677 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1678 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1679 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1680 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1681 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1682 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1683
1684 uint32_t uEcxGst = Guest.ecx;
1685 uint32_t uEcxHst = Host.ecx;
1686 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1687 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1688 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1689 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1690 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1691 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1692 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1693 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1694 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1695 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1696 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1697 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1698 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1699 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1700 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1701 }
1702 }
1703
1704 if (iVerbosity && cExtMax >= 2)
1705 {
1706 char szString[4*4*3+1] = {0};
1707 uint32_t *pu32 = (uint32_t *)szString;
1708 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1709 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1710 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1711 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1712 if (cExtMax >= 3)
1713 {
1714 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1715 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1716 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1717 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1718 }
1719 if (cExtMax >= 4)
1720 {
1721 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1722 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1723 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1724 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1725 }
1726 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1727 }
1728
1729 if (iVerbosity && cExtMax >= 5)
1730 {
1731 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1732 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1733 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1734 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1735 char sz1[32];
1736 char sz2[32];
1737
1738 pHlp->pfnPrintf(pHlp,
1739 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1740 "TLB 2/4M Data: %s %3d entries\n",
1741 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1742 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1743 pHlp->pfnPrintf(pHlp,
1744 "TLB 4K Instr/Uni: %s %3d entries\n"
1745 "TLB 4K Data: %s %3d entries\n",
1746 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1747 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1748 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1749 "L1 Instr Cache Lines Per Tag: %d\n"
1750 "L1 Instr Cache Associativity: %s\n"
1751 "L1 Instr Cache Size: %d KB\n",
1752 (uEDX >> 0) & 0xff,
1753 (uEDX >> 8) & 0xff,
1754 getCacheAss((uEDX >> 16) & 0xff, sz1),
1755 (uEDX >> 24) & 0xff);
1756 pHlp->pfnPrintf(pHlp,
1757 "L1 Data Cache Line Size: %d bytes\n"
1758 "L1 Data Cache Lines Per Tag: %d\n"
1759 "L1 Data Cache Associativity: %s\n"
1760 "L1 Data Cache Size: %d KB\n",
1761 (uECX >> 0) & 0xff,
1762 (uECX >> 8) & 0xff,
1763 getCacheAss((uECX >> 16) & 0xff, sz1),
1764 (uECX >> 24) & 0xff);
1765 }
1766
1767 if (iVerbosity && cExtMax >= 6)
1768 {
1769 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1770 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1771 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1772
1773 pHlp->pfnPrintf(pHlp,
1774 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1775 "L2 TLB 2/4M Data: %s %4d entries\n",
1776 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1777 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1778 pHlp->pfnPrintf(pHlp,
1779 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1780 "L2 TLB 4K Data: %s %4d entries\n",
1781 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1782 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1783 pHlp->pfnPrintf(pHlp,
1784 "L2 Cache Line Size: %d bytes\n"
1785 "L2 Cache Lines Per Tag: %d\n"
1786 "L2 Cache Associativity: %s\n"
1787 "L2 Cache Size: %d KB\n",
1788 (uEDX >> 0) & 0xff,
1789 (uEDX >> 8) & 0xf,
1790 getL2CacheAss((uEDX >> 12) & 0xf),
1791 (uEDX >> 16) & 0xffff);
1792 }
1793
1794 if (iVerbosity && cExtMax >= 7)
1795 {
1796 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1797
1798 pHlp->pfnPrintf(pHlp, "APM Features: ");
1799 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1800 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1801 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1802 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1803 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1804 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1805 for (unsigned iBit = 6; iBit < 32; iBit++)
1806 if (uEDX & RT_BIT(iBit))
1807 pHlp->pfnPrintf(pHlp, " %d", iBit);
1808 pHlp->pfnPrintf(pHlp, "\n");
1809 }
1810
1811 if (iVerbosity && cExtMax >= 8)
1812 {
1813 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1814 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1815
1816 pHlp->pfnPrintf(pHlp,
1817 "Physical Address Width: %d bits\n"
1818 "Virtual Address Width: %d bits\n",
1819 (uEAX >> 0) & 0xff,
1820 (uEAX >> 8) & 0xff);
1821 pHlp->pfnPrintf(pHlp,
1822 "Physical Core Count: %d\n",
1823 (uECX >> 0) & 0xff);
1824 }
1825
1826
1827 /*
1828 * Centaur.
1829 */
1830 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1831
1832 pHlp->pfnPrintf(pHlp,
1833 "\n"
1834 " RAW Centaur CPUIDs\n"
1835 " Function eax ebx ecx edx\n");
1836 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1837 {
1838 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1839 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1840
1841 pHlp->pfnPrintf(pHlp,
1842 "Gst: %08x %08x %08x %08x %08x%s\n"
1843 "Hst: %08x %08x %08x %08x\n",
1844 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1845 i <= cCentaurMax ? "" : "*",
1846 Host.eax, Host.ebx, Host.ecx, Host.edx);
1847 }
1848
1849 /*
1850 * Understandable output
1851 */
1852 if (iVerbosity && cCentaurMax >= 0)
1853 {
1854 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1855 pHlp->pfnPrintf(pHlp,
1856 "Centaur Supports: 0xc0000000-%#010x\n",
1857 Guest.eax);
1858 }
1859
1860 if (iVerbosity && cCentaurMax >= 1)
1861 {
1862 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1863 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1864 uint32_t uEdxHst = Host.edx;
1865
1866 if (iVerbosity == 1)
1867 {
1868 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1869 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1870 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1871 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1872 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1873 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1874 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1875 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1876 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1877 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1878 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1879 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1880 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1881 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1882 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1883 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1884 for (unsigned iBit = 14; iBit < 32; iBit++)
1885 if (uEdxGst & RT_BIT(iBit))
1886 pHlp->pfnPrintf(pHlp, " %d", iBit);
1887 pHlp->pfnPrintf(pHlp, "\n");
1888 }
1889 else
1890 {
1891 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1892 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1893 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1894 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1895 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1896 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1897 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1898 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1899 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1900 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1901 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1902 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1903 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1904 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1905 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1906 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1907 for (unsigned iBit = 14; iBit < 32; iBit++)
1908 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1909 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1910 pHlp->pfnPrintf(pHlp, "\n");
1911 }
1912 }
1913}
1914
1915
1916/**
1917 * Structure used when disassembling and instructions in DBGF.
1918 * This is used so the reader function can get the stuff it needs.
1919 */
1920typedef struct CPUMDISASSTATE
1921{
1922 /** Pointer to the CPU structure. */
1923 PDISCPUSTATE pCpu;
1924 /** The VM handle. */
1925 PVM pVM;
1926 /** Pointer to the first byte in the segemnt. */
1927 RTGCUINTPTR GCPtrSegBase;
1928 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1929 RTGCUINTPTR GCPtrSegEnd;
1930 /** The size of the segment minus 1. */
1931 RTGCUINTPTR cbSegLimit;
1932 /** Pointer to the current page - HC Ptr. */
1933 void const *pvPageHC;
1934 /** Pointer to the current page - GC Ptr. */
1935 RTGCPTR pvPageGC;
1936 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1937 PGMPAGEMAPLOCK PageMapLock;
1938 /** Whether the PageMapLock is valid or not. */
1939 bool fLocked;
1940 /** 64 bits mode or not. */
1941 bool f64Bits;
1942} CPUMDISASSTATE, *PCPUMDISASSTATE;
1943
1944
1945/**
1946 * Instruction reader.
1947 *
1948 * @returns VBox status code.
1949 * @param PtrSrc Address to read from.
1950 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1951 * @param pu8Dst Where to store the bytes.
1952 * @param cbRead Number of bytes to read.
1953 * @param uDisCpu Pointer to the disassembler cpu state.
1954 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1955 */
1956static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1957{
1958 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1959 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1960 Assert(cbRead > 0);
1961 for (;;)
1962 {
1963 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1964
1965 /* Need to update the page translation? */
1966 if ( !pState->pvPageHC
1967 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1968 {
1969 int rc = VINF_SUCCESS;
1970
1971 /* translate the address */
1972 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1973 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1974 {
1975 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1976 if (!pState->pvPageHC)
1977 rc = VERR_INVALID_POINTER;
1978 }
1979 else
1980 {
1981 /* Release mapping lock previously acquired. */
1982 if (pState->fLocked)
1983 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1984 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1985 pState->fLocked = RT_SUCCESS_NP(rc);
1986 }
1987 if (VBOX_FAILURE(rc))
1988 {
1989 pState->pvPageHC = NULL;
1990 return rc;
1991 }
1992 }
1993
1994 /* check the segemnt limit */
1995 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
1996 return VERR_OUT_OF_SELECTOR_BOUNDS;
1997
1998 /* calc how much we can read */
1999 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2000 if (!pState->f64Bits)
2001 {
2002 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2003 if (cb > cbSeg && cbSeg)
2004 cb = cbSeg;
2005 }
2006 if (cb > cbRead)
2007 cb = cbRead;
2008
2009 /* read and advance */
2010 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2011 cbRead -= cb;
2012 if (!cbRead)
2013 return VINF_SUCCESS;
2014 pu8Dst += cb;
2015 PtrSrc += cb;
2016 }
2017}
2018
2019
2020/**
2021 * Disassemble an instruction and return the information in the provided structure.
2022 *
2023 * @returns VBox status code.
2024 * @param pVM VM Handle
2025 * @param pCtx CPU context
2026 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2027 * @param pCpu Disassembly state
2028 * @param pszPrefix String prefix for logging (debug only)
2029 *
2030 */
2031CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2032{
2033 CPUMDISASSTATE State;
2034 int rc;
2035
2036 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2037 State.pCpu = pCpu;
2038 State.pvPageGC = 0;
2039 State.pvPageHC = NULL;
2040 State.pVM = pVM;
2041 State.fLocked = false;
2042 State.f64Bits = false;
2043
2044 /*
2045 * Get selector information.
2046 */
2047 if ( (pCtx->cr0 & X86_CR0_PE)
2048 && pCtx->eflags.Bits.u1VM == 0)
2049 {
2050 if (CPUMAreHiddenSelRegsValid(pVM))
2051 {
2052 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2053 State.GCPtrSegBase = pCtx->csHid.u64Base;
2054 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2055 State.cbSegLimit = pCtx->csHid.u32Limit;
2056 pCpu->mode = (State.f64Bits)
2057 ? CPUMODE_64BIT
2058 : pCtx->csHid.Attr.n.u1DefBig
2059 ? CPUMODE_32BIT
2060 : CPUMODE_16BIT;
2061 }
2062 else
2063 {
2064 SELMSELINFO SelInfo;
2065
2066 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2067 if (!VBOX_SUCCESS(rc))
2068 {
2069 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2070 return rc;
2071 }
2072
2073 /*
2074 * Validate the selector.
2075 */
2076 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2077 if (!VBOX_SUCCESS(rc))
2078 {
2079 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2080 return rc;
2081 }
2082 State.GCPtrSegBase = SelInfo.GCPtrBase;
2083 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2084 State.cbSegLimit = SelInfo.cbLimit;
2085 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2086 }
2087 }
2088 else
2089 {
2090 /* real or V86 mode */
2091 pCpu->mode = CPUMODE_16BIT;
2092 State.GCPtrSegBase = pCtx->cs * 16;
2093 State.GCPtrSegEnd = 0xFFFFFFFF;
2094 State.cbSegLimit = 0xFFFFFFFF;
2095 }
2096
2097 /*
2098 * Disassemble the instruction.
2099 */
2100 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2101 pCpu->apvUserData[0] = &State;
2102
2103 uint32_t cbInstr;
2104#ifndef LOG_ENABLED
2105 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2106 if (VBOX_SUCCESS(rc))
2107 {
2108#else
2109 char szOutput[160];
2110 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2111 if (VBOX_SUCCESS(rc))
2112 {
2113 /* log it */
2114 if (pszPrefix)
2115 Log(("%s: %s", pszPrefix, szOutput));
2116 else
2117 Log(("%s", szOutput));
2118#endif
2119 rc = VINF_SUCCESS;
2120 }
2121 else
2122 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2123
2124 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2125 if (State.fLocked)
2126 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2127
2128 return rc;
2129}
2130
2131#ifdef DEBUG
2132
2133/**
2134 * Disassemble an instruction and dump it to the log
2135 *
2136 * @returns VBox status code.
2137 * @param pVM VM Handle
2138 * @param pCtx CPU context
2139 * @param pc GC instruction pointer
2140 * @param prefix String prefix for logging
2141 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2142 *
2143 */
2144CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2145{
2146 DISCPUSTATE cpu;
2147
2148 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2149}
2150
2151/**
2152 * Disassemble an instruction and dump it to the log
2153 *
2154 * @returns VBox status code.
2155 * @param pVM VM Handle
2156 * @param pCtx CPU context
2157 * @param pc GC instruction pointer
2158 * @param prefix String prefix for logging
2159 * @param nrInstructions
2160 *
2161 */
2162CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2163{
2164 for(int i=0;i<nrInstructions;i++)
2165 {
2166 DISCPUSTATE cpu;
2167
2168 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2169 pc += cpu.opsize;
2170 }
2171}
2172
2173#endif /* DEBUG */
2174
2175#ifdef DEBUG
2176/**
2177 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2178 *
2179 * @internal
2180 */
2181CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2182{
2183 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2184}
2185#endif /* DEBUG */
2186
2187
2188/**
2189 * API for controlling a few of the CPU features found in CR4.
2190 *
2191 * Currently only X86_CR4_TSD is accepted as input.
2192 *
2193 * @returns VBox status code.
2194 *
2195 * @param pVM The VM handle.
2196 * @param fOr The CR4 OR mask.
2197 * @param fAnd The CR4 AND mask.
2198 */
2199CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2200{
2201 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2202 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2203
2204 pVM->cpum.s.CR4.OrMask &= fAnd;
2205 pVM->cpum.s.CR4.OrMask |= fOr;
2206
2207 return VINF_SUCCESS;
2208}
2209
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