VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 12016

Last change on this file since 12016 was 12016, checked in by vboxsync, 16 years ago

Reset EFER to zero & MXCSR to 0x1f80.
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File size: 106.5 KB
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1/* $Id: CPUM.cpp 12016 2008-09-03 07:51:11Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/pdm.h>
43#include <VBox/mm.h>
44#include <VBox/selm.h>
45#include <VBox/dbgf.h>
46#include <VBox/patm.h>
47#include <VBox/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm.h>
57#include <iprt/string.h>
58#include <iprt/mp.h>
59#include <iprt/cpuset.h>
60
61
62/*******************************************************************************
63* Defined Constants And Macros *
64*******************************************************************************/
65/** The saved state version. */
66#define CPUM_SAVED_STATE_VERSION_VER1_6 6
67#define CPUM_SAVED_STATE_VERSION 8
68
69
70/*******************************************************************************
71* Structures and Typedefs *
72*******************************************************************************/
73
74/**
75 * What kind of cpu info dump to perform.
76 */
77typedef enum CPUMDUMPTYPE
78{
79 CPUMDUMPTYPE_TERSE,
80 CPUMDUMPTYPE_DEFAULT,
81 CPUMDUMPTYPE_VERBOSE
82
83} CPUMDUMPTYPE;
84/** Pointer to a cpu info dump type. */
85typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
86
87/*******************************************************************************
88* Internal Functions *
89*******************************************************************************/
90static int cpumR3CpuIdInit(PVM pVM);
91static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
92static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
93static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99
100
101/**
102 * Initializes the CPUM.
103 *
104 * @returns VBox status code.
105 * @param pVM The VM to operate on.
106 */
107CPUMR3DECL(int) CPUMR3Init(PVM pVM)
108{
109 LogFlow(("CPUMR3Init\n"));
110
111 /*
112 * Assert alignment and sizes.
113 */
114 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
115 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
116
117 /*
118 * Setup any fixed pointers and offsets.
119 */
120 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
121 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
122 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
123 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
124
125 /* Hidden selector registers are invalid by default. */
126 pVM->cpum.s.fValidHiddenSelRegs = false;
127
128 /*
129 * Check that the CPU supports the minimum features we require.
130 */
131 /** @todo check the contract! */
132 if (!ASMHasCpuId())
133 {
134 Log(("The CPU doesn't support CPUID!\n"));
135 return VERR_UNSUPPORTED_CPU;
136 }
137 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
138 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
139
140 /* Setup the CR4 AND and OR masks used in the switcher */
141 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
142 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
143 {
144 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
145 /* No FXSAVE implies no SSE */
146 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
147 pVM->cpum.s.CR4.OrMask = 0;
148 }
149 else
150 {
151 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
152 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
153 }
154
155 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
156 {
157 Log(("The CPU doesn't support MMX!\n"));
158 return VERR_UNSUPPORTED_CPU;
159 }
160 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
161 {
162 Log(("The CPU doesn't support TSC!\n"));
163 return VERR_UNSUPPORTED_CPU;
164 }
165 /* Bogus on AMD? */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
167 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
168
169 /*
170 * Setup hypervisor startup values.
171 */
172
173 /*
174 * Register saved state data item.
175 */
176 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
177 NULL, cpumR3Save, NULL,
178 NULL, cpumR3Load, NULL);
179 if (VBOX_FAILURE(rc))
180 return rc;
181
182 /* Query the CPU manufacturer. */
183 uint32_t uEAX, uEBX, uECX, uEDX;
184 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
185 if ( uEAX >= 1
186 && uEBX == X86_CPUID_VENDOR_AMD_EBX
187 && uECX == X86_CPUID_VENDOR_AMD_ECX
188 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
189 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
190 else if ( uEAX >= 1
191 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
192 && uECX == X86_CPUID_VENDOR_INTEL_ECX
193 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
194 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
195 else /** @todo Via */
196 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
197
198 /*
199 * Register info handlers.
200 */
201 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
202 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
203 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
204 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
205 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
206 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
207
208 /*
209 * Initialize the Guest CPU state.
210 */
211 rc = cpumR3CpuIdInit(pVM);
212 if (VBOX_FAILURE(rc))
213 return rc;
214 CPUMR3Reset(pVM);
215 return VINF_SUCCESS;
216}
217
218
219/**
220 * Initializes the emulated CPU's cpuid information.
221 *
222 * @returns VBox status code.
223 * @param pVM The VM to operate on.
224 */
225static int cpumR3CpuIdInit(PVM pVM)
226{
227 PCPUM pCPUM = &pVM->cpum.s;
228 uint32_t i;
229
230 /*
231 * Get the host CPUIDs.
232 */
233 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
234 ASMCpuId_Idx_ECX(i, 0,
235 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
236 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
237 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
238 ASMCpuId(0x80000000 + i,
239 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
240 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
241 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
242 ASMCpuId(0xc0000000 + i,
243 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
244 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
245
246
247 /*
248 * Only report features we can support.
249 */
250 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
251 | X86_CPUID_FEATURE_EDX_VME
252 | X86_CPUID_FEATURE_EDX_DE
253 | X86_CPUID_FEATURE_EDX_PSE
254 | X86_CPUID_FEATURE_EDX_TSC
255 | X86_CPUID_FEATURE_EDX_MSR
256 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
257 | X86_CPUID_FEATURE_EDX_MCE
258 | X86_CPUID_FEATURE_EDX_CX8
259 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
260 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
261 //| X86_CPUID_FEATURE_EDX_SEP
262 | X86_CPUID_FEATURE_EDX_MTRR
263 | X86_CPUID_FEATURE_EDX_PGE
264 | X86_CPUID_FEATURE_EDX_MCA
265 | X86_CPUID_FEATURE_EDX_CMOV
266 | X86_CPUID_FEATURE_EDX_PAT
267 | X86_CPUID_FEATURE_EDX_PSE36
268 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
269 | X86_CPUID_FEATURE_EDX_CLFSH
270 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
271 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
272 | X86_CPUID_FEATURE_EDX_MMX
273 | X86_CPUID_FEATURE_EDX_FXSR
274 | X86_CPUID_FEATURE_EDX_SSE
275 | X86_CPUID_FEATURE_EDX_SSE2
276 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
277 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
278 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
279 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
280 | 0;
281 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
282 | X86_CPUID_FEATURE_ECX_MONITOR
283 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
284 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
285 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
286 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
287 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
288 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
289 //| X86_CPUID_FEATURE_ECX_CX16
290 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
291 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
292 /* ECX Bit 23 - POPCOUNT instruction. */
293 //| X86_CPUID_FEATURE_ECX_POPCOUNT
294 | 0;
295
296 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
297 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
298 | X86_CPUID_AMD_FEATURE_EDX_VME
299 | X86_CPUID_AMD_FEATURE_EDX_DE
300 | X86_CPUID_AMD_FEATURE_EDX_PSE
301 | X86_CPUID_AMD_FEATURE_EDX_TSC
302 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
303 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
304 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
305 | X86_CPUID_AMD_FEATURE_EDX_CX8
306 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
307 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
308 //| X86_CPUID_AMD_FEATURE_EDX_SEP
309 | X86_CPUID_AMD_FEATURE_EDX_MTRR
310 | X86_CPUID_AMD_FEATURE_EDX_PGE
311 | X86_CPUID_AMD_FEATURE_EDX_MCA
312 | X86_CPUID_AMD_FEATURE_EDX_CMOV
313 | X86_CPUID_AMD_FEATURE_EDX_PAT
314 | X86_CPUID_AMD_FEATURE_EDX_PSE36
315 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
316 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
317 | X86_CPUID_AMD_FEATURE_EDX_MMX
318 | X86_CPUID_AMD_FEATURE_EDX_FXSR
319 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
320 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
321 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
322 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
323 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
324 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
325 | 0;
326 pCPUM->aGuestCpuIdExt[1].ecx &= 0
327 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
328 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
329 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
330 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
331 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
332 //| X86_CPUID_AMD_FEATURE_ECX_ABM
333 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
334 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
335 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
336 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
337 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
338 //| X86_CPUID_AMD_FEATURE_ECX_WDT
339 | 0;
340
341 /*
342 * Hide HTT, multicode, SMP, whatever.
343 * (APIC-ID := 0 and #LogCpus := 0)
344 */
345 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
346
347 /* Cpuid 2:
348 * Intel: Cache and TLB information
349 * AMD: Reserved
350 * Safe to expose
351 */
352
353 /* Cpuid 3:
354 * Intel: EAX, EBX - reserved
355 * ECX, EDX - Processor Serial Number if available, otherwise reserved
356 * AMD: Reserved
357 * Safe to expose
358 */
359 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
360 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
361
362 /* Cpuid 4:
363 * Intel: Deterministic Cache Parameters Leaf
364 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
365 * AMD: Reserved
366 * Safe to expose, except for EAX:
367 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
368 * Bits 31-26: Maximum number of processor cores in this physical package**
369 */
370 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
371 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
372
373 /* Cpuid 5: Monitor/mwait Leaf
374 * Intel: ECX, EDX - reserved
375 * EAX, EBX - Smallest and largest monitor line size
376 * AMD: EDX - reserved
377 * EAX, EBX - Smallest and largest monitor line size
378 * ECX - extensions (ignored for now)
379 * Safe to expose
380 */
381 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
382 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
383
384 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
385
386 /*
387 * Determine the default.
388 *
389 * Intel returns values of the highest standard function, while AMD
390 * returns zeros. VIA on the other hand seems to returning nothing or
391 * perhaps some random garbage, we don't try to duplicate this behavior.
392 */
393 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
394 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
395 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
396
397 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
398 * Safe to pass on to the guest.
399 *
400 * Intel: 0x800000005 reserved
401 * 0x800000006 L2 cache information
402 * AMD: 0x800000005 L1 cache information
403 * 0x800000006 L2/L3 cache information
404 */
405
406 /* Cpuid 0x800000007:
407 * AMD: EAX, EBX, ECX - reserved
408 * EDX: Advanced Power Management Information
409 * Intel: Reserved
410 */
411 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
412 {
413 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
414
415 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
416
417 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
418 {
419 /* Only expose the TSC invariant capability bit to the guest. */
420 pCPUM->aGuestCpuIdExt[7].edx &= 0
421 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
422 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
423 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
424 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
425 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
426 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
427 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
428 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
429 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
430 | 0;
431 }
432 else
433 pCPUM->aGuestCpuIdExt[7].edx = 0;
434 }
435
436 /* Cpuid 0x800000008:
437 * AMD: EBX, EDX - reserved
438 * EAX: Virtual/Physical address Size
439 * ECX: Number of cores + APICIdCoreIdSize
440 * Intel: EAX: Virtual/Physical address Size
441 * EBX, ECX, EDX - reserved
442 */
443 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
444 {
445 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
446 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
447 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
448 * NC (0-7) Number of cores; 0 equals 1 core */
449 pCPUM->aGuestCpuIdExt[8].ecx = 0;
450 }
451
452 /*
453 * Limit it the number of entries and fill the remaining with the defaults.
454 *
455 * The limits are masking off stuff about power saving and similar, this
456 * is perhaps a bit crudely done as there is probably some relatively harmless
457 * info too in these leaves (like words about having a constant TSC).
458 */
459#if 0
460 /** @todo NT4 installation regression - investigate */
461 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
462 pCPUM->aGuestCpuIdStd[0].eax = 5;
463#else
464 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
465 pCPUM->aGuestCpuIdStd[0].eax = 2;
466#endif
467 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
468 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
469
470 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
471 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
472 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
473 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
474 : 0;
475 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
476 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
477
478 /*
479 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
480 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
481 * We currently don't support more than 1 processor.
482 */
483 pCPUM->aGuestCpuIdStd[4].eax = 0;
484
485 /*
486 * Centaur stuff (VIA).
487 *
488 * The important part here (we think) is to make sure the 0xc0000000
489 * function returns 0xc0000001. As for the features, we don't currently
490 * let on about any of those... 0xc0000002 seems to be some
491 * temperature/hz/++ stuff, include it as well (static).
492 */
493 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
494 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
495 {
496 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
497 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
498 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
499 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
500 i++)
501 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
502 }
503 else
504 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
505 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
506
507
508 /*
509 * Load CPUID overrides from configuration.
510 */
511 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
512 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
513 for (i=0;; )
514 {
515 while (cElements-- > 0)
516 {
517 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
518 if (pNode)
519 {
520 uint32_t u32;
521 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
522 if (VBOX_SUCCESS(rc))
523 pCpuId->eax = u32;
524 else
525 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
526
527 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
528 if (VBOX_SUCCESS(rc))
529 pCpuId->ebx = u32;
530 else
531 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
532
533 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
534 if (VBOX_SUCCESS(rc))
535 pCpuId->ecx = u32;
536 else
537 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
538
539 rc = CFGMR3QueryU32(pNode, "edx", &u32);
540 if (VBOX_SUCCESS(rc))
541 pCpuId->edx = u32;
542 else
543 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
544 }
545 pCpuId++;
546 i++;
547 }
548
549 /* next */
550 if ((i & UINT32_C(0xc0000000)) == 0)
551 {
552 pCpuId = &pCPUM->aGuestCpuIdExt[0];
553 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
554 i = UINT32_C(0x80000000);
555 }
556 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
557 {
558 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
559 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
560 i = UINT32_C(0xc0000000);
561 }
562 else
563 break;
564 }
565
566 /* Check if PAE was explicitely enabled by the user. */
567 bool fEnable = false;
568 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
569 if (VBOX_SUCCESS(rc) && fEnable)
570 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
571
572 /*
573 * Log the cpuid and we're good.
574 */
575 RTCPUSET OnlineSet;
576 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
577 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
578 LogRel(("************************* CPUID dump ************************\n"));
579 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
580 LogRel(("\n"));
581 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
582 LogRel(("******************** End of CPUID dump **********************\n"));
583 return VINF_SUCCESS;
584}
585
586
587
588
589/**
590 * Applies relocations to data and code managed by this
591 * component. This function will be called at init and
592 * whenever the VMM need to relocate it self inside the GC.
593 *
594 * The CPUM will update the addresses used by the switcher.
595 *
596 * @param pVM The VM.
597 */
598CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
599{
600 LogFlow(("CPUMR3Relocate\n"));
601 /*
602 * Switcher pointers.
603 */
604 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
605 pVM->cpum.s.pHyperCoreGC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
606 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
607}
608
609
610/**
611 * Queries the pointer to the internal CPUMCTX structure
612 *
613 * @returns VBox status code.
614 * @param pVM Handle to the virtual machine.
615 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
616 */
617CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
618{
619 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
620 /*
621 * Store the address. (Later we might check how's calling, thus the RC.)
622 */
623 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
624 return VINF_SUCCESS;
625}
626
627
628/**
629 * Terminates the CPUM.
630 *
631 * Termination means cleaning up and freeing all resources,
632 * the VM it self is at this point powered off or suspended.
633 *
634 * @returns VBox status code.
635 * @param pVM The VM to operate on.
636 */
637CPUMR3DECL(int) CPUMR3Term(PVM pVM)
638{
639 /** @todo ? */
640 return 0;
641}
642
643
644/**
645 * Resets the CPU.
646 *
647 * @returns VINF_SUCCESS.
648 * @param pVM The VM handle.
649 */
650CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
651{
652 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
653
654 /*
655 * Initialize everything to ZERO first.
656 */
657 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
658 memset(pCtx, 0, sizeof(*pCtx));
659 pVM->cpum.s.fUseFlags = fUseFlags;
660
661 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
662 pCtx->eip = 0x0000fff0;
663 pCtx->edx = 0x00000600; /* P6 processor */
664 pCtx->eflags.Bits.u1Reserved0 = 1;
665
666 pCtx->cs = 0xf000;
667 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
668 pCtx->csHid.u32Limit = 0x0000ffff;
669 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
670 pCtx->csHid.Attr.n.u1Present = 1;
671 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
672
673 pCtx->dsHid.u32Limit = 0x0000ffff;
674 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
675 pCtx->dsHid.Attr.n.u1Present = 1;
676 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
677
678 pCtx->esHid.u32Limit = 0x0000ffff;
679 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
680 pCtx->esHid.Attr.n.u1Present = 1;
681 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
682
683 pCtx->fsHid.u32Limit = 0x0000ffff;
684 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
685 pCtx->fsHid.Attr.n.u1Present = 1;
686 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
687
688 pCtx->gsHid.u32Limit = 0x0000ffff;
689 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
690 pCtx->gsHid.Attr.n.u1Present = 1;
691 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
692
693 pCtx->ssHid.u32Limit = 0x0000ffff;
694 pCtx->ssHid.Attr.n.u1Present = 1;
695 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
696 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
697
698 pCtx->idtr.cbIdt = 0xffff;
699 pCtx->gdtr.cbGdt = 0xffff;
700
701 pCtx->ldtrHid.u32Limit = 0xffff;
702 pCtx->ldtrHid.Attr.n.u1Present = 1;
703 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
704
705 pCtx->trHid.u32Limit = 0xffff;
706 pCtx->trHid.Attr.n.u1Present = 1;
707 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
708
709 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
710 pCtx->dr7 = 0x400;
711
712 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
713 pCtx->fpu.FCW = 0x37f;
714
715 /* Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
716 pCtx->fpu.MXCSR = 0x1F80;
717
718 /* Init PAT MSR */
719 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
720
721 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
722 * The Intel docs don't mention it.
723 */
724 pCtx->msrEFER = 0;
725}
726
727
728/**
729 * Execute state save operation.
730 *
731 * @returns VBox status code.
732 * @param pVM VM Handle.
733 * @param pSSM SSM operation handle.
734 */
735static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
736{
737 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
738 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
739
740 /*
741 * Save.
742 */
743 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
744 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
745 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
746 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
747
748 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
749 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
750
751 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
752 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
753
754 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
755 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
756
757 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
758
759 /* Add the cpuid for checking that the cpu is unchanged. */
760 uint32_t au32CpuId[8] = {0};
761 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
762 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
763 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
764}
765
766/**
767 * Load a version 1.6 CPUMCTX structure.
768 *
769 * @returns VBox status code.
770 * @param pVM VM Handle.
771 * @param pCpumctx16 Version 1.6 CPUMCTX
772 */
773static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
774{
775#define CPUMCTX16_LOADREG(regname) pVM->cpum.s.Guest.regname = pCpumctx16->regname;
776
777#define CPUMCTX16_LOADHIDREG(regname) \
778 pVM->cpum.s.Guest.regname##Hid.u64Base = pCpumctx16->regname##Hid.u32Base; \
779 pVM->cpum.s.Guest.regname##Hid.u32Limit = pCpumctx16->regname##Hid.u32Limit; \
780 pVM->cpum.s.Guest.regname##Hid.Attr = pCpumctx16->regname##Hid.Attr;
781
782#define CPUMCTX16_LOADSEGREG(regname) \
783 pVM->cpum.s.Guest.regname = pCpumctx16->regname; \
784 CPUMCTX16_LOADHIDREG(regname);
785
786 pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
787
788 CPUMCTX16_LOADREG(rax);
789 CPUMCTX16_LOADREG(rbx);
790 CPUMCTX16_LOADREG(rcx);
791 CPUMCTX16_LOADREG(rdx);
792 CPUMCTX16_LOADREG(rdi);
793 CPUMCTX16_LOADREG(rsi);
794 CPUMCTX16_LOADREG(rbp);
795 CPUMCTX16_LOADREG(esp);
796 CPUMCTX16_LOADREG(rip);
797 CPUMCTX16_LOADREG(rflags);
798
799 CPUMCTX16_LOADSEGREG(cs);
800 CPUMCTX16_LOADSEGREG(ds);
801 CPUMCTX16_LOADSEGREG(es);
802 CPUMCTX16_LOADSEGREG(fs);
803 CPUMCTX16_LOADSEGREG(gs);
804 CPUMCTX16_LOADSEGREG(ss);
805
806 CPUMCTX16_LOADREG(r8);
807 CPUMCTX16_LOADREG(r9);
808 CPUMCTX16_LOADREG(r10);
809 CPUMCTX16_LOADREG(r11);
810 CPUMCTX16_LOADREG(r12);
811 CPUMCTX16_LOADREG(r13);
812 CPUMCTX16_LOADREG(r14);
813 CPUMCTX16_LOADREG(r15);
814
815 CPUMCTX16_LOADREG(cr0);
816 CPUMCTX16_LOADREG(cr2);
817 CPUMCTX16_LOADREG(cr3);
818 CPUMCTX16_LOADREG(cr4);
819
820 CPUMCTX16_LOADREG(dr0);
821 CPUMCTX16_LOADREG(dr1);
822 CPUMCTX16_LOADREG(dr2);
823 CPUMCTX16_LOADREG(dr3);
824 CPUMCTX16_LOADREG(dr4);
825 CPUMCTX16_LOADREG(dr5);
826 CPUMCTX16_LOADREG(dr6);
827 CPUMCTX16_LOADREG(dr7);
828
829 pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
830 pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
831 pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
832 pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
833
834 CPUMCTX16_LOADREG(ldtr);
835 CPUMCTX16_LOADREG(tr);
836
837 pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
838
839 CPUMCTX16_LOADREG(msrEFER);
840 CPUMCTX16_LOADREG(msrSTAR);
841 CPUMCTX16_LOADREG(msrPAT);
842 CPUMCTX16_LOADREG(msrLSTAR);
843 CPUMCTX16_LOADREG(msrCSTAR);
844 CPUMCTX16_LOADREG(msrSFMASK);
845 CPUMCTX16_LOADREG(msrKERNELGSBASE);
846
847 CPUMCTX16_LOADHIDREG(ldtr);
848 CPUMCTX16_LOADHIDREG(tr);
849
850#undef CPUMCTX16_LOADHIDREG
851#undef CPUMCTX16_LOADSEGREG
852#undef CPUMCTX16_LOADREG
853}
854
855/**
856 * Execute state load operation.
857 *
858 * @returns VBox status code.
859 * @param pVM VM Handle.
860 * @param pSSM SSM operation handle.
861 * @param u32Version Data layout version.
862 */
863static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
864{
865 /*
866 * Validate version.
867 */
868 if ( u32Version != CPUM_SAVED_STATE_VERSION
869 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
870 {
871 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
872 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
873 }
874
875 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
876 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
877 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
878 else
879 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
880
881 /*
882 * Restore.
883 */
884 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
885 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
886 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
887 pVM->cpum.s.Hyper.cr3 = uCR3;
888 pVM->cpum.s.Hyper.esp = uESP;
889 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
890 {
891 CPUMCTX_VER1_6 cpumctx16;
892 memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
893 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
894
895 /* Save the old cpumctx state into the new one. */
896 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
897 }
898 else
899 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
900
901 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
902 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
903
904 uint32_t cElements;
905 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
906 /* Support old saved states with a smaller standard cpuid array. */
907 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
908 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
909 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
910
911 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
912 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
913 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
914 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
915
916 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
917 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
918 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
919 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
920
921 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
922
923 /*
924 * Check that the basic cpuid id information is unchanged.
925 */
926 uint32_t au32CpuId[8] = {0};
927 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
928 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
929 uint32_t au32CpuIdSaved[8];
930 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
931 if (VBOX_SUCCESS(rc))
932 {
933 /* Ignore APIC ID (AMD specs). */
934 au32CpuId[5] &= ~0xff000000;
935 au32CpuIdSaved[5] &= ~0xff000000;
936 /* Ignore the number of Logical CPUs (AMD specs). */
937 au32CpuId[5] &= ~0x00ff0000;
938 au32CpuIdSaved[5] &= ~0x00ff0000;
939
940 /* do the compare */
941 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
942 {
943 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
944 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
945 "Saved=%.*Vhxs\n"
946 "Real =%.*Vhxs\n",
947 sizeof(au32CpuIdSaved), au32CpuIdSaved,
948 sizeof(au32CpuId), au32CpuId));
949 else
950 {
951 LogRel(("cpumR3Load: CpuId mismatch!\n"
952 "Saved=%.*Vhxs\n"
953 "Real =%.*Vhxs\n",
954 sizeof(au32CpuIdSaved), au32CpuIdSaved,
955 sizeof(au32CpuId), au32CpuId));
956 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
957 }
958 }
959 }
960
961 return rc;
962}
963
964
965/**
966 * Formats the EFLAGS value into mnemonics.
967 *
968 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
969 * @param efl The EFLAGS value.
970 */
971static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
972{
973 /*
974 * Format the flags.
975 */
976 static struct
977 {
978 const char *pszSet; const char *pszClear; uint32_t fFlag;
979 } s_aFlags[] =
980 {
981 { "vip",NULL, X86_EFL_VIP },
982 { "vif",NULL, X86_EFL_VIF },
983 { "ac", NULL, X86_EFL_AC },
984 { "vm", NULL, X86_EFL_VM },
985 { "rf", NULL, X86_EFL_RF },
986 { "nt", NULL, X86_EFL_NT },
987 { "ov", "nv", X86_EFL_OF },
988 { "dn", "up", X86_EFL_DF },
989 { "ei", "di", X86_EFL_IF },
990 { "tf", NULL, X86_EFL_TF },
991 { "nt", "pl", X86_EFL_SF },
992 { "nz", "zr", X86_EFL_ZF },
993 { "ac", "na", X86_EFL_AF },
994 { "po", "pe", X86_EFL_PF },
995 { "cy", "nc", X86_EFL_CF },
996 };
997 char *psz = pszEFlags;
998 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
999 {
1000 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1001 if (pszAdd)
1002 {
1003 strcpy(psz, pszAdd);
1004 psz += strlen(pszAdd);
1005 *psz++ = ' ';
1006 }
1007 }
1008 psz[-1] = '\0';
1009}
1010
1011
1012/**
1013 * Formats a full register dump.
1014 *
1015 * @param pVM VM Handle.
1016 * @param pCtx The context to format.
1017 * @param pCtxCore The context core to format.
1018 * @param pHlp Output functions.
1019 * @param enmType The dump type.
1020 * @param pszPrefix Register name prefix.
1021 */
1022static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1023{
1024 /*
1025 * Format the EFLAGS.
1026 */
1027 uint32_t efl = pCtxCore->eflags.u32;
1028 char szEFlags[80];
1029 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1030
1031 /*
1032 * Format the registers.
1033 */
1034 switch (enmType)
1035 {
1036 case CPUMDUMPTYPE_TERSE:
1037 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1038 {
1039 pHlp->pfnPrintf(pHlp,
1040 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1041 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1042 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1043 "%sr14=%016RX64 %sr15=%016RX64\n"
1044 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1045 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1046 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1047 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1048 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1049 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1050 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1051 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1052 }
1053 else
1054 pHlp->pfnPrintf(pHlp,
1055 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1056 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1057 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1058 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1059 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1060 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1061 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1062 break;
1063
1064 case CPUMDUMPTYPE_DEFAULT:
1065 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1066 {
1067 pHlp->pfnPrintf(pHlp,
1068 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1069 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1070 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1071 "%sr14=%016RX64 %sr15=%016RX64\n"
1072 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1073 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1074 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1075 ,
1076 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1077 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1078 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1079 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1080 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1081 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1082 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1083 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1084 }
1085 else
1086 pHlp->pfnPrintf(pHlp,
1087 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1088 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1089 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1090 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1091 ,
1092 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1093 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1094 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1095 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1096 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1097 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1098 break;
1099
1100 case CPUMDUMPTYPE_VERBOSE:
1101 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1102 {
1103 pHlp->pfnPrintf(pHlp,
1104 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1105 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1106 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1107 "%sr14=%016RX64 %sr15=%016RX64\n"
1108 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1109 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1110 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1111 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1112 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1113 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1114 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1115 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1116 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1117 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1118 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1119 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1120 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1121 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1122 ,
1123 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1124 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1125 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1126 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1127 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1128 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1129 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1130 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1131 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1132 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1133 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1134 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1135 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1136 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1137 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1138 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1139 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1140 }
1141 else
1142 pHlp->pfnPrintf(pHlp,
1143 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1144 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1145 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1146 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1147 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1148 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1149 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1150 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1151 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1152 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1153 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1154 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1155 ,
1156 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1157 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1158 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
1159 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1160 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
1161 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1162 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1163 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1164 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1165 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1166 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1167 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1168
1169 pHlp->pfnPrintf(pHlp,
1170 "FPU:\n"
1171 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1172 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1173 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1174 ,
1175 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1176 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1177 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1178 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1179
1180
1181 pHlp->pfnPrintf(pHlp,
1182 "MSR:\n"
1183 "%sEFER =%016RX64\n"
1184 "%sPAT =%016RX64\n"
1185 "%sSTAR =%016RX64\n"
1186 "%sCSTAR =%016RX64\n"
1187 "%sLSTAR =%016RX64\n"
1188 "%sSFMASK =%016RX64\n"
1189 "%sKERNELGSBASE =%016RX64\n",
1190 pszPrefix, pCtx->msrEFER,
1191 pszPrefix, pCtx->msrPAT,
1192 pszPrefix, pCtx->msrSTAR,
1193 pszPrefix, pCtx->msrCSTAR,
1194 pszPrefix, pCtx->msrLSTAR,
1195 pszPrefix, pCtx->msrSFMASK,
1196 pszPrefix, pCtx->msrKERNELGSBASE);
1197
1198 break;
1199 }
1200}
1201
1202
1203/**
1204 * Display all cpu states and any other cpum info.
1205 *
1206 * @param pVM VM Handle.
1207 * @param pHlp The info helper functions.
1208 * @param pszArgs Arguments, ignored.
1209 */
1210static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1211{
1212 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1213 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1214 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1215 cpumR3InfoHost(pVM, pHlp, pszArgs);
1216}
1217
1218
1219/**
1220 * Parses the info argument.
1221 *
1222 * The argument starts with 'verbose', 'terse' or 'default' and then
1223 * continues with the comment string.
1224 *
1225 * @param pszArgs The pointer to the argument string.
1226 * @param penmType Where to store the dump type request.
1227 * @param ppszComment Where to store the pointer to the comment string.
1228 */
1229static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1230{
1231 if (!pszArgs)
1232 {
1233 *penmType = CPUMDUMPTYPE_DEFAULT;
1234 *ppszComment = "";
1235 }
1236 else
1237 {
1238 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1239 {
1240 pszArgs += 5;
1241 *penmType = CPUMDUMPTYPE_VERBOSE;
1242 }
1243 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1244 {
1245 pszArgs += 5;
1246 *penmType = CPUMDUMPTYPE_TERSE;
1247 }
1248 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1249 {
1250 pszArgs += 7;
1251 *penmType = CPUMDUMPTYPE_DEFAULT;
1252 }
1253 else
1254 *penmType = CPUMDUMPTYPE_DEFAULT;
1255 *ppszComment = RTStrStripL(pszArgs);
1256 }
1257}
1258
1259
1260/**
1261 * Display the guest cpu state.
1262 *
1263 * @param pVM VM Handle.
1264 * @param pHlp The info helper functions.
1265 * @param pszArgs Arguments, ignored.
1266 */
1267static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1268{
1269 CPUMDUMPTYPE enmType;
1270 const char *pszComment;
1271 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1272 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1273 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1274}
1275
1276/**
1277 * Display the current guest instruction
1278 *
1279 * @param pVM VM Handle.
1280 * @param pHlp The info helper functions.
1281 * @param pszArgs Arguments, ignored.
1282 */
1283static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1284{
1285 char szInstruction[256];
1286 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1287 if (VBOX_SUCCESS(rc))
1288 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1289}
1290
1291
1292/**
1293 * Display the hypervisor cpu state.
1294 *
1295 * @param pVM VM Handle.
1296 * @param pHlp The info helper functions.
1297 * @param pszArgs Arguments, ignored.
1298 */
1299static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1300{
1301 CPUMDUMPTYPE enmType;
1302 const char *pszComment;
1303 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1304 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1305 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1306 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1307}
1308
1309
1310/**
1311 * Display the host cpu state.
1312 *
1313 * @param pVM VM Handle.
1314 * @param pHlp The info helper functions.
1315 * @param pszArgs Arguments, ignored.
1316 */
1317static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1318{
1319 CPUMDUMPTYPE enmType;
1320 const char *pszComment;
1321 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1322 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1323
1324 /*
1325 * Format the EFLAGS.
1326 */
1327 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1328#if HC_ARCH_BITS == 32
1329 uint32_t efl = pCtx->eflags.u32;
1330#else
1331 uint64_t efl = pCtx->rflags;
1332#endif
1333 char szEFlags[80];
1334 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1335
1336 /*
1337 * Format the registers.
1338 */
1339#if HC_ARCH_BITS == 32
1340# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1341 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1342# endif
1343 {
1344 pHlp->pfnPrintf(pHlp,
1345 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1346 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1347 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1348 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1349 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1350 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1351 ,
1352 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1353 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1354 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1355 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1356 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1357 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1358 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1359 }
1360# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1361 else
1362# endif
1363#endif
1364#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1365 {
1366 pHlp->pfnPrintf(pHlp,
1367 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1368 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1369 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1370 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1371 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1372 "r14=%016RX64 r15=%016RX64\n"
1373 "iopl=%d %31s\n"
1374 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1375 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1376 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1377 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1378 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1379 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1380 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1381 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1382 ,
1383 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1384 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1385 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1386 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1387 pCtx->r11, pCtx->r12, pCtx->r13,
1388 pCtx->r14, pCtx->r15,
1389 X86_EFL_GET_IOPL(efl), szEFlags,
1390 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1391 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1392 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1393 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1394 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1395 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1396 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1397 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1398 }
1399#endif
1400}
1401
1402
1403/**
1404 * Get L1 cache / TLS associativity.
1405 */
1406static const char *getCacheAss(unsigned u, char *pszBuf)
1407{
1408 if (u == 0)
1409 return "res0 ";
1410 if (u == 1)
1411 return "direct";
1412 if (u >= 256)
1413 return "???";
1414
1415 RTStrPrintf(pszBuf, 16, "%d way", u);
1416 return pszBuf;
1417}
1418
1419
1420/**
1421 * Get L2 cache soociativity.
1422 */
1423const char *getL2CacheAss(unsigned u)
1424{
1425 switch (u)
1426 {
1427 case 0: return "off ";
1428 case 1: return "direct";
1429 case 2: return "2 way ";
1430 case 3: return "res3 ";
1431 case 4: return "4 way ";
1432 case 5: return "res5 ";
1433 case 6: return "8 way "; case 7: return "res7 ";
1434 case 8: return "16 way";
1435 case 9: return "res9 ";
1436 case 10: return "res10 ";
1437 case 11: return "res11 ";
1438 case 12: return "res12 ";
1439 case 13: return "res13 ";
1440 case 14: return "res14 ";
1441 case 15: return "fully ";
1442 default:
1443 return "????";
1444 }
1445}
1446
1447
1448/**
1449 * Display the guest CpuId leaves.
1450 *
1451 * @param pVM VM Handle.
1452 * @param pHlp The info helper functions.
1453 * @param pszArgs "terse", "default" or "verbose".
1454 */
1455static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1456{
1457 /*
1458 * Parse the argument.
1459 */
1460 unsigned iVerbosity = 1;
1461 if (pszArgs)
1462 {
1463 pszArgs = RTStrStripL(pszArgs);
1464 if (!strcmp(pszArgs, "terse"))
1465 iVerbosity--;
1466 else if (!strcmp(pszArgs, "verbose"))
1467 iVerbosity++;
1468 }
1469
1470 /*
1471 * Start cracking.
1472 */
1473 CPUMCPUID Host;
1474 CPUMCPUID Guest;
1475 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1476
1477 pHlp->pfnPrintf(pHlp,
1478 " RAW Standard CPUIDs\n"
1479 " Function eax ebx ecx edx\n");
1480 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1481 {
1482 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1483 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1484
1485 pHlp->pfnPrintf(pHlp,
1486 "Gst: %08x %08x %08x %08x %08x%s\n"
1487 "Hst: %08x %08x %08x %08x\n",
1488 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1489 i <= cStdMax ? "" : "*",
1490 Host.eax, Host.ebx, Host.ecx, Host.edx);
1491 }
1492
1493 /*
1494 * If verbose, decode it.
1495 */
1496 if (iVerbosity)
1497 {
1498 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1499 pHlp->pfnPrintf(pHlp,
1500 "Name: %.04s%.04s%.04s\n"
1501 "Supports: 0-%x\n",
1502 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1503 }
1504
1505 /*
1506 * Get Features.
1507 */
1508 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1509 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1510 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1511 if (cStdMax >= 1 && iVerbosity)
1512 {
1513 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1514 uint32_t uEAX = Guest.eax;
1515
1516 pHlp->pfnPrintf(pHlp,
1517 "Family: %d \tExtended: %d \tEffective: %d\n"
1518 "Model: %d \tExtended: %d \tEffective: %d\n"
1519 "Stepping: %d\n"
1520 "APIC ID: %#04x\n"
1521 "Logical CPUs: %d\n"
1522 "CLFLUSH Size: %d\n"
1523 "Brand ID: %#04x\n",
1524 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1525 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1526 ASMGetCpuStepping(uEAX),
1527 (Guest.ebx >> 24) & 0xff,
1528 (Guest.ebx >> 16) & 0xff,
1529 (Guest.ebx >> 8) & 0xff,
1530 (Guest.ebx >> 0) & 0xff);
1531 if (iVerbosity == 1)
1532 {
1533 uint32_t uEDX = Guest.edx;
1534 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1535 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1536 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1537 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1538 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1539 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1540 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1541 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1542 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1543 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1544 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1545 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1546 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1547 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1548 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1549 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1550 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1551 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1552 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1553 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1554 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1555 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1556 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1557 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1558 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1559 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1560 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1561 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1562 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1563 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1564 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1565 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1566 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1567 pHlp->pfnPrintf(pHlp, "\n");
1568
1569 uint32_t uECX = Guest.ecx;
1570 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1571 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1572 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1573 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1574 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1575 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1576 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1577 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1578 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1579 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1580 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1581 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1582 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1583 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1584 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1585 for (unsigned iBit = 14; iBit < 32; iBit++)
1586 if (uECX & RT_BIT(iBit))
1587 pHlp->pfnPrintf(pHlp, " %d", iBit);
1588 pHlp->pfnPrintf(pHlp, "\n");
1589 }
1590 else
1591 {
1592 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1593
1594 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1595 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1596 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1597 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1598
1599 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1600 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1601 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1602 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1603 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1604 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1605 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1606 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1607 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1608 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1609 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1610 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1611 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1612 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1613 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1614 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1615 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1616 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1617 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1618 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1619 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1620 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1621 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1622 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1623 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1624 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1625 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1626 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1627 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1628 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1629 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1630 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1631 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1632
1633 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1634 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1635 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1636 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1637 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1638 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1639 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1640 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1641 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1642 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1643 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1644 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1645 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1646 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1647 }
1648 }
1649 if (cStdMax >= 2 && iVerbosity)
1650 {
1651 /** @todo */
1652 }
1653
1654 /*
1655 * Extended.
1656 * Implemented after AMD specs.
1657 */
1658 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1659
1660 pHlp->pfnPrintf(pHlp,
1661 "\n"
1662 " RAW Extended CPUIDs\n"
1663 " Function eax ebx ecx edx\n");
1664 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1665 {
1666 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1667 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1668
1669 pHlp->pfnPrintf(pHlp,
1670 "Gst: %08x %08x %08x %08x %08x%s\n"
1671 "Hst: %08x %08x %08x %08x\n",
1672 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1673 i <= cExtMax ? "" : "*",
1674 Host.eax, Host.ebx, Host.ecx, Host.edx);
1675 }
1676
1677 /*
1678 * Understandable output
1679 */
1680 if (iVerbosity && cExtMax >= 0)
1681 {
1682 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1683 pHlp->pfnPrintf(pHlp,
1684 "Ext Name: %.4s%.4s%.4s\n"
1685 "Ext Supports: 0x80000000-%#010x\n",
1686 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1687 }
1688
1689 if (iVerbosity && cExtMax >= 1)
1690 {
1691 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1692 uint32_t uEAX = Guest.eax;
1693 pHlp->pfnPrintf(pHlp,
1694 "Family: %d \tExtended: %d \tEffective: %d\n"
1695 "Model: %d \tExtended: %d \tEffective: %d\n"
1696 "Stepping: %d\n"
1697 "Brand ID: %#05x\n",
1698 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1699 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1700 ASMGetCpuStepping(uEAX),
1701 Guest.ebx & 0xfff);
1702
1703 if (iVerbosity == 1)
1704 {
1705 uint32_t uEDX = Guest.edx;
1706 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1707 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1708 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1709 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1710 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1711 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1712 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1713 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1714 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1715 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1716 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1717 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1718 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1719 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1720 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1721 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1722 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1723 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1724 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1725 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1726 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1727 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1728 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1729 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1730 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1731 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1732 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1733 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1734 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1735 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1736 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1737 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1738 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1739 pHlp->pfnPrintf(pHlp, "\n");
1740
1741 uint32_t uECX = Guest.ecx;
1742 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1743 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1744 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1745 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1746 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1747 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1748 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1749 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1750 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1751 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1752 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1753 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1754 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1755 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1756 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1757 for (unsigned iBit = 5; iBit < 32; iBit++)
1758 if (uECX & RT_BIT(iBit))
1759 pHlp->pfnPrintf(pHlp, " %d", iBit);
1760 pHlp->pfnPrintf(pHlp, "\n");
1761 }
1762 else
1763 {
1764 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1765
1766 uint32_t uEdxGst = Guest.edx;
1767 uint32_t uEdxHst = Host.edx;
1768 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1769 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1770 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1771 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1772 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1773 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1774 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1775 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1776 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1777 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1778 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1779 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1780 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1781 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1782 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1783 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1784 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1785 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1786 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1787 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1788 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1789 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1790 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1791 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1792 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1793 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1794 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1795 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1796 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1797 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1798 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1799 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1800 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1801
1802 uint32_t uEcxGst = Guest.ecx;
1803 uint32_t uEcxHst = Host.ecx;
1804 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1805 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1806 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1807 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1808 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1809 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1810 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1811 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1812 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1813 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1814 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1815 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1816 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1817 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1818 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1819 }
1820 }
1821
1822 if (iVerbosity && cExtMax >= 2)
1823 {
1824 char szString[4*4*3+1] = {0};
1825 uint32_t *pu32 = (uint32_t *)szString;
1826 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1827 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1828 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1829 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1830 if (cExtMax >= 3)
1831 {
1832 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1833 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1834 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1835 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1836 }
1837 if (cExtMax >= 4)
1838 {
1839 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1840 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1841 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1842 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1843 }
1844 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1845 }
1846
1847 if (iVerbosity && cExtMax >= 5)
1848 {
1849 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1850 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1851 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1852 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1853 char sz1[32];
1854 char sz2[32];
1855
1856 pHlp->pfnPrintf(pHlp,
1857 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1858 "TLB 2/4M Data: %s %3d entries\n",
1859 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1860 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1861 pHlp->pfnPrintf(pHlp,
1862 "TLB 4K Instr/Uni: %s %3d entries\n"
1863 "TLB 4K Data: %s %3d entries\n",
1864 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1865 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1866 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1867 "L1 Instr Cache Lines Per Tag: %d\n"
1868 "L1 Instr Cache Associativity: %s\n"
1869 "L1 Instr Cache Size: %d KB\n",
1870 (uEDX >> 0) & 0xff,
1871 (uEDX >> 8) & 0xff,
1872 getCacheAss((uEDX >> 16) & 0xff, sz1),
1873 (uEDX >> 24) & 0xff);
1874 pHlp->pfnPrintf(pHlp,
1875 "L1 Data Cache Line Size: %d bytes\n"
1876 "L1 Data Cache Lines Per Tag: %d\n"
1877 "L1 Data Cache Associativity: %s\n"
1878 "L1 Data Cache Size: %d KB\n",
1879 (uECX >> 0) & 0xff,
1880 (uECX >> 8) & 0xff,
1881 getCacheAss((uECX >> 16) & 0xff, sz1),
1882 (uECX >> 24) & 0xff);
1883 }
1884
1885 if (iVerbosity && cExtMax >= 6)
1886 {
1887 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1888 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1889 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1890
1891 pHlp->pfnPrintf(pHlp,
1892 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1893 "L2 TLB 2/4M Data: %s %4d entries\n",
1894 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1895 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1896 pHlp->pfnPrintf(pHlp,
1897 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1898 "L2 TLB 4K Data: %s %4d entries\n",
1899 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1900 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1901 pHlp->pfnPrintf(pHlp,
1902 "L2 Cache Line Size: %d bytes\n"
1903 "L2 Cache Lines Per Tag: %d\n"
1904 "L2 Cache Associativity: %s\n"
1905 "L2 Cache Size: %d KB\n",
1906 (uEDX >> 0) & 0xff,
1907 (uEDX >> 8) & 0xf,
1908 getL2CacheAss((uEDX >> 12) & 0xf),
1909 (uEDX >> 16) & 0xffff);
1910 }
1911
1912 if (iVerbosity && cExtMax >= 7)
1913 {
1914 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1915
1916 pHlp->pfnPrintf(pHlp, "APM Features: ");
1917 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1918 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1919 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1920 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1921 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1922 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1923 for (unsigned iBit = 6; iBit < 32; iBit++)
1924 if (uEDX & RT_BIT(iBit))
1925 pHlp->pfnPrintf(pHlp, " %d", iBit);
1926 pHlp->pfnPrintf(pHlp, "\n");
1927 }
1928
1929 if (iVerbosity && cExtMax >= 8)
1930 {
1931 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1932 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1933
1934 pHlp->pfnPrintf(pHlp,
1935 "Physical Address Width: %d bits\n"
1936 "Virtual Address Width: %d bits\n",
1937 (uEAX >> 0) & 0xff,
1938 (uEAX >> 8) & 0xff);
1939 pHlp->pfnPrintf(pHlp,
1940 "Physical Core Count: %d\n",
1941 (uECX >> 0) & 0xff);
1942 }
1943
1944
1945 /*
1946 * Centaur.
1947 */
1948 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1949
1950 pHlp->pfnPrintf(pHlp,
1951 "\n"
1952 " RAW Centaur CPUIDs\n"
1953 " Function eax ebx ecx edx\n");
1954 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1955 {
1956 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1957 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1958
1959 pHlp->pfnPrintf(pHlp,
1960 "Gst: %08x %08x %08x %08x %08x%s\n"
1961 "Hst: %08x %08x %08x %08x\n",
1962 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1963 i <= cCentaurMax ? "" : "*",
1964 Host.eax, Host.ebx, Host.ecx, Host.edx);
1965 }
1966
1967 /*
1968 * Understandable output
1969 */
1970 if (iVerbosity && cCentaurMax >= 0)
1971 {
1972 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1973 pHlp->pfnPrintf(pHlp,
1974 "Centaur Supports: 0xc0000000-%#010x\n",
1975 Guest.eax);
1976 }
1977
1978 if (iVerbosity && cCentaurMax >= 1)
1979 {
1980 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1981 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1982 uint32_t uEdxHst = Host.edx;
1983
1984 if (iVerbosity == 1)
1985 {
1986 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1987 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1988 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1989 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1990 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1991 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1992 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1993 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1994 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1995 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1996 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1997 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1998 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1999 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2000 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2001 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2002 for (unsigned iBit = 14; iBit < 32; iBit++)
2003 if (uEdxGst & RT_BIT(iBit))
2004 pHlp->pfnPrintf(pHlp, " %d", iBit);
2005 pHlp->pfnPrintf(pHlp, "\n");
2006 }
2007 else
2008 {
2009 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2010 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2011 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2012 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2013 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2014 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2015 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2016 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2017 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2018 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2019 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2020 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2021 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2022 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2023 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2024 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2025 for (unsigned iBit = 14; iBit < 32; iBit++)
2026 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2027 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2028 pHlp->pfnPrintf(pHlp, "\n");
2029 }
2030 }
2031}
2032
2033
2034/**
2035 * Structure used when disassembling and instructions in DBGF.
2036 * This is used so the reader function can get the stuff it needs.
2037 */
2038typedef struct CPUMDISASSTATE
2039{
2040 /** Pointer to the CPU structure. */
2041 PDISCPUSTATE pCpu;
2042 /** The VM handle. */
2043 PVM pVM;
2044 /** Pointer to the first byte in the segemnt. */
2045 RTGCUINTPTR GCPtrSegBase;
2046 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2047 RTGCUINTPTR GCPtrSegEnd;
2048 /** The size of the segment minus 1. */
2049 RTGCUINTPTR cbSegLimit;
2050 /** Pointer to the current page - HC Ptr. */
2051 void const *pvPageHC;
2052 /** Pointer to the current page - GC Ptr. */
2053 RTGCPTR pvPageGC;
2054 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2055 PGMPAGEMAPLOCK PageMapLock;
2056 /** Whether the PageMapLock is valid or not. */
2057 bool fLocked;
2058 /** 64 bits mode or not. */
2059 bool f64Bits;
2060} CPUMDISASSTATE, *PCPUMDISASSTATE;
2061
2062
2063/**
2064 * Instruction reader.
2065 *
2066 * @returns VBox status code.
2067 * @param PtrSrc Address to read from.
2068 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2069 * @param pu8Dst Where to store the bytes.
2070 * @param cbRead Number of bytes to read.
2071 * @param uDisCpu Pointer to the disassembler cpu state.
2072 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2073 */
2074static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2075{
2076 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2077 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2078 Assert(cbRead > 0);
2079 for (;;)
2080 {
2081 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2082
2083 /* Need to update the page translation? */
2084 if ( !pState->pvPageHC
2085 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2086 {
2087 int rc = VINF_SUCCESS;
2088
2089 /* translate the address */
2090 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2091 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2092 {
2093 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
2094 if (!pState->pvPageHC)
2095 rc = VERR_INVALID_POINTER;
2096 }
2097 else
2098 {
2099 /* Release mapping lock previously acquired. */
2100 if (pState->fLocked)
2101 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2102 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
2103 pState->fLocked = RT_SUCCESS_NP(rc);
2104 }
2105 if (VBOX_FAILURE(rc))
2106 {
2107 pState->pvPageHC = NULL;
2108 return rc;
2109 }
2110 }
2111
2112 /* check the segemnt limit */
2113 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2114 return VERR_OUT_OF_SELECTOR_BOUNDS;
2115
2116 /* calc how much we can read */
2117 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2118 if (!pState->f64Bits)
2119 {
2120 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2121 if (cb > cbSeg && cbSeg)
2122 cb = cbSeg;
2123 }
2124 if (cb > cbRead)
2125 cb = cbRead;
2126
2127 /* read and advance */
2128 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2129 cbRead -= cb;
2130 if (!cbRead)
2131 return VINF_SUCCESS;
2132 pu8Dst += cb;
2133 PtrSrc += cb;
2134 }
2135}
2136
2137
2138/**
2139 * Disassemble an instruction and return the information in the provided structure.
2140 *
2141 * @returns VBox status code.
2142 * @param pVM VM Handle
2143 * @param pCtx CPU context
2144 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2145 * @param pCpu Disassembly state
2146 * @param pszPrefix String prefix for logging (debug only)
2147 *
2148 */
2149CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2150{
2151 CPUMDISASSTATE State;
2152 int rc;
2153
2154 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2155 State.pCpu = pCpu;
2156 State.pvPageGC = 0;
2157 State.pvPageHC = NULL;
2158 State.pVM = pVM;
2159 State.fLocked = false;
2160 State.f64Bits = false;
2161
2162 /*
2163 * Get selector information.
2164 */
2165 if ( (pCtx->cr0 & X86_CR0_PE)
2166 && pCtx->eflags.Bits.u1VM == 0)
2167 {
2168 if (CPUMAreHiddenSelRegsValid(pVM))
2169 {
2170 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2171 State.GCPtrSegBase = pCtx->csHid.u64Base;
2172 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2173 State.cbSegLimit = pCtx->csHid.u32Limit;
2174 pCpu->mode = (State.f64Bits)
2175 ? CPUMODE_64BIT
2176 : pCtx->csHid.Attr.n.u1DefBig
2177 ? CPUMODE_32BIT
2178 : CPUMODE_16BIT;
2179 }
2180 else
2181 {
2182 SELMSELINFO SelInfo;
2183
2184 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2185 if (!VBOX_SUCCESS(rc))
2186 {
2187 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2188 return rc;
2189 }
2190
2191 /*
2192 * Validate the selector.
2193 */
2194 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2195 if (!VBOX_SUCCESS(rc))
2196 {
2197 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2198 return rc;
2199 }
2200 State.GCPtrSegBase = SelInfo.GCPtrBase;
2201 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2202 State.cbSegLimit = SelInfo.cbLimit;
2203 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2204 }
2205 }
2206 else
2207 {
2208 /* real or V86 mode */
2209 pCpu->mode = CPUMODE_16BIT;
2210 State.GCPtrSegBase = pCtx->cs * 16;
2211 State.GCPtrSegEnd = 0xFFFFFFFF;
2212 State.cbSegLimit = 0xFFFFFFFF;
2213 }
2214
2215 /*
2216 * Disassemble the instruction.
2217 */
2218 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2219 pCpu->apvUserData[0] = &State;
2220
2221 uint32_t cbInstr;
2222#ifndef LOG_ENABLED
2223 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2224 if (VBOX_SUCCESS(rc))
2225 {
2226#else
2227 char szOutput[160];
2228 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2229 if (VBOX_SUCCESS(rc))
2230 {
2231 /* log it */
2232 if (pszPrefix)
2233 Log(("%s: %s", pszPrefix, szOutput));
2234 else
2235 Log(("%s", szOutput));
2236#endif
2237 rc = VINF_SUCCESS;
2238 }
2239 else
2240 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2241
2242 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2243 if (State.fLocked)
2244 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2245
2246 return rc;
2247}
2248
2249#ifdef DEBUG
2250
2251/**
2252 * Disassemble an instruction and dump it to the log
2253 *
2254 * @returns VBox status code.
2255 * @param pVM VM Handle
2256 * @param pCtx CPU context
2257 * @param pc GC instruction pointer
2258 * @param prefix String prefix for logging
2259 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2260 *
2261 */
2262CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2263{
2264 DISCPUSTATE cpu;
2265
2266 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2267}
2268
2269/**
2270 * Disassemble an instruction and dump it to the log
2271 *
2272 * @returns VBox status code.
2273 * @param pVM VM Handle
2274 * @param pCtx CPU context
2275 * @param pc GC instruction pointer
2276 * @param prefix String prefix for logging
2277 * @param nrInstructions
2278 *
2279 */
2280CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2281{
2282 for(int i=0;i<nrInstructions;i++)
2283 {
2284 DISCPUSTATE cpu;
2285
2286 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2287 pc += cpu.opsize;
2288 }
2289}
2290
2291#endif /* DEBUG */
2292
2293#ifdef DEBUG
2294/**
2295 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2296 *
2297 * @internal
2298 */
2299CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2300{
2301 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2302}
2303#endif /* DEBUG */
2304
2305
2306/**
2307 * API for controlling a few of the CPU features found in CR4.
2308 *
2309 * Currently only X86_CR4_TSD is accepted as input.
2310 *
2311 * @returns VBox status code.
2312 *
2313 * @param pVM The VM handle.
2314 * @param fOr The CR4 OR mask.
2315 * @param fAnd The CR4 AND mask.
2316 */
2317CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2318{
2319 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2320 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2321
2322 pVM->cpum.s.CR4.OrMask &= fAnd;
2323 pVM->cpum.s.CR4.OrMask |= fOr;
2324
2325 return VINF_SUCCESS;
2326}
2327
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